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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
27c766aa JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/moduleparam.h> | |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/timer.h> | |
1da177e4 | 32 | #include <linux/watchdog.h> |
d052d1be | 33 | #include <linux/platform_device.h> |
1da177e4 | 34 | #include <linux/interrupt.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
41dc8b72 AC |
36 | #include <linux/uaccess.h> |
37 | #include <linux/io.h> | |
e02f838e | 38 | #include <linux/cpufreq.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
25dc46e3 | 40 | #include <linux/err.h> |
3016a552 | 41 | #include <linux/of.h> |
4f1f653a LKA |
42 | #include <linux/mfd/syscon.h> |
43 | #include <linux/regmap.h> | |
f286e133 | 44 | #include <linux/delay.h> |
1da177e4 | 45 | |
a8f5401a TF |
46 | #define S3C2410_WTCON 0x00 |
47 | #define S3C2410_WTDAT 0x04 | |
48 | #define S3C2410_WTCNT 0x08 | |
1da177e4 | 49 | |
a8f5401a TF |
50 | #define S3C2410_WTCON_RSTEN (1 << 0) |
51 | #define S3C2410_WTCON_INTEN (1 << 2) | |
52 | #define S3C2410_WTCON_ENABLE (1 << 5) | |
1da177e4 | 53 | |
a8f5401a TF |
54 | #define S3C2410_WTCON_DIV16 (0 << 3) |
55 | #define S3C2410_WTCON_DIV32 (1 << 3) | |
56 | #define S3C2410_WTCON_DIV64 (2 << 3) | |
57 | #define S3C2410_WTCON_DIV128 (3 << 3) | |
58 | ||
59 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) | |
60 | #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) | |
1da177e4 | 61 | |
1da177e4 LT |
62 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) |
63 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
64 | ||
cffc9a60 | 65 | #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
4f1f653a LKA |
66 | #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
67 | #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c | |
68 | #define QUIRK_HAS_PMU_CONFIG (1 << 0) | |
cffc9a60 DA |
69 | #define QUIRK_HAS_RST_STAT (1 << 1) |
70 | ||
71 | /* These quirks require that we have a PMU register map */ | |
72 | #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ | |
73 | QUIRK_HAS_RST_STAT) | |
4f1f653a | 74 | |
86a1e189 | 75 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 76 | static int tmr_margin; |
1da177e4 | 77 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 AC |
78 | static int soft_noboot; |
79 | static int debug; | |
1da177e4 LT |
80 | |
81 | module_param(tmr_margin, int, 0); | |
82 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 83 | module_param(nowayout, bool, 0); |
1da177e4 LT |
84 | module_param(soft_noboot, int, 0); |
85 | module_param(debug, int, 0); | |
86 | ||
76550d32 | 87 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
41dc8b72 AC |
88 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
89 | MODULE_PARM_DESC(tmr_atboot, | |
90 | "Watchdog is started at boot time if set to 1, default=" | |
91 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
92 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
93 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e | 94 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
76550d32 RD |
95 | "0 to reboot (default 0)"); |
96 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); | |
1da177e4 | 97 | |
4f1f653a LKA |
98 | /** |
99 | * struct s3c2410_wdt_variant - Per-variant config data | |
100 | * | |
101 | * @disable_reg: Offset in pmureg for the register that disables the watchdog | |
102 | * timer reset functionality. | |
103 | * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog | |
104 | * timer reset functionality. | |
105 | * @mask_bit: Bit number for the watchdog timer in the disable register and the | |
106 | * mask reset register. | |
cffc9a60 DA |
107 | * @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
108 | * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog | |
109 | * reset. | |
4f1f653a LKA |
110 | * @quirks: A bitfield of quirks. |
111 | */ | |
112 | ||
113 | struct s3c2410_wdt_variant { | |
114 | int disable_reg; | |
115 | int mask_reset_reg; | |
116 | int mask_bit; | |
cffc9a60 DA |
117 | int rst_stat_reg; |
118 | int rst_stat_bit; | |
4f1f653a LKA |
119 | u32 quirks; |
120 | }; | |
121 | ||
af4ea631 LKA |
122 | struct s3c2410_wdt { |
123 | struct device *dev; | |
124 | struct clk *clock; | |
125 | void __iomem *reg_base; | |
126 | unsigned int count; | |
127 | spinlock_t lock; | |
128 | unsigned long wtcon_save; | |
129 | unsigned long wtdat_save; | |
130 | struct watchdog_device wdt_device; | |
131 | struct notifier_block freq_transition; | |
4f1f653a LKA |
132 | struct s3c2410_wdt_variant *drv_data; |
133 | struct regmap *pmureg; | |
134 | }; | |
135 | ||
136 | static const struct s3c2410_wdt_variant drv_data_s3c2410 = { | |
137 | .quirks = 0 | |
138 | }; | |
139 | ||
140 | #ifdef CONFIG_OF | |
141 | static const struct s3c2410_wdt_variant drv_data_exynos5250 = { | |
142 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
143 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
144 | .mask_bit = 20, | |
cffc9a60 DA |
145 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
146 | .rst_stat_bit = 20, | |
147 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
4f1f653a LKA |
148 | }; |
149 | ||
150 | static const struct s3c2410_wdt_variant drv_data_exynos5420 = { | |
151 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
152 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
153 | .mask_bit = 0, | |
cffc9a60 DA |
154 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
155 | .rst_stat_bit = 9, | |
156 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
4f1f653a LKA |
157 | }; |
158 | ||
2b9366b6 NKC |
159 | static const struct s3c2410_wdt_variant drv_data_exynos7 = { |
160 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
161 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
5476b2b7 | 162 | .mask_bit = 23, |
2b9366b6 NKC |
163 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
164 | .rst_stat_bit = 23, /* A57 WDTRESET */ | |
165 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
166 | }; | |
167 | ||
4f1f653a LKA |
168 | static const struct of_device_id s3c2410_wdt_match[] = { |
169 | { .compatible = "samsung,s3c2410-wdt", | |
170 | .data = &drv_data_s3c2410 }, | |
171 | { .compatible = "samsung,exynos5250-wdt", | |
172 | .data = &drv_data_exynos5250 }, | |
173 | { .compatible = "samsung,exynos5420-wdt", | |
174 | .data = &drv_data_exynos5420 }, | |
2b9366b6 NKC |
175 | { .compatible = "samsung,exynos7-wdt", |
176 | .data = &drv_data_exynos7 }, | |
4f1f653a | 177 | {}, |
af4ea631 | 178 | }; |
4f1f653a LKA |
179 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
180 | #endif | |
181 | ||
182 | static const struct platform_device_id s3c2410_wdt_ids[] = { | |
183 | { | |
184 | .name = "s3c2410-wdt", | |
185 | .driver_data = (unsigned long)&drv_data_s3c2410, | |
186 | }, | |
187 | {} | |
188 | }; | |
189 | MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); | |
1da177e4 LT |
190 | |
191 | /* watchdog control routines */ | |
192 | ||
27c766aa JP |
193 | #define DBG(fmt, ...) \ |
194 | do { \ | |
195 | if (debug) \ | |
196 | pr_info(fmt, ##__VA_ARGS__); \ | |
197 | } while (0) | |
1da177e4 LT |
198 | |
199 | /* functions */ | |
200 | ||
af4ea631 LKA |
201 | static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
202 | { | |
203 | return container_of(nb, struct s3c2410_wdt, freq_transition); | |
204 | } | |
205 | ||
4f1f653a LKA |
206 | static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) |
207 | { | |
208 | int ret; | |
209 | u32 mask_val = 1 << wdt->drv_data->mask_bit; | |
210 | u32 val = 0; | |
211 | ||
212 | /* No need to do anything if no PMU CONFIG needed */ | |
213 | if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) | |
214 | return 0; | |
215 | ||
216 | if (mask) | |
217 | val = mask_val; | |
218 | ||
219 | ret = regmap_update_bits(wdt->pmureg, | |
220 | wdt->drv_data->disable_reg, | |
221 | mask_val, val); | |
222 | if (ret < 0) | |
223 | goto error; | |
224 | ||
225 | ret = regmap_update_bits(wdt->pmureg, | |
226 | wdt->drv_data->mask_reset_reg, | |
227 | mask_val, val); | |
228 | error: | |
229 | if (ret < 0) | |
230 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
231 | ||
232 | return ret; | |
233 | } | |
234 | ||
25dc46e3 | 235 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 236 | { |
af4ea631 LKA |
237 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
238 | ||
239 | spin_lock(&wdt->lock); | |
240 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
241 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
242 | |
243 | return 0; | |
1da177e4 LT |
244 | } |
245 | ||
af4ea631 | 246 | static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
41dc8b72 AC |
247 | { |
248 | unsigned long wtcon; | |
249 | ||
af4ea631 | 250 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
41dc8b72 | 251 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
af4ea631 | 252 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
41dc8b72 AC |
253 | } |
254 | ||
25dc46e3 | 255 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 | 256 | { |
af4ea631 LKA |
257 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
258 | ||
259 | spin_lock(&wdt->lock); | |
260 | __s3c2410wdt_stop(wdt); | |
261 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
262 | |
263 | return 0; | |
1da177e4 LT |
264 | } |
265 | ||
25dc46e3 | 266 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
267 | { |
268 | unsigned long wtcon; | |
af4ea631 | 269 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
1da177e4 | 270 | |
af4ea631 | 271 | spin_lock(&wdt->lock); |
41dc8b72 | 272 | |
af4ea631 | 273 | __s3c2410wdt_stop(wdt); |
1da177e4 | 274 | |
af4ea631 | 275 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
276 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
277 | ||
278 | if (soft_noboot) { | |
279 | wtcon |= S3C2410_WTCON_INTEN; | |
280 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
281 | } else { | |
282 | wtcon &= ~S3C2410_WTCON_INTEN; | |
283 | wtcon |= S3C2410_WTCON_RSTEN; | |
284 | } | |
285 | ||
af4ea631 LKA |
286 | DBG("%s: count=0x%08x, wtcon=%08lx\n", |
287 | __func__, wdt->count, wtcon); | |
1da177e4 | 288 | |
af4ea631 LKA |
289 | writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
290 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
291 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
292 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
293 | |
294 | return 0; | |
1da177e4 LT |
295 | } |
296 | ||
af4ea631 | 297 | static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
e02f838e | 298 | { |
af4ea631 | 299 | return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
e02f838e BD |
300 | } |
301 | ||
25dc46e3 | 302 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) |
1da177e4 | 303 | { |
af4ea631 LKA |
304 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
305 | unsigned long freq = clk_get_rate(wdt->clock); | |
1da177e4 LT |
306 | unsigned int count; |
307 | unsigned int divisor = 1; | |
308 | unsigned long wtcon; | |
309 | ||
310 | if (timeout < 1) | |
311 | return -EINVAL; | |
312 | ||
17862440 | 313 | freq = DIV_ROUND_UP(freq, 128); |
1da177e4 LT |
314 | count = timeout * freq; |
315 | ||
e02f838e | 316 | DBG("%s: count=%d, timeout=%d, freq=%lu\n", |
fa9363c5 | 317 | __func__, count, timeout, freq); |
1da177e4 LT |
318 | |
319 | /* if the count is bigger than the watchdog register, | |
320 | then work out what we need to do (and if) we can | |
321 | actually make this value | |
322 | */ | |
323 | ||
324 | if (count >= 0x10000) { | |
17862440 | 325 | divisor = DIV_ROUND_UP(count, 0xffff); |
1da177e4 | 326 | |
17862440 | 327 | if (divisor > 0x100) { |
af4ea631 | 328 | dev_err(wdt->dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
329 | return -EINVAL; |
330 | } | |
331 | } | |
332 | ||
1da177e4 | 333 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", |
17862440 | 334 | __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor)); |
1da177e4 | 335 | |
17862440 | 336 | count = DIV_ROUND_UP(count, divisor); |
af4ea631 | 337 | wdt->count = count; |
1da177e4 LT |
338 | |
339 | /* update the pre-scaler */ | |
af4ea631 | 340 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
341 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
342 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
343 | ||
af4ea631 LKA |
344 | writel(count, wdt->reg_base + S3C2410_WTDAT); |
345 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
1da177e4 | 346 | |
5f2430f5 | 347 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 348 | |
1da177e4 LT |
349 | return 0; |
350 | } | |
351 | ||
4d8b229d GR |
352 | static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, |
353 | void *data) | |
c71f5cd2 DR |
354 | { |
355 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); | |
356 | void __iomem *wdt_base = wdt->reg_base; | |
357 | ||
358 | /* disable watchdog, to be safe */ | |
359 | writel(0, wdt_base + S3C2410_WTCON); | |
360 | ||
361 | /* put initial values into count and data */ | |
362 | writel(0x80, wdt_base + S3C2410_WTCNT); | |
363 | writel(0x80, wdt_base + S3C2410_WTDAT); | |
364 | ||
365 | /* set the watchdog to go and reset... */ | |
366 | writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | | |
367 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), | |
368 | wdt_base + S3C2410_WTCON); | |
369 | ||
370 | /* wait for reset to assert... */ | |
371 | mdelay(500); | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
a77dba7e | 376 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 377 | |
41dc8b72 | 378 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
379 | .options = OPTIONS, |
380 | .firmware_version = 0, | |
381 | .identity = "S3C2410 Watchdog", | |
382 | }; | |
383 | ||
25dc46e3 WS |
384 | static struct watchdog_ops s3c2410wdt_ops = { |
385 | .owner = THIS_MODULE, | |
386 | .start = s3c2410wdt_start, | |
387 | .stop = s3c2410wdt_stop, | |
388 | .ping = s3c2410wdt_keepalive, | |
389 | .set_timeout = s3c2410wdt_set_heartbeat, | |
c71f5cd2 | 390 | .restart = s3c2410wdt_restart, |
1da177e4 LT |
391 | }; |
392 | ||
25dc46e3 WS |
393 | static struct watchdog_device s3c2410_wdd = { |
394 | .info = &s3c2410_wdt_ident, | |
395 | .ops = &s3c2410wdt_ops, | |
c1fd5f64 | 396 | .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
397 | }; |
398 | ||
1da177e4 LT |
399 | /* interrupt handler code */ |
400 | ||
7d12e780 | 401 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 402 | { |
af4ea631 | 403 | struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
1da177e4 | 404 | |
af4ea631 LKA |
405 | dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
406 | ||
407 | s3c2410wdt_keepalive(&wdt->wdt_device); | |
1da177e4 LT |
408 | return IRQ_HANDLED; |
409 | } | |
e02f838e | 410 | |
0f1dd98d | 411 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
e02f838e BD |
412 | |
413 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
414 | unsigned long val, void *data) | |
415 | { | |
416 | int ret; | |
af4ea631 | 417 | struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
e02f838e | 418 | |
af4ea631 | 419 | if (!s3c2410wdt_is_running(wdt)) |
e02f838e BD |
420 | goto done; |
421 | ||
422 | if (val == CPUFREQ_PRECHANGE) { | |
423 | /* To ensure that over the change we don't cause the | |
424 | * watchdog to trigger, we perform an keep-alive if | |
425 | * the watchdog is running. | |
426 | */ | |
427 | ||
af4ea631 | 428 | s3c2410wdt_keepalive(&wdt->wdt_device); |
e02f838e | 429 | } else if (val == CPUFREQ_POSTCHANGE) { |
af4ea631 | 430 | s3c2410wdt_stop(&wdt->wdt_device); |
e02f838e | 431 | |
af4ea631 LKA |
432 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
433 | wdt->wdt_device.timeout); | |
e02f838e BD |
434 | |
435 | if (ret >= 0) | |
af4ea631 | 436 | s3c2410wdt_start(&wdt->wdt_device); |
e02f838e BD |
437 | else |
438 | goto err; | |
439 | } | |
440 | ||
441 | done: | |
442 | return 0; | |
443 | ||
444 | err: | |
af4ea631 LKA |
445 | dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
446 | wdt->wdt_device.timeout); | |
e02f838e BD |
447 | return ret; |
448 | } | |
449 | ||
af4ea631 | 450 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
e02f838e | 451 | { |
af4ea631 LKA |
452 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
453 | ||
454 | return cpufreq_register_notifier(&wdt->freq_transition, | |
e02f838e BD |
455 | CPUFREQ_TRANSITION_NOTIFIER); |
456 | } | |
457 | ||
af4ea631 | 458 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e | 459 | { |
af4ea631 LKA |
460 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
461 | ||
462 | cpufreq_unregister_notifier(&wdt->freq_transition, | |
e02f838e BD |
463 | CPUFREQ_TRANSITION_NOTIFIER); |
464 | } | |
465 | ||
466 | #else | |
af4ea631 LKA |
467 | |
468 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) | |
e02f838e BD |
469 | { |
470 | return 0; | |
471 | } | |
472 | ||
af4ea631 | 473 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e BD |
474 | { |
475 | } | |
476 | #endif | |
477 | ||
cffc9a60 DA |
478 | static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
479 | { | |
480 | unsigned int rst_stat; | |
481 | int ret; | |
482 | ||
483 | if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) | |
484 | return 0; | |
485 | ||
486 | ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); | |
487 | if (ret) | |
488 | dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); | |
489 | else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) | |
490 | return WDIOF_CARDRESET; | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
4f1f653a LKA |
495 | /* s3c2410_get_wdt_driver_data */ |
496 | static inline struct s3c2410_wdt_variant * | |
497 | get_wdt_drv_data(struct platform_device *pdev) | |
498 | { | |
499 | if (pdev->dev.of_node) { | |
500 | const struct of_device_id *match; | |
501 | match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node); | |
502 | return (struct s3c2410_wdt_variant *)match->data; | |
503 | } else { | |
504 | return (struct s3c2410_wdt_variant *) | |
505 | platform_get_device_id(pdev)->driver_data; | |
506 | } | |
507 | } | |
508 | ||
2d991a16 | 509 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 510 | { |
e8ef92b8 | 511 | struct device *dev; |
af4ea631 LKA |
512 | struct s3c2410_wdt *wdt; |
513 | struct resource *wdt_mem; | |
514 | struct resource *wdt_irq; | |
46b814d6 | 515 | unsigned int wtcon; |
1da177e4 LT |
516 | int started = 0; |
517 | int ret; | |
1da177e4 | 518 | |
fa9363c5 | 519 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 520 | |
e8ef92b8 | 521 | dev = &pdev->dev; |
e8ef92b8 | 522 | |
af4ea631 LKA |
523 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
524 | if (!wdt) | |
525 | return -ENOMEM; | |
526 | ||
527 | wdt->dev = &pdev->dev; | |
528 | spin_lock_init(&wdt->lock); | |
529 | wdt->wdt_device = s3c2410_wdd; | |
1da177e4 | 530 | |
4f1f653a | 531 | wdt->drv_data = get_wdt_drv_data(pdev); |
cffc9a60 | 532 | if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
4f1f653a LKA |
533 | wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
534 | "samsung,syscon-phandle"); | |
535 | if (IS_ERR(wdt->pmureg)) { | |
536 | dev_err(dev, "syscon regmap lookup failed.\n"); | |
537 | return PTR_ERR(wdt->pmureg); | |
538 | } | |
539 | } | |
540 | ||
78d3e00b MH |
541 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
542 | if (wdt_irq == NULL) { | |
543 | dev_err(dev, "no irq resource specified\n"); | |
544 | ret = -ENOENT; | |
545 | goto err; | |
546 | } | |
547 | ||
548 | /* get the memory region for the watchdog timer */ | |
bd5cc119 | 549 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
af4ea631 LKA |
550 | wdt->reg_base = devm_ioremap_resource(dev, wdt_mem); |
551 | if (IS_ERR(wdt->reg_base)) { | |
552 | ret = PTR_ERR(wdt->reg_base); | |
04ecc7dc | 553 | goto err; |
1da177e4 LT |
554 | } |
555 | ||
af4ea631 | 556 | DBG("probe: mapped reg_base=%p\n", wdt->reg_base); |
1da177e4 | 557 | |
af4ea631 LKA |
558 | wdt->clock = devm_clk_get(dev, "watchdog"); |
559 | if (IS_ERR(wdt->clock)) { | |
e8ef92b8 | 560 | dev_err(dev, "failed to find watchdog clock source\n"); |
af4ea631 | 561 | ret = PTR_ERR(wdt->clock); |
04ecc7dc | 562 | goto err; |
1da177e4 LT |
563 | } |
564 | ||
01b6af91 SK |
565 | ret = clk_prepare_enable(wdt->clock); |
566 | if (ret < 0) { | |
567 | dev_err(dev, "failed to enable clock\n"); | |
568 | return ret; | |
569 | } | |
1da177e4 | 570 | |
af4ea631 | 571 | ret = s3c2410wdt_cpufreq_register(wdt); |
78d3e00b | 572 | if (ret < 0) { |
3828924a | 573 | dev_err(dev, "failed to register cpufreq\n"); |
e02f838e BD |
574 | goto err_clk; |
575 | } | |
576 | ||
af4ea631 LKA |
577 | watchdog_set_drvdata(&wdt->wdt_device, wdt); |
578 | ||
1da177e4 LT |
579 | /* see if we can actually set the requested timer margin, and if |
580 | * not, try the default value */ | |
581 | ||
af4ea631 LKA |
582 | watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev); |
583 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
584 | wdt->wdt_device.timeout); | |
585 | if (ret) { | |
586 | started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
41dc8b72 | 587 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 588 | |
41dc8b72 AC |
589 | if (started == 0) |
590 | dev_info(dev, | |
591 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 592 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 593 | else |
a77dba7e WVS |
594 | dev_info(dev, "default timer value is out of range, " |
595 | "cannot start\n"); | |
1da177e4 LT |
596 | } |
597 | ||
04ecc7dc JH |
598 | ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
599 | pdev->name, pdev); | |
78d3e00b MH |
600 | if (ret != 0) { |
601 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
602 | goto err_cpufreq; | |
603 | } | |
604 | ||
af4ea631 | 605 | watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
c71f5cd2 | 606 | watchdog_set_restart_priority(&wdt->wdt_device, 128); |
ff0b3cd4 | 607 | |
cffc9a60 | 608 | wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
6551881c | 609 | wdt->wdt_device.parent = &pdev->dev; |
cffc9a60 | 610 | |
af4ea631 | 611 | ret = watchdog_register_device(&wdt->wdt_device); |
1da177e4 | 612 | if (ret) { |
25dc46e3 | 613 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
04ecc7dc | 614 | goto err_cpufreq; |
1da177e4 LT |
615 | } |
616 | ||
4f1f653a LKA |
617 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
618 | if (ret < 0) | |
619 | goto err_unregister; | |
620 | ||
1da177e4 | 621 | if (tmr_atboot && started == 0) { |
e8ef92b8 | 622 | dev_info(dev, "starting watchdog timer\n"); |
af4ea631 | 623 | s3c2410wdt_start(&wdt->wdt_device); |
655516c8 BD |
624 | } else if (!tmr_atboot) { |
625 | /* if we're not enabling the watchdog, then ensure it is | |
626 | * disabled if it has been left running from the bootloader | |
627 | * or other source */ | |
628 | ||
af4ea631 | 629 | s3c2410wdt_stop(&wdt->wdt_device); |
1da177e4 LT |
630 | } |
631 | ||
af4ea631 LKA |
632 | platform_set_drvdata(pdev, wdt); |
633 | ||
46b814d6 BD |
634 | /* print out a statement of readiness */ |
635 | ||
af4ea631 | 636 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
46b814d6 | 637 | |
e8ef92b8 | 638 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 639 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
640 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
641 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 642 | |
1da177e4 | 643 | return 0; |
0b6dd8a6 | 644 | |
4f1f653a LKA |
645 | err_unregister: |
646 | watchdog_unregister_device(&wdt->wdt_device); | |
647 | ||
e02f838e | 648 | err_cpufreq: |
af4ea631 | 649 | s3c2410wdt_cpufreq_deregister(wdt); |
e02f838e | 650 | |
0b6dd8a6 | 651 | err_clk: |
af4ea631 | 652 | clk_disable_unprepare(wdt->clock); |
0b6dd8a6 | 653 | |
78d3e00b | 654 | err: |
0b6dd8a6 | 655 | return ret; |
1da177e4 LT |
656 | } |
657 | ||
4b12b896 | 658 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 659 | { |
4f1f653a | 660 | int ret; |
af4ea631 LKA |
661 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
662 | ||
4f1f653a LKA |
663 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
664 | if (ret < 0) | |
665 | return ret; | |
666 | ||
af4ea631 | 667 | watchdog_unregister_device(&wdt->wdt_device); |
1da177e4 | 668 | |
af4ea631 | 669 | s3c2410wdt_cpufreq_deregister(wdt); |
1da177e4 | 670 | |
af4ea631 | 671 | clk_disable_unprepare(wdt->clock); |
1da177e4 | 672 | |
1da177e4 LT |
673 | return 0; |
674 | } | |
675 | ||
3ae5eaec | 676 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 677 | { |
af4ea631 LKA |
678 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
679 | ||
4f1f653a LKA |
680 | s3c2410wdt_mask_and_disable_reset(wdt, true); |
681 | ||
af4ea631 | 682 | s3c2410wdt_stop(&wdt->wdt_device); |
94f1e9f3 BD |
683 | } |
684 | ||
0183984c | 685 | #ifdef CONFIG_PM_SLEEP |
af4bb822 | 686 | |
0183984c | 687 | static int s3c2410wdt_suspend(struct device *dev) |
af4bb822 | 688 | { |
4f1f653a | 689 | int ret; |
af4ea631 LKA |
690 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
691 | ||
9480e307 | 692 | /* Save watchdog state, and turn it off. */ |
af4ea631 LKA |
693 | wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
694 | wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); | |
af4bb822 | 695 | |
4f1f653a LKA |
696 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
697 | if (ret < 0) | |
698 | return ret; | |
699 | ||
9480e307 | 700 | /* Note that WTCNT doesn't need to be saved. */ |
af4ea631 | 701 | s3c2410wdt_stop(&wdt->wdt_device); |
af4bb822 BD |
702 | |
703 | return 0; | |
704 | } | |
705 | ||
0183984c | 706 | static int s3c2410wdt_resume(struct device *dev) |
af4bb822 | 707 | { |
4f1f653a | 708 | int ret; |
af4ea631 | 709 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
af4bb822 | 710 | |
af4ea631 LKA |
711 | /* Restore watchdog state. */ |
712 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); | |
713 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ | |
714 | writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); | |
af4bb822 | 715 | |
4f1f653a LKA |
716 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
717 | if (ret < 0) | |
718 | return ret; | |
719 | ||
0183984c | 720 | dev_info(dev, "watchdog %sabled\n", |
af4ea631 | 721 | (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
af4bb822 BD |
722 | |
723 | return 0; | |
724 | } | |
0183984c | 725 | #endif |
af4bb822 | 726 | |
0183984c JH |
727 | static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
728 | s3c2410wdt_resume); | |
af4bb822 | 729 | |
3ae5eaec | 730 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 731 | .probe = s3c2410wdt_probe, |
82268714 | 732 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 733 | .shutdown = s3c2410wdt_shutdown, |
4f1f653a | 734 | .id_table = s3c2410_wdt_ids, |
3ae5eaec | 735 | .driver = { |
3ae5eaec | 736 | .name = "s3c2410-wdt", |
0183984c | 737 | .pm = &s3c2410wdt_pm_ops, |
3016a552 | 738 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 739 | }, |
1da177e4 LT |
740 | }; |
741 | ||
6b761b29 | 742 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 743 | |
af4bb822 BD |
744 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
745 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
746 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
747 | MODULE_LICENSE("GPL"); |