[linux-2.6-block.git] / drivers / watchdog / imx2_wdt.c

/*
 * Watchdog driver for IMX2 and later processors
 *
 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * some parts adapted by similar drivers from Darius Augulis and Vladimir
 * Zapolskiy, additional improvements by Wim Van Sebroeck.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 *
 *			MX1:		MX2+:
 *			----		-----
 * Registers:		32-bit		16-bit
 * Stopable timer:	Yes		No
 * Need to enable clk:	No		Yes
 * Halt on suspend:	Manual		Can be automatic
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/timer.h>
#include <linux/watchdog.h>

#define DRIVER_NAME "imx2-wdt"

#define IMX2_WDT_WCR		0x00		/* Control Register */
#define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WRE	(1 << 3)	/* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE	(1 << 2)	/* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST	(1 << 0)	/* -> Watchdog timer Suspend */

#define IMX2_WDT_WSR		0x02		/* Service Register */
#define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
#define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */

#define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT	(1 << 1)	/* -> Reset due to Timeout */

#define IMX2_WDT_WMCR		0x08		/* Misc Register */

#define IMX2_WDT_MAX_TIME	128
#define IMX2_WDT_DEFAULT_TIME	60		/* in seconds */

#define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)

struct imx2_wdt_device {
	struct clk *clk;
	struct regmap *regmap;
	struct timer_list timer;	/* Pings the watchdog when closed */
	struct watchdog_device wdog;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");


static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
				__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");

static const struct watchdog_info imx2_wdt_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};

static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
			    void *data)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;

	/* Assert SRS signal */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	/*
	 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	 * written twice), we add another two writes to ensure there must be at
	 * least two writes happen in the same one 32kHz clock period.  We save
	 * the target check here, since the writes shouldn't be a huge burden
	 * for other platforms.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);

	/* wait for reset to assert... */
	mdelay(500);

	return 0;
}

static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	/* Suspend timer in low power mode, write once-only */
	val |= IMX2_WDT_WCR_WDZST;
	/* Strip the old watchdog Time-Out value */
	val &= ~IMX2_WDT_WCR_WT;
	/* Generate reset if WDOG times out */
	val &= ~IMX2_WDT_WCR_WRE;
	/* Keep Watchdog Disabled */
	val &= ~IMX2_WDT_WCR_WDE;
	/* Set the watchdog's Time-Out value */
	val |= WDOG_SEC_TO_COUNT(wdog->timeout);

	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);

	/* enable the watchdog */
	val |= IMX2_WDT_WCR_WDE;
	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}

static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	return val & IMX2_WDT_WCR_WDE;
}

static int imx2_wdt_ping(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	return 0;
}

static void imx2_wdt_timer_ping(unsigned long arg)
{
	struct watchdog_device *wdog = (struct watchdog_device *)arg;
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	imx2_wdt_ping(wdog);
	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
}

static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int new_timeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	wdog->timeout = new_timeout;

	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
			   WDOG_SEC_TO_COUNT(new_timeout));
	return 0;
}

static int imx2_wdt_start(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/* delete the timer that pings the watchdog after close */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
	} else
		imx2_wdt_setup(wdog);

	return imx2_wdt_ping(wdog);
}

static int imx2_wdt_stop(struct watchdog_device *wdog)
{
	/*
	 * We don't need a clk_disable, it cannot be disabled once started.
	 * We use a timer to ping the watchdog while /dev/watchdog is closed
	 */
	imx2_wdt_timer_ping((unsigned long)wdog);
	return 0;
}

static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_timer_ping((unsigned long)wdog);
	}
}

static const struct watchdog_ops imx2_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx2_wdt_start,
	.stop = imx2_wdt_stop,
	.ping = imx2_wdt_ping,
	.set_timeout = imx2_wdt_set_timeout,
	.restart = imx2_wdt_restart,
};

static const struct regmap_config imx2_wdt_regmap_config = {
	.reg_bits = 16,
	.reg_stride = 2,
	.val_bits = 16,
	.max_register = 0x8,
};

static int __init imx2_wdt_probe(struct platform_device *pdev)
{
	struct imx2_wdt_device *wdev;
	struct watchdog_device *wdog;
	struct resource *res;
	void __iomem *base;
	int ret;
	u32 val;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
						 &imx2_wdt_regmap_config);
	if (IS_ERR(wdev->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(wdev->regmap);
	}

	wdev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdev->clk)) {
		dev_err(&pdev->dev, "can't get Watchdog clock\n");
		return PTR_ERR(wdev->clk);
	}

	wdog			= &wdev->wdog;
	wdog->info		= &imx2_wdt_info;
	wdog->ops		= &imx2_wdt_ops;
	wdog->min_timeout	= 1;
	wdog->max_timeout	= IMX2_WDT_MAX_TIME;
	wdog->parent		= &pdev->dev;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;

	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	if (wdog->timeout != timeout)
		dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
			 timeout, wdog->timeout);

	platform_set_drvdata(pdev, wdog);
	watchdog_set_drvdata(wdog, wdev);
	watchdog_set_nowayout(wdog, nowayout);
	watchdog_set_restart_priority(wdog, 128);
	watchdog_init_timeout(wdog, timeout, &pdev->dev);

	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);

	imx2_wdt_ping_if_active(wdog);

	/*
	 * Disable the watchdog power down counter at boot. Otherwise the power
	 * down counter will pull down the #WDOG interrupt line for one clock
	 * cycle.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);

	ret = watchdog_register_device(wdog);
	if (ret) {
		dev_err(&pdev->dev, "cannot register watchdog device\n");
		goto disable_clk;
	}

	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
		 wdog->timeout, nowayout);

	return 0;

disable_clk:
	clk_disable_unprepare(wdev->clk);
	return ret;
}

static int __exit imx2_wdt_remove(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	watchdog_unregister_device(wdog);

	if (imx2_wdt_is_running(wdev)) {
		del_timer_sync(&wdev->timer);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
	}
	return 0;
}

static void imx2_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/*
		 * We are running, we need to delete the timer but will
		 * give max timeout before reboot will take place
		 */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
	}
}

#ifdef CONFIG_PM_SLEEP
/* Disable watchdog if it is active or non-active but still running */
static int imx2_wdt_suspend(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* The watchdog IP block is running */
	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);

		/* The watchdog is not active */
		if (!watchdog_active(wdog))
			del_timer_sync(&wdev->timer);
	}

	clk_disable_unprepare(wdev->clk);

	return 0;
}

/* Enable watchdog and configure it if necessary */
static int imx2_wdt_resume(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	int ret;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
		/*
		 * If the watchdog is still active and resumes
		 * from deep sleep state, need to restart the
		 * watchdog again.
		 */
		imx2_wdt_setup(wdog);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
	} else if (imx2_wdt_is_running(wdev)) {
		/* Resuming from non-deep sleep state. */
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
		/*
		 * But the watchdog is not active, then start
		 * the timer again.
		 */
		if (!watchdog_active(wdog))
			mod_timer(&wdev->timer,
				  jiffies + wdog->timeout * HZ / 2);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
			 imx2_wdt_resume);

static const struct of_device_id imx2_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx21-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);

static struct platform_driver imx2_wdt_driver = {
	.remove		= __exit_p(imx2_wdt_remove),
	.shutdown	= imx2_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.pm     = &imx2_wdt_pm_ops,
		.of_match_table = imx2_wdt_dt_ids,
	},
};

module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);

MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
bb2fd8a8 WS	1	/*
	2	* Watchdog driver for IMX2 and later processors
	3	*
	4	* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
1a9c5efa	5	* Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8 WS	6	*
	7	* some parts adapted by similar drivers from Darius Augulis and Vladimir
	8	* Zapolskiy, additional improvements by Wim Van Sebroeck.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
	15	*
	16	* MX1: MX2+:
	17	* ---- -----
	18	* Registers: 32-bit 16-bit
	19	* Stopable timer: Yes No
	20	* Need to enable clk: No Yes
	21	* Halt on suspend: Manual Can be automatic
	22	*/
	23
30cb042a	24	#include <linux/clk.h>
334a9d81	25	#include <linux/delay.h>
bb2fd8a8	26	#include <linux/init.h>
30cb042a XL	27	#include <linux/io.h>
30cb042a XL	28	#include <linux/jiffies.h>
bb2fd8a8	29	#include <linux/kernel.h>
bb2fd8a8 WS	30	#include <linux/module.h>
bb2fd8a8 WS	31	#include <linux/moduleparam.h>
f728f4bf	32	#include <linux/of_address.h>
bb2fd8a8	33	#include <linux/platform_device.h>
a7977003	34	#include <linux/regmap.h>
bb2fd8a8	35	#include <linux/timer.h>
30cb042a	36	#include <linux/watchdog.h>
bb2fd8a8 WS	37
	38	#define DRIVER_NAME "imx2-wdt"
	39
	40	#define IMX2_WDT_WCR 0x00 /* Control Register */
	41	#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
	42	#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
	43	#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
1a9c5efa	44	#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
bb2fd8a8 WS	45
	46	#define IMX2_WDT_WSR 0x02 /* Service Register */
	47	#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
	48	#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
	49
474ef121 OS	50	#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
	51	#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
	52
5fe65ce7 MP	53	#define IMX2_WDT_WMCR 0x08 /* Misc Register */
5fe65ce7 MP	54
bb2fd8a8 WS	55	#define IMX2_WDT_MAX_TIME 128
	56	#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
	57
	58	#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
	59
faad5de0	60	struct imx2_wdt_device {
bb2fd8a8	61	struct clk *clk;
a7977003	62	struct regmap *regmap;
bb2fd8a8	63	struct timer_list timer; /* Pings the watchdog when closed */
faad5de0 AG	64	struct watchdog_device wdog;
faad5de0 AG	65	};
bb2fd8a8	66
86a1e189 WVS	67	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	68	module_param(nowayout, bool, 0);
bb2fd8a8 WS	69	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	70	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	71
	72
	73	static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
	74	module_param(timeout, uint, 0);
	75	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
	76	__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
	77
	78	static const struct watchdog_info imx2_wdt_info = {
	79	.identity = "imx2+ watchdog",
	80	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE,
	81	};
	82
4d8b229d GR	83	static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
4d8b229d GR	84	void *data)
334a9d81	85	{
2d9d2475	86	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
334a9d81	87	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
2d9d2475	88
334a9d81	89	/* Assert SRS signal */
9493c0d8	90	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	91	/*
	92	* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	93	* written twice), we add another two writes to ensure there must be at
	94	* least two writes happen in the same one 32kHz clock period. We save
	95	* the target check here, since the writes shouldn't be a huge burden
	96	* for other platforms.
	97	*/
9493c0d8 FE	98	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
9493c0d8 FE	99	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	100
	101	/* wait for reset to assert... */
	102	mdelay(500);
	103
2d9d2475	104	return 0;
334a9d81 JL	105	}
334a9d81 JL	106
faad5de0	107	static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8	108	{
faad5de0	109	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003 XL	110	u32 val;
a7977003 XL	111
faad5de0	112	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8	113
1a9c5efa AH	114	/* Suspend timer in low power mode, write once-only */
1a9c5efa AH	115	val \|= IMX2_WDT_WCR_WDZST;
bb2fd8a8 WS	116	/* Strip the old watchdog Time-Out value */
	117	val &= ~IMX2_WDT_WCR_WT;
	118	/* Generate reset if WDOG times out */
	119	val &= ~IMX2_WDT_WCR_WRE;
	120	/* Keep Watchdog Disabled */
	121	val &= ~IMX2_WDT_WCR_WDE;
	122	/* Set the watchdog's Time-Out value */
faad5de0	123	val \|= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8	124
faad5de0	125	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	126
	127	/* enable the watchdog */
	128	val \|= IMX2_WDT_WCR_WDE;
faad5de0	129	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	130	}
bb2fd8a8 WS	131
faad5de0	132	static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8	133	{
faad5de0	134	u32 val;
bb2fd8a8	135
faad5de0 AG	136	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
	137
	138	return val & IMX2_WDT_WCR_WDE;
bb2fd8a8 WS	139	}
bb2fd8a8 WS	140
faad5de0	141	static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8	142	{
faad5de0	143	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	144
faad5de0 AG	145	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	146	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	147	return 0;
bb2fd8a8 WS	148	}
bb2fd8a8 WS	149
faad5de0	150	static void imx2_wdt_timer_ping(unsigned long arg)
bb2fd8a8	151	{
faad5de0 AG	152	struct watchdog_device wdog = (struct watchdog_device )arg;
	153	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	154
	155	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	156	imx2_wdt_ping(wdog);
	157	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
bb2fd8a8 WS	158	}
bb2fd8a8 WS	159
faad5de0 AG	160	static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
faad5de0 AG	161	unsigned int new_timeout)
bb2fd8a8	162	{
faad5de0 AG	163	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
faad5de0 AG	164
30dd4a8f MG	165	wdog->timeout = new_timeout;
30dd4a8f MG	166
faad5de0	167	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003	168	WDOG_SEC_TO_COUNT(new_timeout));
faad5de0	169	return 0;
bb2fd8a8 WS	170	}
bb2fd8a8 WS	171
faad5de0	172	static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8	173	{
faad5de0	174	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	175
faad5de0 AG	176	if (imx2_wdt_is_running(wdev)) {
	177	/* delete the timer that pings the watchdog after close */
	178	del_timer_sync(&wdev->timer);
	179	imx2_wdt_set_timeout(wdog, wdog->timeout);
	180	} else
	181	imx2_wdt_setup(wdog);
	182
	183	return imx2_wdt_ping(wdog);
bb2fd8a8 WS	184	}
bb2fd8a8 WS	185
faad5de0	186	static int imx2_wdt_stop(struct watchdog_device *wdog)
bb2fd8a8	187	{
faad5de0 AG	188	/*
	189	* We don't need a clk_disable, it cannot be disabled once started.
	190	* We use a timer to ping the watchdog while /dev/watchdog is closed
	191	*/
	192	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	193	return 0;
	194	}
	195
faad5de0	196	static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
bb2fd8a8	197	{
faad5de0	198	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	199
faad5de0 AG	200	if (imx2_wdt_is_running(wdev)) {
	201	imx2_wdt_set_timeout(wdog, wdog->timeout);
	202	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	203	}
	204	}
	205
4bd8ce33	206	static const struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8	207	.owner = THIS_MODULE,
faad5de0 AG	208	.start = imx2_wdt_start,
	209	.stop = imx2_wdt_stop,
	210	.ping = imx2_wdt_ping,
	211	.set_timeout = imx2_wdt_set_timeout,
2d9d2475	212	.restart = imx2_wdt_restart,
bb2fd8a8 WS	213	};
bb2fd8a8 WS	214
4bd8ce33	215	static const struct regmap_config imx2_wdt_regmap_config = {
a7977003 XL	216	.reg_bits = 16,
	217	.reg_stride = 2,
	218	.val_bits = 16,
	219	.max_register = 0x8,
	220	};
	221
bb2fd8a8 WS	222	static int __init imx2_wdt_probe(struct platform_device *pdev)
bb2fd8a8 WS	223	{
faad5de0 AG	224	struct imx2_wdt_device *wdev;
faad5de0 AG	225	struct watchdog_device *wdog;
bb2fd8a8	226	struct resource *res;
a7977003 XL	227	void __iomem *base;
a7977003 XL	228	int ret;
faad5de0 AG	229	u32 val;
	230
	231	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	232	if (!wdev)
	233	return -ENOMEM;
bb2fd8a8 WS	234
bb2fd8a8 WS	235	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a7977003 XL	236	base = devm_ioremap_resource(&pdev->dev, res);
	237	if (IS_ERR(base))
	238	return PTR_ERR(base);
	239
faad5de0 AG	240	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
	241	&imx2_wdt_regmap_config);
	242	if (IS_ERR(wdev->regmap)) {
a7977003	243	dev_err(&pdev->dev, "regmap init failed\n");
faad5de0	244	return PTR_ERR(wdev->regmap);
a7977003	245	}
bb2fd8a8	246
faad5de0 AG	247	wdev->clk = devm_clk_get(&pdev->dev, NULL);
faad5de0 AG	248	if (IS_ERR(wdev->clk)) {
bb2fd8a8	249	dev_err(&pdev->dev, "can't get Watchdog clock\n");
faad5de0	250	return PTR_ERR(wdev->clk);
bb2fd8a8 WS	251	}
bb2fd8a8 WS	252
faad5de0 AG	253	wdog = &wdev->wdog;
	254	wdog->info = &imx2_wdt_info;
	255	wdog->ops = &imx2_wdt_ops;
	256	wdog->min_timeout = 1;
	257	wdog->max_timeout = IMX2_WDT_MAX_TIME;
8135193c	258	wdog->parent = &pdev->dev;
bb2fd8a8	259
aefb163c FE	260	ret = clk_prepare_enable(wdev->clk);
	261	if (ret)
	262	return ret;
bb2fd8a8	263
faad5de0 AG	264	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
faad5de0 AG	265	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8	266
faad5de0 AG	267	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	268	if (wdog->timeout != timeout)
	269	dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
	270	timeout, wdog->timeout);
	271
	272	platform_set_drvdata(pdev, wdog);
	273	watchdog_set_drvdata(wdog, wdev);
	274	watchdog_set_nowayout(wdog, nowayout);
2d9d2475	275	watchdog_set_restart_priority(wdog, 128);
faad5de0 AG	276	watchdog_init_timeout(wdog, timeout, &pdev->dev);
	277
	278	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
bb2fd8a8	279
faad5de0 AG	280	imx2_wdt_ping_if_active(wdog);
faad5de0 AG	281
5fe65ce7 MP	282	/*
	283	* Disable the watchdog power down counter at boot. Otherwise the power
	284	* down counter will pull down the #WDOG interrupt line for one clock
	285	* cycle.
	286	*/
	287	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
	288
faad5de0 AG	289	ret = watchdog_register_device(wdog);
	290	if (ret) {
	291	dev_err(&pdev->dev, "cannot register watchdog device\n");
db11cba2	292	goto disable_clk;
faad5de0 AG	293	}
	294
	295	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
	296	wdog->timeout, nowayout);
	297
	298	return 0;
db11cba2 FE	299
	300	disable_clk:
	301	clk_disable_unprepare(wdev->clk);
	302	return ret;
bb2fd8a8 WS	303	}
	304
	305	static int __exit imx2_wdt_remove(struct platform_device *pdev)
	306	{
faad5de0 AG	307	struct watchdog_device *wdog = platform_get_drvdata(pdev);
faad5de0 AG	308	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	309
faad5de0	310	watchdog_unregister_device(wdog);
bb2fd8a8	311
faad5de0 AG	312	if (imx2_wdt_is_running(wdev)) {
	313	del_timer_sync(&wdev->timer);
	314	imx2_wdt_ping(wdog);
	315	dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
bdf49574	316	}
bb2fd8a8 WS	317	return 0;
	318	}
	319
	320	static void imx2_wdt_shutdown(struct platform_device *pdev)
	321	{
faad5de0 AG	322	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	323	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	324
	325	if (imx2_wdt_is_running(wdev)) {
	326	/*
	327	* We are running, we need to delete the timer but will
	328	* give max timeout before reboot will take place
	329	*/
	330	del_timer_sync(&wdev->timer);
	331	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	332	imx2_wdt_ping(wdog);
	333	dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8 WS	334	}
	335	}
	336
aefbaf3a	337	#ifdef CONFIG_PM_SLEEP
bbd59009	338	/* Disable watchdog if it is active or non-active but still running */
aefbaf3a XL	339	static int imx2_wdt_suspend(struct device *dev)
	340	{
	341	struct watchdog_device *wdog = dev_get_drvdata(dev);
	342	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	343
bbd59009 XL	344	/* The watchdog IP block is running */
	345	if (imx2_wdt_is_running(wdev)) {
	346	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	347	imx2_wdt_ping(wdog);
aefbaf3a	348
bbd59009 XL	349	/* The watchdog is not active */
	350	if (!watchdog_active(wdog))
	351	del_timer_sync(&wdev->timer);
	352	}
aefbaf3a XL	353
	354	clk_disable_unprepare(wdev->clk);
	355
	356	return 0;
	357	}
	358
	359	/* Enable watchdog and configure it if necessary */
	360	static int imx2_wdt_resume(struct device *dev)
	361	{
	362	struct watchdog_device *wdog = dev_get_drvdata(dev);
	363	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
aefb163c	364	int ret;
aefbaf3a	365
aefb163c FE	366	ret = clk_prepare_enable(wdev->clk);
	367	if (ret)
	368	return ret;
aefbaf3a XL	369
aefbaf3a XL	370	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
bbd59009 XL	371	/*
	372	* If the watchdog is still active and resumes
	373	* from deep sleep state, need to restart the
	374	* watchdog again.
aefbaf3a XL	375	*/
	376	imx2_wdt_setup(wdog);
	377	imx2_wdt_set_timeout(wdog, wdog->timeout);
	378	imx2_wdt_ping(wdog);
	379	} else if (imx2_wdt_is_running(wdev)) {
bbd59009 XL	380	/* Resuming from non-deep sleep state. */
bbd59009 XL	381	imx2_wdt_set_timeout(wdog, wdog->timeout);
aefbaf3a	382	imx2_wdt_ping(wdog);
bbd59009 XL	383	/*
	384	* But the watchdog is not active, then start
	385	* the timer again.
	386	*/
	387	if (!watchdog_active(wdog))
	388	mod_timer(&wdev->timer,
	389	jiffies + wdog->timeout * HZ / 2);
aefbaf3a XL	390	}
	391
	392	return 0;
	393	}
	394	#endif
	395
	396	static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
	397	imx2_wdt_resume);
	398
f5a427ee SG	399	static const struct of_device_id imx2_wdt_dt_ids[] = {
	400	{ .compatible = "fsl,imx21-wdt", },
	401	{ /* sentinel */ }
	402	};
813296a1	403	MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee	404
bb2fd8a8	405	static struct platform_driver imx2_wdt_driver = {
bb2fd8a8 WS	406	.remove = __exit_p(imx2_wdt_remove),
	407	.shutdown = imx2_wdt_shutdown,
	408	.driver = {
	409	.name = DRIVER_NAME,
aefbaf3a	410	.pm = &imx2_wdt_pm_ops,
f5a427ee	411	.of_match_table = imx2_wdt_dt_ids,
bb2fd8a8 WS	412	},
	413	};
	414
1cb9204c	415	module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
bb2fd8a8 WS	416
	417	MODULE_AUTHOR("Wolfram Sang");
	418	MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
	419	MODULE_LICENSE("GPL v2");
bb2fd8a8	420	MODULE_ALIAS("platform:" DRIVER_NAME);