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[ARM] pxafb: cleanup of the color format manipulation code
[linux-2.6-block.git] / drivers / video / pxafb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/errno.h>
30#include <linux/string.h>
31#include <linux/interrupt.h>
32#include <linux/slab.h>
27ac792c 33#include <linux/mm.h>
1da177e4
LT		 34#include <linux/fb.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/ioport.h>
38#include <linux/cpufreq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4 40#include <linux/dma-mapping.h>
72e3524c
RK		 41#include <linux/clk.h>
42#include <linux/err.h>
2ba162b9 43#include <linux/completion.h>
b91dbce5 44#include <linux/mutex.h>
3c42a449
EM		 45#include <linux/kthread.h>
46#include <linux/freezer.h>
1da177e4 47
a09e64fb 48#include <mach/hardware.h>
1da177e4
LT		 49#include <asm/io.h>
50#include <asm/irq.h>
bf1b8ab6 51#include <asm/div64.h>
a09e64fb 52#include <mach/pxa-regs.h>
a09e64fb
RK		 53#include <mach/bitfield.h>
54#include <mach/pxafb.h>
1da177e4
LT		 55
56/*
57 * Complain if VAR is out of range.
58 */
59#define DEBUG_VAR 1
60
61#include "pxafb.h"
62
63/* Bits which should not be set in machine configuration structures */
b0086efb 64#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
67
68#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
878f5783 69 LCCR3_PCD | LCCR3_BPP(0xf))
1da177e4 70
b0086efb 71static int pxafb_activate_var(struct fb_var_screeninfo *var,
72 struct pxafb_info *);
1da177e4 73static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
6e354846 74static void setup_base_frame(struct pxafb_info *fbi, int branch);
1da177e4 75
77e19675
EM		 76static unsigned long video_mem_size = 0;
77
a7535ba7
EM		 78static inline unsigned long
79lcd_readl(struct pxafb_info *fbi, unsigned int off)
80{
81 return __raw_readl(fbi->mmio_base + off);
82}
83
84static inline void
85lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
86{
87 __raw_writel(val, fbi->mmio_base + off);
88}
89
1da177e4
LT		 90static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
91{
92 unsigned long flags;
93
94 local_irq_save(flags);
95 /*
96 * We need to handle two requests being made at the same time.
97 * There are two important cases:
b0086efb 98 * 1. When we are changing VT (C_REENABLE) while unblanking
99 * (C_ENABLE) We must perform the unblanking, which will
100 * do our REENABLE for us.
101 * 2. When we are blanking, but immediately unblank before
102 * we have blanked. We do the "REENABLE" thing here as
103 * well, just to be sure.
1da177e4
LT		 104 */
105 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
106 state = (u_int) -1;
107 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
108 state = C_REENABLE;
109
110 if (state != (u_int)-1) {
111 fbi->task_state = state;
112 schedule_work(&fbi->task);
113 }
114 local_irq_restore(flags);
115}
116
117static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
118{
119 chan &= 0xffff;
120 chan >>= 16 - bf->length;
121 return chan << bf->offset;
122}
123
124static int
125pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
126 u_int trans, struct fb_info *info)
127{
128 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 129 u_int val;
130
131 if (regno >= fbi->palette_size)
132 return 1;
133
134 if (fbi->fb.var.grayscale) {
135 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
136 return 0;
137 }
138
139 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
140 case LCCR4_PAL_FOR_0:
141 val = ((red >> 0) & 0xf800);
142 val |= ((green >> 5) & 0x07e0);
143 val |= ((blue >> 11) & 0x001f);
1da177e4 144 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 145 break;
146 case LCCR4_PAL_FOR_1:
147 val = ((red << 8) & 0x00f80000);
148 val |= ((green >> 0) & 0x0000fc00);
149 val |= ((blue >> 8) & 0x000000f8);
b0086efb 150 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 151 break;
152 case LCCR4_PAL_FOR_2:
153 val = ((red << 8) & 0x00fc0000);
154 val |= ((green >> 0) & 0x0000fc00);
155 val |= ((blue >> 8) & 0x000000fc);
b0086efb 156 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 157 break;
a0427509
EM		 158 case LCCR4_PAL_FOR_3:
159 val = ((red << 8) & 0x00ff0000);
160 val |= ((green >> 0) & 0x0000ff00);
161 val |= ((blue >> 8) & 0x000000ff);
162 ((u32 *)(fbi->palette_cpu))[regno] = val;
163 break;
1da177e4 164 }
9ffa7396
HK		 165
166 return 0;
1da177e4
LT		 167}
168
169static int
170pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
171 u_int trans, struct fb_info *info)
172{
173 struct pxafb_info *fbi = (struct pxafb_info *)info;
174 unsigned int val;
175 int ret = 1;
176
177 /*
178 * If inverse mode was selected, invert all the colours
179 * rather than the register number. The register number
180 * is what you poke into the framebuffer to produce the
181 * colour you requested.
182 */
183 if (fbi->cmap_inverse) {
184 red = 0xffff - red;
185 green = 0xffff - green;
186 blue = 0xffff - blue;
187 }
188
189 /*
190 * If greyscale is true, then we convert the RGB value
191 * to greyscale no matter what visual we are using.
192 */
193 if (fbi->fb.var.grayscale)
194 red = green = blue = (19595 * red + 38470 * green +
195 7471 * blue) >> 16;
196
197 switch (fbi->fb.fix.visual) {
198 case FB_VISUAL_TRUECOLOR:
199 /*
200 * 16-bit True Colour. We encode the RGB value
201 * according to the RGB bitfield information.
202 */
203 if (regno < 16) {
204 u32 *pal = fbi->fb.pseudo_palette;
205
206 val = chan_to_field(red, &fbi->fb.var.red);
207 val |= chan_to_field(green, &fbi->fb.var.green);
208 val |= chan_to_field(blue, &fbi->fb.var.blue);
209
210 pal[regno] = val;
211 ret = 0;
212 }
213 break;
214
215 case FB_VISUAL_STATIC_PSEUDOCOLOR:
216 case FB_VISUAL_PSEUDOCOLOR:
217 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
218 break;
219 }
220
221 return ret;
222}
223
878f5783
EM		 224/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
225static inline int var_to_depth(struct fb_var_screeninfo *var)
1da177e4 226{
878f5783
EM		 227 return var->red.length + var->green.length +
228 var->blue.length + var->transp.length;
229}
230
231/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
232static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
233{
234 int bpp = -EINVAL;
235
b0086efb 236 switch (var->bits_per_pixel) {
878f5783
EM		 237 case 1: bpp = 0; break;
238 case 2: bpp = 1; break;
239 case 4: bpp = 2; break;
240 case 8: bpp = 3; break;
241 case 16: bpp = 4; break;
c1450f15 242 case 24:
878f5783
EM		 243 switch (var_to_depth(var)) {
244 case 18: bpp = 6; break; /* 18-bits/pixel packed */
245 case 19: bpp = 8; break; /* 19-bits/pixel packed */
246 case 24: bpp = 9; break;
c1450f15
SS		 247 }
248 break;
249 case 32:
878f5783
EM		 250 switch (var_to_depth(var)) {
251 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
252 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
253 case 25: bpp = 10; break;
c1450f15
SS		 254 }
255 break;
b0086efb 256 }
878f5783
EM		 257 return bpp;
258}
259
260/*
261 * pxafb_var_to_lccr3():
262 * Convert a bits per pixel value to the correct bit pattern for LCCR3
263 *
264 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
265 * implication of the acutal use of transparency bit, which we handle it
266 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
267 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
268 *
269 * Transparency for palette pixel formats is not supported at the moment.
270 */
271static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
272{
273 int bpp = pxafb_var_to_bpp(var);
274 uint32_t lccr3;
275
276 if (bpp < 0)
277 return 0;
278
279 lccr3 = LCCR3_BPP(bpp);
280
281 switch (var_to_depth(var)) {
282 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
283 case 18: lccr3 |= LCCR3_PDFOR_3; break;
284 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
285 break;
286 case 19:
287 case 25: lccr3 |= LCCR3_PDFOR_0; break;
288 }
289 return lccr3;
290}
291
292#define SET_PIXFMT(v, r, g, b, t) \
293({ \
294 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
295 (v)->transp.length = (t) ? (t) : 0; \
296 (v)->blue.length = (b); (v)->blue.offset = 0; \
297 (v)->green.length = (g); (v)->green.offset = (b); \
298 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
299})
300
301/* set the RGBT bitfields of fb_var_screeninf according to
302 * var->bits_per_pixel and given depth
303 */
304static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
305{
306 if (depth == 0)
307 depth = var->bits_per_pixel;
308
309 if (var->bits_per_pixel < 16) {
310 /* indexed pixel formats */
311 var->red.offset = 0; var->red.length = 8;
312 var->green.offset = 0; var->green.length = 8;
313 var->blue.offset = 0; var->blue.length = 8;
314 var->transp.offset = 0; var->transp.length = 8;
315 }
316
317 switch (depth) {
318 case 16: var->transp.length ?
319 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
320 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
321 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
322 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
323 case 24: var->transp.length ?
324 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
325 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
326 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
327 }
1da177e4
LT		 328}
329
330#ifdef CONFIG_CPU_FREQ
331/*
332 * pxafb_display_dma_period()
333 * Calculate the minimum period (in picoseconds) between two DMA
334 * requests for the LCD controller. If we hit this, it means we're
335 * doing nothing but LCD DMA.
336 */
337static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
338{
b0086efb 339 /*
340 * Period = pixclock * bits_per_byte * bytes_per_transfer
341 * / memory_bits_per_pixel;
342 */
343 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 344}
1da177e4
LT		 345#endif
346
d14b272b
RP		 347/*
348 * Select the smallest mode that allows the desired resolution to be
349 * displayed. If desired parameters can be rounded up.
350 */
b0086efb 351static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
352 struct fb_var_screeninfo *var)
d14b272b
RP		 353{
354 struct pxafb_mode_info *mode = NULL;
355 struct pxafb_mode_info *modelist = mach->modes;
356 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
357 unsigned int i;
358
b0086efb 359 for (i = 0; i < mach->num_modes; i++) {
360 if (modelist[i].xres >= var->xres &&
361 modelist[i].yres >= var->yres &&
362 modelist[i].xres < best_x &&
363 modelist[i].yres < best_y &&
364 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 365 best_x = modelist[i].xres;
366 best_y = modelist[i].yres;
367 mode = &modelist[i];
368 }
369 }
370
371 return mode;
372}
373
b0086efb 374static void pxafb_setmode(struct fb_var_screeninfo *var,
375 struct pxafb_mode_info *mode)
d14b272b
RP		 376{
377 var->xres = mode->xres;
378 var->yres = mode->yres;
379 var->bits_per_pixel = mode->bpp;
380 var->pixclock = mode->pixclock;
381 var->hsync_len = mode->hsync_len;
382 var->left_margin = mode->left_margin;
383 var->right_margin = mode->right_margin;
384 var->vsync_len = mode->vsync_len;
385 var->upper_margin = mode->upper_margin;
386 var->lower_margin = mode->lower_margin;
387 var->sync = mode->sync;
388 var->grayscale = mode->cmap_greyscale;
878f5783
EM		 389
390 /* set the initial RGBA bitfields */
391 pxafb_set_pixfmt(var, mode->depth);
d14b272b
RP		 392}
393
1da177e4
LT		 394/*
395 * pxafb_check_var():
396 * Get the video params out of 'var'. If a value doesn't fit, round it up,
397 * if it's too big, return -EINVAL.
398 *
399 * Round up in the following order: bits_per_pixel, xres,
400 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
401 * bitfields, horizontal timing, vertical timing.
402 */
403static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
404{
405 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 406 struct pxafb_mach_info *inf = fbi->dev->platform_data;
878f5783 407 int err;
1da177e4
LT		 408
409 if (var->xres < MIN_XRES)
410 var->xres = MIN_XRES;
411 if (var->yres < MIN_YRES)
412 var->yres = MIN_YRES;
d14b272b
RP		 413
414 if (inf->fixed_modes) {
415 struct pxafb_mode_info *mode;
416
417 mode = pxafb_getmode(inf, var);
418 if (!mode)
419 return -EINVAL;
420 pxafb_setmode(var, mode);
421 } else {
422 if (var->xres > inf->modes->xres)
423 return -EINVAL;
424 if (var->yres > inf->modes->yres)
425 return -EINVAL;
426 if (var->bits_per_pixel > inf->modes->bpp)
427 return -EINVAL;
428 }
429
7e4b19c9
EM		 430 /* we don't support xpan, force xres_virtual to be equal to xres */
431 var->xres_virtual = var->xres;
432
433 if (var->accel_flags & FB_ACCELF_TEXT)
434 var->yres_virtual = fbi->fb.fix.smem_len /
435 (var->xres_virtual * var->bits_per_pixel / 8);
436 else
437 var->yres_virtual = max(var->yres_virtual, var->yres);
1da177e4 438
878f5783
EM		 439 /* do a test conversion to BPP fields to check the color formats */
440 err = pxafb_var_to_bpp(var);
441 if (err < 0)
442 return err;
c1450f15 443
878f5783 444 pxafb_set_pixfmt(var, var_to_depth(var));
1da177e4
LT		 445
446#ifdef CONFIG_CPU_FREQ
78d3cfd3
RK		 447 pr_debug("pxafb: dma period = %d ps\n",
448 pxafb_display_dma_period(var));
1da177e4
LT		 449#endif
450
451 return 0;
452}
453
1da177e4
LT		 454/*
455 * pxafb_set_par():
456 * Set the user defined part of the display for the specified console
457 */
458static int pxafb_set_par(struct fb_info *info)
459{
460 struct pxafb_info *fbi = (struct pxafb_info *)info;
461 struct fb_var_screeninfo *var = &info->var;
1da177e4 462
c1450f15 463 if (var->bits_per_pixel >= 16)
1da177e4
LT		 464 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
465 else if (!fbi->cmap_static)
466 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
467 else {
468 /*
469 * Some people have weird ideas about wanting static
470 * pseudocolor maps. I suspect their user space
471 * applications are broken.
472 */
473 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
474 }
475
476 fbi->fb.fix.line_length = var->xres_virtual *
477 var->bits_per_pixel / 8;
c1450f15 478 if (var->bits_per_pixel >= 16)
1da177e4
LT		 479 fbi->palette_size = 0;
480 else
b0086efb 481 fbi->palette_size = var->bits_per_pixel == 1 ?
482 4 : 1 << var->bits_per_pixel;
1da177e4 483
2c42dd8e 484 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4 485
c1450f15 486 if (fbi->fb.var.bits_per_pixel >= 16)
1da177e4
LT		 487 fb_dealloc_cmap(&fbi->fb.cmap);
488 else
489 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
490
491 pxafb_activate_var(var, fbi);
492
493 return 0;
494}
495
6e354846
EM		 496static int pxafb_pan_display(struct fb_var_screeninfo *var,
497 struct fb_info *info)
498{
499 struct pxafb_info *fbi = (struct pxafb_info *)info;
500 int dma = DMA_MAX + DMA_BASE;
501
502 if (fbi->state != C_ENABLE)
503 return 0;
504
505 setup_base_frame(fbi, 1);
506
507 if (fbi->lccr0 & LCCR0_SDS)
508 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
509
510 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
511 return 0;
512}
513
1da177e4
LT		 514/*
515 * pxafb_blank():
516 * Blank the display by setting all palette values to zero. Note, the
517 * 16 bpp mode does not really use the palette, so this will not
518 * blank the display in all modes.
519 */
520static int pxafb_blank(int blank, struct fb_info *info)
521{
522 struct pxafb_info *fbi = (struct pxafb_info *)info;
523 int i;
524
1da177e4
LT		 525 switch (blank) {
526 case FB_BLANK_POWERDOWN:
527 case FB_BLANK_VSYNC_SUSPEND:
528 case FB_BLANK_HSYNC_SUSPEND:
529 case FB_BLANK_NORMAL:
530 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
531 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
532 for (i = 0; i < fbi->palette_size; i++)
533 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
534
535 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 536 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 537 break;
538
539 case FB_BLANK_UNBLANK:
b0086efb 540 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 541 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
542 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
543 fb_set_cmap(&fbi->fb.cmap, info);
544 pxafb_schedule_work(fbi, C_ENABLE);
545 }
546 return 0;
547}
548
1da177e4
LT		 549static struct fb_ops pxafb_ops = {
550 .owner = THIS_MODULE,
551 .fb_check_var = pxafb_check_var,
552 .fb_set_par = pxafb_set_par,
6e354846 553 .fb_pan_display = pxafb_pan_display,
1da177e4
LT		 554 .fb_setcolreg = pxafb_setcolreg,
555 .fb_fillrect = cfb_fillrect,
556 .fb_copyarea = cfb_copyarea,
557 .fb_imageblit = cfb_imageblit,
558 .fb_blank = pxafb_blank,
1da177e4
LT		 559};
560
561/*
562 * Calculate the PCD value from the clock rate (in picoseconds).
563 * We take account of the PPCR clock setting.
564 * From PXA Developer's Manual:
565 *
566 * PixelClock = LCLK
567 * -------------
568 * 2 ( PCD + 1 )
569 *
570 * PCD = LCLK
571 * ------------- - 1
572 * 2(PixelClock)
573 *
574 * Where:
575 * LCLK = LCD/Memory Clock
576 * PCD = LCCR3[7:0]
577 *
578 * PixelClock here is in Hz while the pixclock argument given is the
579 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
580 *
581 * The function get_lclk_frequency_10khz returns LCLK in units of
582 * 10khz. Calling the result of this function lclk gives us the
583 * following
584 *
585 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
586 * -------------------------------------- - 1
587 * 2
588 *
589 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
590 */
b0086efb 591static inline unsigned int get_pcd(struct pxafb_info *fbi,
592 unsigned int pixclock)
1da177e4
LT		 593{
594 unsigned long long pcd;
595
596 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 597 * (DPC) bit? or perhaps set it based on the various clock
598 * speeds */
599 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
600 pcd *= pixclock;
bf1b8ab6 601 do_div(pcd, 100000000 * 2);
1da177e4
LT		 602 /* no need for this, since we should subtract 1 anyway. they cancel */
603 /* pcd += 1; */ /* make up for integer math truncations */
604 return (unsigned int)pcd;
605}
606
ba44cd2d
RP		 607/*
608 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 609 * function correctly. We export it here. Note that 'hsync_time' and
610 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
611 * of the hsync period in seconds.
ba44cd2d
RP		 612 */
613static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
614{
72e3524c 615 unsigned long htime;
ba44cd2d
RP		 616
617 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 618 fbi->hsync_time = 0;
ba44cd2d
RP		 619 return;
620 }
621
72e3524c
RK		 622 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
623
ba44cd2d
RP		 624 fbi->hsync_time = htime;
625}
626
627unsigned long pxafb_get_hsync_time(struct device *dev)
628{
629 struct pxafb_info *fbi = dev_get_drvdata(dev);
630
631 /* If display is blanked/suspended, hsync isn't active */
632 if (!fbi || (fbi->state != C_ENABLE))
633 return 0;
634
635 return fbi->hsync_time;
636}
637EXPORT_SYMBOL(pxafb_get_hsync_time);
638
2c42dd8e 639static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
640 unsigned int offset, size_t size)
641{
642 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
643 unsigned int dma_desc_off, pal_desc_off;
644
6e354846 645 if (dma < 0 || dma >= DMA_MAX * 2)
2c42dd8e 646 return -EINVAL;
647
648 dma_desc = &fbi->dma_buff->dma_desc[dma];
649 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
650
77e19675 651 dma_desc->fsadr = fbi->video_mem_phys + offset;
2c42dd8e 652 dma_desc->fidr = 0;
653 dma_desc->ldcmd = size;
654
6e354846 655 if (pal < 0 || pal >= PAL_MAX * 2) {
2c42dd8e 656 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
657 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
658 } else {
62cfcf4f
JS		 659 pal_desc = &fbi->dma_buff->pal_desc[pal];
660 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
2c42dd8e 661
662 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
663 pal_desc->fidr = 0;
664
665 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
666 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
667 else
668 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
669
670 pal_desc->ldcmd |= LDCMD_PAL;
671
672 /* flip back and forth between palette and frame buffer */
673 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
674 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
675 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
676 }
677
678 return 0;
679}
680
6e354846
EM		 681static void setup_base_frame(struct pxafb_info *fbi, int branch)
682{
683 struct fb_var_screeninfo *var = &fbi->fb.var;
684 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
685 unsigned int nbytes, offset;
686 int dma, pal, bpp = var->bits_per_pixel;
687
688 dma = DMA_BASE + (branch ? DMA_MAX : 0);
689 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
690
691 nbytes = fix->line_length * var->yres;
692 offset = fix->line_length * var->yoffset;
693
694 if (fbi->lccr0 & LCCR0_SDS) {
695 nbytes = nbytes / 2;
696 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
697 }
698
699 setup_frame_dma(fbi, dma, pal, offset, nbytes);
700}
701
3c42a449
EM		 702#ifdef CONFIG_FB_PXA_SMARTPANEL
703static int setup_smart_dma(struct pxafb_info *fbi)
704{
705 struct pxafb_dma_descriptor *dma_desc;
706 unsigned long dma_desc_off, cmd_buff_off;
707
708 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
709 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
710 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
711
712 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
713 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
714 dma_desc->fidr = 0;
715 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
716
717 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
718 return 0;
719}
720
721int pxafb_smart_flush(struct fb_info *info)
722{
723 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
724 uint32_t prsr;
725 int ret = 0;
726
727 /* disable controller until all registers are set up */
728 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
729
730 /* 1. make it an even number of commands to align on 32-bit boundary
731 * 2. add the interrupt command to the end of the chain so we can
732 * keep track of the end of the transfer
733 */
734
735 while (fbi->n_smart_cmds & 1)
736 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
737
738 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
739 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
740 setup_smart_dma(fbi);
741
742 /* continue to execute next command */
743 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
744 lcd_writel(fbi, PRSR, prsr);
745
746 /* stop the processor in case it executed "wait for sync" cmd */
747 lcd_writel(fbi, CMDCR, 0x0001);
748
749 /* don't send interrupts for fifo underruns on channel 6 */
750 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
751
752 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
753 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
754 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
a0427509 755 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
3c42a449
EM		 756 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
757 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
758
759 /* begin sending */
760 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
761
762 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
763 pr_warning("%s: timeout waiting for command done\n",
764 __func__);
765 ret = -ETIMEDOUT;
766 }
767
768 /* quick disable */
769 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
770 lcd_writel(fbi, PRSR, prsr);
771 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
772 lcd_writel(fbi, FDADR6, 0);
773 fbi->n_smart_cmds = 0;
774 return ret;
775}
776
777int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
778{
779 int i;
780 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
781
69bdea70
EM		 782 for (i = 0; i < n_cmds; i++, cmds++) {
783 /* if it is a software delay, flush and delay */
784 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
785 pxafb_smart_flush(info);
786 mdelay(*cmds & 0xff);
787 continue;
788 }
789
790 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
3c42a449
EM		 791 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
792 pxafb_smart_flush(info);
793
69bdea70 794 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
3c42a449
EM		 795 }
796
797 return 0;
798}
799
800static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
801{
802 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
803 return (t == 0) ? 1 : t;
804}
805
806static void setup_smart_timing(struct pxafb_info *fbi,
807 struct fb_var_screeninfo *var)
808{
809 struct pxafb_mach_info *inf = fbi->dev->platform_data;
810 struct pxafb_mode_info *mode = &inf->modes[0];
811 unsigned long lclk = clk_get_rate(fbi->clk);
812 unsigned t1, t2, t3, t4;
813
814 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
815 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
816 t3 = mode->op_hold_time;
817 t4 = mode->cmd_inh_time;
818
819 fbi->reg_lccr1 =
820 LCCR1_DisWdth(var->xres) |
821 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
822 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
823 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
824
825 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
c1f99c21
EM		 826 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
827 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
828 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
3c42a449
EM		 829
830 /* FIXME: make this configurable */
831 fbi->reg_cmdcr = 1;
832}
833
834static int pxafb_smart_thread(void *arg)
835{
7f1133cb 836 struct pxafb_info *fbi = arg;
3c42a449
EM		 837 struct pxafb_mach_info *inf = fbi->dev->platform_data;
838
839 if (!fbi || !inf->smart_update) {
840 pr_err("%s: not properly initialized, thread terminated\n",
841 __func__);
842 return -EINVAL;
843 }
844
845 pr_debug("%s(): task starting\n", __func__);
846
847 set_freezable();
848 while (!kthread_should_stop()) {
849
850 if (try_to_freeze())
851 continue;
852
07f651c7
EM		 853 mutex_lock(&fbi->ctrlr_lock);
854
3c42a449
EM		 855 if (fbi->state == C_ENABLE) {
856 inf->smart_update(&fbi->fb);
857 complete(&fbi->refresh_done);
858 }
859
07f651c7
EM		 860 mutex_unlock(&fbi->ctrlr_lock);
861
3c42a449
EM		 862 set_current_state(TASK_INTERRUPTIBLE);
863 schedule_timeout(30 * HZ / 1000);
864 }
865
866 pr_debug("%s(): task ending\n", __func__);
867 return 0;
868}
869
870static int pxafb_smart_init(struct pxafb_info *fbi)
871{
07df1c4f 872 if (!(fbi->lccr0 & LCCR0_LCDT))
6cc4abe4
EM		 873 return 0;
874
07df1c4f
EM		 875 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
876 fbi->n_smart_cmds = 0;
877
878 init_completion(&fbi->command_done);
879 init_completion(&fbi->refresh_done);
880
3c42a449
EM		 881 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
882 "lcd_refresh");
883 if (IS_ERR(fbi->smart_thread)) {
07df1c4f 884 pr_err("%s: unable to create kernel thread\n", __func__);
3c42a449
EM		 885 return PTR_ERR(fbi->smart_thread);
886 }
a5718a14 887
3c42a449
EM		 888 return 0;
889}
890#else
891int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
892{
893 return 0;
894}
895
896int pxafb_smart_flush(struct fb_info *info)
897{
898 return 0;
899}
07df1c4f
EM		 900
901static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
902#endif /* CONFIG_FB_PXA_SMARTPANEL */
3c42a449 903
90eabbf0
EM		 904static void setup_parallel_timing(struct pxafb_info *fbi,
905 struct fb_var_screeninfo *var)
906{
907 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
908
909 fbi->reg_lccr1 =
910 LCCR1_DisWdth(var->xres) +
911 LCCR1_HorSnchWdth(var->hsync_len) +
912 LCCR1_BegLnDel(var->left_margin) +
913 LCCR1_EndLnDel(var->right_margin);
914
915 /*
916 * If we have a dual scan LCD, we need to halve
917 * the YRES parameter.
918 */
919 lines_per_panel = var->yres;
920 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
921 lines_per_panel /= 2;
922
923 fbi->reg_lccr2 =
924 LCCR2_DisHght(lines_per_panel) +
925 LCCR2_VrtSnchWdth(var->vsync_len) +
926 LCCR2_BegFrmDel(var->upper_margin) +
927 LCCR2_EndFrmDel(var->lower_margin);
928
929 fbi->reg_lccr3 = fbi->lccr3 |
930 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
931 LCCR3_HorSnchH : LCCR3_HorSnchL) |
932 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
933 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
934
935 if (pcd) {
936 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
937 set_hsync_time(fbi, pcd);
938 }
939}
940
1da177e4
LT		 941/*
942 * pxafb_activate_var():
b0086efb 943 * Configures LCD Controller based on entries in var parameter.
944 * Settings are only written to the controller if changes were made.
1da177e4 945 */
b0086efb 946static int pxafb_activate_var(struct fb_var_screeninfo *var,
947 struct pxafb_info *fbi)
1da177e4 948{
1da177e4 949 u_long flags;
1da177e4 950
1da177e4 951#if DEBUG_VAR
3c42a449
EM		 952 if (!(fbi->lccr0 & LCCR0_LCDT)) {
953 if (var->xres < 16 || var->xres > 1024)
954 printk(KERN_ERR "%s: invalid xres %d\n",
955 fbi->fb.fix.id, var->xres);
956 switch (var->bits_per_pixel) {
957 case 1:
958 case 2:
959 case 4:
960 case 8:
961 case 16:
c1450f15
SS		 962 case 24:
963 case 32:
3c42a449
EM		 964 break;
965 default:
966 printk(KERN_ERR "%s: invalid bit depth %d\n",
967 fbi->fb.fix.id, var->bits_per_pixel);
968 break;
969 }
970
971 if (var->hsync_len < 1 || var->hsync_len > 64)
972 printk(KERN_ERR "%s: invalid hsync_len %d\n",
973 fbi->fb.fix.id, var->hsync_len);
974 if (var->left_margin < 1 || var->left_margin > 255)
975 printk(KERN_ERR "%s: invalid left_margin %d\n",
976 fbi->fb.fix.id, var->left_margin);
977 if (var->right_margin < 1 || var->right_margin > 255)
978 printk(KERN_ERR "%s: invalid right_margin %d\n",
979 fbi->fb.fix.id, var->right_margin);
980 if (var->yres < 1 || var->yres > 1024)
981 printk(KERN_ERR "%s: invalid yres %d\n",
982 fbi->fb.fix.id, var->yres);
983 if (var->vsync_len < 1 || var->vsync_len > 64)
984 printk(KERN_ERR "%s: invalid vsync_len %d\n",
985 fbi->fb.fix.id, var->vsync_len);
986 if (var->upper_margin < 0 || var->upper_margin > 255)
987 printk(KERN_ERR "%s: invalid upper_margin %d\n",
988 fbi->fb.fix.id, var->upper_margin);
989 if (var->lower_margin < 0 || var->lower_margin > 255)
990 printk(KERN_ERR "%s: invalid lower_margin %d\n",
991 fbi->fb.fix.id, var->lower_margin);
1da177e4 992 }
1da177e4 993#endif
90eabbf0
EM		 994 /* Update shadow copy atomically */
995 local_irq_save(flags);
1da177e4 996
3c42a449
EM		 997#ifdef CONFIG_FB_PXA_SMARTPANEL
998 if (fbi->lccr0 & LCCR0_LCDT)
999 setup_smart_timing(fbi, var);
1000 else
1001#endif
1002 setup_parallel_timing(fbi, var);
90eabbf0 1003
6e354846
EM		 1004 setup_base_frame(fbi, 0);
1005
90eabbf0 1006 fbi->reg_lccr0 = fbi->lccr0 |
1da177e4 1007 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 1008 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4 1009
878f5783 1010 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1da177e4 1011
a7535ba7 1012 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 1013 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1da177e4
LT		 1014 local_irq_restore(flags);
1015
1016 /*
1017 * Only update the registers if the controller is enabled
1018 * and something has changed.
1019 */
a7535ba7
EM		 1020 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1021 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1022 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1023 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
a0427509 1024 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
a7535ba7
EM		 1025 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1026 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1da177e4
LT		 1027 pxafb_schedule_work(fbi, C_REENABLE);
1028
1029 return 0;
1030}
1031
1032/*
1033 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1034 * Do not call them directly; set_ctrlr_state does the correct serialisation
1035 * to ensure that things happen in the right way 100% of time time.
1036 * -- rmk
1037 */
1038static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1039{
ca5da710 1040 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 1041
a5718a14
EM		 1042 if (fbi->backlight_power)
1043 fbi->backlight_power(on);
1da177e4
LT		 1044}
1045
1046static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1047{
ca5da710 1048 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4 1049
a5718a14
EM		 1050 if (fbi->lcd_power)
1051 fbi->lcd_power(on, &fbi->fb.var);
1da177e4
LT		 1052}
1053
1da177e4
LT		 1054static void pxafb_enable_controller(struct pxafb_info *fbi)
1055{
ca5da710 1056 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 1057 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1058 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 1059 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1060 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1061 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1062 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 1063
8d372266 1064 /* enable LCD controller clock */
72e3524c 1065 clk_enable(fbi->clk);
8d372266 1066
3c42a449
EM		 1067 if (fbi->lccr0 & LCCR0_LCDT)
1068 return;
1069
1da177e4 1070 /* Sequence from 11.7.10 */
a0427509 1071 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
a7535ba7
EM		 1072 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1073 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1074 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1075 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1076
1077 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1078 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1079 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 1080}
1081
1082static void pxafb_disable_controller(struct pxafb_info *fbi)
1083{
ce4fb7b8 1084 uint32_t lccr0;
1085
3c42a449
EM		 1086#ifdef CONFIG_FB_PXA_SMARTPANEL
1087 if (fbi->lccr0 & LCCR0_LCDT) {
1088 wait_for_completion_timeout(&fbi->refresh_done,
1089 200 * HZ / 1000);
1090 return;
1091 }
1092#endif
1093
ce4fb7b8 1094 /* Clear LCD Status Register */
a7535ba7 1095 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 1096
a7535ba7
EM		 1097 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1098 lcd_writel(fbi, LCCR0, lccr0);
1099 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 1100
2ba162b9 1101 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
8d372266
NP		 1102
1103 /* disable LCD controller clock */
72e3524c 1104 clk_disable(fbi->clk);
1da177e4
LT		 1105}
1106
1107/*
1108 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1109 */
7d12e780 1110static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 1111{
1112 struct pxafb_info *fbi = dev_id;
a7535ba7 1113 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1da177e4
LT		 1114
1115 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 1116 lccr0 = lcd_readl(fbi, LCCR0);
1117 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
2ba162b9 1118 complete(&fbi->disable_done);
1da177e4
LT		 1119 }
1120
3c42a449
EM		 1121#ifdef CONFIG_FB_PXA_SMARTPANEL
1122 if (lcsr & LCSR_CMD_INT)
1123 complete(&fbi->command_done);
1124#endif
1125
a7535ba7 1126 lcd_writel(fbi, LCSR, lcsr);
1da177e4
LT		 1127 return IRQ_HANDLED;
1128}
1129
1130/*
1131 * This function must be called from task context only, since it will
1132 * sleep when disabling the LCD controller, or if we get two contending
1133 * processes trying to alter state.
1134 */
1135static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1136{
1137 u_int old_state;
1138
b91dbce5 1139 mutex_lock(&fbi->ctrlr_lock);
1da177e4
LT		 1140
1141 old_state = fbi->state;
1142
1143 /*
1144 * Hack around fbcon initialisation.
1145 */
1146 if (old_state == C_STARTUP && state == C_REENABLE)
1147 state = C_ENABLE;
1148
1149 switch (state) {
1150 case C_DISABLE_CLKCHANGE:
1151 /*
1152 * Disable controller for clock change. If the
1153 * controller is already disabled, then do nothing.
1154 */
1155 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1156 fbi->state = state;
b0086efb 1157 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 1158 pxafb_disable_controller(fbi);
1159 }
1160 break;
1161
1162 case C_DISABLE_PM:
1163 case C_DISABLE:
1164 /*
1165 * Disable controller
1166 */
1167 if (old_state != C_DISABLE) {
1168 fbi->state = state;
1169 __pxafb_backlight_power(fbi, 0);
1170 __pxafb_lcd_power(fbi, 0);
1171 if (old_state != C_DISABLE_CLKCHANGE)
1172 pxafb_disable_controller(fbi);
1173 }
1174 break;
1175
1176 case C_ENABLE_CLKCHANGE:
1177 /*
1178 * Enable the controller after clock change. Only
1179 * do this if we were disabled for the clock change.
1180 */
1181 if (old_state == C_DISABLE_CLKCHANGE) {
1182 fbi->state = C_ENABLE;
1183 pxafb_enable_controller(fbi);
b0086efb 1184 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 1185 }
1186 break;
1187
1188 case C_REENABLE:
1189 /*
1190 * Re-enable the controller only if it was already
1191 * enabled. This is so we reprogram the control
1192 * registers.
1193 */
1194 if (old_state == C_ENABLE) {
d14b272b 1195 __pxafb_lcd_power(fbi, 0);
1da177e4 1196 pxafb_disable_controller(fbi);
1da177e4 1197 pxafb_enable_controller(fbi);
d14b272b 1198 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 1199 }
1200 break;
1201
1202 case C_ENABLE_PM:
1203 /*
1204 * Re-enable the controller after PM. This is not
1205 * perfect - think about the case where we were doing
1206 * a clock change, and we suspended half-way through.
1207 */
1208 if (old_state != C_DISABLE_PM)
1209 break;
1210 /* fall through */
1211
1212 case C_ENABLE:
1213 /*
1214 * Power up the LCD screen, enable controller, and
1215 * turn on the backlight.
1216 */
1217 if (old_state != C_ENABLE) {
1218 fbi->state = C_ENABLE;
1da177e4
LT		 1219 pxafb_enable_controller(fbi);
1220 __pxafb_lcd_power(fbi, 1);
1221 __pxafb_backlight_power(fbi, 1);
1222 }
1223 break;
1224 }
b91dbce5 1225 mutex_unlock(&fbi->ctrlr_lock);
1da177e4
LT		 1226}
1227
1228/*
1229 * Our LCD controller task (which is called when we blank or unblank)
1230 * via keventd.
1231 */
6d5aefb8 1232static void pxafb_task(struct work_struct *work)
1da177e4 1233{
6d5aefb8
DH		 1234 struct pxafb_info *fbi =
1235 container_of(work, struct pxafb_info, task);
1da177e4
LT		 1236 u_int state = xchg(&fbi->task_state, -1);
1237
1238 set_ctrlr_state(fbi, state);
1239}
1240
1241#ifdef CONFIG_CPU_FREQ
1242/*
1243 * CPU clock speed change handler. We need to adjust the LCD timing
1244 * parameters when the CPU clock is adjusted by the power management
1245 * subsystem.
1246 *
1247 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1248 */
1249static int
1250pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1251{
1252 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 1253 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 1254 u_int pcd;
1255
1256 switch (val) {
1257 case CPUFREQ_PRECHANGE:
1258 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1259 break;
1260
1261 case CPUFREQ_POSTCHANGE:
72e3524c 1262 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 1263 set_hsync_time(fbi, pcd);
b0086efb 1264 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1265 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 1266 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1267 break;
1268 }
1269 return 0;
1270}
1271
1272static int
1273pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1274{
1275 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1276 struct fb_var_screeninfo *var = &fbi->fb.var;
1277 struct cpufreq_policy *policy = data;
1278
1279 switch (val) {
1280 case CPUFREQ_ADJUST:
1281 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1282 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1283 "new clock %d kHz\n", pxafb_display_dma_period(var),
1284 policy->max);
b0086efb 1285 /* TODO: fill in min/max values */
1da177e4 1286 break;
1da177e4
LT		 1287 }
1288 return 0;
1289}
1290#endif
1291
1292#ifdef CONFIG_PM
1293/*
1294 * Power management hooks. Note that we won't be called from IRQ context,
1295 * unlike the blank functions above, so we may sleep.
1296 */
3ae5eaec 1297static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1298{
3ae5eaec 1299 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1300
9480e307 1301 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1302 return 0;
1303}
1304
3ae5eaec 1305static int pxafb_resume(struct platform_device *dev)
1da177e4 1306{
3ae5eaec 1307 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1308
9480e307 1309 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1310 return 0;
1311}
1312#else
1313#define pxafb_suspend NULL
1314#define pxafb_resume NULL
1315#endif
1316
77e19675 1317static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1da177e4 1318{
77e19675 1319 int size = PAGE_ALIGN(fbi->video_mem_size);
3c42a449 1320
77e19675
EM		 1321 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1322 if (fbi->video_mem == NULL)
1323 return -ENOMEM;
1da177e4 1324
77e19675
EM		 1325 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1326 fbi->video_mem_size = size;
84f43c30 1327
77e19675
EM		 1328 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1329 fbi->fb.fix.smem_len = fbi->video_mem_size;
1330 fbi->fb.screen_base = fbi->video_mem;
84f43c30 1331
77e19675 1332 return fbi->video_mem ? 0 : -ENOMEM;
84f43c30 1333}
1334
ebdf982a
GL		 1335static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1336 struct pxafb_mach_info *inf)
84f43c30 1337{
1338 unsigned int lcd_conn = inf->lcd_conn;
77e19675
EM		 1339 struct pxafb_mode_info *m;
1340 int i;
84f43c30 1341
1342 fbi->cmap_inverse = inf->cmap_inverse;
1343 fbi->cmap_static = inf->cmap_static;
a0427509 1344 fbi->lccr4 = inf->lccr4;
84f43c30 1345
1ec26db1 1346 switch (lcd_conn & LCD_TYPE_MASK) {
84f43c30 1347 case LCD_TYPE_MONO_STN:
1348 fbi->lccr0 = LCCR0_CMS;
1349 break;
1350 case LCD_TYPE_MONO_DSTN:
1351 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1352 break;
1353 case LCD_TYPE_COLOR_STN:
1354 fbi->lccr0 = 0;
1355 break;
1356 case LCD_TYPE_COLOR_DSTN:
1357 fbi->lccr0 = LCCR0_SDS;
1358 break;
1359 case LCD_TYPE_COLOR_TFT:
1360 fbi->lccr0 = LCCR0_PAS;
1361 break;
1362 case LCD_TYPE_SMART_PANEL:
1363 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1364 break;
1365 default:
1366 /* fall back to backward compatibility way */
1367 fbi->lccr0 = inf->lccr0;
1368 fbi->lccr3 = inf->lccr3;
ebdf982a 1369 goto decode_mode;
84f43c30 1370 }
1371
1372 if (lcd_conn == LCD_MONO_STN_8BPP)
1373 fbi->lccr0 |= LCCR0_DPD;
1374
9a1ac7e4
EM		 1375 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1376
84f43c30 1377 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1378 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1379 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1380
ebdf982a 1381decode_mode:
77e19675
EM		 1382 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1383
1384 /* decide video memory size as follows:
1385 * 1. default to mode of maximum resolution
1386 * 2. allow platform to override
1387 * 3. allow module parameter to override
1388 */
1389 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1390 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1391 m->xres * m->yres * m->bpp / 8);
1392
1393 if (inf->video_mem_size > fbi->video_mem_size)
1394 fbi->video_mem_size = inf->video_mem_size;
1395
1396 if (video_mem_size > fbi->video_mem_size)
1397 fbi->video_mem_size = video_mem_size;
84f43c30 1398}
1399
9e6c2976 1400static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1da177e4
LT		 1401{
1402 struct pxafb_info *fbi;
1403 void *addr;
1404 struct pxafb_mach_info *inf = dev->platform_data;
1405
1406 /* Alloc the pxafb_info and pseudo_palette in one step */
1407 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1408 if (!fbi)
1409 return NULL;
1410
1411 memset(fbi, 0, sizeof(struct pxafb_info));
1412 fbi->dev = dev;
1413
72e3524c
RK		 1414 fbi->clk = clk_get(dev, "LCDCLK");
1415 if (IS_ERR(fbi->clk)) {
1416 kfree(fbi);
1417 return NULL;
1418 }
1419
1da177e4
LT		 1420 strcpy(fbi->fb.fix.id, PXA_NAME);
1421
1422 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1423 fbi->fb.fix.type_aux = 0;
1424 fbi->fb.fix.xpanstep = 0;
7e4b19c9 1425 fbi->fb.fix.ypanstep = 1;
1da177e4
LT		 1426 fbi->fb.fix.ywrapstep = 0;
1427 fbi->fb.fix.accel = FB_ACCEL_NONE;
1428
1429 fbi->fb.var.nonstd = 0;
1430 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1431 fbi->fb.var.height = -1;
1432 fbi->fb.var.width = -1;
7e4b19c9 1433 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1da177e4
LT		 1434 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1435
1436 fbi->fb.fbops = &pxafb_ops;
1437 fbi->fb.flags = FBINFO_DEFAULT;
1438 fbi->fb.node = -1;
1439
1440 addr = fbi;
1441 addr = addr + sizeof(struct pxafb_info);
1442 fbi->fb.pseudo_palette = addr;
1443
b0086efb 1444 fbi->state = C_STARTUP;
1445 fbi->task_state = (u_char)-1;
d14b272b 1446
84f43c30 1447 pxafb_decode_mach_info(fbi, inf);
1da177e4
LT		 1448
1449 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1450 INIT_WORK(&fbi->task, pxafb_task);
b91dbce5 1451 mutex_init(&fbi->ctrlr_lock);
2ba162b9 1452 init_completion(&fbi->disable_done);
1da177e4
LT		 1453
1454 return fbi;
1455}
1456
1457#ifdef CONFIG_FB_PXA_PARAMETERS
9e6c2976 1458static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1459{
1460 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1461
1462 const char *name = this_opt+5;
1463 unsigned int namelen = strlen(name);
1464 int res_specified = 0, bpp_specified = 0;
1465 unsigned int xres = 0, yres = 0, bpp = 0;
1466 int yres_specified = 0;
1467 int i;
1468 for (i = namelen-1; i >= 0; i--) {
1469 switch (name[i]) {
1470 case '-':
1471 namelen = i;
1472 if (!bpp_specified && !yres_specified) {
1473 bpp = simple_strtoul(&name[i+1], NULL, 0);
1474 bpp_specified = 1;
1475 } else
1476 goto done;
1477 break;
1478 case 'x':
1479 if (!yres_specified) {
1480 yres = simple_strtoul(&name[i+1], NULL, 0);
1481 yres_specified = 1;
1482 } else
1483 goto done;
1484 break;
1485 case '0' ... '9':
1486 break;
1487 default:
1488 goto done;
1489 }
1490 }
1491 if (i < 0 && yres_specified) {
1492 xres = simple_strtoul(name, NULL, 0);
1493 res_specified = 1;
1494 }
1495done:
1496 if (res_specified) {
1497 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1498 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1499 }
1500 if (bpp_specified)
1501 switch (bpp) {
1502 case 1:
1503 case 2:
1504 case 4:
1505 case 8:
1506 case 16:
1507 inf->modes[0].bpp = bpp;
1508 dev_info(dev, "overriding bit depth: %d\n", bpp);
1509 break;
1510 default:
1511 dev_err(dev, "Depth %d is not valid\n", bpp);
1512 return -EINVAL;
1513 }
1514 return 0;
1515}
1516
9e6c2976 1517static int __devinit parse_opt(struct device *dev, char *this_opt)
817daf14 1518{
1519 struct pxafb_mach_info *inf = dev->platform_data;
1520 struct pxafb_mode_info *mode = &inf->modes[0];
1521 char s[64];
1522
1523 s[0] = '\0';
1524
77e19675
EM		 1525 if (!strncmp(this_opt, "vmem:", 5)) {
1526 video_mem_size = memparse(this_opt + 5, NULL);
1527 } else if (!strncmp(this_opt, "mode:", 5)) {
817daf14 1528 return parse_opt_mode(dev, this_opt);
1529 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1530 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1531 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1532 } else if (!strncmp(this_opt, "left:", 5)) {
1533 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1534 sprintf(s, "left: %u\n", mode->left_margin);
1535 } else if (!strncmp(this_opt, "right:", 6)) {
1536 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1537 sprintf(s, "right: %u\n", mode->right_margin);
1538 } else if (!strncmp(this_opt, "upper:", 6)) {
1539 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1540 sprintf(s, "upper: %u\n", mode->upper_margin);
1541 } else if (!strncmp(this_opt, "lower:", 6)) {
1542 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1543 sprintf(s, "lower: %u\n", mode->lower_margin);
1544 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1545 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1546 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1547 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1548 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1549 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1550 } else if (!strncmp(this_opt, "hsync:", 6)) {
1551 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1552 sprintf(s, "hsync: Active Low\n");
1553 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1554 } else {
1555 sprintf(s, "hsync: Active High\n");
1556 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1557 }
1558 } else if (!strncmp(this_opt, "vsync:", 6)) {
1559 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1560 sprintf(s, "vsync: Active Low\n");
1561 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1562 } else {
1563 sprintf(s, "vsync: Active High\n");
1564 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1565 }
1566 } else if (!strncmp(this_opt, "dpc:", 4)) {
1567 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1568 sprintf(s, "double pixel clock: false\n");
1569 inf->lccr3 &= ~LCCR3_DPC;
1570 } else {
1571 sprintf(s, "double pixel clock: true\n");
1572 inf->lccr3 |= LCCR3_DPC;
1573 }
1574 } else if (!strncmp(this_opt, "outputen:", 9)) {
1575 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1576 sprintf(s, "output enable: active low\n");
1577 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1578 } else {
1579 sprintf(s, "output enable: active high\n");
1580 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1581 }
1582 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1583 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1584 sprintf(s, "pixel clock polarity: falling edge\n");
1585 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1586 } else {
1587 sprintf(s, "pixel clock polarity: rising edge\n");
1588 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1589 }
1590 } else if (!strncmp(this_opt, "color", 5)) {
1591 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1592 } else if (!strncmp(this_opt, "mono", 4)) {
1593 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1594 } else if (!strncmp(this_opt, "active", 6)) {
1595 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1596 } else if (!strncmp(this_opt, "passive", 7)) {
1597 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1598 } else if (!strncmp(this_opt, "single", 6)) {
1599 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1600 } else if (!strncmp(this_opt, "dual", 4)) {
1601 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1602 } else if (!strncmp(this_opt, "4pix", 4)) {
1603 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1604 } else if (!strncmp(this_opt, "8pix", 4)) {
1605 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1606 } else {
1607 dev_err(dev, "unknown option: %s\n", this_opt);
1608 return -EINVAL;
1609 }
1610
1611 if (s[0] != '\0')
1612 dev_info(dev, "override %s", s);
1613
1614 return 0;
1615}
1616
9e6c2976 1617static int __devinit pxafb_parse_options(struct device *dev, char *options)
817daf14 1618{
1da177e4 1619 char *this_opt;
817daf14 1620 int ret;
1da177e4 1621
817daf14 1622 if (!options || !*options)
1623 return 0;
1da177e4
LT		 1624
1625 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1626
1627 /* could be made table driven or similar?... */
817daf14 1628 while ((this_opt = strsep(&options, ",")) != NULL) {
1629 ret = parse_opt(dev, this_opt);
1630 if (ret)
1631 return ret;
1632 }
1633 return 0;
1da177e4 1634}
92ac73c1 1635
1636static char g_options[256] __devinitdata = "";
1637
f1edfc42 1638#ifndef MODULE
9e6c2976 1639static int __init pxafb_setup_options(void)
92ac73c1 1640{
1641 char *options = NULL;
1642
1643 if (fb_get_options("pxafb", &options))
1644 return -ENODEV;
1645
1646 if (options)
1647 strlcpy(g_options, options, sizeof(g_options));
1648
1649 return 0;
1650}
1651#else
1652#define pxafb_setup_options() (0)
1653
1654module_param_string(options, g_options, sizeof(g_options), 0);
1655MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1656#endif
1657
1658#else
1659#define pxafb_parse_options(...) (0)
1660#define pxafb_setup_options() (0)
1da177e4
LT		 1661#endif
1662
1da177e4 1663#ifdef DEBUG_VAR
4f3e2664
EM		 1664/* Check for various illegal bit-combinations. Currently only
1665 * a warning is given. */
1666static void __devinit pxafb_check_options(struct device *dev,
1667 struct pxafb_mach_info *inf)
1668{
1669 if (inf->lcd_conn)
1670 return;
1da177e4 1671
b0086efb 1672 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
4f3e2664 1673 dev_warn(dev, "machine LCCR0 setting contains "
b0086efb 1674 "illegal bits: %08x\n",
1675 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1676 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
4f3e2664 1677 dev_warn(dev, "machine LCCR3 setting contains "
b0086efb 1678 "illegal bits: %08x\n",
1679 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1680 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 1681 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1682 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1683 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
4f3e2664 1684 dev_warn(dev, "Double Pixel Data (DPD) mode is "
b0086efb 1685 "only valid in passive mono"
1686 " single panel mode\n");
1687 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 1688 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
4f3e2664 1689 dev_warn(dev, "Dual panel only valid in passive mode\n");
b0086efb 1690 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1691 (inf->modes->upper_margin || inf->modes->lower_margin))
4f3e2664 1692 dev_warn(dev, "Upper and lower margins must be 0 in "
b0086efb 1693 "passive mode\n");
4f3e2664
EM		 1694}
1695#else
1696#define pxafb_check_options(...) do {} while (0)
1da177e4
LT		 1697#endif
1698
4f3e2664
EM		 1699static int __devinit pxafb_probe(struct platform_device *dev)
1700{
1701 struct pxafb_info *fbi;
1702 struct pxafb_mach_info *inf;
1703 struct resource *r;
1704 int irq, ret;
1705
1706 dev_dbg(&dev->dev, "pxafb_probe\n");
1707
1708 inf = dev->dev.platform_data;
1709 ret = -ENOMEM;
1710 fbi = NULL;
1711 if (!inf)
1712 goto failed;
1713
1714 ret = pxafb_parse_options(&dev->dev, g_options);
1715 if (ret < 0)
1716 goto failed;
1717
1718 pxafb_check_options(&dev->dev, inf);
1719
b0086efb 1720 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1721 inf->modes->xres,
1722 inf->modes->yres,
1723 inf->modes->bpp);
1724 if (inf->modes->xres == 0 ||
1725 inf->modes->yres == 0 ||
1726 inf->modes->bpp == 0) {
3ae5eaec 1727 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 1728 ret = -EINVAL;
1729 goto failed;
1730 }
a5718a14 1731
3ae5eaec 1732 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 1733 if (!fbi) {
b0086efb 1734 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 1735 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 1736 ret = -ENOMEM;
1da177e4
LT		 1737 goto failed;
1738 }
1739
a5718a14
EM		 1740 fbi->backlight_power = inf->pxafb_backlight_power;
1741 fbi->lcd_power = inf->pxafb_lcd_power;
1742
ce4fb7b8 1743 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1744 if (r == NULL) {
1745 dev_err(&dev->dev, "no I/O memory resource defined\n");
1746 ret = -ENODEV;
ee98476b 1747 goto failed_fbi;
ce4fb7b8 1748 }
1749
1750 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1751 if (r == NULL) {
1752 dev_err(&dev->dev, "failed to request I/O memory\n");
1753 ret = -EBUSY;
ee98476b 1754 goto failed_fbi;
ce4fb7b8 1755 }
1756
1757 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1758 if (fbi->mmio_base == NULL) {
1759 dev_err(&dev->dev, "failed to map I/O memory\n");
1760 ret = -EBUSY;
1761 goto failed_free_res;
1762 }
1763
77e19675
EM		 1764 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1765 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
1766 &fbi->dma_buff_phys, GFP_KERNEL);
1767 if (fbi->dma_buff == NULL) {
1768 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
1769 ret = -ENOMEM;
1770 goto failed_free_io;
1771 }
1772
1773 ret = pxafb_init_video_memory(fbi);
1da177e4 1774 if (ret) {
3ae5eaec 1775 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 1776 ret = -ENOMEM;
77e19675 1777 goto failed_free_dma;
1da177e4 1778 }
1da177e4 1779
ce4fb7b8 1780 irq = platform_get_irq(dev, 0);
1781 if (irq < 0) {
1782 dev_err(&dev->dev, "no IRQ defined\n");
1783 ret = -ENODEV;
1784 goto failed_free_mem;
1785 }
1786
1787 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1da177e4 1788 if (ret) {
3ae5eaec 1789 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 1790 ret = -EBUSY;
ce4fb7b8 1791 goto failed_free_mem;
1da177e4
LT		 1792 }
1793
3c42a449
EM		 1794 ret = pxafb_smart_init(fbi);
1795 if (ret) {
1796 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1797 goto failed_free_irq;
1798 }
07df1c4f 1799
1da177e4
LT		 1800 /*
1801 * This makes sure that our colour bitfield
1802 * descriptors are correctly initialised.
1803 */
ee98476b
JK		 1804 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1805 if (ret) {
1806 dev_err(&dev->dev, "failed to get suitable mode\n");
1807 goto failed_free_irq;
1808 }
1809
1810 ret = pxafb_set_par(&fbi->fb);
1811 if (ret) {
1812 dev_err(&dev->dev, "Failed to set parameters\n");
1813 goto failed_free_irq;
1814 }
1da177e4 1815
3ae5eaec 1816 platform_set_drvdata(dev, fbi);
1da177e4
LT		 1817
1818 ret = register_framebuffer(&fbi->fb);
1819 if (ret < 0) {
b0086efb 1820 dev_err(&dev->dev,
1821 "Failed to register framebuffer device: %d\n", ret);
ee98476b 1822 goto failed_free_cmap;
1da177e4
LT		 1823 }
1824
1da177e4
LT		 1825#ifdef CONFIG_CPU_FREQ
1826 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1827 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 1828 cpufreq_register_notifier(&fbi->freq_transition,
1829 CPUFREQ_TRANSITION_NOTIFIER);
1830 cpufreq_register_notifier(&fbi->freq_policy,
1831 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 1832#endif
1833
1834 /*
1835 * Ok, now enable the LCD controller
1836 */
1837 set_ctrlr_state(fbi, C_ENABLE);
1838
1839 return 0;
1840
ee98476b
JK		 1841failed_free_cmap:
1842 if (fbi->fb.cmap.len)
1843 fb_dealloc_cmap(&fbi->fb.cmap);
ce4fb7b8 1844failed_free_irq:
1845 free_irq(irq, fbi);
ce4fb7b8 1846failed_free_mem:
77e19675
EM		 1847 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1848failed_free_dma:
1849 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
1850 fbi->dma_buff, fbi->dma_buff_phys);
ee98476b
JK		 1851failed_free_io:
1852 iounmap(fbi->mmio_base);
1853failed_free_res:
1854 release_mem_region(r->start, r->end - r->start + 1);
1855failed_fbi:
1856 clk_put(fbi->clk);
3ae5eaec 1857 platform_set_drvdata(dev, NULL);
1da177e4 1858 kfree(fbi);
ee98476b 1859failed:
1da177e4
LT		 1860 return ret;
1861}
1862
9f17f287
JK		 1863static int __devexit pxafb_remove(struct platform_device *dev)
1864{
1865 struct pxafb_info *fbi = platform_get_drvdata(dev);
1866 struct resource *r;
1867 int irq;
1868 struct fb_info *info;
1869
1870 if (!fbi)
1871 return 0;
1872
1873 info = &fbi->fb;
1874
1875 unregister_framebuffer(info);
1876
1877 pxafb_disable_controller(fbi);
1878
1879 if (fbi->fb.cmap.len)
1880 fb_dealloc_cmap(&fbi->fb.cmap);
1881
1882 irq = platform_get_irq(dev, 0);
1883 free_irq(irq, fbi);
1884
77e19675
EM		 1885 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1886
1887 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
1888 fbi->dma_buff, fbi->dma_buff_phys);
9f17f287
JK		 1889
1890 iounmap(fbi->mmio_base);
1891
1892 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1893 release_mem_region(r->start, r->end - r->start + 1);
1894
1895 clk_put(fbi->clk);
1896 kfree(fbi);
1897
1898 return 0;
1899}
1900
3ae5eaec 1901static struct platform_driver pxafb_driver = {
1da177e4 1902 .probe = pxafb_probe,
9f17f287 1903 .remove = pxafb_remove,
1da177e4
LT		 1904 .suspend = pxafb_suspend,
1905 .resume = pxafb_resume,
3ae5eaec 1906 .driver = {
9f17f287 1907 .owner = THIS_MODULE,
3ae5eaec
RK		 1908 .name = "pxa2xx-fb",
1909 },
1da177e4
LT		 1910};
1911
9e6c2976 1912static int __init pxafb_init(void)
1da177e4 1913{
92ac73c1 1914 if (pxafb_setup_options())
1915 return -EINVAL;
1da177e4 1916
3ae5eaec 1917 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 1918}
1919
9f17f287
JK		 1920static void __exit pxafb_exit(void)
1921{
1922 platform_driver_unregister(&pxafb_driver);
1923}
1924
1da177e4 1925module_init(pxafb_init);
9f17f287 1926module_exit(pxafb_exit);
1da177e4
LT		 1927
1928MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1929MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)