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[ARM] pxafb: allow insertion of delay to the smart panel command sequence
[linux-2.6-block.git] / drivers / video / pxafb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/errno.h>
30#include <linux/string.h>
31#include <linux/interrupt.h>
32#include <linux/slab.h>
27ac792c 33#include <linux/mm.h>
1da177e4
LT		 34#include <linux/fb.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/ioport.h>
38#include <linux/cpufreq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4 40#include <linux/dma-mapping.h>
72e3524c
RK		 41#include <linux/clk.h>
42#include <linux/err.h>
2ba162b9 43#include <linux/completion.h>
b91dbce5 44#include <linux/mutex.h>
3c42a449
EM		 45#include <linux/kthread.h>
46#include <linux/freezer.h>
1da177e4 47
a09e64fb 48#include <mach/hardware.h>
1da177e4
LT		 49#include <asm/io.h>
50#include <asm/irq.h>
bf1b8ab6 51#include <asm/div64.h>
a09e64fb 52#include <mach/pxa-regs.h>
a09e64fb
RK		 53#include <mach/bitfield.h>
54#include <mach/pxafb.h>
1da177e4
LT		 55
56/*
57 * Complain if VAR is out of range.
58 */
59#define DEBUG_VAR 1
60
61#include "pxafb.h"
62
63/* Bits which should not be set in machine configuration structures */
b0086efb 64#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
67
68#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP)
1da177e4 70
b0086efb 71static int pxafb_activate_var(struct fb_var_screeninfo *var,
72 struct pxafb_info *);
1da177e4
LT		 73static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
74
a7535ba7
EM		 75static inline unsigned long
76lcd_readl(struct pxafb_info *fbi, unsigned int off)
77{
78 return __raw_readl(fbi->mmio_base + off);
79}
80
81static inline void
82lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
83{
84 __raw_writel(val, fbi->mmio_base + off);
85}
86
1da177e4
LT		 87static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
88{
89 unsigned long flags;
90
91 local_irq_save(flags);
92 /*
93 * We need to handle two requests being made at the same time.
94 * There are two important cases:
b0086efb 95 * 1. When we are changing VT (C_REENABLE) while unblanking
96 * (C_ENABLE) We must perform the unblanking, which will
97 * do our REENABLE for us.
98 * 2. When we are blanking, but immediately unblank before
99 * we have blanked. We do the "REENABLE" thing here as
100 * well, just to be sure.
1da177e4
LT		 101 */
102 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
103 state = (u_int) -1;
104 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
105 state = C_REENABLE;
106
107 if (state != (u_int)-1) {
108 fbi->task_state = state;
109 schedule_work(&fbi->task);
110 }
111 local_irq_restore(flags);
112}
113
114static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
115{
116 chan &= 0xffff;
117 chan >>= 16 - bf->length;
118 return chan << bf->offset;
119}
120
121static int
122pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
123 u_int trans, struct fb_info *info)
124{
125 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 126 u_int val;
127
128 if (regno >= fbi->palette_size)
129 return 1;
130
131 if (fbi->fb.var.grayscale) {
132 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
133 return 0;
134 }
135
136 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
137 case LCCR4_PAL_FOR_0:
138 val = ((red >> 0) & 0xf800);
139 val |= ((green >> 5) & 0x07e0);
140 val |= ((blue >> 11) & 0x001f);
1da177e4 141 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 142 break;
143 case LCCR4_PAL_FOR_1:
144 val = ((red << 8) & 0x00f80000);
145 val |= ((green >> 0) & 0x0000fc00);
146 val |= ((blue >> 8) & 0x000000f8);
b0086efb 147 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 148 break;
149 case LCCR4_PAL_FOR_2:
150 val = ((red << 8) & 0x00fc0000);
151 val |= ((green >> 0) & 0x0000fc00);
152 val |= ((blue >> 8) & 0x000000fc);
b0086efb 153 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 154 break;
1da177e4 155 }
9ffa7396
HK		 156
157 return 0;
1da177e4
LT		 158}
159
160static int
161pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
162 u_int trans, struct fb_info *info)
163{
164 struct pxafb_info *fbi = (struct pxafb_info *)info;
165 unsigned int val;
166 int ret = 1;
167
168 /*
169 * If inverse mode was selected, invert all the colours
170 * rather than the register number. The register number
171 * is what you poke into the framebuffer to produce the
172 * colour you requested.
173 */
174 if (fbi->cmap_inverse) {
175 red = 0xffff - red;
176 green = 0xffff - green;
177 blue = 0xffff - blue;
178 }
179
180 /*
181 * If greyscale is true, then we convert the RGB value
182 * to greyscale no matter what visual we are using.
183 */
184 if (fbi->fb.var.grayscale)
185 red = green = blue = (19595 * red + 38470 * green +
186 7471 * blue) >> 16;
187
188 switch (fbi->fb.fix.visual) {
189 case FB_VISUAL_TRUECOLOR:
190 /*
191 * 16-bit True Colour. We encode the RGB value
192 * according to the RGB bitfield information.
193 */
194 if (regno < 16) {
195 u32 *pal = fbi->fb.pseudo_palette;
196
197 val = chan_to_field(red, &fbi->fb.var.red);
198 val |= chan_to_field(green, &fbi->fb.var.green);
199 val |= chan_to_field(blue, &fbi->fb.var.blue);
200
201 pal[regno] = val;
202 ret = 0;
203 }
204 break;
205
206 case FB_VISUAL_STATIC_PSEUDOCOLOR:
207 case FB_VISUAL_PSEUDOCOLOR:
208 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
209 break;
210 }
211
212 return ret;
213}
214
215/*
216 * pxafb_bpp_to_lccr3():
217 * Convert a bits per pixel value to the correct bit pattern for LCCR3
218 */
219static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
220{
b0086efb 221 int ret = 0;
222 switch (var->bits_per_pixel) {
223 case 1: ret = LCCR3_1BPP; break;
224 case 2: ret = LCCR3_2BPP; break;
225 case 4: ret = LCCR3_4BPP; break;
226 case 8: ret = LCCR3_8BPP; break;
227 case 16: ret = LCCR3_16BPP; break;
c1450f15
SS		 228 case 24:
229 switch (var->red.length + var->green.length +
230 var->blue.length + var->transp.length) {
231 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
232 case 19: ret = LCCR3_19BPP_P; break;
233 }
234 break;
235 case 32:
236 switch (var->red.length + var->green.length +
237 var->blue.length + var->transp.length) {
238 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
239 case 19: ret = LCCR3_19BPP; break;
240 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
241 case 25: ret = LCCR3_25BPP; break;
242 }
243 break;
b0086efb 244 }
245 return ret;
1da177e4
LT		 246}
247
248#ifdef CONFIG_CPU_FREQ
249/*
250 * pxafb_display_dma_period()
251 * Calculate the minimum period (in picoseconds) between two DMA
252 * requests for the LCD controller. If we hit this, it means we're
253 * doing nothing but LCD DMA.
254 */
255static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
256{
b0086efb 257 /*
258 * Period = pixclock * bits_per_byte * bytes_per_transfer
259 * / memory_bits_per_pixel;
260 */
261 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 262}
1da177e4
LT		 263#endif
264
d14b272b
RP		 265/*
266 * Select the smallest mode that allows the desired resolution to be
267 * displayed. If desired parameters can be rounded up.
268 */
b0086efb 269static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
270 struct fb_var_screeninfo *var)
d14b272b
RP		 271{
272 struct pxafb_mode_info *mode = NULL;
273 struct pxafb_mode_info *modelist = mach->modes;
274 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
275 unsigned int i;
276
b0086efb 277 for (i = 0; i < mach->num_modes; i++) {
278 if (modelist[i].xres >= var->xres &&
279 modelist[i].yres >= var->yres &&
280 modelist[i].xres < best_x &&
281 modelist[i].yres < best_y &&
282 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 283 best_x = modelist[i].xres;
284 best_y = modelist[i].yres;
285 mode = &modelist[i];
286 }
287 }
288
289 return mode;
290}
291
b0086efb 292static void pxafb_setmode(struct fb_var_screeninfo *var,
293 struct pxafb_mode_info *mode)
d14b272b
RP		 294{
295 var->xres = mode->xres;
296 var->yres = mode->yres;
297 var->bits_per_pixel = mode->bpp;
298 var->pixclock = mode->pixclock;
299 var->hsync_len = mode->hsync_len;
300 var->left_margin = mode->left_margin;
301 var->right_margin = mode->right_margin;
302 var->vsync_len = mode->vsync_len;
303 var->upper_margin = mode->upper_margin;
304 var->lower_margin = mode->lower_margin;
305 var->sync = mode->sync;
306 var->grayscale = mode->cmap_greyscale;
307 var->xres_virtual = var->xres;
308 var->yres_virtual = var->yres;
309}
310
1da177e4
LT		 311/*
312 * pxafb_check_var():
313 * Get the video params out of 'var'. If a value doesn't fit, round it up,
314 * if it's too big, return -EINVAL.
315 *
316 * Round up in the following order: bits_per_pixel, xres,
317 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
318 * bitfields, horizontal timing, vertical timing.
319 */
320static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
321{
322 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 323 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1da177e4
LT		 324
325 if (var->xres < MIN_XRES)
326 var->xres = MIN_XRES;
327 if (var->yres < MIN_YRES)
328 var->yres = MIN_YRES;
d14b272b
RP		 329
330 if (inf->fixed_modes) {
331 struct pxafb_mode_info *mode;
332
333 mode = pxafb_getmode(inf, var);
334 if (!mode)
335 return -EINVAL;
336 pxafb_setmode(var, mode);
337 } else {
338 if (var->xres > inf->modes->xres)
339 return -EINVAL;
340 if (var->yres > inf->modes->yres)
341 return -EINVAL;
342 if (var->bits_per_pixel > inf->modes->bpp)
343 return -EINVAL;
344 }
345
1da177e4
LT		 346 var->xres_virtual =
347 max(var->xres_virtual, var->xres);
348 var->yres_virtual =
349 max(var->yres_virtual, var->yres);
350
b0086efb 351 /*
1da177e4
LT		 352 * Setup the RGB parameters for this display.
353 *
354 * The pixel packing format is described on page 7-11 of the
355 * PXA2XX Developer's Manual.
b0086efb 356 */
1da177e4
LT		 357 if (var->bits_per_pixel == 16) {
358 var->red.offset = 11; var->red.length = 5;
359 var->green.offset = 5; var->green.length = 6;
360 var->blue.offset = 0; var->blue.length = 5;
361 var->transp.offset = var->transp.length = 0;
c1450f15
SS		 362 } else if (var->bits_per_pixel > 16) {
363 struct pxafb_mode_info *mode;
364
365 mode = pxafb_getmode(inf, var);
366 if (!mode)
367 return -EINVAL;
368
369 switch (mode->depth) {
370 case 18: /* RGB666 */
371 var->transp.offset = var->transp.length = 0;
372 var->red.offset = 12; var->red.length = 6;
373 var->green.offset = 6; var->green.length = 6;
374 var->blue.offset = 0; var->blue.length = 6;
375 break;
376 case 19: /* RGBT666 */
377 var->transp.offset = 18; var->transp.length = 1;
378 var->red.offset = 12; var->red.length = 6;
379 var->green.offset = 6; var->green.length = 6;
380 var->blue.offset = 0; var->blue.length = 6;
381 break;
382 case 24: /* RGB888 */
383 var->transp.offset = var->transp.length = 0;
384 var->red.offset = 16; var->red.length = 8;
385 var->green.offset = 8; var->green.length = 8;
386 var->blue.offset = 0; var->blue.length = 8;
387 break;
388 case 25: /* RGBT888 */
389 var->transp.offset = 24; var->transp.length = 1;
390 var->red.offset = 16; var->red.length = 8;
391 var->green.offset = 8; var->green.length = 8;
392 var->blue.offset = 0; var->blue.length = 8;
393 break;
394 default:
395 return -EINVAL;
396 }
1da177e4 397 } else {
b0086efb 398 var->red.offset = var->green.offset = 0;
399 var->blue.offset = var->transp.offset = 0;
1da177e4
LT		 400 var->red.length = 8;
401 var->green.length = 8;
402 var->blue.length = 8;
403 var->transp.length = 0;
404 }
405
406#ifdef CONFIG_CPU_FREQ
78d3cfd3
RK		 407 pr_debug("pxafb: dma period = %d ps\n",
408 pxafb_display_dma_period(var));
1da177e4
LT		 409#endif
410
411 return 0;
412}
413
414static inline void pxafb_set_truecolor(u_int is_true_color)
415{
b0086efb 416 /* do your machine-specific setup if needed */
1da177e4
LT		 417}
418
419/*
420 * pxafb_set_par():
421 * Set the user defined part of the display for the specified console
422 */
423static int pxafb_set_par(struct fb_info *info)
424{
425 struct pxafb_info *fbi = (struct pxafb_info *)info;
426 struct fb_var_screeninfo *var = &info->var;
1da177e4 427
c1450f15 428 if (var->bits_per_pixel >= 16)
1da177e4
LT		 429 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
430 else if (!fbi->cmap_static)
431 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
432 else {
433 /*
434 * Some people have weird ideas about wanting static
435 * pseudocolor maps. I suspect their user space
436 * applications are broken.
437 */
438 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
439 }
440
441 fbi->fb.fix.line_length = var->xres_virtual *
442 var->bits_per_pixel / 8;
c1450f15 443 if (var->bits_per_pixel >= 16)
1da177e4
LT		 444 fbi->palette_size = 0;
445 else
b0086efb 446 fbi->palette_size = var->bits_per_pixel == 1 ?
447 4 : 1 << var->bits_per_pixel;
1da177e4 448
2c42dd8e 449 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4
LT		 450
451 /*
452 * Set (any) board control register to handle new color depth
453 */
454 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
455
c1450f15 456 if (fbi->fb.var.bits_per_pixel >= 16)
1da177e4
LT		 457 fb_dealloc_cmap(&fbi->fb.cmap);
458 else
459 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
460
461 pxafb_activate_var(var, fbi);
462
463 return 0;
464}
465
1da177e4
LT		 466/*
467 * pxafb_blank():
468 * Blank the display by setting all palette values to zero. Note, the
469 * 16 bpp mode does not really use the palette, so this will not
470 * blank the display in all modes.
471 */
472static int pxafb_blank(int blank, struct fb_info *info)
473{
474 struct pxafb_info *fbi = (struct pxafb_info *)info;
475 int i;
476
1da177e4
LT		 477 switch (blank) {
478 case FB_BLANK_POWERDOWN:
479 case FB_BLANK_VSYNC_SUSPEND:
480 case FB_BLANK_HSYNC_SUSPEND:
481 case FB_BLANK_NORMAL:
482 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
483 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
484 for (i = 0; i < fbi->palette_size; i++)
485 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
486
487 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 488 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 489 break;
490
491 case FB_BLANK_UNBLANK:
b0086efb 492 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 493 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
494 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
495 fb_set_cmap(&fbi->fb.cmap, info);
496 pxafb_schedule_work(fbi, C_ENABLE);
497 }
498 return 0;
499}
500
216d526c 501static int pxafb_mmap(struct fb_info *info,
1da177e4
LT		 502 struct vm_area_struct *vma)
503{
504 struct pxafb_info *fbi = (struct pxafb_info *)info;
505 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
506
507 if (off < info->fix.smem_len) {
3c42a449 508 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
1da177e4
LT		 509 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
510 fbi->map_dma, fbi->map_size);
511 }
512 return -EINVAL;
513}
514
515static struct fb_ops pxafb_ops = {
516 .owner = THIS_MODULE,
517 .fb_check_var = pxafb_check_var,
518 .fb_set_par = pxafb_set_par,
519 .fb_setcolreg = pxafb_setcolreg,
520 .fb_fillrect = cfb_fillrect,
521 .fb_copyarea = cfb_copyarea,
522 .fb_imageblit = cfb_imageblit,
523 .fb_blank = pxafb_blank,
1da177e4
LT		 524 .fb_mmap = pxafb_mmap,
525};
526
527/*
528 * Calculate the PCD value from the clock rate (in picoseconds).
529 * We take account of the PPCR clock setting.
530 * From PXA Developer's Manual:
531 *
532 * PixelClock = LCLK
533 * -------------
534 * 2 ( PCD + 1 )
535 *
536 * PCD = LCLK
537 * ------------- - 1
538 * 2(PixelClock)
539 *
540 * Where:
541 * LCLK = LCD/Memory Clock
542 * PCD = LCCR3[7:0]
543 *
544 * PixelClock here is in Hz while the pixclock argument given is the
545 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
546 *
547 * The function get_lclk_frequency_10khz returns LCLK in units of
548 * 10khz. Calling the result of this function lclk gives us the
549 * following
550 *
551 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
552 * -------------------------------------- - 1
553 * 2
554 *
555 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
556 */
b0086efb 557static inline unsigned int get_pcd(struct pxafb_info *fbi,
558 unsigned int pixclock)
1da177e4
LT		 559{
560 unsigned long long pcd;
561
562 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 563 * (DPC) bit? or perhaps set it based on the various clock
564 * speeds */
565 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
566 pcd *= pixclock;
bf1b8ab6 567 do_div(pcd, 100000000 * 2);
1da177e4
LT		 568 /* no need for this, since we should subtract 1 anyway. they cancel */
569 /* pcd += 1; */ /* make up for integer math truncations */
570 return (unsigned int)pcd;
571}
572
ba44cd2d
RP		 573/*
574 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 575 * function correctly. We export it here. Note that 'hsync_time' and
576 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
577 * of the hsync period in seconds.
ba44cd2d
RP		 578 */
579static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
580{
72e3524c 581 unsigned long htime;
ba44cd2d
RP		 582
583 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 584 fbi->hsync_time = 0;
ba44cd2d
RP		 585 return;
586 }
587
72e3524c
RK		 588 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
589
ba44cd2d
RP		 590 fbi->hsync_time = htime;
591}
592
593unsigned long pxafb_get_hsync_time(struct device *dev)
594{
595 struct pxafb_info *fbi = dev_get_drvdata(dev);
596
597 /* If display is blanked/suspended, hsync isn't active */
598 if (!fbi || (fbi->state != C_ENABLE))
599 return 0;
600
601 return fbi->hsync_time;
602}
603EXPORT_SYMBOL(pxafb_get_hsync_time);
604
2c42dd8e 605static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
606 unsigned int offset, size_t size)
607{
608 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
609 unsigned int dma_desc_off, pal_desc_off;
610
611 if (dma < 0 || dma >= DMA_MAX)
612 return -EINVAL;
613
614 dma_desc = &fbi->dma_buff->dma_desc[dma];
615 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
616
617 dma_desc->fsadr = fbi->screen_dma + offset;
618 dma_desc->fidr = 0;
619 dma_desc->ldcmd = size;
620
621 if (pal < 0 || pal >= PAL_MAX) {
622 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
623 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
624 } else {
62cfcf4f
JS		 625 pal_desc = &fbi->dma_buff->pal_desc[pal];
626 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
2c42dd8e 627
628 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
629 pal_desc->fidr = 0;
630
631 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
632 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
633 else
634 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
635
636 pal_desc->ldcmd |= LDCMD_PAL;
637
638 /* flip back and forth between palette and frame buffer */
639 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
640 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
641 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
642 }
643
644 return 0;
645}
646
3c42a449
EM		 647#ifdef CONFIG_FB_PXA_SMARTPANEL
648static int setup_smart_dma(struct pxafb_info *fbi)
649{
650 struct pxafb_dma_descriptor *dma_desc;
651 unsigned long dma_desc_off, cmd_buff_off;
652
653 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
654 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
655 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
656
657 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
658 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
659 dma_desc->fidr = 0;
660 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
661
662 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
663 return 0;
664}
665
666int pxafb_smart_flush(struct fb_info *info)
667{
668 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
669 uint32_t prsr;
670 int ret = 0;
671
672 /* disable controller until all registers are set up */
673 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
674
675 /* 1. make it an even number of commands to align on 32-bit boundary
676 * 2. add the interrupt command to the end of the chain so we can
677 * keep track of the end of the transfer
678 */
679
680 while (fbi->n_smart_cmds & 1)
681 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
682
683 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
684 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
685 setup_smart_dma(fbi);
686
687 /* continue to execute next command */
688 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
689 lcd_writel(fbi, PRSR, prsr);
690
691 /* stop the processor in case it executed "wait for sync" cmd */
692 lcd_writel(fbi, CMDCR, 0x0001);
693
694 /* don't send interrupts for fifo underruns on channel 6 */
695 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
696
697 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
698 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
699 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
700 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
701 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
702
703 /* begin sending */
704 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
705
706 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
707 pr_warning("%s: timeout waiting for command done\n",
708 __func__);
709 ret = -ETIMEDOUT;
710 }
711
712 /* quick disable */
713 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
714 lcd_writel(fbi, PRSR, prsr);
715 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
716 lcd_writel(fbi, FDADR6, 0);
717 fbi->n_smart_cmds = 0;
718 return ret;
719}
720
721int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
722{
723 int i;
724 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
725
69bdea70
EM		 726 for (i = 0; i < n_cmds; i++, cmds++) {
727 /* if it is a software delay, flush and delay */
728 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
729 pxafb_smart_flush(info);
730 mdelay(*cmds & 0xff);
731 continue;
732 }
733
734 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
3c42a449
EM		 735 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
736 pxafb_smart_flush(info);
737
69bdea70 738 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
3c42a449
EM		 739 }
740
741 return 0;
742}
743
744static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
745{
746 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
747 return (t == 0) ? 1 : t;
748}
749
750static void setup_smart_timing(struct pxafb_info *fbi,
751 struct fb_var_screeninfo *var)
752{
753 struct pxafb_mach_info *inf = fbi->dev->platform_data;
754 struct pxafb_mode_info *mode = &inf->modes[0];
755 unsigned long lclk = clk_get_rate(fbi->clk);
756 unsigned t1, t2, t3, t4;
757
758 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
759 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
760 t3 = mode->op_hold_time;
761 t4 = mode->cmd_inh_time;
762
763 fbi->reg_lccr1 =
764 LCCR1_DisWdth(var->xres) |
765 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
766 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
767 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
768
769 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
c1f99c21
EM		 770 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
771 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
772 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
3c42a449
EM		 773
774 /* FIXME: make this configurable */
775 fbi->reg_cmdcr = 1;
776}
777
778static int pxafb_smart_thread(void *arg)
779{
7f1133cb 780 struct pxafb_info *fbi = arg;
3c42a449
EM		 781 struct pxafb_mach_info *inf = fbi->dev->platform_data;
782
783 if (!fbi || !inf->smart_update) {
784 pr_err("%s: not properly initialized, thread terminated\n",
785 __func__);
786 return -EINVAL;
787 }
788
789 pr_debug("%s(): task starting\n", __func__);
790
791 set_freezable();
792 while (!kthread_should_stop()) {
793
794 if (try_to_freeze())
795 continue;
796
797 if (fbi->state == C_ENABLE) {
798 inf->smart_update(&fbi->fb);
799 complete(&fbi->refresh_done);
800 }
801
802 set_current_state(TASK_INTERRUPTIBLE);
803 schedule_timeout(30 * HZ / 1000);
804 }
805
806 pr_debug("%s(): task ending\n", __func__);
807 return 0;
808}
809
810static int pxafb_smart_init(struct pxafb_info *fbi)
811{
07df1c4f 812 if (!(fbi->lccr0 & LCCR0_LCDT))
6cc4abe4
EM		 813 return 0;
814
07df1c4f
EM		 815 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
816 fbi->n_smart_cmds = 0;
817
818 init_completion(&fbi->command_done);
819 init_completion(&fbi->refresh_done);
820
3c42a449
EM		 821 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
822 "lcd_refresh");
823 if (IS_ERR(fbi->smart_thread)) {
07df1c4f 824 pr_err("%s: unable to create kernel thread\n", __func__);
3c42a449
EM		 825 return PTR_ERR(fbi->smart_thread);
826 }
a5718a14 827
3c42a449
EM		 828 return 0;
829}
830#else
831int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
832{
833 return 0;
834}
835
836int pxafb_smart_flush(struct fb_info *info)
837{
838 return 0;
839}
07df1c4f
EM		 840
841static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
842#endif /* CONFIG_FB_PXA_SMARTPANEL */
3c42a449 843
90eabbf0
EM		 844static void setup_parallel_timing(struct pxafb_info *fbi,
845 struct fb_var_screeninfo *var)
846{
847 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
848
849 fbi->reg_lccr1 =
850 LCCR1_DisWdth(var->xres) +
851 LCCR1_HorSnchWdth(var->hsync_len) +
852 LCCR1_BegLnDel(var->left_margin) +
853 LCCR1_EndLnDel(var->right_margin);
854
855 /*
856 * If we have a dual scan LCD, we need to halve
857 * the YRES parameter.
858 */
859 lines_per_panel = var->yres;
860 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
861 lines_per_panel /= 2;
862
863 fbi->reg_lccr2 =
864 LCCR2_DisHght(lines_per_panel) +
865 LCCR2_VrtSnchWdth(var->vsync_len) +
866 LCCR2_BegFrmDel(var->upper_margin) +
867 LCCR2_EndFrmDel(var->lower_margin);
868
869 fbi->reg_lccr3 = fbi->lccr3 |
870 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
871 LCCR3_HorSnchH : LCCR3_HorSnchL) |
872 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
873 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
874
875 if (pcd) {
876 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
877 set_hsync_time(fbi, pcd);
878 }
879}
880
1da177e4
LT		 881/*
882 * pxafb_activate_var():
b0086efb 883 * Configures LCD Controller based on entries in var parameter.
884 * Settings are only written to the controller if changes were made.
1da177e4 885 */
b0086efb 886static int pxafb_activate_var(struct fb_var_screeninfo *var,
887 struct pxafb_info *fbi)
1da177e4 888{
1da177e4 889 u_long flags;
2c42dd8e 890 size_t nbytes;
1da177e4 891
1da177e4 892#if DEBUG_VAR
3c42a449
EM		 893 if (!(fbi->lccr0 & LCCR0_LCDT)) {
894 if (var->xres < 16 || var->xres > 1024)
895 printk(KERN_ERR "%s: invalid xres %d\n",
896 fbi->fb.fix.id, var->xres);
897 switch (var->bits_per_pixel) {
898 case 1:
899 case 2:
900 case 4:
901 case 8:
902 case 16:
c1450f15
SS		 903 case 24:
904 case 32:
3c42a449
EM		 905 break;
906 default:
907 printk(KERN_ERR "%s: invalid bit depth %d\n",
908 fbi->fb.fix.id, var->bits_per_pixel);
909 break;
910 }
911
912 if (var->hsync_len < 1 || var->hsync_len > 64)
913 printk(KERN_ERR "%s: invalid hsync_len %d\n",
914 fbi->fb.fix.id, var->hsync_len);
915 if (var->left_margin < 1 || var->left_margin > 255)
916 printk(KERN_ERR "%s: invalid left_margin %d\n",
917 fbi->fb.fix.id, var->left_margin);
918 if (var->right_margin < 1 || var->right_margin > 255)
919 printk(KERN_ERR "%s: invalid right_margin %d\n",
920 fbi->fb.fix.id, var->right_margin);
921 if (var->yres < 1 || var->yres > 1024)
922 printk(KERN_ERR "%s: invalid yres %d\n",
923 fbi->fb.fix.id, var->yres);
924 if (var->vsync_len < 1 || var->vsync_len > 64)
925 printk(KERN_ERR "%s: invalid vsync_len %d\n",
926 fbi->fb.fix.id, var->vsync_len);
927 if (var->upper_margin < 0 || var->upper_margin > 255)
928 printk(KERN_ERR "%s: invalid upper_margin %d\n",
929 fbi->fb.fix.id, var->upper_margin);
930 if (var->lower_margin < 0 || var->lower_margin > 255)
931 printk(KERN_ERR "%s: invalid lower_margin %d\n",
932 fbi->fb.fix.id, var->lower_margin);
1da177e4 933 }
1da177e4 934#endif
90eabbf0
EM		 935 /* Update shadow copy atomically */
936 local_irq_save(flags);
1da177e4 937
3c42a449
EM		 938#ifdef CONFIG_FB_PXA_SMARTPANEL
939 if (fbi->lccr0 & LCCR0_LCDT)
940 setup_smart_timing(fbi, var);
941 else
942#endif
943 setup_parallel_timing(fbi, var);
90eabbf0
EM		 944
945 fbi->reg_lccr0 = fbi->lccr0 |
1da177e4 946 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 947 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4 948
90eabbf0 949 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
1da177e4 950
90eabbf0 951 nbytes = var->yres * fbi->fb.fix.line_length;
1da177e4 952
90eabbf0
EM		 953 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
954 nbytes = nbytes / 2;
2c42dd8e 955 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
90eabbf0 956 }
2c42dd8e 957
3c42a449 958 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
2c42dd8e 959 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
960 else
961 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
1da177e4 962
a7535ba7 963 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 964 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1da177e4
LT		 965 local_irq_restore(flags);
966
967 /*
968 * Only update the registers if the controller is enabled
969 * and something has changed.
970 */
a7535ba7
EM		 971 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
972 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
973 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
974 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
975 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
976 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1da177e4
LT		 977 pxafb_schedule_work(fbi, C_REENABLE);
978
979 return 0;
980}
981
982/*
983 * NOTE! The following functions are purely helpers for set_ctrlr_state.
984 * Do not call them directly; set_ctrlr_state does the correct serialisation
985 * to ensure that things happen in the right way 100% of time time.
986 * -- rmk
987 */
988static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
989{
ca5da710 990 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 991
a5718a14
EM		 992 if (fbi->backlight_power)
993 fbi->backlight_power(on);
1da177e4
LT		 994}
995
996static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
997{
ca5da710 998 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4 999
a5718a14
EM		 1000 if (fbi->lcd_power)
1001 fbi->lcd_power(on, &fbi->fb.var);
1da177e4
LT		 1002}
1003
1da177e4
LT		 1004static void pxafb_enable_controller(struct pxafb_info *fbi)
1005{
ca5da710 1006 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 1007 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1008 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 1009 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1010 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1011 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1012 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 1013
8d372266 1014 /* enable LCD controller clock */
72e3524c 1015 clk_enable(fbi->clk);
8d372266 1016
3c42a449
EM		 1017 if (fbi->lccr0 & LCCR0_LCDT)
1018 return;
1019
1da177e4 1020 /* Sequence from 11.7.10 */
a7535ba7
EM		 1021 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1022 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1023 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1024 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1025
1026 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1027 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1028 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 1029}
1030
1031static void pxafb_disable_controller(struct pxafb_info *fbi)
1032{
ce4fb7b8 1033 uint32_t lccr0;
1034
3c42a449
EM		 1035#ifdef CONFIG_FB_PXA_SMARTPANEL
1036 if (fbi->lccr0 & LCCR0_LCDT) {
1037 wait_for_completion_timeout(&fbi->refresh_done,
1038 200 * HZ / 1000);
1039 return;
1040 }
1041#endif
1042
ce4fb7b8 1043 /* Clear LCD Status Register */
a7535ba7 1044 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 1045
a7535ba7
EM		 1046 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1047 lcd_writel(fbi, LCCR0, lccr0);
1048 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 1049
2ba162b9 1050 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
8d372266
NP		 1051
1052 /* disable LCD controller clock */
72e3524c 1053 clk_disable(fbi->clk);
1da177e4
LT		 1054}
1055
1056/*
1057 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1058 */
7d12e780 1059static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 1060{
1061 struct pxafb_info *fbi = dev_id;
a7535ba7 1062 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1da177e4
LT		 1063
1064 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 1065 lccr0 = lcd_readl(fbi, LCCR0);
1066 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
2ba162b9 1067 complete(&fbi->disable_done);
1da177e4
LT		 1068 }
1069
3c42a449
EM		 1070#ifdef CONFIG_FB_PXA_SMARTPANEL
1071 if (lcsr & LCSR_CMD_INT)
1072 complete(&fbi->command_done);
1073#endif
1074
a7535ba7 1075 lcd_writel(fbi, LCSR, lcsr);
1da177e4
LT		 1076 return IRQ_HANDLED;
1077}
1078
1079/*
1080 * This function must be called from task context only, since it will
1081 * sleep when disabling the LCD controller, or if we get two contending
1082 * processes trying to alter state.
1083 */
1084static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1085{
1086 u_int old_state;
1087
b91dbce5 1088 mutex_lock(&fbi->ctrlr_lock);
1da177e4
LT		 1089
1090 old_state = fbi->state;
1091
1092 /*
1093 * Hack around fbcon initialisation.
1094 */
1095 if (old_state == C_STARTUP && state == C_REENABLE)
1096 state = C_ENABLE;
1097
1098 switch (state) {
1099 case C_DISABLE_CLKCHANGE:
1100 /*
1101 * Disable controller for clock change. If the
1102 * controller is already disabled, then do nothing.
1103 */
1104 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1105 fbi->state = state;
b0086efb 1106 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 1107 pxafb_disable_controller(fbi);
1108 }
1109 break;
1110
1111 case C_DISABLE_PM:
1112 case C_DISABLE:
1113 /*
1114 * Disable controller
1115 */
1116 if (old_state != C_DISABLE) {
1117 fbi->state = state;
1118 __pxafb_backlight_power(fbi, 0);
1119 __pxafb_lcd_power(fbi, 0);
1120 if (old_state != C_DISABLE_CLKCHANGE)
1121 pxafb_disable_controller(fbi);
1122 }
1123 break;
1124
1125 case C_ENABLE_CLKCHANGE:
1126 /*
1127 * Enable the controller after clock change. Only
1128 * do this if we were disabled for the clock change.
1129 */
1130 if (old_state == C_DISABLE_CLKCHANGE) {
1131 fbi->state = C_ENABLE;
1132 pxafb_enable_controller(fbi);
b0086efb 1133 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 1134 }
1135 break;
1136
1137 case C_REENABLE:
1138 /*
1139 * Re-enable the controller only if it was already
1140 * enabled. This is so we reprogram the control
1141 * registers.
1142 */
1143 if (old_state == C_ENABLE) {
d14b272b 1144 __pxafb_lcd_power(fbi, 0);
1da177e4 1145 pxafb_disable_controller(fbi);
1da177e4 1146 pxafb_enable_controller(fbi);
d14b272b 1147 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 1148 }
1149 break;
1150
1151 case C_ENABLE_PM:
1152 /*
1153 * Re-enable the controller after PM. This is not
1154 * perfect - think about the case where we were doing
1155 * a clock change, and we suspended half-way through.
1156 */
1157 if (old_state != C_DISABLE_PM)
1158 break;
1159 /* fall through */
1160
1161 case C_ENABLE:
1162 /*
1163 * Power up the LCD screen, enable controller, and
1164 * turn on the backlight.
1165 */
1166 if (old_state != C_ENABLE) {
1167 fbi->state = C_ENABLE;
1da177e4
LT		 1168 pxafb_enable_controller(fbi);
1169 __pxafb_lcd_power(fbi, 1);
1170 __pxafb_backlight_power(fbi, 1);
1171 }
1172 break;
1173 }
b91dbce5 1174 mutex_unlock(&fbi->ctrlr_lock);
1da177e4
LT		 1175}
1176
1177/*
1178 * Our LCD controller task (which is called when we blank or unblank)
1179 * via keventd.
1180 */
6d5aefb8 1181static void pxafb_task(struct work_struct *work)
1da177e4 1182{
6d5aefb8
DH		 1183 struct pxafb_info *fbi =
1184 container_of(work, struct pxafb_info, task);
1da177e4
LT		 1185 u_int state = xchg(&fbi->task_state, -1);
1186
1187 set_ctrlr_state(fbi, state);
1188}
1189
1190#ifdef CONFIG_CPU_FREQ
1191/*
1192 * CPU clock speed change handler. We need to adjust the LCD timing
1193 * parameters when the CPU clock is adjusted by the power management
1194 * subsystem.
1195 *
1196 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1197 */
1198static int
1199pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1200{
1201 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 1202 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 1203 u_int pcd;
1204
1205 switch (val) {
1206 case CPUFREQ_PRECHANGE:
1207 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1208 break;
1209
1210 case CPUFREQ_POSTCHANGE:
72e3524c 1211 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 1212 set_hsync_time(fbi, pcd);
b0086efb 1213 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1214 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 1215 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1216 break;
1217 }
1218 return 0;
1219}
1220
1221static int
1222pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1223{
1224 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1225 struct fb_var_screeninfo *var = &fbi->fb.var;
1226 struct cpufreq_policy *policy = data;
1227
1228 switch (val) {
1229 case CPUFREQ_ADJUST:
1230 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1231 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1232 "new clock %d kHz\n", pxafb_display_dma_period(var),
1233 policy->max);
b0086efb 1234 /* TODO: fill in min/max values */
1da177e4 1235 break;
1da177e4
LT		 1236 }
1237 return 0;
1238}
1239#endif
1240
1241#ifdef CONFIG_PM
1242/*
1243 * Power management hooks. Note that we won't be called from IRQ context,
1244 * unlike the blank functions above, so we may sleep.
1245 */
3ae5eaec 1246static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1247{
3ae5eaec 1248 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1249
9480e307 1250 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1251 return 0;
1252}
1253
3ae5eaec 1254static int pxafb_resume(struct platform_device *dev)
1da177e4 1255{
3ae5eaec 1256 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1257
9480e307 1258 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1259 return 0;
1260}
1261#else
1262#define pxafb_suspend NULL
1263#define pxafb_resume NULL
1264#endif
1265
1266/*
1267 * pxafb_map_video_memory():
1268 * Allocates the DRAM memory for the frame buffer. This buffer is
1269 * remapped into a non-cached, non-buffered, memory region to
1270 * allow palette and pixel writes to occur without flushing the
1271 * cache. Once this area is remapped, all virtual memory
1272 * access to the video memory should occur at the new region.
1273 */
9e6c2976 1274static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1da177e4 1275{
1da177e4
LT		 1276 /*
1277 * We reserve one page for the palette, plus the size
1278 * of the framebuffer.
1279 */
3c42a449
EM		 1280 fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1281 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1da177e4
LT		 1282 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1283 &fbi->map_dma, GFP_KERNEL);
1284
1285 if (fbi->map_cpu) {
1286 /* prevent initial garbage on screen */
1287 memset(fbi->map_cpu, 0, fbi->map_size);
3c42a449
EM		 1288 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1289 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1290
1da177e4
LT		 1291 /*
1292 * FIXME: this is actually the wrong thing to place in
1293 * smem_start. But fbdev suffers from the problem that
1294 * it needs an API which doesn't exist (in this case,
1295 * dma_writecombine_mmap)
1296 */
1297 fbi->fb.fix.smem_start = fbi->screen_dma;
1da177e4
LT		 1298 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1299
3c42a449 1300 fbi->dma_buff = (void *) fbi->map_cpu;
2c42dd8e 1301 fbi->dma_buff_phys = fbi->map_dma;
3c42a449
EM		 1302 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1303
e84e954a 1304 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
1da177e4
LT		 1305 }
1306
1307 return fbi->map_cpu ? 0 : -ENOMEM;
1308}
1309
84f43c30 1310static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1311 struct pxafb_mode_info *modes,
1312 unsigned int num_modes)
1313{
1314 unsigned int i, smemlen;
1315
1316 pxafb_setmode(&fbi->fb.var, &modes[0]);
1317
1318 for (i = 0; i < num_modes; i++) {
1319 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1320 if (smemlen > fbi->fb.fix.smem_len)
1321 fbi->fb.fix.smem_len = smemlen;
1322 }
1323}
1324
ebdf982a
GL		 1325static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1326 struct pxafb_mach_info *inf)
84f43c30 1327{
1328 unsigned int lcd_conn = inf->lcd_conn;
1329
1330 fbi->cmap_inverse = inf->cmap_inverse;
1331 fbi->cmap_static = inf->cmap_static;
1332
1ec26db1 1333 switch (lcd_conn & LCD_TYPE_MASK) {
84f43c30 1334 case LCD_TYPE_MONO_STN:
1335 fbi->lccr0 = LCCR0_CMS;
1336 break;
1337 case LCD_TYPE_MONO_DSTN:
1338 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1339 break;
1340 case LCD_TYPE_COLOR_STN:
1341 fbi->lccr0 = 0;
1342 break;
1343 case LCD_TYPE_COLOR_DSTN:
1344 fbi->lccr0 = LCCR0_SDS;
1345 break;
1346 case LCD_TYPE_COLOR_TFT:
1347 fbi->lccr0 = LCCR0_PAS;
1348 break;
1349 case LCD_TYPE_SMART_PANEL:
1350 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1351 break;
1352 default:
1353 /* fall back to backward compatibility way */
1354 fbi->lccr0 = inf->lccr0;
1355 fbi->lccr3 = inf->lccr3;
1356 fbi->lccr4 = inf->lccr4;
ebdf982a 1357 goto decode_mode;
84f43c30 1358 }
1359
1360 if (lcd_conn == LCD_MONO_STN_8BPP)
1361 fbi->lccr0 |= LCCR0_DPD;
1362
9a1ac7e4
EM		 1363 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1364
84f43c30 1365 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1366 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1367 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1368
ebdf982a 1369decode_mode:
84f43c30 1370 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
84f43c30 1371}
1372
9e6c2976 1373static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1da177e4
LT		 1374{
1375 struct pxafb_info *fbi;
1376 void *addr;
1377 struct pxafb_mach_info *inf = dev->platform_data;
1378
1379 /* Alloc the pxafb_info and pseudo_palette in one step */
1380 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1381 if (!fbi)
1382 return NULL;
1383
1384 memset(fbi, 0, sizeof(struct pxafb_info));
1385 fbi->dev = dev;
1386
72e3524c
RK		 1387 fbi->clk = clk_get(dev, "LCDCLK");
1388 if (IS_ERR(fbi->clk)) {
1389 kfree(fbi);
1390 return NULL;
1391 }
1392
1da177e4
LT		 1393 strcpy(fbi->fb.fix.id, PXA_NAME);
1394
1395 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1396 fbi->fb.fix.type_aux = 0;
1397 fbi->fb.fix.xpanstep = 0;
1398 fbi->fb.fix.ypanstep = 0;
1399 fbi->fb.fix.ywrapstep = 0;
1400 fbi->fb.fix.accel = FB_ACCEL_NONE;
1401
1402 fbi->fb.var.nonstd = 0;
1403 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1404 fbi->fb.var.height = -1;
1405 fbi->fb.var.width = -1;
1406 fbi->fb.var.accel_flags = 0;
1407 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1408
1409 fbi->fb.fbops = &pxafb_ops;
1410 fbi->fb.flags = FBINFO_DEFAULT;
1411 fbi->fb.node = -1;
1412
1413 addr = fbi;
1414 addr = addr + sizeof(struct pxafb_info);
1415 fbi->fb.pseudo_palette = addr;
1416
b0086efb 1417 fbi->state = C_STARTUP;
1418 fbi->task_state = (u_char)-1;
d14b272b 1419
84f43c30 1420 pxafb_decode_mach_info(fbi, inf);
1da177e4
LT		 1421
1422 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1423 INIT_WORK(&fbi->task, pxafb_task);
b91dbce5 1424 mutex_init(&fbi->ctrlr_lock);
2ba162b9 1425 init_completion(&fbi->disable_done);
1da177e4
LT		 1426
1427 return fbi;
1428}
1429
1430#ifdef CONFIG_FB_PXA_PARAMETERS
9e6c2976 1431static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1432{
1433 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1434
1435 const char *name = this_opt+5;
1436 unsigned int namelen = strlen(name);
1437 int res_specified = 0, bpp_specified = 0;
1438 unsigned int xres = 0, yres = 0, bpp = 0;
1439 int yres_specified = 0;
1440 int i;
1441 for (i = namelen-1; i >= 0; i--) {
1442 switch (name[i]) {
1443 case '-':
1444 namelen = i;
1445 if (!bpp_specified && !yres_specified) {
1446 bpp = simple_strtoul(&name[i+1], NULL, 0);
1447 bpp_specified = 1;
1448 } else
1449 goto done;
1450 break;
1451 case 'x':
1452 if (!yres_specified) {
1453 yres = simple_strtoul(&name[i+1], NULL, 0);
1454 yres_specified = 1;
1455 } else
1456 goto done;
1457 break;
1458 case '0' ... '9':
1459 break;
1460 default:
1461 goto done;
1462 }
1463 }
1464 if (i < 0 && yres_specified) {
1465 xres = simple_strtoul(name, NULL, 0);
1466 res_specified = 1;
1467 }
1468done:
1469 if (res_specified) {
1470 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1471 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1472 }
1473 if (bpp_specified)
1474 switch (bpp) {
1475 case 1:
1476 case 2:
1477 case 4:
1478 case 8:
1479 case 16:
1480 inf->modes[0].bpp = bpp;
1481 dev_info(dev, "overriding bit depth: %d\n", bpp);
1482 break;
1483 default:
1484 dev_err(dev, "Depth %d is not valid\n", bpp);
1485 return -EINVAL;
1486 }
1487 return 0;
1488}
1489
9e6c2976 1490static int __devinit parse_opt(struct device *dev, char *this_opt)
817daf14 1491{
1492 struct pxafb_mach_info *inf = dev->platform_data;
1493 struct pxafb_mode_info *mode = &inf->modes[0];
1494 char s[64];
1495
1496 s[0] = '\0';
1497
1498 if (!strncmp(this_opt, "mode:", 5)) {
1499 return parse_opt_mode(dev, this_opt);
1500 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1501 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1502 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1503 } else if (!strncmp(this_opt, "left:", 5)) {
1504 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1505 sprintf(s, "left: %u\n", mode->left_margin);
1506 } else if (!strncmp(this_opt, "right:", 6)) {
1507 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1508 sprintf(s, "right: %u\n", mode->right_margin);
1509 } else if (!strncmp(this_opt, "upper:", 6)) {
1510 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1511 sprintf(s, "upper: %u\n", mode->upper_margin);
1512 } else if (!strncmp(this_opt, "lower:", 6)) {
1513 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1514 sprintf(s, "lower: %u\n", mode->lower_margin);
1515 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1516 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1517 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1518 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1519 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1520 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1521 } else if (!strncmp(this_opt, "hsync:", 6)) {
1522 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1523 sprintf(s, "hsync: Active Low\n");
1524 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1525 } else {
1526 sprintf(s, "hsync: Active High\n");
1527 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1528 }
1529 } else if (!strncmp(this_opt, "vsync:", 6)) {
1530 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1531 sprintf(s, "vsync: Active Low\n");
1532 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1533 } else {
1534 sprintf(s, "vsync: Active High\n");
1535 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1536 }
1537 } else if (!strncmp(this_opt, "dpc:", 4)) {
1538 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1539 sprintf(s, "double pixel clock: false\n");
1540 inf->lccr3 &= ~LCCR3_DPC;
1541 } else {
1542 sprintf(s, "double pixel clock: true\n");
1543 inf->lccr3 |= LCCR3_DPC;
1544 }
1545 } else if (!strncmp(this_opt, "outputen:", 9)) {
1546 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1547 sprintf(s, "output enable: active low\n");
1548 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1549 } else {
1550 sprintf(s, "output enable: active high\n");
1551 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1552 }
1553 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1554 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1555 sprintf(s, "pixel clock polarity: falling edge\n");
1556 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1557 } else {
1558 sprintf(s, "pixel clock polarity: rising edge\n");
1559 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1560 }
1561 } else if (!strncmp(this_opt, "color", 5)) {
1562 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1563 } else if (!strncmp(this_opt, "mono", 4)) {
1564 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1565 } else if (!strncmp(this_opt, "active", 6)) {
1566 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1567 } else if (!strncmp(this_opt, "passive", 7)) {
1568 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1569 } else if (!strncmp(this_opt, "single", 6)) {
1570 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1571 } else if (!strncmp(this_opt, "dual", 4)) {
1572 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1573 } else if (!strncmp(this_opt, "4pix", 4)) {
1574 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1575 } else if (!strncmp(this_opt, "8pix", 4)) {
1576 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1577 } else {
1578 dev_err(dev, "unknown option: %s\n", this_opt);
1579 return -EINVAL;
1580 }
1581
1582 if (s[0] != '\0')
1583 dev_info(dev, "override %s", s);
1584
1585 return 0;
1586}
1587
9e6c2976 1588static int __devinit pxafb_parse_options(struct device *dev, char *options)
817daf14 1589{
1da177e4 1590 char *this_opt;
817daf14 1591 int ret;
1da177e4 1592
817daf14 1593 if (!options || !*options)
1594 return 0;
1da177e4
LT		 1595
1596 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1597
1598 /* could be made table driven or similar?... */
817daf14 1599 while ((this_opt = strsep(&options, ",")) != NULL) {
1600 ret = parse_opt(dev, this_opt);
1601 if (ret)
1602 return ret;
1603 }
1604 return 0;
1da177e4 1605}
92ac73c1 1606
1607static char g_options[256] __devinitdata = "";
1608
f1edfc42 1609#ifndef MODULE
9e6c2976 1610static int __init pxafb_setup_options(void)
92ac73c1 1611{
1612 char *options = NULL;
1613
1614 if (fb_get_options("pxafb", &options))
1615 return -ENODEV;
1616
1617 if (options)
1618 strlcpy(g_options, options, sizeof(g_options));
1619
1620 return 0;
1621}
1622#else
1623#define pxafb_setup_options() (0)
1624
1625module_param_string(options, g_options, sizeof(g_options), 0);
1626MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1627#endif
1628
1629#else
1630#define pxafb_parse_options(...) (0)
1631#define pxafb_setup_options() (0)
1da177e4
LT		 1632#endif
1633
1da177e4 1634#ifdef DEBUG_VAR
4f3e2664
EM		 1635/* Check for various illegal bit-combinations. Currently only
1636 * a warning is given. */
1637static void __devinit pxafb_check_options(struct device *dev,
1638 struct pxafb_mach_info *inf)
1639{
1640 if (inf->lcd_conn)
1641 return;
1da177e4 1642
b0086efb 1643 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
4f3e2664 1644 dev_warn(dev, "machine LCCR0 setting contains "
b0086efb 1645 "illegal bits: %08x\n",
1646 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1647 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
4f3e2664 1648 dev_warn(dev, "machine LCCR3 setting contains "
b0086efb 1649 "illegal bits: %08x\n",
1650 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1651 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 1652 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1653 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1654 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
4f3e2664 1655 dev_warn(dev, "Double Pixel Data (DPD) mode is "
b0086efb 1656 "only valid in passive mono"
1657 " single panel mode\n");
1658 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 1659 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
4f3e2664 1660 dev_warn(dev, "Dual panel only valid in passive mode\n");
b0086efb 1661 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1662 (inf->modes->upper_margin || inf->modes->lower_margin))
4f3e2664 1663 dev_warn(dev, "Upper and lower margins must be 0 in "
b0086efb 1664 "passive mode\n");
4f3e2664
EM		 1665}
1666#else
1667#define pxafb_check_options(...) do {} while (0)
1da177e4
LT		 1668#endif
1669
4f3e2664
EM		 1670static int __devinit pxafb_probe(struct platform_device *dev)
1671{
1672 struct pxafb_info *fbi;
1673 struct pxafb_mach_info *inf;
1674 struct resource *r;
1675 int irq, ret;
1676
1677 dev_dbg(&dev->dev, "pxafb_probe\n");
1678
1679 inf = dev->dev.platform_data;
1680 ret = -ENOMEM;
1681 fbi = NULL;
1682 if (!inf)
1683 goto failed;
1684
1685 ret = pxafb_parse_options(&dev->dev, g_options);
1686 if (ret < 0)
1687 goto failed;
1688
1689 pxafb_check_options(&dev->dev, inf);
1690
b0086efb 1691 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1692 inf->modes->xres,
1693 inf->modes->yres,
1694 inf->modes->bpp);
1695 if (inf->modes->xres == 0 ||
1696 inf->modes->yres == 0 ||
1697 inf->modes->bpp == 0) {
3ae5eaec 1698 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 1699 ret = -EINVAL;
1700 goto failed;
1701 }
a5718a14 1702
3ae5eaec 1703 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 1704 if (!fbi) {
b0086efb 1705 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 1706 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 1707 ret = -ENOMEM;
1da177e4
LT		 1708 goto failed;
1709 }
1710
a5718a14
EM		 1711 fbi->backlight_power = inf->pxafb_backlight_power;
1712 fbi->lcd_power = inf->pxafb_lcd_power;
1713
ce4fb7b8 1714 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1715 if (r == NULL) {
1716 dev_err(&dev->dev, "no I/O memory resource defined\n");
1717 ret = -ENODEV;
ee98476b 1718 goto failed_fbi;
ce4fb7b8 1719 }
1720
1721 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1722 if (r == NULL) {
1723 dev_err(&dev->dev, "failed to request I/O memory\n");
1724 ret = -EBUSY;
ee98476b 1725 goto failed_fbi;
ce4fb7b8 1726 }
1727
1728 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1729 if (fbi->mmio_base == NULL) {
1730 dev_err(&dev->dev, "failed to map I/O memory\n");
1731 ret = -EBUSY;
1732 goto failed_free_res;
1733 }
1734
1da177e4
LT		 1735 /* Initialize video memory */
1736 ret = pxafb_map_video_memory(fbi);
1737 if (ret) {
3ae5eaec 1738 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 1739 ret = -ENOMEM;
ce4fb7b8 1740 goto failed_free_io;
1da177e4 1741 }
1da177e4 1742
ce4fb7b8 1743 irq = platform_get_irq(dev, 0);
1744 if (irq < 0) {
1745 dev_err(&dev->dev, "no IRQ defined\n");
1746 ret = -ENODEV;
1747 goto failed_free_mem;
1748 }
1749
1750 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1da177e4 1751 if (ret) {
3ae5eaec 1752 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 1753 ret = -EBUSY;
ce4fb7b8 1754 goto failed_free_mem;
1da177e4
LT		 1755 }
1756
3c42a449
EM		 1757 ret = pxafb_smart_init(fbi);
1758 if (ret) {
1759 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1760 goto failed_free_irq;
1761 }
07df1c4f 1762
1da177e4
LT		 1763 /*
1764 * This makes sure that our colour bitfield
1765 * descriptors are correctly initialised.
1766 */
ee98476b
JK		 1767 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1768 if (ret) {
1769 dev_err(&dev->dev, "failed to get suitable mode\n");
1770 goto failed_free_irq;
1771 }
1772
1773 ret = pxafb_set_par(&fbi->fb);
1774 if (ret) {
1775 dev_err(&dev->dev, "Failed to set parameters\n");
1776 goto failed_free_irq;
1777 }
1da177e4 1778
3ae5eaec 1779 platform_set_drvdata(dev, fbi);
1da177e4
LT		 1780
1781 ret = register_framebuffer(&fbi->fb);
1782 if (ret < 0) {
b0086efb 1783 dev_err(&dev->dev,
1784 "Failed to register framebuffer device: %d\n", ret);
ee98476b 1785 goto failed_free_cmap;
1da177e4
LT		 1786 }
1787
1da177e4
LT		 1788#ifdef CONFIG_CPU_FREQ
1789 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1790 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 1791 cpufreq_register_notifier(&fbi->freq_transition,
1792 CPUFREQ_TRANSITION_NOTIFIER);
1793 cpufreq_register_notifier(&fbi->freq_policy,
1794 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 1795#endif
1796
1797 /*
1798 * Ok, now enable the LCD controller
1799 */
1800 set_ctrlr_state(fbi, C_ENABLE);
1801
1802 return 0;
1803
ee98476b
JK		 1804failed_free_cmap:
1805 if (fbi->fb.cmap.len)
1806 fb_dealloc_cmap(&fbi->fb.cmap);
ce4fb7b8 1807failed_free_irq:
1808 free_irq(irq, fbi);
ce4fb7b8 1809failed_free_mem:
1810 dma_free_writecombine(&dev->dev, fbi->map_size,
1811 fbi->map_cpu, fbi->map_dma);
ee98476b
JK		 1812failed_free_io:
1813 iounmap(fbi->mmio_base);
1814failed_free_res:
1815 release_mem_region(r->start, r->end - r->start + 1);
1816failed_fbi:
1817 clk_put(fbi->clk);
3ae5eaec 1818 platform_set_drvdata(dev, NULL);
1da177e4 1819 kfree(fbi);
ee98476b 1820failed:
1da177e4
LT		 1821 return ret;
1822}
1823
9f17f287
JK		 1824static int __devexit pxafb_remove(struct platform_device *dev)
1825{
1826 struct pxafb_info *fbi = platform_get_drvdata(dev);
1827 struct resource *r;
1828 int irq;
1829 struct fb_info *info;
1830
1831 if (!fbi)
1832 return 0;
1833
1834 info = &fbi->fb;
1835
1836 unregister_framebuffer(info);
1837
1838 pxafb_disable_controller(fbi);
1839
1840 if (fbi->fb.cmap.len)
1841 fb_dealloc_cmap(&fbi->fb.cmap);
1842
1843 irq = platform_get_irq(dev, 0);
1844 free_irq(irq, fbi);
1845
1846 dma_free_writecombine(&dev->dev, fbi->map_size,
1847 fbi->map_cpu, fbi->map_dma);
1848
1849 iounmap(fbi->mmio_base);
1850
1851 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1852 release_mem_region(r->start, r->end - r->start + 1);
1853
1854 clk_put(fbi->clk);
1855 kfree(fbi);
1856
1857 return 0;
1858}
1859
3ae5eaec 1860static struct platform_driver pxafb_driver = {
1da177e4 1861 .probe = pxafb_probe,
9f17f287 1862 .remove = pxafb_remove,
1da177e4
LT		 1863 .suspend = pxafb_suspend,
1864 .resume = pxafb_resume,
3ae5eaec 1865 .driver = {
9f17f287 1866 .owner = THIS_MODULE,
3ae5eaec
RK		 1867 .name = "pxa2xx-fb",
1868 },
1da177e4
LT		 1869};
1870
9e6c2976 1871static int __init pxafb_init(void)
1da177e4 1872{
92ac73c1 1873 if (pxafb_setup_options())
1874 return -EINVAL;
1da177e4 1875
3ae5eaec 1876 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 1877}
1878
9f17f287
JK		 1879static void __exit pxafb_exit(void)
1880{
1881 platform_driver_unregister(&pxafb_driver);
1882}
1883
1da177e4 1884module_init(pxafb_init);
9f17f287 1885module_exit(pxafb_exit);
1da177e4
LT		 1886
1887MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1888MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)