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[ARM] pxa: add document on the MFP design and how to use it
[linux-2.6-block.git] / drivers / video / pxafb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/errno.h>
30#include <linux/string.h>
31#include <linux/interrupt.h>
32#include <linux/slab.h>
27ac792c 33#include <linux/mm.h>
1da177e4
LT		 34#include <linux/fb.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/ioport.h>
38#include <linux/cpufreq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4 40#include <linux/dma-mapping.h>
72e3524c
RK		 41#include <linux/clk.h>
42#include <linux/err.h>
2ba162b9 43#include <linux/completion.h>
b91dbce5 44#include <linux/mutex.h>
3c42a449
EM		 45#include <linux/kthread.h>
46#include <linux/freezer.h>
1da177e4 47
a09e64fb 48#include <mach/hardware.h>
1da177e4
LT		 49#include <asm/io.h>
50#include <asm/irq.h>
bf1b8ab6 51#include <asm/div64.h>
a09e64fb 52#include <mach/pxa-regs.h>
a09e64fb
RK		 53#include <mach/bitfield.h>
54#include <mach/pxafb.h>
1da177e4
LT		 55
56/*
57 * Complain if VAR is out of range.
58 */
59#define DEBUG_VAR 1
60
61#include "pxafb.h"
62
63/* Bits which should not be set in machine configuration structures */
b0086efb 64#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
67
68#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP)
1da177e4 70
b0086efb 71static int pxafb_activate_var(struct fb_var_screeninfo *var,
72 struct pxafb_info *);
1da177e4
LT		 73static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
74
a7535ba7
EM		 75static inline unsigned long
76lcd_readl(struct pxafb_info *fbi, unsigned int off)
77{
78 return __raw_readl(fbi->mmio_base + off);
79}
80
81static inline void
82lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
83{
84 __raw_writel(val, fbi->mmio_base + off);
85}
86
1da177e4
LT		 87static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
88{
89 unsigned long flags;
90
91 local_irq_save(flags);
92 /*
93 * We need to handle two requests being made at the same time.
94 * There are two important cases:
b0086efb 95 * 1. When we are changing VT (C_REENABLE) while unblanking
96 * (C_ENABLE) We must perform the unblanking, which will
97 * do our REENABLE for us.
98 * 2. When we are blanking, but immediately unblank before
99 * we have blanked. We do the "REENABLE" thing here as
100 * well, just to be sure.
1da177e4
LT		 101 */
102 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
103 state = (u_int) -1;
104 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
105 state = C_REENABLE;
106
107 if (state != (u_int)-1) {
108 fbi->task_state = state;
109 schedule_work(&fbi->task);
110 }
111 local_irq_restore(flags);
112}
113
114static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
115{
116 chan &= 0xffff;
117 chan >>= 16 - bf->length;
118 return chan << bf->offset;
119}
120
121static int
122pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
123 u_int trans, struct fb_info *info)
124{
125 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 126 u_int val;
127
128 if (regno >= fbi->palette_size)
129 return 1;
130
131 if (fbi->fb.var.grayscale) {
132 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
133 return 0;
134 }
135
136 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
137 case LCCR4_PAL_FOR_0:
138 val = ((red >> 0) & 0xf800);
139 val |= ((green >> 5) & 0x07e0);
140 val |= ((blue >> 11) & 0x001f);
1da177e4 141 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 142 break;
143 case LCCR4_PAL_FOR_1:
144 val = ((red << 8) & 0x00f80000);
145 val |= ((green >> 0) & 0x0000fc00);
146 val |= ((blue >> 8) & 0x000000f8);
b0086efb 147 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 148 break;
149 case LCCR4_PAL_FOR_2:
150 val = ((red << 8) & 0x00fc0000);
151 val |= ((green >> 0) & 0x0000fc00);
152 val |= ((blue >> 8) & 0x000000fc);
b0086efb 153 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 154 break;
1da177e4 155 }
9ffa7396
HK		 156
157 return 0;
1da177e4
LT		 158}
159
160static int
161pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
162 u_int trans, struct fb_info *info)
163{
164 struct pxafb_info *fbi = (struct pxafb_info *)info;
165 unsigned int val;
166 int ret = 1;
167
168 /*
169 * If inverse mode was selected, invert all the colours
170 * rather than the register number. The register number
171 * is what you poke into the framebuffer to produce the
172 * colour you requested.
173 */
174 if (fbi->cmap_inverse) {
175 red = 0xffff - red;
176 green = 0xffff - green;
177 blue = 0xffff - blue;
178 }
179
180 /*
181 * If greyscale is true, then we convert the RGB value
182 * to greyscale no matter what visual we are using.
183 */
184 if (fbi->fb.var.grayscale)
185 red = green = blue = (19595 * red + 38470 * green +
186 7471 * blue) >> 16;
187
188 switch (fbi->fb.fix.visual) {
189 case FB_VISUAL_TRUECOLOR:
190 /*
191 * 16-bit True Colour. We encode the RGB value
192 * according to the RGB bitfield information.
193 */
194 if (regno < 16) {
195 u32 *pal = fbi->fb.pseudo_palette;
196
197 val = chan_to_field(red, &fbi->fb.var.red);
198 val |= chan_to_field(green, &fbi->fb.var.green);
199 val |= chan_to_field(blue, &fbi->fb.var.blue);
200
201 pal[regno] = val;
202 ret = 0;
203 }
204 break;
205
206 case FB_VISUAL_STATIC_PSEUDOCOLOR:
207 case FB_VISUAL_PSEUDOCOLOR:
208 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
209 break;
210 }
211
212 return ret;
213}
214
215/*
216 * pxafb_bpp_to_lccr3():
217 * Convert a bits per pixel value to the correct bit pattern for LCCR3
218 */
219static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
220{
b0086efb 221 int ret = 0;
222 switch (var->bits_per_pixel) {
223 case 1: ret = LCCR3_1BPP; break;
224 case 2: ret = LCCR3_2BPP; break;
225 case 4: ret = LCCR3_4BPP; break;
226 case 8: ret = LCCR3_8BPP; break;
227 case 16: ret = LCCR3_16BPP; break;
c1450f15
SS		 228 case 24:
229 switch (var->red.length + var->green.length +
230 var->blue.length + var->transp.length) {
231 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
232 case 19: ret = LCCR3_19BPP_P; break;
233 }
234 break;
235 case 32:
236 switch (var->red.length + var->green.length +
237 var->blue.length + var->transp.length) {
238 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
239 case 19: ret = LCCR3_19BPP; break;
240 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
241 case 25: ret = LCCR3_25BPP; break;
242 }
243 break;
b0086efb 244 }
245 return ret;
1da177e4
LT		 246}
247
248#ifdef CONFIG_CPU_FREQ
249/*
250 * pxafb_display_dma_period()
251 * Calculate the minimum period (in picoseconds) between two DMA
252 * requests for the LCD controller. If we hit this, it means we're
253 * doing nothing but LCD DMA.
254 */
255static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
256{
b0086efb 257 /*
258 * Period = pixclock * bits_per_byte * bytes_per_transfer
259 * / memory_bits_per_pixel;
260 */
261 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 262}
1da177e4
LT		 263#endif
264
d14b272b
RP		 265/*
266 * Select the smallest mode that allows the desired resolution to be
267 * displayed. If desired parameters can be rounded up.
268 */
b0086efb 269static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
270 struct fb_var_screeninfo *var)
d14b272b
RP		 271{
272 struct pxafb_mode_info *mode = NULL;
273 struct pxafb_mode_info *modelist = mach->modes;
274 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
275 unsigned int i;
276
b0086efb 277 for (i = 0; i < mach->num_modes; i++) {
278 if (modelist[i].xres >= var->xres &&
279 modelist[i].yres >= var->yres &&
280 modelist[i].xres < best_x &&
281 modelist[i].yres < best_y &&
282 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 283 best_x = modelist[i].xres;
284 best_y = modelist[i].yres;
285 mode = &modelist[i];
286 }
287 }
288
289 return mode;
290}
291
b0086efb 292static void pxafb_setmode(struct fb_var_screeninfo *var,
293 struct pxafb_mode_info *mode)
d14b272b
RP		 294{
295 var->xres = mode->xres;
296 var->yres = mode->yres;
297 var->bits_per_pixel = mode->bpp;
298 var->pixclock = mode->pixclock;
299 var->hsync_len = mode->hsync_len;
300 var->left_margin = mode->left_margin;
301 var->right_margin = mode->right_margin;
302 var->vsync_len = mode->vsync_len;
303 var->upper_margin = mode->upper_margin;
304 var->lower_margin = mode->lower_margin;
305 var->sync = mode->sync;
306 var->grayscale = mode->cmap_greyscale;
307 var->xres_virtual = var->xres;
308 var->yres_virtual = var->yres;
309}
310
1da177e4
LT		 311/*
312 * pxafb_check_var():
313 * Get the video params out of 'var'. If a value doesn't fit, round it up,
314 * if it's too big, return -EINVAL.
315 *
316 * Round up in the following order: bits_per_pixel, xres,
317 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
318 * bitfields, horizontal timing, vertical timing.
319 */
320static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
321{
322 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 323 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1da177e4
LT		 324
325 if (var->xres < MIN_XRES)
326 var->xres = MIN_XRES;
327 if (var->yres < MIN_YRES)
328 var->yres = MIN_YRES;
d14b272b
RP		 329
330 if (inf->fixed_modes) {
331 struct pxafb_mode_info *mode;
332
333 mode = pxafb_getmode(inf, var);
334 if (!mode)
335 return -EINVAL;
336 pxafb_setmode(var, mode);
337 } else {
338 if (var->xres > inf->modes->xres)
339 return -EINVAL;
340 if (var->yres > inf->modes->yres)
341 return -EINVAL;
342 if (var->bits_per_pixel > inf->modes->bpp)
343 return -EINVAL;
344 }
345
1da177e4
LT		 346 var->xres_virtual =
347 max(var->xres_virtual, var->xres);
348 var->yres_virtual =
349 max(var->yres_virtual, var->yres);
350
b0086efb 351 /*
1da177e4
LT		 352 * Setup the RGB parameters for this display.
353 *
354 * The pixel packing format is described on page 7-11 of the
355 * PXA2XX Developer's Manual.
b0086efb 356 */
1da177e4
LT		 357 if (var->bits_per_pixel == 16) {
358 var->red.offset = 11; var->red.length = 5;
359 var->green.offset = 5; var->green.length = 6;
360 var->blue.offset = 0; var->blue.length = 5;
361 var->transp.offset = var->transp.length = 0;
c1450f15
SS		 362 } else if (var->bits_per_pixel > 16) {
363 struct pxafb_mode_info *mode;
364
365 mode = pxafb_getmode(inf, var);
366 if (!mode)
367 return -EINVAL;
368
369 switch (mode->depth) {
370 case 18: /* RGB666 */
371 var->transp.offset = var->transp.length = 0;
372 var->red.offset = 12; var->red.length = 6;
373 var->green.offset = 6; var->green.length = 6;
374 var->blue.offset = 0; var->blue.length = 6;
375 break;
376 case 19: /* RGBT666 */
377 var->transp.offset = 18; var->transp.length = 1;
378 var->red.offset = 12; var->red.length = 6;
379 var->green.offset = 6; var->green.length = 6;
380 var->blue.offset = 0; var->blue.length = 6;
381 break;
382 case 24: /* RGB888 */
383 var->transp.offset = var->transp.length = 0;
384 var->red.offset = 16; var->red.length = 8;
385 var->green.offset = 8; var->green.length = 8;
386 var->blue.offset = 0; var->blue.length = 8;
387 break;
388 case 25: /* RGBT888 */
389 var->transp.offset = 24; var->transp.length = 1;
390 var->red.offset = 16; var->red.length = 8;
391 var->green.offset = 8; var->green.length = 8;
392 var->blue.offset = 0; var->blue.length = 8;
393 break;
394 default:
395 return -EINVAL;
396 }
1da177e4 397 } else {
b0086efb 398 var->red.offset = var->green.offset = 0;
399 var->blue.offset = var->transp.offset = 0;
1da177e4
LT		 400 var->red.length = 8;
401 var->green.length = 8;
402 var->blue.length = 8;
403 var->transp.length = 0;
404 }
405
406#ifdef CONFIG_CPU_FREQ
78d3cfd3
RK		 407 pr_debug("pxafb: dma period = %d ps\n",
408 pxafb_display_dma_period(var));
1da177e4
LT		 409#endif
410
411 return 0;
412}
413
414static inline void pxafb_set_truecolor(u_int is_true_color)
415{
b0086efb 416 /* do your machine-specific setup if needed */
1da177e4
LT		 417}
418
419/*
420 * pxafb_set_par():
421 * Set the user defined part of the display for the specified console
422 */
423static int pxafb_set_par(struct fb_info *info)
424{
425 struct pxafb_info *fbi = (struct pxafb_info *)info;
426 struct fb_var_screeninfo *var = &info->var;
1da177e4 427
c1450f15 428 if (var->bits_per_pixel >= 16)
1da177e4
LT		 429 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
430 else if (!fbi->cmap_static)
431 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
432 else {
433 /*
434 * Some people have weird ideas about wanting static
435 * pseudocolor maps. I suspect their user space
436 * applications are broken.
437 */
438 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
439 }
440
441 fbi->fb.fix.line_length = var->xres_virtual *
442 var->bits_per_pixel / 8;
c1450f15 443 if (var->bits_per_pixel >= 16)
1da177e4
LT		 444 fbi->palette_size = 0;
445 else
b0086efb 446 fbi->palette_size = var->bits_per_pixel == 1 ?
447 4 : 1 << var->bits_per_pixel;
1da177e4 448
2c42dd8e 449 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4
LT		 450
451 /*
452 * Set (any) board control register to handle new color depth
453 */
454 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
455
c1450f15 456 if (fbi->fb.var.bits_per_pixel >= 16)
1da177e4
LT		 457 fb_dealloc_cmap(&fbi->fb.cmap);
458 else
459 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
460
461 pxafb_activate_var(var, fbi);
462
463 return 0;
464}
465
1da177e4
LT		 466/*
467 * pxafb_blank():
468 * Blank the display by setting all palette values to zero. Note, the
469 * 16 bpp mode does not really use the palette, so this will not
470 * blank the display in all modes.
471 */
472static int pxafb_blank(int blank, struct fb_info *info)
473{
474 struct pxafb_info *fbi = (struct pxafb_info *)info;
475 int i;
476
1da177e4
LT		 477 switch (blank) {
478 case FB_BLANK_POWERDOWN:
479 case FB_BLANK_VSYNC_SUSPEND:
480 case FB_BLANK_HSYNC_SUSPEND:
481 case FB_BLANK_NORMAL:
482 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
483 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
484 for (i = 0; i < fbi->palette_size; i++)
485 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
486
487 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 488 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 489 break;
490
491 case FB_BLANK_UNBLANK:
b0086efb 492 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 493 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
494 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
495 fb_set_cmap(&fbi->fb.cmap, info);
496 pxafb_schedule_work(fbi, C_ENABLE);
497 }
498 return 0;
499}
500
216d526c 501static int pxafb_mmap(struct fb_info *info,
1da177e4
LT		 502 struct vm_area_struct *vma)
503{
504 struct pxafb_info *fbi = (struct pxafb_info *)info;
505 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
506
507 if (off < info->fix.smem_len) {
3c42a449 508 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
1da177e4
LT		 509 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
510 fbi->map_dma, fbi->map_size);
511 }
512 return -EINVAL;
513}
514
515static struct fb_ops pxafb_ops = {
516 .owner = THIS_MODULE,
517 .fb_check_var = pxafb_check_var,
518 .fb_set_par = pxafb_set_par,
519 .fb_setcolreg = pxafb_setcolreg,
520 .fb_fillrect = cfb_fillrect,
521 .fb_copyarea = cfb_copyarea,
522 .fb_imageblit = cfb_imageblit,
523 .fb_blank = pxafb_blank,
1da177e4
LT		 524 .fb_mmap = pxafb_mmap,
525};
526
527/*
528 * Calculate the PCD value from the clock rate (in picoseconds).
529 * We take account of the PPCR clock setting.
530 * From PXA Developer's Manual:
531 *
532 * PixelClock = LCLK
533 * -------------
534 * 2 ( PCD + 1 )
535 *
536 * PCD = LCLK
537 * ------------- - 1
538 * 2(PixelClock)
539 *
540 * Where:
541 * LCLK = LCD/Memory Clock
542 * PCD = LCCR3[7:0]
543 *
544 * PixelClock here is in Hz while the pixclock argument given is the
545 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
546 *
547 * The function get_lclk_frequency_10khz returns LCLK in units of
548 * 10khz. Calling the result of this function lclk gives us the
549 * following
550 *
551 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
552 * -------------------------------------- - 1
553 * 2
554 *
555 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
556 */
b0086efb 557static inline unsigned int get_pcd(struct pxafb_info *fbi,
558 unsigned int pixclock)
1da177e4
LT		 559{
560 unsigned long long pcd;
561
562 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 563 * (DPC) bit? or perhaps set it based on the various clock
564 * speeds */
565 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
566 pcd *= pixclock;
bf1b8ab6 567 do_div(pcd, 100000000 * 2);
1da177e4
LT		 568 /* no need for this, since we should subtract 1 anyway. they cancel */
569 /* pcd += 1; */ /* make up for integer math truncations */
570 return (unsigned int)pcd;
571}
572
ba44cd2d
RP		 573/*
574 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 575 * function correctly. We export it here. Note that 'hsync_time' and
576 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
577 * of the hsync period in seconds.
ba44cd2d
RP		 578 */
579static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
580{
72e3524c 581 unsigned long htime;
ba44cd2d
RP		 582
583 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 584 fbi->hsync_time = 0;
ba44cd2d
RP		 585 return;
586 }
587
72e3524c
RK		 588 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
589
ba44cd2d
RP		 590 fbi->hsync_time = htime;
591}
592
593unsigned long pxafb_get_hsync_time(struct device *dev)
594{
595 struct pxafb_info *fbi = dev_get_drvdata(dev);
596
597 /* If display is blanked/suspended, hsync isn't active */
598 if (!fbi || (fbi->state != C_ENABLE))
599 return 0;
600
601 return fbi->hsync_time;
602}
603EXPORT_SYMBOL(pxafb_get_hsync_time);
604
2c42dd8e 605static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
606 unsigned int offset, size_t size)
607{
608 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
609 unsigned int dma_desc_off, pal_desc_off;
610
611 if (dma < 0 || dma >= DMA_MAX)
612 return -EINVAL;
613
614 dma_desc = &fbi->dma_buff->dma_desc[dma];
615 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
616
617 dma_desc->fsadr = fbi->screen_dma + offset;
618 dma_desc->fidr = 0;
619 dma_desc->ldcmd = size;
620
621 if (pal < 0 || pal >= PAL_MAX) {
622 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
623 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
624 } else {
62cfcf4f
JS		 625 pal_desc = &fbi->dma_buff->pal_desc[pal];
626 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
2c42dd8e 627
628 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
629 pal_desc->fidr = 0;
630
631 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
632 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
633 else
634 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
635
636 pal_desc->ldcmd |= LDCMD_PAL;
637
638 /* flip back and forth between palette and frame buffer */
639 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
640 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
641 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
642 }
643
644 return 0;
645}
646
3c42a449
EM		 647#ifdef CONFIG_FB_PXA_SMARTPANEL
648static int setup_smart_dma(struct pxafb_info *fbi)
649{
650 struct pxafb_dma_descriptor *dma_desc;
651 unsigned long dma_desc_off, cmd_buff_off;
652
653 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
654 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
655 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
656
657 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
658 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
659 dma_desc->fidr = 0;
660 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
661
662 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
663 return 0;
664}
665
666int pxafb_smart_flush(struct fb_info *info)
667{
668 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
669 uint32_t prsr;
670 int ret = 0;
671
672 /* disable controller until all registers are set up */
673 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
674
675 /* 1. make it an even number of commands to align on 32-bit boundary
676 * 2. add the interrupt command to the end of the chain so we can
677 * keep track of the end of the transfer
678 */
679
680 while (fbi->n_smart_cmds & 1)
681 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
682
683 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
684 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
685 setup_smart_dma(fbi);
686
687 /* continue to execute next command */
688 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
689 lcd_writel(fbi, PRSR, prsr);
690
691 /* stop the processor in case it executed "wait for sync" cmd */
692 lcd_writel(fbi, CMDCR, 0x0001);
693
694 /* don't send interrupts for fifo underruns on channel 6 */
695 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
696
697 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
698 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
699 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
700 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
701 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
702
703 /* begin sending */
704 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
705
706 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
707 pr_warning("%s: timeout waiting for command done\n",
708 __func__);
709 ret = -ETIMEDOUT;
710 }
711
712 /* quick disable */
713 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
714 lcd_writel(fbi, PRSR, prsr);
715 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
716 lcd_writel(fbi, FDADR6, 0);
717 fbi->n_smart_cmds = 0;
718 return ret;
719}
720
721int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
722{
723 int i;
724 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
725
69bdea70
EM		 726 for (i = 0; i < n_cmds; i++, cmds++) {
727 /* if it is a software delay, flush and delay */
728 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
729 pxafb_smart_flush(info);
730 mdelay(*cmds & 0xff);
731 continue;
732 }
733
734 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
3c42a449
EM		 735 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
736 pxafb_smart_flush(info);
737
69bdea70 738 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
3c42a449
EM		 739 }
740
741 return 0;
742}
743
744static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
745{
746 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
747 return (t == 0) ? 1 : t;
748}
749
750static void setup_smart_timing(struct pxafb_info *fbi,
751 struct fb_var_screeninfo *var)
752{
753 struct pxafb_mach_info *inf = fbi->dev->platform_data;
754 struct pxafb_mode_info *mode = &inf->modes[0];
755 unsigned long lclk = clk_get_rate(fbi->clk);
756 unsigned t1, t2, t3, t4;
757
758 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
759 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
760 t3 = mode->op_hold_time;
761 t4 = mode->cmd_inh_time;
762
763 fbi->reg_lccr1 =
764 LCCR1_DisWdth(var->xres) |
765 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
766 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
767 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
768
769 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
c1f99c21
EM		 770 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
771 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
772 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
3c42a449
EM		 773
774 /* FIXME: make this configurable */
775 fbi->reg_cmdcr = 1;
776}
777
778static int pxafb_smart_thread(void *arg)
779{
7f1133cb 780 struct pxafb_info *fbi = arg;
3c42a449
EM		 781 struct pxafb_mach_info *inf = fbi->dev->platform_data;
782
783 if (!fbi || !inf->smart_update) {
784 pr_err("%s: not properly initialized, thread terminated\n",
785 __func__);
786 return -EINVAL;
787 }
788
789 pr_debug("%s(): task starting\n", __func__);
790
791 set_freezable();
792 while (!kthread_should_stop()) {
793
794 if (try_to_freeze())
795 continue;
796
07f651c7
EM		 797 mutex_lock(&fbi->ctrlr_lock);
798
3c42a449
EM		 799 if (fbi->state == C_ENABLE) {
800 inf->smart_update(&fbi->fb);
801 complete(&fbi->refresh_done);
802 }
803
07f651c7
EM		 804 mutex_unlock(&fbi->ctrlr_lock);
805
3c42a449
EM		 806 set_current_state(TASK_INTERRUPTIBLE);
807 schedule_timeout(30 * HZ / 1000);
808 }
809
810 pr_debug("%s(): task ending\n", __func__);
811 return 0;
812}
813
814static int pxafb_smart_init(struct pxafb_info *fbi)
815{
07df1c4f 816 if (!(fbi->lccr0 & LCCR0_LCDT))
6cc4abe4
EM		 817 return 0;
818
07df1c4f
EM		 819 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
820 fbi->n_smart_cmds = 0;
821
822 init_completion(&fbi->command_done);
823 init_completion(&fbi->refresh_done);
824
3c42a449
EM		 825 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
826 "lcd_refresh");
827 if (IS_ERR(fbi->smart_thread)) {
07df1c4f 828 pr_err("%s: unable to create kernel thread\n", __func__);
3c42a449
EM		 829 return PTR_ERR(fbi->smart_thread);
830 }
a5718a14 831
3c42a449
EM		 832 return 0;
833}
834#else
835int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
836{
837 return 0;
838}
839
840int pxafb_smart_flush(struct fb_info *info)
841{
842 return 0;
843}
07df1c4f
EM		 844
845static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
846#endif /* CONFIG_FB_PXA_SMARTPANEL */
3c42a449 847
90eabbf0
EM		 848static void setup_parallel_timing(struct pxafb_info *fbi,
849 struct fb_var_screeninfo *var)
850{
851 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
852
853 fbi->reg_lccr1 =
854 LCCR1_DisWdth(var->xres) +
855 LCCR1_HorSnchWdth(var->hsync_len) +
856 LCCR1_BegLnDel(var->left_margin) +
857 LCCR1_EndLnDel(var->right_margin);
858
859 /*
860 * If we have a dual scan LCD, we need to halve
861 * the YRES parameter.
862 */
863 lines_per_panel = var->yres;
864 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
865 lines_per_panel /= 2;
866
867 fbi->reg_lccr2 =
868 LCCR2_DisHght(lines_per_panel) +
869 LCCR2_VrtSnchWdth(var->vsync_len) +
870 LCCR2_BegFrmDel(var->upper_margin) +
871 LCCR2_EndFrmDel(var->lower_margin);
872
873 fbi->reg_lccr3 = fbi->lccr3 |
874 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
875 LCCR3_HorSnchH : LCCR3_HorSnchL) |
876 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
877 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
878
879 if (pcd) {
880 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
881 set_hsync_time(fbi, pcd);
882 }
883}
884
1da177e4
LT		 885/*
886 * pxafb_activate_var():
b0086efb 887 * Configures LCD Controller based on entries in var parameter.
888 * Settings are only written to the controller if changes were made.
1da177e4 889 */
b0086efb 890static int pxafb_activate_var(struct fb_var_screeninfo *var,
891 struct pxafb_info *fbi)
1da177e4 892{
1da177e4 893 u_long flags;
2c42dd8e 894 size_t nbytes;
1da177e4 895
1da177e4 896#if DEBUG_VAR
3c42a449
EM		 897 if (!(fbi->lccr0 & LCCR0_LCDT)) {
898 if (var->xres < 16 || var->xres > 1024)
899 printk(KERN_ERR "%s: invalid xres %d\n",
900 fbi->fb.fix.id, var->xres);
901 switch (var->bits_per_pixel) {
902 case 1:
903 case 2:
904 case 4:
905 case 8:
906 case 16:
c1450f15
SS		 907 case 24:
908 case 32:
3c42a449
EM		 909 break;
910 default:
911 printk(KERN_ERR "%s: invalid bit depth %d\n",
912 fbi->fb.fix.id, var->bits_per_pixel);
913 break;
914 }
915
916 if (var->hsync_len < 1 || var->hsync_len > 64)
917 printk(KERN_ERR "%s: invalid hsync_len %d\n",
918 fbi->fb.fix.id, var->hsync_len);
919 if (var->left_margin < 1 || var->left_margin > 255)
920 printk(KERN_ERR "%s: invalid left_margin %d\n",
921 fbi->fb.fix.id, var->left_margin);
922 if (var->right_margin < 1 || var->right_margin > 255)
923 printk(KERN_ERR "%s: invalid right_margin %d\n",
924 fbi->fb.fix.id, var->right_margin);
925 if (var->yres < 1 || var->yres > 1024)
926 printk(KERN_ERR "%s: invalid yres %d\n",
927 fbi->fb.fix.id, var->yres);
928 if (var->vsync_len < 1 || var->vsync_len > 64)
929 printk(KERN_ERR "%s: invalid vsync_len %d\n",
930 fbi->fb.fix.id, var->vsync_len);
931 if (var->upper_margin < 0 || var->upper_margin > 255)
932 printk(KERN_ERR "%s: invalid upper_margin %d\n",
933 fbi->fb.fix.id, var->upper_margin);
934 if (var->lower_margin < 0 || var->lower_margin > 255)
935 printk(KERN_ERR "%s: invalid lower_margin %d\n",
936 fbi->fb.fix.id, var->lower_margin);
1da177e4 937 }
1da177e4 938#endif
90eabbf0
EM		 939 /* Update shadow copy atomically */
940 local_irq_save(flags);
1da177e4 941
3c42a449
EM		 942#ifdef CONFIG_FB_PXA_SMARTPANEL
943 if (fbi->lccr0 & LCCR0_LCDT)
944 setup_smart_timing(fbi, var);
945 else
946#endif
947 setup_parallel_timing(fbi, var);
90eabbf0
EM		 948
949 fbi->reg_lccr0 = fbi->lccr0 |
1da177e4 950 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 951 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4 952
90eabbf0 953 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
1da177e4 954
90eabbf0 955 nbytes = var->yres * fbi->fb.fix.line_length;
1da177e4 956
90eabbf0
EM		 957 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
958 nbytes = nbytes / 2;
2c42dd8e 959 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
90eabbf0 960 }
2c42dd8e 961
3c42a449 962 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
2c42dd8e 963 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
964 else
965 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
1da177e4 966
a7535ba7 967 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 968 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1da177e4
LT		 969 local_irq_restore(flags);
970
971 /*
972 * Only update the registers if the controller is enabled
973 * and something has changed.
974 */
a7535ba7
EM		 975 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
976 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
977 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
978 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
979 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
980 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1da177e4
LT		 981 pxafb_schedule_work(fbi, C_REENABLE);
982
983 return 0;
984}
985
986/*
987 * NOTE! The following functions are purely helpers for set_ctrlr_state.
988 * Do not call them directly; set_ctrlr_state does the correct serialisation
989 * to ensure that things happen in the right way 100% of time time.
990 * -- rmk
991 */
992static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
993{
ca5da710 994 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 995
a5718a14
EM		 996 if (fbi->backlight_power)
997 fbi->backlight_power(on);
1da177e4
LT		 998}
999
1000static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1001{
ca5da710 1002 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4 1003
a5718a14
EM		 1004 if (fbi->lcd_power)
1005 fbi->lcd_power(on, &fbi->fb.var);
1da177e4
LT		 1006}
1007
1da177e4
LT		 1008static void pxafb_enable_controller(struct pxafb_info *fbi)
1009{
ca5da710 1010 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 1011 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1012 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 1013 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1014 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1015 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1016 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 1017
8d372266 1018 /* enable LCD controller clock */
72e3524c 1019 clk_enable(fbi->clk);
8d372266 1020
3c42a449
EM		 1021 if (fbi->lccr0 & LCCR0_LCDT)
1022 return;
1023
1da177e4 1024 /* Sequence from 11.7.10 */
a7535ba7
EM		 1025 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1026 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1027 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1028 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1029
1030 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1031 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1032 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 1033}
1034
1035static void pxafb_disable_controller(struct pxafb_info *fbi)
1036{
ce4fb7b8 1037 uint32_t lccr0;
1038
3c42a449
EM		 1039#ifdef CONFIG_FB_PXA_SMARTPANEL
1040 if (fbi->lccr0 & LCCR0_LCDT) {
1041 wait_for_completion_timeout(&fbi->refresh_done,
1042 200 * HZ / 1000);
1043 return;
1044 }
1045#endif
1046
ce4fb7b8 1047 /* Clear LCD Status Register */
a7535ba7 1048 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 1049
a7535ba7
EM		 1050 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1051 lcd_writel(fbi, LCCR0, lccr0);
1052 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 1053
2ba162b9 1054 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
8d372266
NP		 1055
1056 /* disable LCD controller clock */
72e3524c 1057 clk_disable(fbi->clk);
1da177e4
LT		 1058}
1059
1060/*
1061 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1062 */
7d12e780 1063static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 1064{
1065 struct pxafb_info *fbi = dev_id;
a7535ba7 1066 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1da177e4
LT		 1067
1068 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 1069 lccr0 = lcd_readl(fbi, LCCR0);
1070 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
2ba162b9 1071 complete(&fbi->disable_done);
1da177e4
LT		 1072 }
1073
3c42a449
EM		 1074#ifdef CONFIG_FB_PXA_SMARTPANEL
1075 if (lcsr & LCSR_CMD_INT)
1076 complete(&fbi->command_done);
1077#endif
1078
a7535ba7 1079 lcd_writel(fbi, LCSR, lcsr);
1da177e4
LT		 1080 return IRQ_HANDLED;
1081}
1082
1083/*
1084 * This function must be called from task context only, since it will
1085 * sleep when disabling the LCD controller, or if we get two contending
1086 * processes trying to alter state.
1087 */
1088static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1089{
1090 u_int old_state;
1091
b91dbce5 1092 mutex_lock(&fbi->ctrlr_lock);
1da177e4
LT		 1093
1094 old_state = fbi->state;
1095
1096 /*
1097 * Hack around fbcon initialisation.
1098 */
1099 if (old_state == C_STARTUP && state == C_REENABLE)
1100 state = C_ENABLE;
1101
1102 switch (state) {
1103 case C_DISABLE_CLKCHANGE:
1104 /*
1105 * Disable controller for clock change. If the
1106 * controller is already disabled, then do nothing.
1107 */
1108 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1109 fbi->state = state;
b0086efb 1110 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 1111 pxafb_disable_controller(fbi);
1112 }
1113 break;
1114
1115 case C_DISABLE_PM:
1116 case C_DISABLE:
1117 /*
1118 * Disable controller
1119 */
1120 if (old_state != C_DISABLE) {
1121 fbi->state = state;
1122 __pxafb_backlight_power(fbi, 0);
1123 __pxafb_lcd_power(fbi, 0);
1124 if (old_state != C_DISABLE_CLKCHANGE)
1125 pxafb_disable_controller(fbi);
1126 }
1127 break;
1128
1129 case C_ENABLE_CLKCHANGE:
1130 /*
1131 * Enable the controller after clock change. Only
1132 * do this if we were disabled for the clock change.
1133 */
1134 if (old_state == C_DISABLE_CLKCHANGE) {
1135 fbi->state = C_ENABLE;
1136 pxafb_enable_controller(fbi);
b0086efb 1137 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 1138 }
1139 break;
1140
1141 case C_REENABLE:
1142 /*
1143 * Re-enable the controller only if it was already
1144 * enabled. This is so we reprogram the control
1145 * registers.
1146 */
1147 if (old_state == C_ENABLE) {
d14b272b 1148 __pxafb_lcd_power(fbi, 0);
1da177e4 1149 pxafb_disable_controller(fbi);
1da177e4 1150 pxafb_enable_controller(fbi);
d14b272b 1151 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 1152 }
1153 break;
1154
1155 case C_ENABLE_PM:
1156 /*
1157 * Re-enable the controller after PM. This is not
1158 * perfect - think about the case where we were doing
1159 * a clock change, and we suspended half-way through.
1160 */
1161 if (old_state != C_DISABLE_PM)
1162 break;
1163 /* fall through */
1164
1165 case C_ENABLE:
1166 /*
1167 * Power up the LCD screen, enable controller, and
1168 * turn on the backlight.
1169 */
1170 if (old_state != C_ENABLE) {
1171 fbi->state = C_ENABLE;
1da177e4
LT		 1172 pxafb_enable_controller(fbi);
1173 __pxafb_lcd_power(fbi, 1);
1174 __pxafb_backlight_power(fbi, 1);
1175 }
1176 break;
1177 }
b91dbce5 1178 mutex_unlock(&fbi->ctrlr_lock);
1da177e4
LT		 1179}
1180
1181/*
1182 * Our LCD controller task (which is called when we blank or unblank)
1183 * via keventd.
1184 */
6d5aefb8 1185static void pxafb_task(struct work_struct *work)
1da177e4 1186{
6d5aefb8
DH		 1187 struct pxafb_info *fbi =
1188 container_of(work, struct pxafb_info, task);
1da177e4
LT		 1189 u_int state = xchg(&fbi->task_state, -1);
1190
1191 set_ctrlr_state(fbi, state);
1192}
1193
1194#ifdef CONFIG_CPU_FREQ
1195/*
1196 * CPU clock speed change handler. We need to adjust the LCD timing
1197 * parameters when the CPU clock is adjusted by the power management
1198 * subsystem.
1199 *
1200 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1201 */
1202static int
1203pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1204{
1205 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 1206 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 1207 u_int pcd;
1208
1209 switch (val) {
1210 case CPUFREQ_PRECHANGE:
1211 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1212 break;
1213
1214 case CPUFREQ_POSTCHANGE:
72e3524c 1215 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 1216 set_hsync_time(fbi, pcd);
b0086efb 1217 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1218 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 1219 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1220 break;
1221 }
1222 return 0;
1223}
1224
1225static int
1226pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1227{
1228 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1229 struct fb_var_screeninfo *var = &fbi->fb.var;
1230 struct cpufreq_policy *policy = data;
1231
1232 switch (val) {
1233 case CPUFREQ_ADJUST:
1234 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1235 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1236 "new clock %d kHz\n", pxafb_display_dma_period(var),
1237 policy->max);
b0086efb 1238 /* TODO: fill in min/max values */
1da177e4 1239 break;
1da177e4
LT		 1240 }
1241 return 0;
1242}
1243#endif
1244
1245#ifdef CONFIG_PM
1246/*
1247 * Power management hooks. Note that we won't be called from IRQ context,
1248 * unlike the blank functions above, so we may sleep.
1249 */
3ae5eaec 1250static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1251{
3ae5eaec 1252 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1253
9480e307 1254 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1255 return 0;
1256}
1257
3ae5eaec 1258static int pxafb_resume(struct platform_device *dev)
1da177e4 1259{
3ae5eaec 1260 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1261
9480e307 1262 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1263 return 0;
1264}
1265#else
1266#define pxafb_suspend NULL
1267#define pxafb_resume NULL
1268#endif
1269
1270/*
1271 * pxafb_map_video_memory():
1272 * Allocates the DRAM memory for the frame buffer. This buffer is
1273 * remapped into a non-cached, non-buffered, memory region to
1274 * allow palette and pixel writes to occur without flushing the
1275 * cache. Once this area is remapped, all virtual memory
1276 * access to the video memory should occur at the new region.
1277 */
9e6c2976 1278static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1da177e4 1279{
1da177e4
LT		 1280 /*
1281 * We reserve one page for the palette, plus the size
1282 * of the framebuffer.
1283 */
3c42a449
EM		 1284 fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1285 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1da177e4
LT		 1286 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1287 &fbi->map_dma, GFP_KERNEL);
1288
1289 if (fbi->map_cpu) {
1290 /* prevent initial garbage on screen */
1291 memset(fbi->map_cpu, 0, fbi->map_size);
3c42a449
EM		 1292 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1293 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1294
1da177e4
LT		 1295 /*
1296 * FIXME: this is actually the wrong thing to place in
1297 * smem_start. But fbdev suffers from the problem that
1298 * it needs an API which doesn't exist (in this case,
1299 * dma_writecombine_mmap)
1300 */
1301 fbi->fb.fix.smem_start = fbi->screen_dma;
1da177e4
LT		 1302 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1303
3c42a449 1304 fbi->dma_buff = (void *) fbi->map_cpu;
2c42dd8e 1305 fbi->dma_buff_phys = fbi->map_dma;
3c42a449
EM		 1306 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1307
e84e954a 1308 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
1da177e4
LT		 1309 }
1310
1311 return fbi->map_cpu ? 0 : -ENOMEM;
1312}
1313
84f43c30 1314static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1315 struct pxafb_mode_info *modes,
1316 unsigned int num_modes)
1317{
1318 unsigned int i, smemlen;
1319
1320 pxafb_setmode(&fbi->fb.var, &modes[0]);
1321
1322 for (i = 0; i < num_modes; i++) {
1323 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1324 if (smemlen > fbi->fb.fix.smem_len)
1325 fbi->fb.fix.smem_len = smemlen;
1326 }
1327}
1328
ebdf982a
GL		 1329static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1330 struct pxafb_mach_info *inf)
84f43c30 1331{
1332 unsigned int lcd_conn = inf->lcd_conn;
1333
1334 fbi->cmap_inverse = inf->cmap_inverse;
1335 fbi->cmap_static = inf->cmap_static;
1336
1ec26db1 1337 switch (lcd_conn & LCD_TYPE_MASK) {
84f43c30 1338 case LCD_TYPE_MONO_STN:
1339 fbi->lccr0 = LCCR0_CMS;
1340 break;
1341 case LCD_TYPE_MONO_DSTN:
1342 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1343 break;
1344 case LCD_TYPE_COLOR_STN:
1345 fbi->lccr0 = 0;
1346 break;
1347 case LCD_TYPE_COLOR_DSTN:
1348 fbi->lccr0 = LCCR0_SDS;
1349 break;
1350 case LCD_TYPE_COLOR_TFT:
1351 fbi->lccr0 = LCCR0_PAS;
1352 break;
1353 case LCD_TYPE_SMART_PANEL:
1354 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1355 break;
1356 default:
1357 /* fall back to backward compatibility way */
1358 fbi->lccr0 = inf->lccr0;
1359 fbi->lccr3 = inf->lccr3;
1360 fbi->lccr4 = inf->lccr4;
ebdf982a 1361 goto decode_mode;
84f43c30 1362 }
1363
1364 if (lcd_conn == LCD_MONO_STN_8BPP)
1365 fbi->lccr0 |= LCCR0_DPD;
1366
9a1ac7e4
EM		 1367 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1368
84f43c30 1369 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1370 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1371 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1372
ebdf982a 1373decode_mode:
84f43c30 1374 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
84f43c30 1375}
1376
9e6c2976 1377static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1da177e4
LT		 1378{
1379 struct pxafb_info *fbi;
1380 void *addr;
1381 struct pxafb_mach_info *inf = dev->platform_data;
1382
1383 /* Alloc the pxafb_info and pseudo_palette in one step */
1384 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1385 if (!fbi)
1386 return NULL;
1387
1388 memset(fbi, 0, sizeof(struct pxafb_info));
1389 fbi->dev = dev;
1390
72e3524c
RK		 1391 fbi->clk = clk_get(dev, "LCDCLK");
1392 if (IS_ERR(fbi->clk)) {
1393 kfree(fbi);
1394 return NULL;
1395 }
1396
1da177e4
LT		 1397 strcpy(fbi->fb.fix.id, PXA_NAME);
1398
1399 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1400 fbi->fb.fix.type_aux = 0;
1401 fbi->fb.fix.xpanstep = 0;
1402 fbi->fb.fix.ypanstep = 0;
1403 fbi->fb.fix.ywrapstep = 0;
1404 fbi->fb.fix.accel = FB_ACCEL_NONE;
1405
1406 fbi->fb.var.nonstd = 0;
1407 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1408 fbi->fb.var.height = -1;
1409 fbi->fb.var.width = -1;
1410 fbi->fb.var.accel_flags = 0;
1411 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1412
1413 fbi->fb.fbops = &pxafb_ops;
1414 fbi->fb.flags = FBINFO_DEFAULT;
1415 fbi->fb.node = -1;
1416
1417 addr = fbi;
1418 addr = addr + sizeof(struct pxafb_info);
1419 fbi->fb.pseudo_palette = addr;
1420
b0086efb 1421 fbi->state = C_STARTUP;
1422 fbi->task_state = (u_char)-1;
d14b272b 1423
84f43c30 1424 pxafb_decode_mach_info(fbi, inf);
1da177e4
LT		 1425
1426 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1427 INIT_WORK(&fbi->task, pxafb_task);
b91dbce5 1428 mutex_init(&fbi->ctrlr_lock);
2ba162b9 1429 init_completion(&fbi->disable_done);
1da177e4
LT		 1430
1431 return fbi;
1432}
1433
1434#ifdef CONFIG_FB_PXA_PARAMETERS
9e6c2976 1435static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1436{
1437 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1438
1439 const char *name = this_opt+5;
1440 unsigned int namelen = strlen(name);
1441 int res_specified = 0, bpp_specified = 0;
1442 unsigned int xres = 0, yres = 0, bpp = 0;
1443 int yres_specified = 0;
1444 int i;
1445 for (i = namelen-1; i >= 0; i--) {
1446 switch (name[i]) {
1447 case '-':
1448 namelen = i;
1449 if (!bpp_specified && !yres_specified) {
1450 bpp = simple_strtoul(&name[i+1], NULL, 0);
1451 bpp_specified = 1;
1452 } else
1453 goto done;
1454 break;
1455 case 'x':
1456 if (!yres_specified) {
1457 yres = simple_strtoul(&name[i+1], NULL, 0);
1458 yres_specified = 1;
1459 } else
1460 goto done;
1461 break;
1462 case '0' ... '9':
1463 break;
1464 default:
1465 goto done;
1466 }
1467 }
1468 if (i < 0 && yres_specified) {
1469 xres = simple_strtoul(name, NULL, 0);
1470 res_specified = 1;
1471 }
1472done:
1473 if (res_specified) {
1474 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1475 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1476 }
1477 if (bpp_specified)
1478 switch (bpp) {
1479 case 1:
1480 case 2:
1481 case 4:
1482 case 8:
1483 case 16:
1484 inf->modes[0].bpp = bpp;
1485 dev_info(dev, "overriding bit depth: %d\n", bpp);
1486 break;
1487 default:
1488 dev_err(dev, "Depth %d is not valid\n", bpp);
1489 return -EINVAL;
1490 }
1491 return 0;
1492}
1493
9e6c2976 1494static int __devinit parse_opt(struct device *dev, char *this_opt)
817daf14 1495{
1496 struct pxafb_mach_info *inf = dev->platform_data;
1497 struct pxafb_mode_info *mode = &inf->modes[0];
1498 char s[64];
1499
1500 s[0] = '\0';
1501
1502 if (!strncmp(this_opt, "mode:", 5)) {
1503 return parse_opt_mode(dev, this_opt);
1504 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1505 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1506 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1507 } else if (!strncmp(this_opt, "left:", 5)) {
1508 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1509 sprintf(s, "left: %u\n", mode->left_margin);
1510 } else if (!strncmp(this_opt, "right:", 6)) {
1511 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1512 sprintf(s, "right: %u\n", mode->right_margin);
1513 } else if (!strncmp(this_opt, "upper:", 6)) {
1514 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1515 sprintf(s, "upper: %u\n", mode->upper_margin);
1516 } else if (!strncmp(this_opt, "lower:", 6)) {
1517 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1518 sprintf(s, "lower: %u\n", mode->lower_margin);
1519 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1520 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1521 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1522 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1523 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1524 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1525 } else if (!strncmp(this_opt, "hsync:", 6)) {
1526 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1527 sprintf(s, "hsync: Active Low\n");
1528 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1529 } else {
1530 sprintf(s, "hsync: Active High\n");
1531 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1532 }
1533 } else if (!strncmp(this_opt, "vsync:", 6)) {
1534 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1535 sprintf(s, "vsync: Active Low\n");
1536 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1537 } else {
1538 sprintf(s, "vsync: Active High\n");
1539 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1540 }
1541 } else if (!strncmp(this_opt, "dpc:", 4)) {
1542 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1543 sprintf(s, "double pixel clock: false\n");
1544 inf->lccr3 &= ~LCCR3_DPC;
1545 } else {
1546 sprintf(s, "double pixel clock: true\n");
1547 inf->lccr3 |= LCCR3_DPC;
1548 }
1549 } else if (!strncmp(this_opt, "outputen:", 9)) {
1550 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1551 sprintf(s, "output enable: active low\n");
1552 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1553 } else {
1554 sprintf(s, "output enable: active high\n");
1555 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1556 }
1557 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1558 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1559 sprintf(s, "pixel clock polarity: falling edge\n");
1560 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1561 } else {
1562 sprintf(s, "pixel clock polarity: rising edge\n");
1563 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1564 }
1565 } else if (!strncmp(this_opt, "color", 5)) {
1566 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1567 } else if (!strncmp(this_opt, "mono", 4)) {
1568 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1569 } else if (!strncmp(this_opt, "active", 6)) {
1570 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1571 } else if (!strncmp(this_opt, "passive", 7)) {
1572 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1573 } else if (!strncmp(this_opt, "single", 6)) {
1574 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1575 } else if (!strncmp(this_opt, "dual", 4)) {
1576 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1577 } else if (!strncmp(this_opt, "4pix", 4)) {
1578 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1579 } else if (!strncmp(this_opt, "8pix", 4)) {
1580 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1581 } else {
1582 dev_err(dev, "unknown option: %s\n", this_opt);
1583 return -EINVAL;
1584 }
1585
1586 if (s[0] != '\0')
1587 dev_info(dev, "override %s", s);
1588
1589 return 0;
1590}
1591
9e6c2976 1592static int __devinit pxafb_parse_options(struct device *dev, char *options)
817daf14 1593{
1da177e4 1594 char *this_opt;
817daf14 1595 int ret;
1da177e4 1596
817daf14 1597 if (!options || !*options)
1598 return 0;
1da177e4
LT		 1599
1600 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1601
1602 /* could be made table driven or similar?... */
817daf14 1603 while ((this_opt = strsep(&options, ",")) != NULL) {
1604 ret = parse_opt(dev, this_opt);
1605 if (ret)
1606 return ret;
1607 }
1608 return 0;
1da177e4 1609}
92ac73c1 1610
1611static char g_options[256] __devinitdata = "";
1612
f1edfc42 1613#ifndef MODULE
9e6c2976 1614static int __init pxafb_setup_options(void)
92ac73c1 1615{
1616 char *options = NULL;
1617
1618 if (fb_get_options("pxafb", &options))
1619 return -ENODEV;
1620
1621 if (options)
1622 strlcpy(g_options, options, sizeof(g_options));
1623
1624 return 0;
1625}
1626#else
1627#define pxafb_setup_options() (0)
1628
1629module_param_string(options, g_options, sizeof(g_options), 0);
1630MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1631#endif
1632
1633#else
1634#define pxafb_parse_options(...) (0)
1635#define pxafb_setup_options() (0)
1da177e4
LT		 1636#endif
1637
1da177e4 1638#ifdef DEBUG_VAR
4f3e2664
EM		 1639/* Check for various illegal bit-combinations. Currently only
1640 * a warning is given. */
1641static void __devinit pxafb_check_options(struct device *dev,
1642 struct pxafb_mach_info *inf)
1643{
1644 if (inf->lcd_conn)
1645 return;
1da177e4 1646
b0086efb 1647 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
4f3e2664 1648 dev_warn(dev, "machine LCCR0 setting contains "
b0086efb 1649 "illegal bits: %08x\n",
1650 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1651 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
4f3e2664 1652 dev_warn(dev, "machine LCCR3 setting contains "
b0086efb 1653 "illegal bits: %08x\n",
1654 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1655 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 1656 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1657 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1658 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
4f3e2664 1659 dev_warn(dev, "Double Pixel Data (DPD) mode is "
b0086efb 1660 "only valid in passive mono"
1661 " single panel mode\n");
1662 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 1663 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
4f3e2664 1664 dev_warn(dev, "Dual panel only valid in passive mode\n");
b0086efb 1665 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1666 (inf->modes->upper_margin || inf->modes->lower_margin))
4f3e2664 1667 dev_warn(dev, "Upper and lower margins must be 0 in "
b0086efb 1668 "passive mode\n");
4f3e2664
EM		 1669}
1670#else
1671#define pxafb_check_options(...) do {} while (0)
1da177e4
LT		 1672#endif
1673
4f3e2664
EM		 1674static int __devinit pxafb_probe(struct platform_device *dev)
1675{
1676 struct pxafb_info *fbi;
1677 struct pxafb_mach_info *inf;
1678 struct resource *r;
1679 int irq, ret;
1680
1681 dev_dbg(&dev->dev, "pxafb_probe\n");
1682
1683 inf = dev->dev.platform_data;
1684 ret = -ENOMEM;
1685 fbi = NULL;
1686 if (!inf)
1687 goto failed;
1688
1689 ret = pxafb_parse_options(&dev->dev, g_options);
1690 if (ret < 0)
1691 goto failed;
1692
1693 pxafb_check_options(&dev->dev, inf);
1694
b0086efb 1695 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1696 inf->modes->xres,
1697 inf->modes->yres,
1698 inf->modes->bpp);
1699 if (inf->modes->xres == 0 ||
1700 inf->modes->yres == 0 ||
1701 inf->modes->bpp == 0) {
3ae5eaec 1702 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 1703 ret = -EINVAL;
1704 goto failed;
1705 }
a5718a14 1706
3ae5eaec 1707 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 1708 if (!fbi) {
b0086efb 1709 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 1710 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 1711 ret = -ENOMEM;
1da177e4
LT		 1712 goto failed;
1713 }
1714
a5718a14
EM		 1715 fbi->backlight_power = inf->pxafb_backlight_power;
1716 fbi->lcd_power = inf->pxafb_lcd_power;
1717
ce4fb7b8 1718 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1719 if (r == NULL) {
1720 dev_err(&dev->dev, "no I/O memory resource defined\n");
1721 ret = -ENODEV;
ee98476b 1722 goto failed_fbi;
ce4fb7b8 1723 }
1724
1725 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1726 if (r == NULL) {
1727 dev_err(&dev->dev, "failed to request I/O memory\n");
1728 ret = -EBUSY;
ee98476b 1729 goto failed_fbi;
ce4fb7b8 1730 }
1731
1732 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1733 if (fbi->mmio_base == NULL) {
1734 dev_err(&dev->dev, "failed to map I/O memory\n");
1735 ret = -EBUSY;
1736 goto failed_free_res;
1737 }
1738
1da177e4
LT		 1739 /* Initialize video memory */
1740 ret = pxafb_map_video_memory(fbi);
1741 if (ret) {
3ae5eaec 1742 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 1743 ret = -ENOMEM;
ce4fb7b8 1744 goto failed_free_io;
1da177e4 1745 }
1da177e4 1746
ce4fb7b8 1747 irq = platform_get_irq(dev, 0);
1748 if (irq < 0) {
1749 dev_err(&dev->dev, "no IRQ defined\n");
1750 ret = -ENODEV;
1751 goto failed_free_mem;
1752 }
1753
1754 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1da177e4 1755 if (ret) {
3ae5eaec 1756 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 1757 ret = -EBUSY;
ce4fb7b8 1758 goto failed_free_mem;
1da177e4
LT		 1759 }
1760
3c42a449
EM		 1761 ret = pxafb_smart_init(fbi);
1762 if (ret) {
1763 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1764 goto failed_free_irq;
1765 }
07df1c4f 1766
1da177e4
LT		 1767 /*
1768 * This makes sure that our colour bitfield
1769 * descriptors are correctly initialised.
1770 */
ee98476b
JK		 1771 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1772 if (ret) {
1773 dev_err(&dev->dev, "failed to get suitable mode\n");
1774 goto failed_free_irq;
1775 }
1776
1777 ret = pxafb_set_par(&fbi->fb);
1778 if (ret) {
1779 dev_err(&dev->dev, "Failed to set parameters\n");
1780 goto failed_free_irq;
1781 }
1da177e4 1782
3ae5eaec 1783 platform_set_drvdata(dev, fbi);
1da177e4
LT		 1784
1785 ret = register_framebuffer(&fbi->fb);
1786 if (ret < 0) {
b0086efb 1787 dev_err(&dev->dev,
1788 "Failed to register framebuffer device: %d\n", ret);
ee98476b 1789 goto failed_free_cmap;
1da177e4
LT		 1790 }
1791
1da177e4
LT		 1792#ifdef CONFIG_CPU_FREQ
1793 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1794 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 1795 cpufreq_register_notifier(&fbi->freq_transition,
1796 CPUFREQ_TRANSITION_NOTIFIER);
1797 cpufreq_register_notifier(&fbi->freq_policy,
1798 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 1799#endif
1800
1801 /*
1802 * Ok, now enable the LCD controller
1803 */
1804 set_ctrlr_state(fbi, C_ENABLE);
1805
1806 return 0;
1807
ee98476b
JK		 1808failed_free_cmap:
1809 if (fbi->fb.cmap.len)
1810 fb_dealloc_cmap(&fbi->fb.cmap);
ce4fb7b8 1811failed_free_irq:
1812 free_irq(irq, fbi);
ce4fb7b8 1813failed_free_mem:
1814 dma_free_writecombine(&dev->dev, fbi->map_size,
1815 fbi->map_cpu, fbi->map_dma);
ee98476b
JK		 1816failed_free_io:
1817 iounmap(fbi->mmio_base);
1818failed_free_res:
1819 release_mem_region(r->start, r->end - r->start + 1);
1820failed_fbi:
1821 clk_put(fbi->clk);
3ae5eaec 1822 platform_set_drvdata(dev, NULL);
1da177e4 1823 kfree(fbi);
ee98476b 1824failed:
1da177e4
LT		 1825 return ret;
1826}
1827
9f17f287
JK		 1828static int __devexit pxafb_remove(struct platform_device *dev)
1829{
1830 struct pxafb_info *fbi = platform_get_drvdata(dev);
1831 struct resource *r;
1832 int irq;
1833 struct fb_info *info;
1834
1835 if (!fbi)
1836 return 0;
1837
1838 info = &fbi->fb;
1839
1840 unregister_framebuffer(info);
1841
1842 pxafb_disable_controller(fbi);
1843
1844 if (fbi->fb.cmap.len)
1845 fb_dealloc_cmap(&fbi->fb.cmap);
1846
1847 irq = platform_get_irq(dev, 0);
1848 free_irq(irq, fbi);
1849
1850 dma_free_writecombine(&dev->dev, fbi->map_size,
1851 fbi->map_cpu, fbi->map_dma);
1852
1853 iounmap(fbi->mmio_base);
1854
1855 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1856 release_mem_region(r->start, r->end - r->start + 1);
1857
1858 clk_put(fbi->clk);
1859 kfree(fbi);
1860
1861 return 0;
1862}
1863
3ae5eaec 1864static struct platform_driver pxafb_driver = {
1da177e4 1865 .probe = pxafb_probe,
9f17f287 1866 .remove = pxafb_remove,
1da177e4
LT		 1867 .suspend = pxafb_suspend,
1868 .resume = pxafb_resume,
3ae5eaec 1869 .driver = {
9f17f287 1870 .owner = THIS_MODULE,
3ae5eaec
RK		 1871 .name = "pxa2xx-fb",
1872 },
1da177e4
LT		 1873};
1874
9e6c2976 1875static int __init pxafb_init(void)
1da177e4 1876{
92ac73c1 1877 if (pxafb_setup_options())
1878 return -EINVAL;
1da177e4 1879
3ae5eaec 1880 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 1881}
1882
9f17f287
JK		 1883static void __exit pxafb_exit(void)
1884{
1885 platform_driver_unregister(&pxafb_driver);
1886}
1887
1da177e4 1888module_init(pxafb_init);
9f17f287 1889module_exit(pxafb_exit);
1da177e4
LT		 1890
1891MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1892MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)