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video/sis/: remove compat code
[linux-2.6-block.git] / drivers / video / pxafb.c
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1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/errno.h>
30#include <linux/string.h>
31#include <linux/interrupt.h>
32#include <linux/slab.h>
27ac792c 33#include <linux/mm.h>
1da177e4
LT		 34#include <linux/fb.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/ioport.h>
38#include <linux/cpufreq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4 40#include <linux/dma-mapping.h>
72e3524c
RK		 41#include <linux/clk.h>
42#include <linux/err.h>
2ba162b9 43#include <linux/completion.h>
3c42a449
EM		 44#include <linux/kthread.h>
45#include <linux/freezer.h>
1da177e4
LT		 46
47#include <asm/hardware.h>
48#include <asm/io.h>
49#include <asm/irq.h>
bf1b8ab6 50#include <asm/div64.h>
1da177e4 51#include <asm/arch/pxa-regs.h>
a683b14d 52#include <asm/arch/pxa2xx-gpio.h>
1da177e4
LT		 53#include <asm/arch/bitfield.h>
54#include <asm/arch/pxafb.h>
55
56/*
57 * Complain if VAR is out of range.
58 */
59#define DEBUG_VAR 1
60
61#include "pxafb.h"
62
63/* Bits which should not be set in machine configuration structures */
b0086efb 64#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
67
68#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP)
1da177e4
LT		 70
71static void (*pxafb_backlight_power)(int);
d14b272b 72static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
1da177e4 73
b0086efb 74static int pxafb_activate_var(struct fb_var_screeninfo *var,
75 struct pxafb_info *);
1da177e4
LT		 76static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
77
a7535ba7
EM		 78static inline unsigned long
79lcd_readl(struct pxafb_info *fbi, unsigned int off)
80{
81 return __raw_readl(fbi->mmio_base + off);
82}
83
84static inline void
85lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
86{
87 __raw_writel(val, fbi->mmio_base + off);
88}
89
1da177e4
LT		 90static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
91{
92 unsigned long flags;
93
94 local_irq_save(flags);
95 /*
96 * We need to handle two requests being made at the same time.
97 * There are two important cases:
b0086efb 98 * 1. When we are changing VT (C_REENABLE) while unblanking
99 * (C_ENABLE) We must perform the unblanking, which will
100 * do our REENABLE for us.
101 * 2. When we are blanking, but immediately unblank before
102 * we have blanked. We do the "REENABLE" thing here as
103 * well, just to be sure.
1da177e4
LT		 104 */
105 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
106 state = (u_int) -1;
107 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
108 state = C_REENABLE;
109
110 if (state != (u_int)-1) {
111 fbi->task_state = state;
112 schedule_work(&fbi->task);
113 }
114 local_irq_restore(flags);
115}
116
117static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
118{
119 chan &= 0xffff;
120 chan >>= 16 - bf->length;
121 return chan << bf->offset;
122}
123
124static int
125pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
126 u_int trans, struct fb_info *info)
127{
128 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 129 u_int val;
130
131 if (regno >= fbi->palette_size)
132 return 1;
133
134 if (fbi->fb.var.grayscale) {
135 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
136 return 0;
137 }
138
139 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
140 case LCCR4_PAL_FOR_0:
141 val = ((red >> 0) & 0xf800);
142 val |= ((green >> 5) & 0x07e0);
143 val |= ((blue >> 11) & 0x001f);
1da177e4 144 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 145 break;
146 case LCCR4_PAL_FOR_1:
147 val = ((red << 8) & 0x00f80000);
148 val |= ((green >> 0) & 0x0000fc00);
149 val |= ((blue >> 8) & 0x000000f8);
b0086efb 150 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 151 break;
152 case LCCR4_PAL_FOR_2:
153 val = ((red << 8) & 0x00fc0000);
154 val |= ((green >> 0) & 0x0000fc00);
155 val |= ((blue >> 8) & 0x000000fc);
b0086efb 156 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 157 break;
1da177e4 158 }
9ffa7396
HK		 159
160 return 0;
1da177e4
LT		 161}
162
163static int
164pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
165 u_int trans, struct fb_info *info)
166{
167 struct pxafb_info *fbi = (struct pxafb_info *)info;
168 unsigned int val;
169 int ret = 1;
170
171 /*
172 * If inverse mode was selected, invert all the colours
173 * rather than the register number. The register number
174 * is what you poke into the framebuffer to produce the
175 * colour you requested.
176 */
177 if (fbi->cmap_inverse) {
178 red = 0xffff - red;
179 green = 0xffff - green;
180 blue = 0xffff - blue;
181 }
182
183 /*
184 * If greyscale is true, then we convert the RGB value
185 * to greyscale no matter what visual we are using.
186 */
187 if (fbi->fb.var.grayscale)
188 red = green = blue = (19595 * red + 38470 * green +
189 7471 * blue) >> 16;
190
191 switch (fbi->fb.fix.visual) {
192 case FB_VISUAL_TRUECOLOR:
193 /*
194 * 16-bit True Colour. We encode the RGB value
195 * according to the RGB bitfield information.
196 */
197 if (regno < 16) {
198 u32 *pal = fbi->fb.pseudo_palette;
199
200 val = chan_to_field(red, &fbi->fb.var.red);
201 val |= chan_to_field(green, &fbi->fb.var.green);
202 val |= chan_to_field(blue, &fbi->fb.var.blue);
203
204 pal[regno] = val;
205 ret = 0;
206 }
207 break;
208
209 case FB_VISUAL_STATIC_PSEUDOCOLOR:
210 case FB_VISUAL_PSEUDOCOLOR:
211 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
212 break;
213 }
214
215 return ret;
216}
217
218/*
219 * pxafb_bpp_to_lccr3():
220 * Convert a bits per pixel value to the correct bit pattern for LCCR3
221 */
222static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
223{
b0086efb 224 int ret = 0;
225 switch (var->bits_per_pixel) {
226 case 1: ret = LCCR3_1BPP; break;
227 case 2: ret = LCCR3_2BPP; break;
228 case 4: ret = LCCR3_4BPP; break;
229 case 8: ret = LCCR3_8BPP; break;
230 case 16: ret = LCCR3_16BPP; break;
c1450f15
SS		 231 case 24:
232 switch (var->red.length + var->green.length +
233 var->blue.length + var->transp.length) {
234 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
235 case 19: ret = LCCR3_19BPP_P; break;
236 }
237 break;
238 case 32:
239 switch (var->red.length + var->green.length +
240 var->blue.length + var->transp.length) {
241 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
242 case 19: ret = LCCR3_19BPP; break;
243 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
244 case 25: ret = LCCR3_25BPP; break;
245 }
246 break;
b0086efb 247 }
248 return ret;
1da177e4
LT		 249}
250
251#ifdef CONFIG_CPU_FREQ
252/*
253 * pxafb_display_dma_period()
254 * Calculate the minimum period (in picoseconds) between two DMA
255 * requests for the LCD controller. If we hit this, it means we're
256 * doing nothing but LCD DMA.
257 */
258static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
259{
b0086efb 260 /*
261 * Period = pixclock * bits_per_byte * bytes_per_transfer
262 * / memory_bits_per_pixel;
263 */
264 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 265}
1da177e4
LT		 266#endif
267
d14b272b
RP		 268/*
269 * Select the smallest mode that allows the desired resolution to be
270 * displayed. If desired parameters can be rounded up.
271 */
b0086efb 272static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
273 struct fb_var_screeninfo *var)
d14b272b
RP		 274{
275 struct pxafb_mode_info *mode = NULL;
276 struct pxafb_mode_info *modelist = mach->modes;
277 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
278 unsigned int i;
279
b0086efb 280 for (i = 0; i < mach->num_modes; i++) {
281 if (modelist[i].xres >= var->xres &&
282 modelist[i].yres >= var->yres &&
283 modelist[i].xres < best_x &&
284 modelist[i].yres < best_y &&
285 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 286 best_x = modelist[i].xres;
287 best_y = modelist[i].yres;
288 mode = &modelist[i];
289 }
290 }
291
292 return mode;
293}
294
b0086efb 295static void pxafb_setmode(struct fb_var_screeninfo *var,
296 struct pxafb_mode_info *mode)
d14b272b
RP		 297{
298 var->xres = mode->xres;
299 var->yres = mode->yres;
300 var->bits_per_pixel = mode->bpp;
301 var->pixclock = mode->pixclock;
302 var->hsync_len = mode->hsync_len;
303 var->left_margin = mode->left_margin;
304 var->right_margin = mode->right_margin;
305 var->vsync_len = mode->vsync_len;
306 var->upper_margin = mode->upper_margin;
307 var->lower_margin = mode->lower_margin;
308 var->sync = mode->sync;
309 var->grayscale = mode->cmap_greyscale;
310 var->xres_virtual = var->xres;
311 var->yres_virtual = var->yres;
312}
313
1da177e4
LT		 314/*
315 * pxafb_check_var():
316 * Get the video params out of 'var'. If a value doesn't fit, round it up,
317 * if it's too big, return -EINVAL.
318 *
319 * Round up in the following order: bits_per_pixel, xres,
320 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
321 * bitfields, horizontal timing, vertical timing.
322 */
323static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
324{
325 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 326 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1da177e4
LT		 327
328 if (var->xres < MIN_XRES)
329 var->xres = MIN_XRES;
330 if (var->yres < MIN_YRES)
331 var->yres = MIN_YRES;
d14b272b
RP		 332
333 if (inf->fixed_modes) {
334 struct pxafb_mode_info *mode;
335
336 mode = pxafb_getmode(inf, var);
337 if (!mode)
338 return -EINVAL;
339 pxafb_setmode(var, mode);
340 } else {
341 if (var->xres > inf->modes->xres)
342 return -EINVAL;
343 if (var->yres > inf->modes->yres)
344 return -EINVAL;
345 if (var->bits_per_pixel > inf->modes->bpp)
346 return -EINVAL;
347 }
348
1da177e4
LT		 349 var->xres_virtual =
350 max(var->xres_virtual, var->xres);
351 var->yres_virtual =
352 max(var->yres_virtual, var->yres);
353
b0086efb 354 /*
1da177e4
LT		 355 * Setup the RGB parameters for this display.
356 *
357 * The pixel packing format is described on page 7-11 of the
358 * PXA2XX Developer's Manual.
b0086efb 359 */
1da177e4
LT		 360 if (var->bits_per_pixel == 16) {
361 var->red.offset = 11; var->red.length = 5;
362 var->green.offset = 5; var->green.length = 6;
363 var->blue.offset = 0; var->blue.length = 5;
364 var->transp.offset = var->transp.length = 0;
c1450f15
SS		 365 } else if (var->bits_per_pixel > 16) {
366 struct pxafb_mode_info *mode;
367
368 mode = pxafb_getmode(inf, var);
369 if (!mode)
370 return -EINVAL;
371
372 switch (mode->depth) {
373 case 18: /* RGB666 */
374 var->transp.offset = var->transp.length = 0;
375 var->red.offset = 12; var->red.length = 6;
376 var->green.offset = 6; var->green.length = 6;
377 var->blue.offset = 0; var->blue.length = 6;
378 break;
379 case 19: /* RGBT666 */
380 var->transp.offset = 18; var->transp.length = 1;
381 var->red.offset = 12; var->red.length = 6;
382 var->green.offset = 6; var->green.length = 6;
383 var->blue.offset = 0; var->blue.length = 6;
384 break;
385 case 24: /* RGB888 */
386 var->transp.offset = var->transp.length = 0;
387 var->red.offset = 16; var->red.length = 8;
388 var->green.offset = 8; var->green.length = 8;
389 var->blue.offset = 0; var->blue.length = 8;
390 break;
391 case 25: /* RGBT888 */
392 var->transp.offset = 24; var->transp.length = 1;
393 var->red.offset = 16; var->red.length = 8;
394 var->green.offset = 8; var->green.length = 8;
395 var->blue.offset = 0; var->blue.length = 8;
396 break;
397 default:
398 return -EINVAL;
399 }
1da177e4 400 } else {
b0086efb 401 var->red.offset = var->green.offset = 0;
402 var->blue.offset = var->transp.offset = 0;
1da177e4
LT		 403 var->red.length = 8;
404 var->green.length = 8;
405 var->blue.length = 8;
406 var->transp.length = 0;
407 }
408
409#ifdef CONFIG_CPU_FREQ
78d3cfd3
RK		 410 pr_debug("pxafb: dma period = %d ps\n",
411 pxafb_display_dma_period(var));
1da177e4
LT		 412#endif
413
414 return 0;
415}
416
417static inline void pxafb_set_truecolor(u_int is_true_color)
418{
b0086efb 419 /* do your machine-specific setup if needed */
1da177e4
LT		 420}
421
422/*
423 * pxafb_set_par():
424 * Set the user defined part of the display for the specified console
425 */
426static int pxafb_set_par(struct fb_info *info)
427{
428 struct pxafb_info *fbi = (struct pxafb_info *)info;
429 struct fb_var_screeninfo *var = &info->var;
1da177e4 430
c1450f15 431 if (var->bits_per_pixel >= 16)
1da177e4
LT		 432 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
433 else if (!fbi->cmap_static)
434 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
435 else {
436 /*
437 * Some people have weird ideas about wanting static
438 * pseudocolor maps. I suspect their user space
439 * applications are broken.
440 */
441 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
442 }
443
444 fbi->fb.fix.line_length = var->xres_virtual *
445 var->bits_per_pixel / 8;
c1450f15 446 if (var->bits_per_pixel >= 16)
1da177e4
LT		 447 fbi->palette_size = 0;
448 else
b0086efb 449 fbi->palette_size = var->bits_per_pixel == 1 ?
450 4 : 1 << var->bits_per_pixel;
1da177e4 451
2c42dd8e 452 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4
LT		 453
454 /*
455 * Set (any) board control register to handle new color depth
456 */
457 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
458
c1450f15 459 if (fbi->fb.var.bits_per_pixel >= 16)
1da177e4
LT		 460 fb_dealloc_cmap(&fbi->fb.cmap);
461 else
462 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
463
464 pxafb_activate_var(var, fbi);
465
466 return 0;
467}
468
1da177e4
LT		 469/*
470 * pxafb_blank():
471 * Blank the display by setting all palette values to zero. Note, the
472 * 16 bpp mode does not really use the palette, so this will not
473 * blank the display in all modes.
474 */
475static int pxafb_blank(int blank, struct fb_info *info)
476{
477 struct pxafb_info *fbi = (struct pxafb_info *)info;
478 int i;
479
1da177e4
LT		 480 switch (blank) {
481 case FB_BLANK_POWERDOWN:
482 case FB_BLANK_VSYNC_SUSPEND:
483 case FB_BLANK_HSYNC_SUSPEND:
484 case FB_BLANK_NORMAL:
485 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
486 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
487 for (i = 0; i < fbi->palette_size; i++)
488 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
489
490 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 491 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 492 break;
493
494 case FB_BLANK_UNBLANK:
b0086efb 495 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 496 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
497 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
498 fb_set_cmap(&fbi->fb.cmap, info);
499 pxafb_schedule_work(fbi, C_ENABLE);
500 }
501 return 0;
502}
503
216d526c 504static int pxafb_mmap(struct fb_info *info,
1da177e4
LT		 505 struct vm_area_struct *vma)
506{
507 struct pxafb_info *fbi = (struct pxafb_info *)info;
508 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
509
510 if (off < info->fix.smem_len) {
3c42a449 511 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
1da177e4
LT		 512 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
513 fbi->map_dma, fbi->map_size);
514 }
515 return -EINVAL;
516}
517
518static struct fb_ops pxafb_ops = {
519 .owner = THIS_MODULE,
520 .fb_check_var = pxafb_check_var,
521 .fb_set_par = pxafb_set_par,
522 .fb_setcolreg = pxafb_setcolreg,
523 .fb_fillrect = cfb_fillrect,
524 .fb_copyarea = cfb_copyarea,
525 .fb_imageblit = cfb_imageblit,
526 .fb_blank = pxafb_blank,
1da177e4
LT		 527 .fb_mmap = pxafb_mmap,
528};
529
530/*
531 * Calculate the PCD value from the clock rate (in picoseconds).
532 * We take account of the PPCR clock setting.
533 * From PXA Developer's Manual:
534 *
535 * PixelClock = LCLK
536 * -------------
537 * 2 ( PCD + 1 )
538 *
539 * PCD = LCLK
540 * ------------- - 1
541 * 2(PixelClock)
542 *
543 * Where:
544 * LCLK = LCD/Memory Clock
545 * PCD = LCCR3[7:0]
546 *
547 * PixelClock here is in Hz while the pixclock argument given is the
548 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
549 *
550 * The function get_lclk_frequency_10khz returns LCLK in units of
551 * 10khz. Calling the result of this function lclk gives us the
552 * following
553 *
554 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
555 * -------------------------------------- - 1
556 * 2
557 *
558 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
559 */
b0086efb 560static inline unsigned int get_pcd(struct pxafb_info *fbi,
561 unsigned int pixclock)
1da177e4
LT		 562{
563 unsigned long long pcd;
564
565 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 566 * (DPC) bit? or perhaps set it based on the various clock
567 * speeds */
568 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
569 pcd *= pixclock;
bf1b8ab6 570 do_div(pcd, 100000000 * 2);
1da177e4
LT		 571 /* no need for this, since we should subtract 1 anyway. they cancel */
572 /* pcd += 1; */ /* make up for integer math truncations */
573 return (unsigned int)pcd;
574}
575
ba44cd2d
RP		 576/*
577 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 578 * function correctly. We export it here. Note that 'hsync_time' and
579 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
580 * of the hsync period in seconds.
ba44cd2d
RP		 581 */
582static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
583{
72e3524c 584 unsigned long htime;
ba44cd2d
RP		 585
586 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 587 fbi->hsync_time = 0;
ba44cd2d
RP		 588 return;
589 }
590
72e3524c
RK		 591 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
592
ba44cd2d
RP		 593 fbi->hsync_time = htime;
594}
595
596unsigned long pxafb_get_hsync_time(struct device *dev)
597{
598 struct pxafb_info *fbi = dev_get_drvdata(dev);
599
600 /* If display is blanked/suspended, hsync isn't active */
601 if (!fbi || (fbi->state != C_ENABLE))
602 return 0;
603
604 return fbi->hsync_time;
605}
606EXPORT_SYMBOL(pxafb_get_hsync_time);
607
2c42dd8e 608static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
609 unsigned int offset, size_t size)
610{
611 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
612 unsigned int dma_desc_off, pal_desc_off;
613
614 if (dma < 0 || dma >= DMA_MAX)
615 return -EINVAL;
616
617 dma_desc = &fbi->dma_buff->dma_desc[dma];
618 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
619
620 dma_desc->fsadr = fbi->screen_dma + offset;
621 dma_desc->fidr = 0;
622 dma_desc->ldcmd = size;
623
624 if (pal < 0 || pal >= PAL_MAX) {
625 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
626 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
627 } else {
62cfcf4f
JS		 628 pal_desc = &fbi->dma_buff->pal_desc[pal];
629 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
2c42dd8e 630
631 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
632 pal_desc->fidr = 0;
633
634 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
635 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
636 else
637 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
638
639 pal_desc->ldcmd |= LDCMD_PAL;
640
641 /* flip back and forth between palette and frame buffer */
642 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
643 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
644 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
645 }
646
647 return 0;
648}
649
3c42a449
EM		 650#ifdef CONFIG_FB_PXA_SMARTPANEL
651static int setup_smart_dma(struct pxafb_info *fbi)
652{
653 struct pxafb_dma_descriptor *dma_desc;
654 unsigned long dma_desc_off, cmd_buff_off;
655
656 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
657 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
658 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
659
660 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
661 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
662 dma_desc->fidr = 0;
663 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
664
665 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
666 return 0;
667}
668
669int pxafb_smart_flush(struct fb_info *info)
670{
671 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
672 uint32_t prsr;
673 int ret = 0;
674
675 /* disable controller until all registers are set up */
676 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
677
678 /* 1. make it an even number of commands to align on 32-bit boundary
679 * 2. add the interrupt command to the end of the chain so we can
680 * keep track of the end of the transfer
681 */
682
683 while (fbi->n_smart_cmds & 1)
684 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
685
686 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
687 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
688 setup_smart_dma(fbi);
689
690 /* continue to execute next command */
691 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
692 lcd_writel(fbi, PRSR, prsr);
693
694 /* stop the processor in case it executed "wait for sync" cmd */
695 lcd_writel(fbi, CMDCR, 0x0001);
696
697 /* don't send interrupts for fifo underruns on channel 6 */
698 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
699
700 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
701 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
702 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
703 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
704 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
705
706 /* begin sending */
707 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
708
709 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
710 pr_warning("%s: timeout waiting for command done\n",
711 __func__);
712 ret = -ETIMEDOUT;
713 }
714
715 /* quick disable */
716 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
717 lcd_writel(fbi, PRSR, prsr);
718 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
719 lcd_writel(fbi, FDADR6, 0);
720 fbi->n_smart_cmds = 0;
721 return ret;
722}
723
724int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
725{
726 int i;
727 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
728
729 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
730 for (i = 0; i < n_cmds; i++) {
731 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
732 pxafb_smart_flush(info);
733
734 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
735 }
736
737 return 0;
738}
739
740static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
741{
742 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
743 return (t == 0) ? 1 : t;
744}
745
746static void setup_smart_timing(struct pxafb_info *fbi,
747 struct fb_var_screeninfo *var)
748{
749 struct pxafb_mach_info *inf = fbi->dev->platform_data;
750 struct pxafb_mode_info *mode = &inf->modes[0];
751 unsigned long lclk = clk_get_rate(fbi->clk);
752 unsigned t1, t2, t3, t4;
753
754 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
755 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
756 t3 = mode->op_hold_time;
757 t4 = mode->cmd_inh_time;
758
759 fbi->reg_lccr1 =
760 LCCR1_DisWdth(var->xres) |
761 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
762 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
763 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
764
765 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
766 fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
767
768 /* FIXME: make this configurable */
769 fbi->reg_cmdcr = 1;
770}
771
772static int pxafb_smart_thread(void *arg)
773{
7f1133cb 774 struct pxafb_info *fbi = arg;
3c42a449
EM		 775 struct pxafb_mach_info *inf = fbi->dev->platform_data;
776
777 if (!fbi || !inf->smart_update) {
778 pr_err("%s: not properly initialized, thread terminated\n",
779 __func__);
780 return -EINVAL;
781 }
782
783 pr_debug("%s(): task starting\n", __func__);
784
785 set_freezable();
786 while (!kthread_should_stop()) {
787
788 if (try_to_freeze())
789 continue;
790
791 if (fbi->state == C_ENABLE) {
792 inf->smart_update(&fbi->fb);
793 complete(&fbi->refresh_done);
794 }
795
796 set_current_state(TASK_INTERRUPTIBLE);
797 schedule_timeout(30 * HZ / 1000);
798 }
799
800 pr_debug("%s(): task ending\n", __func__);
801 return 0;
802}
803
804static int pxafb_smart_init(struct pxafb_info *fbi)
805{
806 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
807 "lcd_refresh");
808 if (IS_ERR(fbi->smart_thread)) {
809 printk(KERN_ERR "%s: unable to create kernel thread\n",
810 __func__);
811 return PTR_ERR(fbi->smart_thread);
812 }
813 return 0;
814}
815#else
816int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
817{
818 return 0;
819}
820
821int pxafb_smart_flush(struct fb_info *info)
822{
823 return 0;
824}
825#endif /* CONFIG_FB_SMART_PANEL */
826
90eabbf0
EM		 827static void setup_parallel_timing(struct pxafb_info *fbi,
828 struct fb_var_screeninfo *var)
829{
830 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
831
832 fbi->reg_lccr1 =
833 LCCR1_DisWdth(var->xres) +
834 LCCR1_HorSnchWdth(var->hsync_len) +
835 LCCR1_BegLnDel(var->left_margin) +
836 LCCR1_EndLnDel(var->right_margin);
837
838 /*
839 * If we have a dual scan LCD, we need to halve
840 * the YRES parameter.
841 */
842 lines_per_panel = var->yres;
843 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
844 lines_per_panel /= 2;
845
846 fbi->reg_lccr2 =
847 LCCR2_DisHght(lines_per_panel) +
848 LCCR2_VrtSnchWdth(var->vsync_len) +
849 LCCR2_BegFrmDel(var->upper_margin) +
850 LCCR2_EndFrmDel(var->lower_margin);
851
852 fbi->reg_lccr3 = fbi->lccr3 |
853 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
854 LCCR3_HorSnchH : LCCR3_HorSnchL) |
855 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
856 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
857
858 if (pcd) {
859 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
860 set_hsync_time(fbi, pcd);
861 }
862}
863
1da177e4
LT		 864/*
865 * pxafb_activate_var():
b0086efb 866 * Configures LCD Controller based on entries in var parameter.
867 * Settings are only written to the controller if changes were made.
1da177e4 868 */
b0086efb 869static int pxafb_activate_var(struct fb_var_screeninfo *var,
870 struct pxafb_info *fbi)
1da177e4 871{
1da177e4 872 u_long flags;
2c42dd8e 873 size_t nbytes;
1da177e4 874
1da177e4 875#if DEBUG_VAR
3c42a449
EM		 876 if (!(fbi->lccr0 & LCCR0_LCDT)) {
877 if (var->xres < 16 || var->xres > 1024)
878 printk(KERN_ERR "%s: invalid xres %d\n",
879 fbi->fb.fix.id, var->xres);
880 switch (var->bits_per_pixel) {
881 case 1:
882 case 2:
883 case 4:
884 case 8:
885 case 16:
c1450f15
SS		 886 case 24:
887 case 32:
3c42a449
EM		 888 break;
889 default:
890 printk(KERN_ERR "%s: invalid bit depth %d\n",
891 fbi->fb.fix.id, var->bits_per_pixel);
892 break;
893 }
894
895 if (var->hsync_len < 1 || var->hsync_len > 64)
896 printk(KERN_ERR "%s: invalid hsync_len %d\n",
897 fbi->fb.fix.id, var->hsync_len);
898 if (var->left_margin < 1 || var->left_margin > 255)
899 printk(KERN_ERR "%s: invalid left_margin %d\n",
900 fbi->fb.fix.id, var->left_margin);
901 if (var->right_margin < 1 || var->right_margin > 255)
902 printk(KERN_ERR "%s: invalid right_margin %d\n",
903 fbi->fb.fix.id, var->right_margin);
904 if (var->yres < 1 || var->yres > 1024)
905 printk(KERN_ERR "%s: invalid yres %d\n",
906 fbi->fb.fix.id, var->yres);
907 if (var->vsync_len < 1 || var->vsync_len > 64)
908 printk(KERN_ERR "%s: invalid vsync_len %d\n",
909 fbi->fb.fix.id, var->vsync_len);
910 if (var->upper_margin < 0 || var->upper_margin > 255)
911 printk(KERN_ERR "%s: invalid upper_margin %d\n",
912 fbi->fb.fix.id, var->upper_margin);
913 if (var->lower_margin < 0 || var->lower_margin > 255)
914 printk(KERN_ERR "%s: invalid lower_margin %d\n",
915 fbi->fb.fix.id, var->lower_margin);
1da177e4 916 }
1da177e4 917#endif
90eabbf0
EM		 918 /* Update shadow copy atomically */
919 local_irq_save(flags);
1da177e4 920
3c42a449
EM		 921#ifdef CONFIG_FB_PXA_SMARTPANEL
922 if (fbi->lccr0 & LCCR0_LCDT)
923 setup_smart_timing(fbi, var);
924 else
925#endif
926 setup_parallel_timing(fbi, var);
90eabbf0
EM		 927
928 fbi->reg_lccr0 = fbi->lccr0 |
1da177e4 929 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 930 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4 931
90eabbf0 932 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
1da177e4 933
90eabbf0 934 nbytes = var->yres * fbi->fb.fix.line_length;
1da177e4 935
90eabbf0
EM		 936 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
937 nbytes = nbytes / 2;
2c42dd8e 938 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
90eabbf0 939 }
2c42dd8e 940
3c42a449 941 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
2c42dd8e 942 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
943 else
944 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
1da177e4 945
a7535ba7 946 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 947 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1da177e4
LT		 948 local_irq_restore(flags);
949
950 /*
951 * Only update the registers if the controller is enabled
952 * and something has changed.
953 */
a7535ba7
EM		 954 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
955 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
956 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
957 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
958 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
959 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1da177e4
LT		 960 pxafb_schedule_work(fbi, C_REENABLE);
961
962 return 0;
963}
964
965/*
966 * NOTE! The following functions are purely helpers for set_ctrlr_state.
967 * Do not call them directly; set_ctrlr_state does the correct serialisation
968 * to ensure that things happen in the right way 100% of time time.
969 * -- rmk
970 */
971static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
972{
ca5da710 973 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 974
b0086efb 975 if (pxafb_backlight_power)
976 pxafb_backlight_power(on);
1da177e4
LT		 977}
978
979static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
980{
ca5da710 981 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4
LT		 982
983 if (pxafb_lcd_power)
d14b272b 984 pxafb_lcd_power(on, &fbi->fb.var);
1da177e4
LT		 985}
986
987static void pxafb_setup_gpio(struct pxafb_info *fbi)
988{
989 int gpio, ldd_bits;
b0086efb 990 unsigned int lccr0 = fbi->lccr0;
1da177e4
LT		 991
992 /*
993 * setup is based on type of panel supported
b0086efb 994 */
1da177e4
LT		 995
996 /* 4 bit interface */
997 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
998 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
999 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
1000 ldd_bits = 4;
1001
1002 /* 8 bit interface */
b0086efb 1003 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
1004 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1005 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
1006 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1007 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1008 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
1da177e4
LT		 1009 ldd_bits = 8;
1010
1011 /* 16 bit interface */
1012 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
b0086efb 1013 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1014 (lccr0 & LCCR0_PAS) == LCCR0_Act))
1da177e4
LT		 1015 ldd_bits = 16;
1016
1017 else {
b0086efb 1018 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
1019 "bits per pixel\n");
1da177e4 1020 return;
b0086efb 1021 }
1da177e4
LT		 1022
1023 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
1024 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
c1450f15
SS		 1025 /* 18 bit interface */
1026 if (fbi->fb.var.bits_per_pixel > 16) {
1027 pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
1028 pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
1029 }
1da177e4
LT		 1030 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
1031 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
1032 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
1033 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
1034}
1035
1036static void pxafb_enable_controller(struct pxafb_info *fbi)
1037{
ca5da710 1038 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 1039 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1040 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 1041 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1042 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1043 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1044 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 1045
8d372266 1046 /* enable LCD controller clock */
72e3524c 1047 clk_enable(fbi->clk);
8d372266 1048
3c42a449
EM		 1049 if (fbi->lccr0 & LCCR0_LCDT)
1050 return;
1051
1da177e4 1052 /* Sequence from 11.7.10 */
a7535ba7
EM		 1053 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1054 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1055 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1056 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1057
1058 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1059 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1060 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 1061}
1062
1063static void pxafb_disable_controller(struct pxafb_info *fbi)
1064{
ce4fb7b8 1065 uint32_t lccr0;
1066
3c42a449
EM		 1067#ifdef CONFIG_FB_PXA_SMARTPANEL
1068 if (fbi->lccr0 & LCCR0_LCDT) {
1069 wait_for_completion_timeout(&fbi->refresh_done,
1070 200 * HZ / 1000);
1071 return;
1072 }
1073#endif
1074
ce4fb7b8 1075 /* Clear LCD Status Register */
a7535ba7 1076 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 1077
a7535ba7
EM		 1078 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1079 lcd_writel(fbi, LCCR0, lccr0);
1080 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 1081
2ba162b9 1082 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
8d372266
NP		 1083
1084 /* disable LCD controller clock */
72e3524c 1085 clk_disable(fbi->clk);
1da177e4
LT		 1086}
1087
1088/*
1089 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1090 */
7d12e780 1091static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 1092{
1093 struct pxafb_info *fbi = dev_id;
a7535ba7 1094 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1da177e4
LT		 1095
1096 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 1097 lccr0 = lcd_readl(fbi, LCCR0);
1098 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
2ba162b9 1099 complete(&fbi->disable_done);
1da177e4
LT		 1100 }
1101
3c42a449
EM		 1102#ifdef CONFIG_FB_PXA_SMARTPANEL
1103 if (lcsr & LCSR_CMD_INT)
1104 complete(&fbi->command_done);
1105#endif
1106
a7535ba7 1107 lcd_writel(fbi, LCSR, lcsr);
1da177e4
LT		 1108 return IRQ_HANDLED;
1109}
1110
1111/*
1112 * This function must be called from task context only, since it will
1113 * sleep when disabling the LCD controller, or if we get two contending
1114 * processes trying to alter state.
1115 */
1116static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1117{
1118 u_int old_state;
1119
1120 down(&fbi->ctrlr_sem);
1121
1122 old_state = fbi->state;
1123
1124 /*
1125 * Hack around fbcon initialisation.
1126 */
1127 if (old_state == C_STARTUP && state == C_REENABLE)
1128 state = C_ENABLE;
1129
1130 switch (state) {
1131 case C_DISABLE_CLKCHANGE:
1132 /*
1133 * Disable controller for clock change. If the
1134 * controller is already disabled, then do nothing.
1135 */
1136 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1137 fbi->state = state;
b0086efb 1138 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 1139 pxafb_disable_controller(fbi);
1140 }
1141 break;
1142
1143 case C_DISABLE_PM:
1144 case C_DISABLE:
1145 /*
1146 * Disable controller
1147 */
1148 if (old_state != C_DISABLE) {
1149 fbi->state = state;
1150 __pxafb_backlight_power(fbi, 0);
1151 __pxafb_lcd_power(fbi, 0);
1152 if (old_state != C_DISABLE_CLKCHANGE)
1153 pxafb_disable_controller(fbi);
1154 }
1155 break;
1156
1157 case C_ENABLE_CLKCHANGE:
1158 /*
1159 * Enable the controller after clock change. Only
1160 * do this if we were disabled for the clock change.
1161 */
1162 if (old_state == C_DISABLE_CLKCHANGE) {
1163 fbi->state = C_ENABLE;
1164 pxafb_enable_controller(fbi);
b0086efb 1165 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 1166 }
1167 break;
1168
1169 case C_REENABLE:
1170 /*
1171 * Re-enable the controller only if it was already
1172 * enabled. This is so we reprogram the control
1173 * registers.
1174 */
1175 if (old_state == C_ENABLE) {
d14b272b 1176 __pxafb_lcd_power(fbi, 0);
1da177e4
LT		 1177 pxafb_disable_controller(fbi);
1178 pxafb_setup_gpio(fbi);
1179 pxafb_enable_controller(fbi);
d14b272b 1180 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 1181 }
1182 break;
1183
1184 case C_ENABLE_PM:
1185 /*
1186 * Re-enable the controller after PM. This is not
1187 * perfect - think about the case where we were doing
1188 * a clock change, and we suspended half-way through.
1189 */
1190 if (old_state != C_DISABLE_PM)
1191 break;
1192 /* fall through */
1193
1194 case C_ENABLE:
1195 /*
1196 * Power up the LCD screen, enable controller, and
1197 * turn on the backlight.
1198 */
1199 if (old_state != C_ENABLE) {
1200 fbi->state = C_ENABLE;
1201 pxafb_setup_gpio(fbi);
1202 pxafb_enable_controller(fbi);
1203 __pxafb_lcd_power(fbi, 1);
1204 __pxafb_backlight_power(fbi, 1);
1205 }
1206 break;
1207 }
1208 up(&fbi->ctrlr_sem);
1209}
1210
1211/*
1212 * Our LCD controller task (which is called when we blank or unblank)
1213 * via keventd.
1214 */
6d5aefb8 1215static void pxafb_task(struct work_struct *work)
1da177e4 1216{
6d5aefb8
DH		 1217 struct pxafb_info *fbi =
1218 container_of(work, struct pxafb_info, task);
1da177e4
LT		 1219 u_int state = xchg(&fbi->task_state, -1);
1220
1221 set_ctrlr_state(fbi, state);
1222}
1223
1224#ifdef CONFIG_CPU_FREQ
1225/*
1226 * CPU clock speed change handler. We need to adjust the LCD timing
1227 * parameters when the CPU clock is adjusted by the power management
1228 * subsystem.
1229 *
1230 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1231 */
1232static int
1233pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1234{
1235 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 1236 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 1237 u_int pcd;
1238
1239 switch (val) {
1240 case CPUFREQ_PRECHANGE:
1241 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1242 break;
1243
1244 case CPUFREQ_POSTCHANGE:
72e3524c 1245 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 1246 set_hsync_time(fbi, pcd);
b0086efb 1247 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1248 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 1249 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1250 break;
1251 }
1252 return 0;
1253}
1254
1255static int
1256pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1257{
1258 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1259 struct fb_var_screeninfo *var = &fbi->fb.var;
1260 struct cpufreq_policy *policy = data;
1261
1262 switch (val) {
1263 case CPUFREQ_ADJUST:
1264 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1265 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1266 "new clock %d kHz\n", pxafb_display_dma_period(var),
1267 policy->max);
b0086efb 1268 /* TODO: fill in min/max values */
1da177e4 1269 break;
1da177e4
LT		 1270 }
1271 return 0;
1272}
1273#endif
1274
1275#ifdef CONFIG_PM
1276/*
1277 * Power management hooks. Note that we won't be called from IRQ context,
1278 * unlike the blank functions above, so we may sleep.
1279 */
3ae5eaec 1280static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1281{
3ae5eaec 1282 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1283
9480e307 1284 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1285 return 0;
1286}
1287
3ae5eaec 1288static int pxafb_resume(struct platform_device *dev)
1da177e4 1289{
3ae5eaec 1290 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1291
9480e307 1292 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1293 return 0;
1294}
1295#else
1296#define pxafb_suspend NULL
1297#define pxafb_resume NULL
1298#endif
1299
1300/*
1301 * pxafb_map_video_memory():
1302 * Allocates the DRAM memory for the frame buffer. This buffer is
1303 * remapped into a non-cached, non-buffered, memory region to
1304 * allow palette and pixel writes to occur without flushing the
1305 * cache. Once this area is remapped, all virtual memory
1306 * access to the video memory should occur at the new region.
1307 */
9e6c2976 1308static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1da177e4 1309{
1da177e4
LT		 1310 /*
1311 * We reserve one page for the palette, plus the size
1312 * of the framebuffer.
1313 */
3c42a449
EM		 1314 fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1315 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1da177e4
LT		 1316 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1317 &fbi->map_dma, GFP_KERNEL);
1318
1319 if (fbi->map_cpu) {
1320 /* prevent initial garbage on screen */
1321 memset(fbi->map_cpu, 0, fbi->map_size);
3c42a449
EM		 1322 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1323 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1324
1da177e4
LT		 1325 /*
1326 * FIXME: this is actually the wrong thing to place in
1327 * smem_start. But fbdev suffers from the problem that
1328 * it needs an API which doesn't exist (in this case,
1329 * dma_writecombine_mmap)
1330 */
1331 fbi->fb.fix.smem_start = fbi->screen_dma;
1da177e4
LT		 1332 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1333
3c42a449 1334 fbi->dma_buff = (void *) fbi->map_cpu;
2c42dd8e 1335 fbi->dma_buff_phys = fbi->map_dma;
3c42a449
EM		 1336 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1337
62cfcf4f
JS		 1338 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", fbi->palette_size*sizeof(u16));
1339
3c42a449
EM		 1340#ifdef CONFIG_FB_PXA_SMARTPANEL
1341 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1342 fbi->n_smart_cmds = 0;
1343#endif
1da177e4
LT		 1344 }
1345
1346 return fbi->map_cpu ? 0 : -ENOMEM;
1347}
1348
84f43c30 1349static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1350 struct pxafb_mode_info *modes,
1351 unsigned int num_modes)
1352{
1353 unsigned int i, smemlen;
1354
1355 pxafb_setmode(&fbi->fb.var, &modes[0]);
1356
1357 for (i = 0; i < num_modes; i++) {
1358 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1359 if (smemlen > fbi->fb.fix.smem_len)
1360 fbi->fb.fix.smem_len = smemlen;
1361 }
1362}
1363
ebdf982a
GL		 1364static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1365 struct pxafb_mach_info *inf)
84f43c30 1366{
1367 unsigned int lcd_conn = inf->lcd_conn;
1368
1369 fbi->cmap_inverse = inf->cmap_inverse;
1370 fbi->cmap_static = inf->cmap_static;
1371
1372 switch (lcd_conn & 0xf) {
1373 case LCD_TYPE_MONO_STN:
1374 fbi->lccr0 = LCCR0_CMS;
1375 break;
1376 case LCD_TYPE_MONO_DSTN:
1377 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1378 break;
1379 case LCD_TYPE_COLOR_STN:
1380 fbi->lccr0 = 0;
1381 break;
1382 case LCD_TYPE_COLOR_DSTN:
1383 fbi->lccr0 = LCCR0_SDS;
1384 break;
1385 case LCD_TYPE_COLOR_TFT:
1386 fbi->lccr0 = LCCR0_PAS;
1387 break;
1388 case LCD_TYPE_SMART_PANEL:
1389 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1390 break;
1391 default:
1392 /* fall back to backward compatibility way */
1393 fbi->lccr0 = inf->lccr0;
1394 fbi->lccr3 = inf->lccr3;
1395 fbi->lccr4 = inf->lccr4;
ebdf982a 1396 goto decode_mode;
84f43c30 1397 }
1398
1399 if (lcd_conn == LCD_MONO_STN_8BPP)
1400 fbi->lccr0 |= LCCR0_DPD;
1401
1402 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1403 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1404 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1405
ebdf982a 1406decode_mode:
84f43c30 1407 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
84f43c30 1408}
1409
9e6c2976 1410static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1da177e4
LT		 1411{
1412 struct pxafb_info *fbi;
1413 void *addr;
1414 struct pxafb_mach_info *inf = dev->platform_data;
1415
1416 /* Alloc the pxafb_info and pseudo_palette in one step */
1417 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1418 if (!fbi)
1419 return NULL;
1420
1421 memset(fbi, 0, sizeof(struct pxafb_info));
1422 fbi->dev = dev;
1423
72e3524c
RK		 1424 fbi->clk = clk_get(dev, "LCDCLK");
1425 if (IS_ERR(fbi->clk)) {
1426 kfree(fbi);
1427 return NULL;
1428 }
1429
1da177e4
LT		 1430 strcpy(fbi->fb.fix.id, PXA_NAME);
1431
1432 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1433 fbi->fb.fix.type_aux = 0;
1434 fbi->fb.fix.xpanstep = 0;
1435 fbi->fb.fix.ypanstep = 0;
1436 fbi->fb.fix.ywrapstep = 0;
1437 fbi->fb.fix.accel = FB_ACCEL_NONE;
1438
1439 fbi->fb.var.nonstd = 0;
1440 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1441 fbi->fb.var.height = -1;
1442 fbi->fb.var.width = -1;
1443 fbi->fb.var.accel_flags = 0;
1444 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1445
1446 fbi->fb.fbops = &pxafb_ops;
1447 fbi->fb.flags = FBINFO_DEFAULT;
1448 fbi->fb.node = -1;
1449
1450 addr = fbi;
1451 addr = addr + sizeof(struct pxafb_info);
1452 fbi->fb.pseudo_palette = addr;
1453
b0086efb 1454 fbi->state = C_STARTUP;
1455 fbi->task_state = (u_char)-1;
d14b272b 1456
84f43c30 1457 pxafb_decode_mach_info(fbi, inf);
1da177e4
LT		 1458
1459 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1460 INIT_WORK(&fbi->task, pxafb_task);
1da177e4 1461 init_MUTEX(&fbi->ctrlr_sem);
2ba162b9 1462 init_completion(&fbi->disable_done);
3c42a449
EM		 1463#ifdef CONFIG_FB_PXA_SMARTPANEL
1464 init_completion(&fbi->command_done);
1465 init_completion(&fbi->refresh_done);
1466#endif
1da177e4
LT		 1467
1468 return fbi;
1469}
1470
1471#ifdef CONFIG_FB_PXA_PARAMETERS
9e6c2976 1472static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1473{
1474 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1475
1476 const char *name = this_opt+5;
1477 unsigned int namelen = strlen(name);
1478 int res_specified = 0, bpp_specified = 0;
1479 unsigned int xres = 0, yres = 0, bpp = 0;
1480 int yres_specified = 0;
1481 int i;
1482 for (i = namelen-1; i >= 0; i--) {
1483 switch (name[i]) {
1484 case '-':
1485 namelen = i;
1486 if (!bpp_specified && !yres_specified) {
1487 bpp = simple_strtoul(&name[i+1], NULL, 0);
1488 bpp_specified = 1;
1489 } else
1490 goto done;
1491 break;
1492 case 'x':
1493 if (!yres_specified) {
1494 yres = simple_strtoul(&name[i+1], NULL, 0);
1495 yres_specified = 1;
1496 } else
1497 goto done;
1498 break;
1499 case '0' ... '9':
1500 break;
1501 default:
1502 goto done;
1503 }
1504 }
1505 if (i < 0 && yres_specified) {
1506 xres = simple_strtoul(name, NULL, 0);
1507 res_specified = 1;
1508 }
1509done:
1510 if (res_specified) {
1511 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1512 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1513 }
1514 if (bpp_specified)
1515 switch (bpp) {
1516 case 1:
1517 case 2:
1518 case 4:
1519 case 8:
1520 case 16:
1521 inf->modes[0].bpp = bpp;
1522 dev_info(dev, "overriding bit depth: %d\n", bpp);
1523 break;
1524 default:
1525 dev_err(dev, "Depth %d is not valid\n", bpp);
1526 return -EINVAL;
1527 }
1528 return 0;
1529}
1530
9e6c2976 1531static int __devinit parse_opt(struct device *dev, char *this_opt)
817daf14 1532{
1533 struct pxafb_mach_info *inf = dev->platform_data;
1534 struct pxafb_mode_info *mode = &inf->modes[0];
1535 char s[64];
1536
1537 s[0] = '\0';
1538
1539 if (!strncmp(this_opt, "mode:", 5)) {
1540 return parse_opt_mode(dev, this_opt);
1541 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1542 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1543 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1544 } else if (!strncmp(this_opt, "left:", 5)) {
1545 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1546 sprintf(s, "left: %u\n", mode->left_margin);
1547 } else if (!strncmp(this_opt, "right:", 6)) {
1548 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1549 sprintf(s, "right: %u\n", mode->right_margin);
1550 } else if (!strncmp(this_opt, "upper:", 6)) {
1551 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1552 sprintf(s, "upper: %u\n", mode->upper_margin);
1553 } else if (!strncmp(this_opt, "lower:", 6)) {
1554 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1555 sprintf(s, "lower: %u\n", mode->lower_margin);
1556 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1557 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1558 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1559 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1560 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1561 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1562 } else if (!strncmp(this_opt, "hsync:", 6)) {
1563 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1564 sprintf(s, "hsync: Active Low\n");
1565 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1566 } else {
1567 sprintf(s, "hsync: Active High\n");
1568 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1569 }
1570 } else if (!strncmp(this_opt, "vsync:", 6)) {
1571 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1572 sprintf(s, "vsync: Active Low\n");
1573 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1574 } else {
1575 sprintf(s, "vsync: Active High\n");
1576 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1577 }
1578 } else if (!strncmp(this_opt, "dpc:", 4)) {
1579 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1580 sprintf(s, "double pixel clock: false\n");
1581 inf->lccr3 &= ~LCCR3_DPC;
1582 } else {
1583 sprintf(s, "double pixel clock: true\n");
1584 inf->lccr3 |= LCCR3_DPC;
1585 }
1586 } else if (!strncmp(this_opt, "outputen:", 9)) {
1587 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1588 sprintf(s, "output enable: active low\n");
1589 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1590 } else {
1591 sprintf(s, "output enable: active high\n");
1592 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1593 }
1594 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1595 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1596 sprintf(s, "pixel clock polarity: falling edge\n");
1597 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1598 } else {
1599 sprintf(s, "pixel clock polarity: rising edge\n");
1600 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1601 }
1602 } else if (!strncmp(this_opt, "color", 5)) {
1603 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1604 } else if (!strncmp(this_opt, "mono", 4)) {
1605 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1606 } else if (!strncmp(this_opt, "active", 6)) {
1607 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1608 } else if (!strncmp(this_opt, "passive", 7)) {
1609 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1610 } else if (!strncmp(this_opt, "single", 6)) {
1611 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1612 } else if (!strncmp(this_opt, "dual", 4)) {
1613 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1614 } else if (!strncmp(this_opt, "4pix", 4)) {
1615 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1616 } else if (!strncmp(this_opt, "8pix", 4)) {
1617 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1618 } else {
1619 dev_err(dev, "unknown option: %s\n", this_opt);
1620 return -EINVAL;
1621 }
1622
1623 if (s[0] != '\0')
1624 dev_info(dev, "override %s", s);
1625
1626 return 0;
1627}
1628
9e6c2976 1629static int __devinit pxafb_parse_options(struct device *dev, char *options)
817daf14 1630{
1da177e4 1631 char *this_opt;
817daf14 1632 int ret;
1da177e4 1633
817daf14 1634 if (!options || !*options)
1635 return 0;
1da177e4
LT		 1636
1637 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1638
1639 /* could be made table driven or similar?... */
817daf14 1640 while ((this_opt = strsep(&options, ",")) != NULL) {
1641 ret = parse_opt(dev, this_opt);
1642 if (ret)
1643 return ret;
1644 }
1645 return 0;
1da177e4 1646}
92ac73c1 1647
1648static char g_options[256] __devinitdata = "";
1649
f1edfc42 1650#ifndef MODULE
9e6c2976 1651static int __init pxafb_setup_options(void)
92ac73c1 1652{
1653 char *options = NULL;
1654
1655 if (fb_get_options("pxafb", &options))
1656 return -ENODEV;
1657
1658 if (options)
1659 strlcpy(g_options, options, sizeof(g_options));
1660
1661 return 0;
1662}
1663#else
1664#define pxafb_setup_options() (0)
1665
1666module_param_string(options, g_options, sizeof(g_options), 0);
1667MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1668#endif
1669
1670#else
1671#define pxafb_parse_options(...) (0)
1672#define pxafb_setup_options() (0)
1da177e4
LT		 1673#endif
1674
9e6c2976 1675static int __devinit pxafb_probe(struct platform_device *dev)
1da177e4
LT		 1676{
1677 struct pxafb_info *fbi;
1678 struct pxafb_mach_info *inf;
ce4fb7b8 1679 struct resource *r;
1680 int irq, ret;
1da177e4 1681
2cbbb3b5 1682 dev_dbg(&dev->dev, "pxafb_probe\n");
1da177e4 1683
3ae5eaec 1684 inf = dev->dev.platform_data;
1da177e4
LT		 1685 ret = -ENOMEM;
1686 fbi = NULL;
1687 if (!inf)
1688 goto failed;
1689
3ae5eaec 1690 ret = pxafb_parse_options(&dev->dev, g_options);
1da177e4
LT		 1691 if (ret < 0)
1692 goto failed;
1da177e4
LT		 1693
1694#ifdef DEBUG_VAR
b0086efb 1695 /* Check for various illegal bit-combinations. Currently only
1da177e4
LT		 1696 * a warning is given. */
1697
b0086efb 1698 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1699 dev_warn(&dev->dev, "machine LCCR0 setting contains "
1700 "illegal bits: %08x\n",
1701 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1702 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1703 dev_warn(&dev->dev, "machine LCCR3 setting contains "
1704 "illegal bits: %08x\n",
1705 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1706 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 1707 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1708 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1709 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
b0086efb 1710 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
1711 "only valid in passive mono"
1712 " single panel mode\n");
1713 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 1714 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
b0086efb 1715 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1716 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1717 (inf->modes->upper_margin || inf->modes->lower_margin))
1718 dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
1719 "passive mode\n");
1da177e4
LT		 1720#endif
1721
b0086efb 1722 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1723 inf->modes->xres,
1724 inf->modes->yres,
1725 inf->modes->bpp);
1726 if (inf->modes->xres == 0 ||
1727 inf->modes->yres == 0 ||
1728 inf->modes->bpp == 0) {
3ae5eaec 1729 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 1730 ret = -EINVAL;
1731 goto failed;
1732 }
1733 pxafb_backlight_power = inf->pxafb_backlight_power;
1734 pxafb_lcd_power = inf->pxafb_lcd_power;
3ae5eaec 1735 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 1736 if (!fbi) {
b0086efb 1737 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 1738 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 1739 ret = -ENOMEM;
1da177e4
LT		 1740 goto failed;
1741 }
1742
ce4fb7b8 1743 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1744 if (r == NULL) {
1745 dev_err(&dev->dev, "no I/O memory resource defined\n");
1746 ret = -ENODEV;
ee98476b 1747 goto failed_fbi;
ce4fb7b8 1748 }
1749
1750 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1751 if (r == NULL) {
1752 dev_err(&dev->dev, "failed to request I/O memory\n");
1753 ret = -EBUSY;
ee98476b 1754 goto failed_fbi;
ce4fb7b8 1755 }
1756
1757 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1758 if (fbi->mmio_base == NULL) {
1759 dev_err(&dev->dev, "failed to map I/O memory\n");
1760 ret = -EBUSY;
1761 goto failed_free_res;
1762 }
1763
1da177e4
LT		 1764 /* Initialize video memory */
1765 ret = pxafb_map_video_memory(fbi);
1766 if (ret) {
3ae5eaec 1767 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 1768 ret = -ENOMEM;
ce4fb7b8 1769 goto failed_free_io;
1da177e4 1770 }
1da177e4 1771
ce4fb7b8 1772 irq = platform_get_irq(dev, 0);
1773 if (irq < 0) {
1774 dev_err(&dev->dev, "no IRQ defined\n");
1775 ret = -ENODEV;
1776 goto failed_free_mem;
1777 }
1778
1779 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1da177e4 1780 if (ret) {
3ae5eaec 1781 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 1782 ret = -EBUSY;
ce4fb7b8 1783 goto failed_free_mem;
1da177e4
LT		 1784 }
1785
3c42a449
EM		 1786#ifdef CONFIG_FB_PXA_SMARTPANEL
1787 ret = pxafb_smart_init(fbi);
1788 if (ret) {
1789 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1790 goto failed_free_irq;
1791 }
1792#endif
1da177e4
LT		 1793 /*
1794 * This makes sure that our colour bitfield
1795 * descriptors are correctly initialised.
1796 */
ee98476b
JK		 1797 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1798 if (ret) {
1799 dev_err(&dev->dev, "failed to get suitable mode\n");
1800 goto failed_free_irq;
1801 }
1802
1803 ret = pxafb_set_par(&fbi->fb);
1804 if (ret) {
1805 dev_err(&dev->dev, "Failed to set parameters\n");
1806 goto failed_free_irq;
1807 }
1da177e4 1808
3ae5eaec 1809 platform_set_drvdata(dev, fbi);
1da177e4
LT		 1810
1811 ret = register_framebuffer(&fbi->fb);
1812 if (ret < 0) {
b0086efb 1813 dev_err(&dev->dev,
1814 "Failed to register framebuffer device: %d\n", ret);
ee98476b 1815 goto failed_free_cmap;
1da177e4
LT		 1816 }
1817
1da177e4
LT		 1818#ifdef CONFIG_CPU_FREQ
1819 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1820 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 1821 cpufreq_register_notifier(&fbi->freq_transition,
1822 CPUFREQ_TRANSITION_NOTIFIER);
1823 cpufreq_register_notifier(&fbi->freq_policy,
1824 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 1825#endif
1826
1827 /*
1828 * Ok, now enable the LCD controller
1829 */
1830 set_ctrlr_state(fbi, C_ENABLE);
1831
1832 return 0;
1833
ee98476b
JK		 1834failed_free_cmap:
1835 if (fbi->fb.cmap.len)
1836 fb_dealloc_cmap(&fbi->fb.cmap);
ce4fb7b8 1837failed_free_irq:
1838 free_irq(irq, fbi);
ce4fb7b8 1839failed_free_mem:
1840 dma_free_writecombine(&dev->dev, fbi->map_size,
1841 fbi->map_cpu, fbi->map_dma);
ee98476b
JK		 1842failed_free_io:
1843 iounmap(fbi->mmio_base);
1844failed_free_res:
1845 release_mem_region(r->start, r->end - r->start + 1);
1846failed_fbi:
1847 clk_put(fbi->clk);
3ae5eaec 1848 platform_set_drvdata(dev, NULL);
1da177e4 1849 kfree(fbi);
ee98476b 1850failed:
1da177e4
LT		 1851 return ret;
1852}
1853
9f17f287
JK		 1854static int __devexit pxafb_remove(struct platform_device *dev)
1855{
1856 struct pxafb_info *fbi = platform_get_drvdata(dev);
1857 struct resource *r;
1858 int irq;
1859 struct fb_info *info;
1860
1861 if (!fbi)
1862 return 0;
1863
1864 info = &fbi->fb;
1865
1866 unregister_framebuffer(info);
1867
1868 pxafb_disable_controller(fbi);
1869
1870 if (fbi->fb.cmap.len)
1871 fb_dealloc_cmap(&fbi->fb.cmap);
1872
1873 irq = platform_get_irq(dev, 0);
1874 free_irq(irq, fbi);
1875
1876 dma_free_writecombine(&dev->dev, fbi->map_size,
1877 fbi->map_cpu, fbi->map_dma);
1878
1879 iounmap(fbi->mmio_base);
1880
1881 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1882 release_mem_region(r->start, r->end - r->start + 1);
1883
1884 clk_put(fbi->clk);
1885 kfree(fbi);
1886
1887 return 0;
1888}
1889
3ae5eaec 1890static struct platform_driver pxafb_driver = {
1da177e4 1891 .probe = pxafb_probe,
9f17f287 1892 .remove = pxafb_remove,
1da177e4
LT		 1893 .suspend = pxafb_suspend,
1894 .resume = pxafb_resume,
3ae5eaec 1895 .driver = {
9f17f287 1896 .owner = THIS_MODULE,
3ae5eaec
RK		 1897 .name = "pxa2xx-fb",
1898 },
1da177e4
LT		 1899};
1900
9e6c2976 1901static int __init pxafb_init(void)
1da177e4 1902{
92ac73c1 1903 if (pxafb_setup_options())
1904 return -EINVAL;
1da177e4 1905
3ae5eaec 1906 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 1907}
1908
9f17f287
JK		 1909static void __exit pxafb_exit(void)
1910{
1911 platform_driver_unregister(&pxafb_driver);
1912}
1913
1da177e4 1914module_init(pxafb_init);
9f17f287 1915module_exit(pxafb_exit);
1da177e4
LT		 1916
1917MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1918MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)