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alpha: convert srm code to seq_file
[linux-2.6-block.git] / drivers / video / pxafb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
198fc108
EM		 23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24 *
25 * Copyright (C) 2004, Intel Corporation
26 *
27 * 2003/08/27: <yu.tang@intel.com>
28 * 2004/03/10: <stanley.cai@intel.com>
29 * 2004/10/28: <yan.yin@intel.com>
30 *
31 * Copyright (C) 2006-2008 Marvell International Ltd.
32 * All Rights Reserved
1da177e4
LT		 33 */
34
1da177e4
LT		 35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/kernel.h>
38#include <linux/sched.h>
39#include <linux/errno.h>
40#include <linux/string.h>
41#include <linux/interrupt.h>
42#include <linux/slab.h>
27ac792c 43#include <linux/mm.h>
1da177e4
LT		 44#include <linux/fb.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/ioport.h>
48#include <linux/cpufreq.h>
d052d1be 49#include <linux/platform_device.h>
1da177e4 50#include <linux/dma-mapping.h>
72e3524c
RK		 51#include <linux/clk.h>
52#include <linux/err.h>
2ba162b9 53#include <linux/completion.h>
b91dbce5 54#include <linux/mutex.h>
3c42a449
EM		 55#include <linux/kthread.h>
56#include <linux/freezer.h>
1da177e4 57
a09e64fb 58#include <mach/hardware.h>
1da177e4
LT		 59#include <asm/io.h>
60#include <asm/irq.h>
bf1b8ab6 61#include <asm/div64.h>
a09e64fb
RK		 62#include <mach/bitfield.h>
63#include <mach/pxafb.h>
1da177e4
LT		 64
65/*
66 * Complain if VAR is out of range.
67 */
68#define DEBUG_VAR 1
69
70#include "pxafb.h"
71
72/* Bits which should not be set in machine configuration structures */
b0086efb 73#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
74 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
75 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
76
77#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
878f5783 78 LCCR3_PCD | LCCR3_BPP(0xf))
1da177e4 79
b0086efb 80static int pxafb_activate_var(struct fb_var_screeninfo *var,
81 struct pxafb_info *);
1da177e4 82static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
448ac479
SN		 83static void setup_base_frame(struct pxafb_info *fbi,
84 struct fb_var_screeninfo *var, int branch);
198fc108
EM		 85static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
86 unsigned long offset, size_t size);
1da177e4 87
77e19675 88static unsigned long video_mem_size = 0;
1da177e4 89
a7535ba7
EM		 90static inline unsigned long
91lcd_readl(struct pxafb_info *fbi, unsigned int off)
92{
93 return __raw_readl(fbi->mmio_base + off);
94}
95
96static inline void
97lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
98{
99 __raw_writel(val, fbi->mmio_base + off);
100}
101
1da177e4
LT		 102static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
103{
104 unsigned long flags;
105
106 local_irq_save(flags);
107 /*
108 * We need to handle two requests being made at the same time.
109 * There are two important cases:
b0086efb 110 * 1. When we are changing VT (C_REENABLE) while unblanking
111 * (C_ENABLE) We must perform the unblanking, which will
112 * do our REENABLE for us.
113 * 2. When we are blanking, but immediately unblank before
114 * we have blanked. We do the "REENABLE" thing here as
115 * well, just to be sure.
1da177e4
LT		 116 */
117 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
118 state = (u_int) -1;
119 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
120 state = C_REENABLE;
121
122 if (state != (u_int)-1) {
123 fbi->task_state = state;
124 schedule_work(&fbi->task);
125 }
126 local_irq_restore(flags);
127}
128
129static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
130{
131 chan &= 0xffff;
132 chan >>= 16 - bf->length;
133 return chan << bf->offset;
134}
135
136static int
137pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
138 u_int trans, struct fb_info *info)
139{
140 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 141 u_int val;
142
143 if (regno >= fbi->palette_size)
144 return 1;
145
146 if (fbi->fb.var.grayscale) {
147 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
148 return 0;
149 }
150
151 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
152 case LCCR4_PAL_FOR_0:
153 val = ((red >> 0) & 0xf800);
154 val |= ((green >> 5) & 0x07e0);
155 val |= ((blue >> 11) & 0x001f);
1da177e4 156 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 157 break;
158 case LCCR4_PAL_FOR_1:
159 val = ((red << 8) & 0x00f80000);
160 val |= ((green >> 0) & 0x0000fc00);
161 val |= ((blue >> 8) & 0x000000f8);
b0086efb 162 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 163 break;
164 case LCCR4_PAL_FOR_2:
165 val = ((red << 8) & 0x00fc0000);
166 val |= ((green >> 0) & 0x0000fc00);
167 val |= ((blue >> 8) & 0x000000fc);
b0086efb 168 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 169 break;
a0427509
EM		 170 case LCCR4_PAL_FOR_3:
171 val = ((red << 8) & 0x00ff0000);
172 val |= ((green >> 0) & 0x0000ff00);
173 val |= ((blue >> 8) & 0x000000ff);
174 ((u32 *)(fbi->palette_cpu))[regno] = val;
175 break;
1da177e4 176 }
9ffa7396
HK		 177
178 return 0;
1da177e4
LT		 179}
180
181static int
182pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
183 u_int trans, struct fb_info *info)
184{
185 struct pxafb_info *fbi = (struct pxafb_info *)info;
186 unsigned int val;
187 int ret = 1;
188
189 /*
190 * If inverse mode was selected, invert all the colours
191 * rather than the register number. The register number
192 * is what you poke into the framebuffer to produce the
193 * colour you requested.
194 */
195 if (fbi->cmap_inverse) {
196 red = 0xffff - red;
197 green = 0xffff - green;
198 blue = 0xffff - blue;
199 }
200
201 /*
202 * If greyscale is true, then we convert the RGB value
203 * to greyscale no matter what visual we are using.
204 */
205 if (fbi->fb.var.grayscale)
206 red = green = blue = (19595 * red + 38470 * green +
207 7471 * blue) >> 16;
208
209 switch (fbi->fb.fix.visual) {
210 case FB_VISUAL_TRUECOLOR:
211 /*
212 * 16-bit True Colour. We encode the RGB value
213 * according to the RGB bitfield information.
214 */
215 if (regno < 16) {
216 u32 *pal = fbi->fb.pseudo_palette;
217
218 val = chan_to_field(red, &fbi->fb.var.red);
219 val |= chan_to_field(green, &fbi->fb.var.green);
220 val |= chan_to_field(blue, &fbi->fb.var.blue);
221
222 pal[regno] = val;
223 ret = 0;
224 }
225 break;
226
227 case FB_VISUAL_STATIC_PSEUDOCOLOR:
228 case FB_VISUAL_PSEUDOCOLOR:
229 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
230 break;
231 }
232
233 return ret;
234}
235
878f5783
EM		 236/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
237static inline int var_to_depth(struct fb_var_screeninfo *var)
1da177e4 238{
878f5783
EM		 239 return var->red.length + var->green.length +
240 var->blue.length + var->transp.length;
241}
242
243/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
244static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
245{
246 int bpp = -EINVAL;
247
b0086efb 248 switch (var->bits_per_pixel) {
878f5783
EM		 249 case 1: bpp = 0; break;
250 case 2: bpp = 1; break;
251 case 4: bpp = 2; break;
252 case 8: bpp = 3; break;
253 case 16: bpp = 4; break;
c1450f15 254 case 24:
878f5783
EM		 255 switch (var_to_depth(var)) {
256 case 18: bpp = 6; break; /* 18-bits/pixel packed */
257 case 19: bpp = 8; break; /* 19-bits/pixel packed */
258 case 24: bpp = 9; break;
c1450f15
SS		 259 }
260 break;
261 case 32:
878f5783
EM		 262 switch (var_to_depth(var)) {
263 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
264 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
265 case 25: bpp = 10; break;
c1450f15
SS		 266 }
267 break;
b0086efb 268 }
878f5783
EM		 269 return bpp;
270}
271
272/*
273 * pxafb_var_to_lccr3():
274 * Convert a bits per pixel value to the correct bit pattern for LCCR3
275 *
276 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
277 * implication of the acutal use of transparency bit, which we handle it
278 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
279 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
280 *
281 * Transparency for palette pixel formats is not supported at the moment.
282 */
283static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
284{
285 int bpp = pxafb_var_to_bpp(var);
286 uint32_t lccr3;
287
288 if (bpp < 0)
289 return 0;
290
291 lccr3 = LCCR3_BPP(bpp);
292
293 switch (var_to_depth(var)) {
294 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
295 case 18: lccr3 |= LCCR3_PDFOR_3; break;
296 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
297 break;
298 case 19:
299 case 25: lccr3 |= LCCR3_PDFOR_0; break;
300 }
301 return lccr3;
302}
303
304#define SET_PIXFMT(v, r, g, b, t) \
305({ \
306 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
307 (v)->transp.length = (t) ? (t) : 0; \
308 (v)->blue.length = (b); (v)->blue.offset = 0; \
309 (v)->green.length = (g); (v)->green.offset = (b); \
310 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
311})
312
313/* set the RGBT bitfields of fb_var_screeninf according to
314 * var->bits_per_pixel and given depth
315 */
316static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
317{
318 if (depth == 0)
319 depth = var->bits_per_pixel;
320
321 if (var->bits_per_pixel < 16) {
322 /* indexed pixel formats */
323 var->red.offset = 0; var->red.length = 8;
324 var->green.offset = 0; var->green.length = 8;
325 var->blue.offset = 0; var->blue.length = 8;
326 var->transp.offset = 0; var->transp.length = 8;
327 }
328
329 switch (depth) {
330 case 16: var->transp.length ?
331 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
332 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
333 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
334 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
335 case 24: var->transp.length ?
336 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
337 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
338 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
339 }
1da177e4
LT		 340}
341
342#ifdef CONFIG_CPU_FREQ
343/*
344 * pxafb_display_dma_period()
345 * Calculate the minimum period (in picoseconds) between two DMA
346 * requests for the LCD controller. If we hit this, it means we're
347 * doing nothing but LCD DMA.
348 */
349static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
350{
b0086efb 351 /*
352 * Period = pixclock * bits_per_byte * bytes_per_transfer
353 * / memory_bits_per_pixel;
354 */
355 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 356}
1da177e4
LT		 357#endif
358
d14b272b
RP		 359/*
360 * Select the smallest mode that allows the desired resolution to be
361 * displayed. If desired parameters can be rounded up.
362 */
b0086efb 363static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
364 struct fb_var_screeninfo *var)
d14b272b
RP		 365{
366 struct pxafb_mode_info *mode = NULL;
367 struct pxafb_mode_info *modelist = mach->modes;
368 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
369 unsigned int i;
370
b0086efb 371 for (i = 0; i < mach->num_modes; i++) {
372 if (modelist[i].xres >= var->xres &&
373 modelist[i].yres >= var->yres &&
374 modelist[i].xres < best_x &&
375 modelist[i].yres < best_y &&
376 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 377 best_x = modelist[i].xres;
378 best_y = modelist[i].yres;
379 mode = &modelist[i];
380 }
381 }
382
383 return mode;
384}
385
b0086efb 386static void pxafb_setmode(struct fb_var_screeninfo *var,
387 struct pxafb_mode_info *mode)
d14b272b
RP		 388{
389 var->xres = mode->xres;
390 var->yres = mode->yres;
391 var->bits_per_pixel = mode->bpp;
392 var->pixclock = mode->pixclock;
393 var->hsync_len = mode->hsync_len;
394 var->left_margin = mode->left_margin;
395 var->right_margin = mode->right_margin;
396 var->vsync_len = mode->vsync_len;
397 var->upper_margin = mode->upper_margin;
398 var->lower_margin = mode->lower_margin;
399 var->sync = mode->sync;
400 var->grayscale = mode->cmap_greyscale;
049ad833 401 var->transp.length = mode->transparency;
878f5783
EM		 402
403 /* set the initial RGBA bitfields */
404 pxafb_set_pixfmt(var, mode->depth);
d14b272b
RP		 405}
406
3f16ff60
EM		 407static int pxafb_adjust_timing(struct pxafb_info *fbi,
408 struct fb_var_screeninfo *var)
409{
410 int line_length;
411
412 var->xres = max_t(int, var->xres, MIN_XRES);
413 var->yres = max_t(int, var->yres, MIN_YRES);
414
415 if (!(fbi->lccr0 & LCCR0_LCDT)) {
416 clamp_val(var->hsync_len, 1, 64);
417 clamp_val(var->vsync_len, 1, 64);
418 clamp_val(var->left_margin, 1, 255);
419 clamp_val(var->right_margin, 1, 255);
420 clamp_val(var->upper_margin, 1, 255);
421 clamp_val(var->lower_margin, 1, 255);
422 }
423
424 /* make sure each line is aligned on word boundary */
425 line_length = var->xres * var->bits_per_pixel / 8;
426 line_length = ALIGN(line_length, 4);
427 var->xres = line_length * 8 / var->bits_per_pixel;
428
429 /* we don't support xpan, force xres_virtual to be equal to xres */
430 var->xres_virtual = var->xres;
431
432 if (var->accel_flags & FB_ACCELF_TEXT)
433 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
434 else
435 var->yres_virtual = max(var->yres_virtual, var->yres);
436
437 /* check for limits */
438 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
439 return -EINVAL;
440
441 if (var->yres > var->yres_virtual)
442 return -EINVAL;
443
444 return 0;
d14b272b
RP		 445}
446
1da177e4
LT		 447/*
448 * pxafb_check_var():
449 * Get the video params out of 'var'. If a value doesn't fit, round it up,
450 * if it's too big, return -EINVAL.
451 *
452 * Round up in the following order: bits_per_pixel, xres,
453 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
454 * bitfields, horizontal timing, vertical timing.
455 */
456static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
457{
458 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 459 struct pxafb_mach_info *inf = fbi->dev->platform_data;
878f5783 460 int err;
d14b272b
RP		 461
462 if (inf->fixed_modes) {
463 struct pxafb_mode_info *mode;
464
465 mode = pxafb_getmode(inf, var);
466 if (!mode)
467 return -EINVAL;
468 pxafb_setmode(var, mode);
d14b272b
RP		 469 }
470
878f5783
EM		 471 /* do a test conversion to BPP fields to check the color formats */
472 err = pxafb_var_to_bpp(var);
473 if (err < 0)
474 return err;
1da177e4 475
878f5783 476 pxafb_set_pixfmt(var, var_to_depth(var));
c1450f15 477
3f16ff60
EM		 478 err = pxafb_adjust_timing(fbi, var);
479 if (err)
480 return err;
1da177e4
LT		 481
482#ifdef CONFIG_CPU_FREQ
78d3cfd3
RK		 483 pr_debug("pxafb: dma period = %d ps\n",
484 pxafb_display_dma_period(var));
1da177e4
LT		 485#endif
486
487 return 0;
488}
489
1da177e4
LT		 490/*
491 * pxafb_set_par():
492 * Set the user defined part of the display for the specified console
493 */
494static int pxafb_set_par(struct fb_info *info)
495{
496 struct pxafb_info *fbi = (struct pxafb_info *)info;
497 struct fb_var_screeninfo *var = &info->var;
1da177e4 498
c1450f15 499 if (var->bits_per_pixel >= 16)
1da177e4
LT		 500 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
501 else if (!fbi->cmap_static)
502 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
503 else {
504 /*
505 * Some people have weird ideas about wanting static
506 * pseudocolor maps. I suspect their user space
507 * applications are broken.
508 */
509 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
510 }
511
512 fbi->fb.fix.line_length = var->xres_virtual *
513 var->bits_per_pixel / 8;
c1450f15 514 if (var->bits_per_pixel >= 16)
1da177e4
LT		 515 fbi->palette_size = 0;
516 else
b0086efb 517 fbi->palette_size = var->bits_per_pixel == 1 ?
518 4 : 1 << var->bits_per_pixel;
1da177e4 519
2c42dd8e 520 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4 521
c1450f15 522 if (fbi->fb.var.bits_per_pixel >= 16)
1da177e4
LT		 523 fb_dealloc_cmap(&fbi->fb.cmap);
524 else
525 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
526
527 pxafb_activate_var(var, fbi);
528
529 return 0;
530}
531
6e354846
EM		 532static int pxafb_pan_display(struct fb_var_screeninfo *var,
533 struct fb_info *info)
534{
535 struct pxafb_info *fbi = (struct pxafb_info *)info;
448ac479 536 struct fb_var_screeninfo newvar;
6e354846
EM		 537 int dma = DMA_MAX + DMA_BASE;
538
539 if (fbi->state != C_ENABLE)
540 return 0;
541
448ac479
SN		 542 /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
543 * was passed in and copy the rest from the old screeninfo.
544 */
545 memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
546 newvar.xoffset = var->xoffset;
547 newvar.yoffset = var->yoffset;
548 newvar.vmode &= ~FB_VMODE_YWRAP;
549 newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
550
551 setup_base_frame(fbi, &newvar, 1);
6e354846
EM		 552
553 if (fbi->lccr0 & LCCR0_SDS)
554 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
555
556 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
557 return 0;
558}
559
1da177e4
LT		 560/*
561 * pxafb_blank():
562 * Blank the display by setting all palette values to zero. Note, the
563 * 16 bpp mode does not really use the palette, so this will not
564 * blank the display in all modes.
565 */
566static int pxafb_blank(int blank, struct fb_info *info)
567{
568 struct pxafb_info *fbi = (struct pxafb_info *)info;
569 int i;
570
1da177e4
LT		 571 switch (blank) {
572 case FB_BLANK_POWERDOWN:
573 case FB_BLANK_VSYNC_SUSPEND:
574 case FB_BLANK_HSYNC_SUSPEND:
575 case FB_BLANK_NORMAL:
576 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
577 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
578 for (i = 0; i < fbi->palette_size; i++)
579 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
580
581 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 582 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 583 break;
584
585 case FB_BLANK_UNBLANK:
b0086efb 586 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 587 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
588 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
589 fb_set_cmap(&fbi->fb.cmap, info);
590 pxafb_schedule_work(fbi, C_ENABLE);
591 }
592 return 0;
593}
594
1da177e4
LT		 595static struct fb_ops pxafb_ops = {
596 .owner = THIS_MODULE,
597 .fb_check_var = pxafb_check_var,
598 .fb_set_par = pxafb_set_par,
6e354846 599 .fb_pan_display = pxafb_pan_display,
1da177e4
LT		 600 .fb_setcolreg = pxafb_setcolreg,
601 .fb_fillrect = cfb_fillrect,
602 .fb_copyarea = cfb_copyarea,
603 .fb_imageblit = cfb_imageblit,
604 .fb_blank = pxafb_blank,
1da177e4
LT		 605};
606
198fc108
EM		 607#ifdef CONFIG_FB_PXA_OVERLAY
608static void overlay1fb_setup(struct pxafb_layer *ofb)
609{
610 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
611 unsigned long start = ofb->video_mem_phys;
612 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
613}
614
615/* Depending on the enable status of overlay1/2, the DMA should be
616 * updated from FDADRx (when disabled) or FBRx (when enabled).
617 */
618static void overlay1fb_enable(struct pxafb_layer *ofb)
619{
620 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
621 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
622
623 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
624 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
625 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
626}
627
628static void overlay1fb_disable(struct pxafb_layer *ofb)
629{
630 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
631
632 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
633
634 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
635 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
636 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
637
638 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
639 pr_warning("%s: timeout disabling overlay1\n", __func__);
640
641 lcd_writel(ofb->fbi, LCCR5, lccr5);
642}
643
644static void overlay2fb_setup(struct pxafb_layer *ofb)
645{
646 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
647 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
648
649 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
650 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
651 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
652 } else {
653 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
654 switch (pfor) {
655 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
656 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
657 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
658 }
659 start[1] = start[0] + size;
660 start[2] = start[1] + size / div;
661 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
662 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
663 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
664 }
665}
666
667static void overlay2fb_enable(struct pxafb_layer *ofb)
668{
669 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
670 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
671 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
672 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
673 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
674
675 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
676 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
677 else {
678 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
679 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
680 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
681 }
682 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
683 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
684}
685
686static void overlay2fb_disable(struct pxafb_layer *ofb)
687{
688 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
689
690 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
691
692 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
693 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
694 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
695 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
696 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
697
698 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
699 pr_warning("%s: timeout disabling overlay2\n", __func__);
700}
701
702static struct pxafb_layer_ops ofb_ops[] = {
703 [0] = {
704 .enable = overlay1fb_enable,
705 .disable = overlay1fb_disable,
706 .setup = overlay1fb_setup,
707 },
708 [1] = {
709 .enable = overlay2fb_enable,
710 .disable = overlay2fb_disable,
711 .setup = overlay2fb_setup,
712 },
713};
714
715static int overlayfb_open(struct fb_info *info, int user)
716{
717 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
718
719 /* no support for framebuffer console on overlay */
720 if (user == 0)
721 return -ENODEV;
722
723 /* allow only one user at a time */
724 if (atomic_inc_and_test(&ofb->usage))
725 return -EBUSY;
726
727 /* unblank the base framebuffer */
728 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
729 return 0;
730}
731
732static int overlayfb_release(struct fb_info *info, int user)
733{
734 struct pxafb_layer *ofb = (struct pxafb_layer*) info;
735
736 atomic_dec(&ofb->usage);
737 ofb->ops->disable(ofb);
738
739 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
740 ofb->video_mem = NULL;
741 ofb->video_mem_size = 0;
742 return 0;
743}
744
745static int overlayfb_check_var(struct fb_var_screeninfo *var,
746 struct fb_info *info)
747{
748 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
749 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
750 int xpos, ypos, pfor, bpp;
751
752 xpos = NONSTD_TO_XPOS(var->nonstd);
753 ypos = NONSTD_TO_XPOS(var->nonstd);
754 pfor = NONSTD_TO_PFOR(var->nonstd);
755
756 bpp = pxafb_var_to_bpp(var);
757 if (bpp < 0)
758 return -EINVAL;
759
760 /* no support for YUV format on overlay1 */
761 if (ofb->id == OVERLAY1 && pfor != 0)
762 return -EINVAL;
763
764 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
765 switch (pfor) {
766 case OVERLAY_FORMAT_RGB:
767 bpp = pxafb_var_to_bpp(var);
768 if (bpp < 0)
769 return -EINVAL;
770
771 pxafb_set_pixfmt(var, var_to_depth(var));
772 break;
773 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
774 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
775 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
776 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
777 default:
778 return -EINVAL;
779 }
780
781 /* each line must start at a 32-bit word boundary */
782 if ((xpos * bpp) % 32)
783 return -EINVAL;
784
785 /* xres must align on 32-bit word boundary */
786 var->xres = roundup(var->xres * bpp, 32) / bpp;
787
788 if ((xpos + var->xres > base_var->xres) ||
789 (ypos + var->yres > base_var->yres))
790 return -EINVAL;
791
792 var->xres_virtual = var->xres;
793 var->yres_virtual = max(var->yres, var->yres_virtual);
794 return 0;
795}
796
797static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
798{
799 struct fb_var_screeninfo *var = &ofb->fb.var;
800 int pfor = NONSTD_TO_PFOR(var->nonstd);
801 int size, bpp = 0;
802
803 switch (pfor) {
804 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
805 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
806 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
807 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
808 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
809 }
810
811 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
812
813 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
814
815 /* don't re-allocate if the original video memory is enough */
816 if (ofb->video_mem) {
817 if (ofb->video_mem_size >= size)
818 return 0;
819
820 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
821 }
822
823 ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
824 if (ofb->video_mem == NULL)
825 return -ENOMEM;
826
827 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
828 ofb->video_mem_size = size;
829
537a1bf0 830 mutex_lock(&ofb->fb.mm_lock);
198fc108
EM		 831 ofb->fb.fix.smem_start = ofb->video_mem_phys;
832 ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual;
537a1bf0 833 mutex_unlock(&ofb->fb.mm_lock);
198fc108
EM		 834 ofb->fb.screen_base = ofb->video_mem;
835 return 0;
836}
837
838static int overlayfb_set_par(struct fb_info *info)
839{
840 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
841 struct fb_var_screeninfo *var = &info->var;
842 int xpos, ypos, pfor, bpp, ret;
843
844 ret = overlayfb_map_video_memory(ofb);
845 if (ret)
846 return ret;
847
848 bpp = pxafb_var_to_bpp(var);
849 xpos = NONSTD_TO_XPOS(var->nonstd);
850 ypos = NONSTD_TO_XPOS(var->nonstd);
851 pfor = NONSTD_TO_PFOR(var->nonstd);
852
853 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
854 OVLxC1_BPP(bpp);
855 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
856
857 if (ofb->id == OVERLAY2)
858 ofb->control[1] |= OVL2C2_PFOR(pfor);
859
860 ofb->ops->setup(ofb);
861 ofb->ops->enable(ofb);
862 return 0;
863}
864
865static struct fb_ops overlay_fb_ops = {
866 .owner = THIS_MODULE,
867 .fb_open = overlayfb_open,
868 .fb_release = overlayfb_release,
869 .fb_check_var = overlayfb_check_var,
870 .fb_set_par = overlayfb_set_par,
871};
872
873static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
874 struct pxafb_layer *ofb, int id)
875{
876 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
877
878 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
879 ofb->fb.fix.xpanstep = 0;
880 ofb->fb.fix.ypanstep = 1;
881
882 ofb->fb.var.activate = FB_ACTIVATE_NOW;
883 ofb->fb.var.height = -1;
884 ofb->fb.var.width = -1;
885 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
886
887 ofb->fb.fbops = &overlay_fb_ops;
888 ofb->fb.flags = FBINFO_FLAG_DEFAULT;
889 ofb->fb.node = -1;
890 ofb->fb.pseudo_palette = NULL;
891
892 ofb->id = id;
893 ofb->ops = &ofb_ops[id];
894 atomic_set(&ofb->usage, 0);
895 ofb->fbi = fbi;
896 init_completion(&ofb->branch_done);
897}
898
782385ae
EM		 899static inline int pxafb_overlay_supported(void)
900{
901 if (cpu_is_pxa27x() || cpu_is_pxa3xx())
902 return 1;
903
904 return 0;
905}
906
198fc108
EM		 907static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
908{
909 int i, ret;
910
782385ae
EM		 911 if (!pxafb_overlay_supported())
912 return 0;
913
198fc108
EM		 914 for (i = 0; i < 2; i++) {
915 init_pxafb_overlay(fbi, &fbi->overlay[i], i);
916 ret = register_framebuffer(&fbi->overlay[i].fb);
917 if (ret) {
918 dev_err(fbi->dev, "failed to register overlay %d\n", i);
919 return ret;
920 }
921 }
922
923 /* mask all IU/BS/EOF/SOF interrupts */
924 lcd_writel(fbi, LCCR5, ~0);
925
926 /* place overlay(s) on top of base */
927 fbi->lccr0 |= LCCR0_OUC;
928 pr_info("PXA Overlay driver loaded successfully!\n");
929 return 0;
930}
931
932static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
933{
934 int i;
935
782385ae
EM		 936 if (!pxafb_overlay_supported())
937 return;
938
198fc108
EM		 939 for (i = 0; i < 2; i++)
940 unregister_framebuffer(&fbi->overlay[i].fb);
941}
942#else
943static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
944static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
945#endif /* CONFIG_FB_PXA_OVERLAY */
946
1da177e4
LT		 947/*
948 * Calculate the PCD value from the clock rate (in picoseconds).
949 * We take account of the PPCR clock setting.
950 * From PXA Developer's Manual:
951 *
952 * PixelClock = LCLK
953 * -------------
954 * 2 ( PCD + 1 )
955 *
956 * PCD = LCLK
957 * ------------- - 1
958 * 2(PixelClock)
959 *
960 * Where:
961 * LCLK = LCD/Memory Clock
962 * PCD = LCCR3[7:0]
963 *
964 * PixelClock here is in Hz while the pixclock argument given is the
965 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
966 *
967 * The function get_lclk_frequency_10khz returns LCLK in units of
968 * 10khz. Calling the result of this function lclk gives us the
969 * following
970 *
971 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
972 * -------------------------------------- - 1
973 * 2
974 *
975 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
976 */
b0086efb 977static inline unsigned int get_pcd(struct pxafb_info *fbi,
978 unsigned int pixclock)
1da177e4
LT		 979{
980 unsigned long long pcd;
981
982 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 983 * (DPC) bit? or perhaps set it based on the various clock
984 * speeds */
985 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
986 pcd *= pixclock;
bf1b8ab6 987 do_div(pcd, 100000000 * 2);
1da177e4
LT		 988 /* no need for this, since we should subtract 1 anyway. they cancel */
989 /* pcd += 1; */ /* make up for integer math truncations */
990 return (unsigned int)pcd;
991}
992
ba44cd2d
RP		 993/*
994 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 995 * function correctly. We export it here. Note that 'hsync_time' and
996 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
997 * of the hsync period in seconds.
ba44cd2d
RP		 998 */
999static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1000{
72e3524c 1001 unsigned long htime;
ba44cd2d
RP		 1002
1003 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 1004 fbi->hsync_time = 0;
ba44cd2d
RP		 1005 return;
1006 }
1007
72e3524c
RK		 1008 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1009
ba44cd2d
RP		 1010 fbi->hsync_time = htime;
1011}
1012
1013unsigned long pxafb_get_hsync_time(struct device *dev)
1014{
1015 struct pxafb_info *fbi = dev_get_drvdata(dev);
1016
1017 /* If display is blanked/suspended, hsync isn't active */
1018 if (!fbi || (fbi->state != C_ENABLE))
1019 return 0;
1020
1021 return fbi->hsync_time;
1022}
1023EXPORT_SYMBOL(pxafb_get_hsync_time);
1024
2c42dd8e 1025static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
198fc108 1026 unsigned long start, size_t size)
2c42dd8e 1027{
1028 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1029 unsigned int dma_desc_off, pal_desc_off;
1030
6e354846 1031 if (dma < 0 || dma >= DMA_MAX * 2)
2c42dd8e 1032 return -EINVAL;
1033
1034 dma_desc = &fbi->dma_buff->dma_desc[dma];
1035 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1036
198fc108 1037 dma_desc->fsadr = start;
2c42dd8e 1038 dma_desc->fidr = 0;
1039 dma_desc->ldcmd = size;
1040
6e354846 1041 if (pal < 0 || pal >= PAL_MAX * 2) {
2c42dd8e 1042 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1043 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1044 } else {
62cfcf4f
JS		 1045 pal_desc = &fbi->dma_buff->pal_desc[pal];
1046 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
2c42dd8e 1047
1048 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1049 pal_desc->fidr = 0;
1050
1051 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1052 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1053 else
1054 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1055
1056 pal_desc->ldcmd |= LDCMD_PAL;
1057
1058 /* flip back and forth between palette and frame buffer */
1059 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1060 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1061 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1062 }
1063
1064 return 0;
1065}
1066
448ac479
SN		 1067static void setup_base_frame(struct pxafb_info *fbi,
1068 struct fb_var_screeninfo *var,
1069 int branch)
6e354846 1070{
6e354846 1071 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
198fc108
EM		 1072 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1073 unsigned long offset;
6e354846
EM		 1074
1075 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1076 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1077
1078 nbytes = fix->line_length * var->yres;
198fc108 1079 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
6e354846
EM		 1080
1081 if (fbi->lccr0 & LCCR0_SDS) {
1082 nbytes = nbytes / 2;
1083 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1084 }
1085
1086 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1087}
1088
3c42a449
EM		 1089#ifdef CONFIG_FB_PXA_SMARTPANEL
1090static int setup_smart_dma(struct pxafb_info *fbi)
1091{
1092 struct pxafb_dma_descriptor *dma_desc;
1093 unsigned long dma_desc_off, cmd_buff_off;
1094
1095 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1096 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1097 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1098
1099 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1100 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1101 dma_desc->fidr = 0;
1102 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1103
1104 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1105 return 0;
1106}
1107
1108int pxafb_smart_flush(struct fb_info *info)
1109{
1110 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1111 uint32_t prsr;
1112 int ret = 0;
1113
1114 /* disable controller until all registers are set up */
1115 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1116
1117 /* 1. make it an even number of commands to align on 32-bit boundary
1118 * 2. add the interrupt command to the end of the chain so we can
1119 * keep track of the end of the transfer
1120 */
1121
1122 while (fbi->n_smart_cmds & 1)
1123 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1124
1125 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1126 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1127 setup_smart_dma(fbi);
1128
1129 /* continue to execute next command */
1130 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1131 lcd_writel(fbi, PRSR, prsr);
1132
1133 /* stop the processor in case it executed "wait for sync" cmd */
1134 lcd_writel(fbi, CMDCR, 0x0001);
1135
1136 /* don't send interrupts for fifo underruns on channel 6 */
1137 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1138
1139 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1140 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1141 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
a0427509 1142 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
3c42a449
EM		 1143 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1144 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1145
1146 /* begin sending */
1147 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1148
1149 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1150 pr_warning("%s: timeout waiting for command done\n",
1151 __func__);
1152 ret = -ETIMEDOUT;
1153 }
1154
1155 /* quick disable */
1156 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1157 lcd_writel(fbi, PRSR, prsr);
1158 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1159 lcd_writel(fbi, FDADR6, 0);
1160 fbi->n_smart_cmds = 0;
1161 return ret;
1162}
1163
1164int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1165{
1166 int i;
1167 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1168
69bdea70
EM		 1169 for (i = 0; i < n_cmds; i++, cmds++) {
1170 /* if it is a software delay, flush and delay */
1171 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1172 pxafb_smart_flush(info);
1173 mdelay(*cmds & 0xff);
1174 continue;
1175 }
1176
1177 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
3c42a449
EM		 1178 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1179 pxafb_smart_flush(info);
1180
69bdea70 1181 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
3c42a449
EM		 1182 }
1183
1184 return 0;
1185}
1186
1187static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1188{
1189 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1190 return (t == 0) ? 1 : t;
1191}
1192
1193static void setup_smart_timing(struct pxafb_info *fbi,
1194 struct fb_var_screeninfo *var)
1195{
1196 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1197 struct pxafb_mode_info *mode = &inf->modes[0];
1198 unsigned long lclk = clk_get_rate(fbi->clk);
1199 unsigned t1, t2, t3, t4;
1200
1201 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1202 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1203 t3 = mode->op_hold_time;
1204 t4 = mode->cmd_inh_time;
1205
1206 fbi->reg_lccr1 =
1207 LCCR1_DisWdth(var->xres) |
1208 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1209 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1210 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1211
1212 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
c1f99c21
EM		 1213 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1214 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1215 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
3c42a449
EM		 1216
1217 /* FIXME: make this configurable */
1218 fbi->reg_cmdcr = 1;
1219}
1220
1221static int pxafb_smart_thread(void *arg)
1222{
7f1133cb 1223 struct pxafb_info *fbi = arg;
3c42a449
EM		 1224 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1225
1226 if (!fbi || !inf->smart_update) {
1227 pr_err("%s: not properly initialized, thread terminated\n",
1228 __func__);
1229 return -EINVAL;
1230 }
1231
1232 pr_debug("%s(): task starting\n", __func__);
1233
1234 set_freezable();
1235 while (!kthread_should_stop()) {
1236
1237 if (try_to_freeze())
1238 continue;
1239
07f651c7
EM		 1240 mutex_lock(&fbi->ctrlr_lock);
1241
3c42a449
EM		 1242 if (fbi->state == C_ENABLE) {
1243 inf->smart_update(&fbi->fb);
1244 complete(&fbi->refresh_done);
1245 }
1246
07f651c7
EM		 1247 mutex_unlock(&fbi->ctrlr_lock);
1248
3c42a449
EM		 1249 set_current_state(TASK_INTERRUPTIBLE);
1250 schedule_timeout(30 * HZ / 1000);
1251 }
1252
1253 pr_debug("%s(): task ending\n", __func__);
1254 return 0;
1255}
1256
1257static int pxafb_smart_init(struct pxafb_info *fbi)
1258{
07df1c4f 1259 if (!(fbi->lccr0 & LCCR0_LCDT))
6cc4abe4
EM		 1260 return 0;
1261
07df1c4f
EM		 1262 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1263 fbi->n_smart_cmds = 0;
1264
1265 init_completion(&fbi->command_done);
1266 init_completion(&fbi->refresh_done);
1267
3c42a449
EM		 1268 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1269 "lcd_refresh");
1270 if (IS_ERR(fbi->smart_thread)) {
07df1c4f 1271 pr_err("%s: unable to create kernel thread\n", __func__);
3c42a449
EM		 1272 return PTR_ERR(fbi->smart_thread);
1273 }
a5718a14 1274
3c42a449
EM		 1275 return 0;
1276}
1277#else
1278int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1279{
1280 return 0;
1281}
1282
1283int pxafb_smart_flush(struct fb_info *info)
1284{
1285 return 0;
1286}
07df1c4f
EM		 1287
1288static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1289#endif /* CONFIG_FB_PXA_SMARTPANEL */
3c42a449 1290
90eabbf0
EM		 1291static void setup_parallel_timing(struct pxafb_info *fbi,
1292 struct fb_var_screeninfo *var)
1293{
1294 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1295
1296 fbi->reg_lccr1 =
1297 LCCR1_DisWdth(var->xres) +
1298 LCCR1_HorSnchWdth(var->hsync_len) +
1299 LCCR1_BegLnDel(var->left_margin) +
1300 LCCR1_EndLnDel(var->right_margin);
1301
1302 /*
1303 * If we have a dual scan LCD, we need to halve
1304 * the YRES parameter.
1305 */
1306 lines_per_panel = var->yres;
1307 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1308 lines_per_panel /= 2;
1309
1310 fbi->reg_lccr2 =
1311 LCCR2_DisHght(lines_per_panel) +
1312 LCCR2_VrtSnchWdth(var->vsync_len) +
1313 LCCR2_BegFrmDel(var->upper_margin) +
1314 LCCR2_EndFrmDel(var->lower_margin);
1315
1316 fbi->reg_lccr3 = fbi->lccr3 |
1317 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1318 LCCR3_HorSnchH : LCCR3_HorSnchL) |
1319 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1320 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1321
1322 if (pcd) {
1323 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1324 set_hsync_time(fbi, pcd);
1325 }
1326}
1327
1da177e4
LT		 1328/*
1329 * pxafb_activate_var():
b0086efb 1330 * Configures LCD Controller based on entries in var parameter.
1331 * Settings are only written to the controller if changes were made.
1da177e4 1332 */
b0086efb 1333static int pxafb_activate_var(struct fb_var_screeninfo *var,
1334 struct pxafb_info *fbi)
1da177e4 1335{
1da177e4 1336 u_long flags;
1da177e4 1337
90eabbf0
EM		 1338 /* Update shadow copy atomically */
1339 local_irq_save(flags);
1da177e4 1340
3c42a449
EM		 1341#ifdef CONFIG_FB_PXA_SMARTPANEL
1342 if (fbi->lccr0 & LCCR0_LCDT)
1343 setup_smart_timing(fbi, var);
1344 else
1345#endif
1346 setup_parallel_timing(fbi, var);
90eabbf0 1347
448ac479 1348 setup_base_frame(fbi, var, 0);
6e354846 1349
90eabbf0 1350 fbi->reg_lccr0 = fbi->lccr0 |
1da177e4 1351 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 1352 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4 1353
878f5783 1354 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1da177e4 1355
a7535ba7 1356 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 1357 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1da177e4
LT		 1358 local_irq_restore(flags);
1359
1360 /*
1361 * Only update the registers if the controller is enabled
1362 * and something has changed.
1363 */
a7535ba7
EM		 1364 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1365 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1366 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1367 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
a0427509 1368 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
a7535ba7
EM		 1369 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1370 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1da177e4
LT		 1371 pxafb_schedule_work(fbi, C_REENABLE);
1372
1373 return 0;
1374}
1375
1376/*
1377 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1378 * Do not call them directly; set_ctrlr_state does the correct serialisation
1379 * to ensure that things happen in the right way 100% of time time.
1380 * -- rmk
1381 */
1382static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1383{
ca5da710 1384 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 1385
a5718a14
EM		 1386 if (fbi->backlight_power)
1387 fbi->backlight_power(on);
1da177e4
LT		 1388}
1389
1390static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1391{
ca5da710 1392 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4 1393
a5718a14
EM		 1394 if (fbi->lcd_power)
1395 fbi->lcd_power(on, &fbi->fb.var);
1da177e4
LT		 1396}
1397
1da177e4
LT		 1398static void pxafb_enable_controller(struct pxafb_info *fbi)
1399{
ca5da710 1400 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 1401 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1402 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 1403 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1404 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1405 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1406 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 1407
8d372266 1408 /* enable LCD controller clock */
72e3524c 1409 clk_enable(fbi->clk);
8d372266 1410
3c42a449
EM		 1411 if (fbi->lccr0 & LCCR0_LCDT)
1412 return;
1413
1da177e4 1414 /* Sequence from 11.7.10 */
a0427509 1415 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
a7535ba7
EM		 1416 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1417 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1418 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1419 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1420
1421 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1422 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1423 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 1424}
1425
1426static void pxafb_disable_controller(struct pxafb_info *fbi)
1427{
ce4fb7b8 1428 uint32_t lccr0;
1429
3c42a449
EM		 1430#ifdef CONFIG_FB_PXA_SMARTPANEL
1431 if (fbi->lccr0 & LCCR0_LCDT) {
1432 wait_for_completion_timeout(&fbi->refresh_done,
1433 200 * HZ / 1000);
1434 return;
1435 }
1436#endif
1437
ce4fb7b8 1438 /* Clear LCD Status Register */
a7535ba7 1439 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 1440
a7535ba7
EM		 1441 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1442 lcd_writel(fbi, LCCR0, lccr0);
1443 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 1444
2ba162b9 1445 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
8d372266
NP		 1446
1447 /* disable LCD controller clock */
72e3524c 1448 clk_disable(fbi->clk);
1da177e4
LT		 1449}
1450
1451/*
1452 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1453 */
7d12e780 1454static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 1455{
1456 struct pxafb_info *fbi = dev_id;
ff14ed5d 1457 unsigned int lccr0, lcsr;
1da177e4 1458
198fc108 1459 lcsr = lcd_readl(fbi, LCSR);
1da177e4 1460 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 1461 lccr0 = lcd_readl(fbi, LCCR0);
1462 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
2ba162b9 1463 complete(&fbi->disable_done);
1da177e4
LT		 1464 }
1465
3c42a449
EM		 1466#ifdef CONFIG_FB_PXA_SMARTPANEL
1467 if (lcsr & LCSR_CMD_INT)
1468 complete(&fbi->command_done);
1469#endif
a7535ba7 1470 lcd_writel(fbi, LCSR, lcsr);
198fc108
EM		 1471
1472#ifdef CONFIG_FB_PXA_OVERLAY
ff14ed5d
DL		 1473 {
1474 unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1475 if (lcsr1 & LCSR1_BS(1))
1476 complete(&fbi->overlay[0].branch_done);
198fc108 1477
ff14ed5d
DL		 1478 if (lcsr1 & LCSR1_BS(2))
1479 complete(&fbi->overlay[1].branch_done);
198fc108 1480
ff14ed5d
DL		 1481 lcd_writel(fbi, LCSR1, lcsr1);
1482 }
198fc108 1483#endif
1da177e4
LT		 1484 return IRQ_HANDLED;
1485}
1486
1487/*
1488 * This function must be called from task context only, since it will
1489 * sleep when disabling the LCD controller, or if we get two contending
1490 * processes trying to alter state.
1491 */
1492static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1493{
1494 u_int old_state;
1495
b91dbce5 1496 mutex_lock(&fbi->ctrlr_lock);
1da177e4
LT		 1497
1498 old_state = fbi->state;
1499
1500 /*
1501 * Hack around fbcon initialisation.
1502 */
1503 if (old_state == C_STARTUP && state == C_REENABLE)
1504 state = C_ENABLE;
1505
1506 switch (state) {
1507 case C_DISABLE_CLKCHANGE:
1508 /*
1509 * Disable controller for clock change. If the
1510 * controller is already disabled, then do nothing.
1511 */
1512 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1513 fbi->state = state;
b0086efb 1514 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 1515 pxafb_disable_controller(fbi);
1516 }
1517 break;
1518
1519 case C_DISABLE_PM:
1520 case C_DISABLE:
1521 /*
1522 * Disable controller
1523 */
1524 if (old_state != C_DISABLE) {
1525 fbi->state = state;
1526 __pxafb_backlight_power(fbi, 0);
1527 __pxafb_lcd_power(fbi, 0);
1528 if (old_state != C_DISABLE_CLKCHANGE)
1529 pxafb_disable_controller(fbi);
1530 }
1531 break;
1532
1533 case C_ENABLE_CLKCHANGE:
1534 /*
1535 * Enable the controller after clock change. Only
1536 * do this if we were disabled for the clock change.
1537 */
1538 if (old_state == C_DISABLE_CLKCHANGE) {
1539 fbi->state = C_ENABLE;
1540 pxafb_enable_controller(fbi);
b0086efb 1541 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 1542 }
1543 break;
1544
1545 case C_REENABLE:
1546 /*
1547 * Re-enable the controller only if it was already
1548 * enabled. This is so we reprogram the control
1549 * registers.
1550 */
1551 if (old_state == C_ENABLE) {
d14b272b 1552 __pxafb_lcd_power(fbi, 0);
1da177e4 1553 pxafb_disable_controller(fbi);
1da177e4 1554 pxafb_enable_controller(fbi);
d14b272b 1555 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 1556 }
1557 break;
1558
1559 case C_ENABLE_PM:
1560 /*
1561 * Re-enable the controller after PM. This is not
1562 * perfect - think about the case where we were doing
1563 * a clock change, and we suspended half-way through.
1564 */
1565 if (old_state != C_DISABLE_PM)
1566 break;
1567 /* fall through */
1568
1569 case C_ENABLE:
1570 /*
1571 * Power up the LCD screen, enable controller, and
1572 * turn on the backlight.
1573 */
1574 if (old_state != C_ENABLE) {
1575 fbi->state = C_ENABLE;
1da177e4
LT		 1576 pxafb_enable_controller(fbi);
1577 __pxafb_lcd_power(fbi, 1);
1578 __pxafb_backlight_power(fbi, 1);
1579 }
1580 break;
1581 }
b91dbce5 1582 mutex_unlock(&fbi->ctrlr_lock);
1da177e4
LT		 1583}
1584
1585/*
1586 * Our LCD controller task (which is called when we blank or unblank)
1587 * via keventd.
1588 */
6d5aefb8 1589static void pxafb_task(struct work_struct *work)
1da177e4 1590{
6d5aefb8
DH		 1591 struct pxafb_info *fbi =
1592 container_of(work, struct pxafb_info, task);
1da177e4
LT		 1593 u_int state = xchg(&fbi->task_state, -1);
1594
1595 set_ctrlr_state(fbi, state);
1596}
1597
1598#ifdef CONFIG_CPU_FREQ
1599/*
1600 * CPU clock speed change handler. We need to adjust the LCD timing
1601 * parameters when the CPU clock is adjusted by the power management
1602 * subsystem.
1603 *
1604 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1605 */
1606static int
1607pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1608{
1609 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 1610 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 1611 u_int pcd;
1612
1613 switch (val) {
1614 case CPUFREQ_PRECHANGE:
1615 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1616 break;
1617
1618 case CPUFREQ_POSTCHANGE:
72e3524c 1619 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 1620 set_hsync_time(fbi, pcd);
b0086efb 1621 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1622 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 1623 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1624 break;
1625 }
1626 return 0;
1627}
1628
1629static int
1630pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1631{
1632 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1633 struct fb_var_screeninfo *var = &fbi->fb.var;
1634 struct cpufreq_policy *policy = data;
1635
1636 switch (val) {
1637 case CPUFREQ_ADJUST:
1638 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1639 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1640 "new clock %d kHz\n", pxafb_display_dma_period(var),
1641 policy->max);
b0086efb 1642 /* TODO: fill in min/max values */
1da177e4 1643 break;
1da177e4
LT		 1644 }
1645 return 0;
1646}
1647#endif
1648
1649#ifdef CONFIG_PM
1650/*
1651 * Power management hooks. Note that we won't be called from IRQ context,
1652 * unlike the blank functions above, so we may sleep.
1653 */
4f3edfe3 1654static int pxafb_suspend(struct device *dev)
1da177e4 1655{
4f3edfe3 1656 struct pxafb_info *fbi = dev_get_drvdata(dev);
1da177e4 1657
9480e307 1658 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1659 return 0;
1660}
1661
4f3edfe3 1662static int pxafb_resume(struct device *dev)
1da177e4 1663{
4f3edfe3 1664 struct pxafb_info *fbi = dev_get_drvdata(dev);
1da177e4 1665
9480e307 1666 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1667 return 0;
1668}
4f3edfe3
MR		 1669
1670static struct dev_pm_ops pxafb_pm_ops = {
1671 .suspend = pxafb_suspend,
1672 .resume = pxafb_resume,
1673};
1da177e4
LT		 1674#endif
1675
77e19675 1676static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1da177e4 1677{
77e19675 1678 int size = PAGE_ALIGN(fbi->video_mem_size);
3c42a449 1679
77e19675
EM		 1680 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1681 if (fbi->video_mem == NULL)
1682 return -ENOMEM;
1da177e4 1683
77e19675
EM		 1684 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1685 fbi->video_mem_size = size;
1da177e4 1686
77e19675
EM		 1687 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1688 fbi->fb.fix.smem_len = fbi->video_mem_size;
1689 fbi->fb.screen_base = fbi->video_mem;
84f43c30 1690
77e19675 1691 return fbi->video_mem ? 0 : -ENOMEM;
84f43c30 1692}
1693
ebdf982a
GL		 1694static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1695 struct pxafb_mach_info *inf)
84f43c30 1696{
1697 unsigned int lcd_conn = inf->lcd_conn;
77e19675
EM		 1698 struct pxafb_mode_info *m;
1699 int i;
84f43c30 1700
1701 fbi->cmap_inverse = inf->cmap_inverse;
1702 fbi->cmap_static = inf->cmap_static;
a0427509 1703 fbi->lccr4 = inf->lccr4;
84f43c30 1704
1ec26db1 1705 switch (lcd_conn & LCD_TYPE_MASK) {
84f43c30 1706 case LCD_TYPE_MONO_STN:
1707 fbi->lccr0 = LCCR0_CMS;
1708 break;
1709 case LCD_TYPE_MONO_DSTN:
1710 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1711 break;
1712 case LCD_TYPE_COLOR_STN:
1713 fbi->lccr0 = 0;
1714 break;
1715 case LCD_TYPE_COLOR_DSTN:
1716 fbi->lccr0 = LCCR0_SDS;
1717 break;
1718 case LCD_TYPE_COLOR_TFT:
1719 fbi->lccr0 = LCCR0_PAS;
1720 break;
1721 case LCD_TYPE_SMART_PANEL:
1722 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1723 break;
1724 default:
1725 /* fall back to backward compatibility way */
1726 fbi->lccr0 = inf->lccr0;
1727 fbi->lccr3 = inf->lccr3;
ebdf982a 1728 goto decode_mode;
84f43c30 1729 }
1730
1731 if (lcd_conn == LCD_MONO_STN_8BPP)
1732 fbi->lccr0 |= LCCR0_DPD;
1733
9a1ac7e4
EM		 1734 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1735
84f43c30 1736 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1737 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1738 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1739
ebdf982a 1740decode_mode:
77e19675
EM		 1741 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1742
1743 /* decide video memory size as follows:
1744 * 1. default to mode of maximum resolution
1745 * 2. allow platform to override
1746 * 3. allow module parameter to override
1747 */
1748 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1749 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1750 m->xres * m->yres * m->bpp / 8);
1751
1752 if (inf->video_mem_size > fbi->video_mem_size)
1753 fbi->video_mem_size = inf->video_mem_size;
1754
1755 if (video_mem_size > fbi->video_mem_size)
1756 fbi->video_mem_size = video_mem_size;
84f43c30 1757}
1758
9e6c2976 1759static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1da177e4
LT		 1760{
1761 struct pxafb_info *fbi;
1762 void *addr;
1763 struct pxafb_mach_info *inf = dev->platform_data;
1764
1765 /* Alloc the pxafb_info and pseudo_palette in one step */
1766 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1767 if (!fbi)
1768 return NULL;
1769
1770 memset(fbi, 0, sizeof(struct pxafb_info));
1771 fbi->dev = dev;
1772
e0d8b13a 1773 fbi->clk = clk_get(dev, NULL);
72e3524c
RK		 1774 if (IS_ERR(fbi->clk)) {
1775 kfree(fbi);
1776 return NULL;
1777 }
1778
1da177e4
LT		 1779 strcpy(fbi->fb.fix.id, PXA_NAME);
1780
1781 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1782 fbi->fb.fix.type_aux = 0;
1783 fbi->fb.fix.xpanstep = 0;
7e4b19c9 1784 fbi->fb.fix.ypanstep = 1;
1da177e4
LT		 1785 fbi->fb.fix.ywrapstep = 0;
1786 fbi->fb.fix.accel = FB_ACCEL_NONE;
1787
1788 fbi->fb.var.nonstd = 0;
1789 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1790 fbi->fb.var.height = -1;
1791 fbi->fb.var.width = -1;
7e4b19c9 1792 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1da177e4
LT		 1793 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1794
1795 fbi->fb.fbops = &pxafb_ops;
1796 fbi->fb.flags = FBINFO_DEFAULT;
1797 fbi->fb.node = -1;
1798
1799 addr = fbi;
1800 addr = addr + sizeof(struct pxafb_info);
1801 fbi->fb.pseudo_palette = addr;
1802
b0086efb 1803 fbi->state = C_STARTUP;
1804 fbi->task_state = (u_char)-1;
d14b272b 1805
84f43c30 1806 pxafb_decode_mach_info(fbi, inf);
1da177e4
LT		 1807
1808 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1809 INIT_WORK(&fbi->task, pxafb_task);
b91dbce5 1810 mutex_init(&fbi->ctrlr_lock);
2ba162b9 1811 init_completion(&fbi->disable_done);
1da177e4
LT		 1812
1813 return fbi;
1814}
1815
1816#ifdef CONFIG_FB_PXA_PARAMETERS
9e6c2976 1817static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1818{
1819 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1820
1821 const char *name = this_opt+5;
1822 unsigned int namelen = strlen(name);
1823 int res_specified = 0, bpp_specified = 0;
1824 unsigned int xres = 0, yres = 0, bpp = 0;
1825 int yres_specified = 0;
1826 int i;
1827 for (i = namelen-1; i >= 0; i--) {
1828 switch (name[i]) {
1829 case '-':
1830 namelen = i;
1831 if (!bpp_specified && !yres_specified) {
1832 bpp = simple_strtoul(&name[i+1], NULL, 0);
1833 bpp_specified = 1;
1834 } else
1835 goto done;
1836 break;
1837 case 'x':
1838 if (!yres_specified) {
1839 yres = simple_strtoul(&name[i+1], NULL, 0);
1840 yres_specified = 1;
1841 } else
1842 goto done;
1843 break;
1844 case '0' ... '9':
1845 break;
1846 default:
1847 goto done;
1848 }
1849 }
1850 if (i < 0 && yres_specified) {
1851 xres = simple_strtoul(name, NULL, 0);
1852 res_specified = 1;
1853 }
1854done:
1855 if (res_specified) {
1856 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1857 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1858 }
1859 if (bpp_specified)
1860 switch (bpp) {
1861 case 1:
1862 case 2:
1863 case 4:
1864 case 8:
1865 case 16:
1866 inf->modes[0].bpp = bpp;
1867 dev_info(dev, "overriding bit depth: %d\n", bpp);
1868 break;
1869 default:
1870 dev_err(dev, "Depth %d is not valid\n", bpp);
1871 return -EINVAL;
1872 }
1873 return 0;
1874}
1875
9e6c2976 1876static int __devinit parse_opt(struct device *dev, char *this_opt)
817daf14 1877{
1878 struct pxafb_mach_info *inf = dev->platform_data;
1879 struct pxafb_mode_info *mode = &inf->modes[0];
1880 char s[64];
1881
1882 s[0] = '\0';
1883
77e19675
EM		 1884 if (!strncmp(this_opt, "vmem:", 5)) {
1885 video_mem_size = memparse(this_opt + 5, NULL);
1886 } else if (!strncmp(this_opt, "mode:", 5)) {
817daf14 1887 return parse_opt_mode(dev, this_opt);
1888 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1889 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1890 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1891 } else if (!strncmp(this_opt, "left:", 5)) {
1892 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1893 sprintf(s, "left: %u\n", mode->left_margin);
1894 } else if (!strncmp(this_opt, "right:", 6)) {
1895 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1896 sprintf(s, "right: %u\n", mode->right_margin);
1897 } else if (!strncmp(this_opt, "upper:", 6)) {
1898 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1899 sprintf(s, "upper: %u\n", mode->upper_margin);
1900 } else if (!strncmp(this_opt, "lower:", 6)) {
1901 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1902 sprintf(s, "lower: %u\n", mode->lower_margin);
1903 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1904 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1905 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1906 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1907 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1908 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1909 } else if (!strncmp(this_opt, "hsync:", 6)) {
1910 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1911 sprintf(s, "hsync: Active Low\n");
1912 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1913 } else {
1914 sprintf(s, "hsync: Active High\n");
1915 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1916 }
1917 } else if (!strncmp(this_opt, "vsync:", 6)) {
1918 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1919 sprintf(s, "vsync: Active Low\n");
1920 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1921 } else {
1922 sprintf(s, "vsync: Active High\n");
1923 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1924 }
1925 } else if (!strncmp(this_opt, "dpc:", 4)) {
1926 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1927 sprintf(s, "double pixel clock: false\n");
1928 inf->lccr3 &= ~LCCR3_DPC;
1929 } else {
1930 sprintf(s, "double pixel clock: true\n");
1931 inf->lccr3 |= LCCR3_DPC;
1932 }
1933 } else if (!strncmp(this_opt, "outputen:", 9)) {
1934 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1935 sprintf(s, "output enable: active low\n");
1936 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1937 } else {
1938 sprintf(s, "output enable: active high\n");
1939 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1940 }
1941 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1942 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1943 sprintf(s, "pixel clock polarity: falling edge\n");
1944 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1945 } else {
1946 sprintf(s, "pixel clock polarity: rising edge\n");
1947 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1948 }
1949 } else if (!strncmp(this_opt, "color", 5)) {
1950 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1951 } else if (!strncmp(this_opt, "mono", 4)) {
1952 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1953 } else if (!strncmp(this_opt, "active", 6)) {
1954 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1955 } else if (!strncmp(this_opt, "passive", 7)) {
1956 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1957 } else if (!strncmp(this_opt, "single", 6)) {
1958 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1959 } else if (!strncmp(this_opt, "dual", 4)) {
1960 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1961 } else if (!strncmp(this_opt, "4pix", 4)) {
1962 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1963 } else if (!strncmp(this_opt, "8pix", 4)) {
1964 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1965 } else {
1966 dev_err(dev, "unknown option: %s\n", this_opt);
1967 return -EINVAL;
1968 }
1969
1970 if (s[0] != '\0')
1971 dev_info(dev, "override %s", s);
1972
1973 return 0;
1974}
1975
9e6c2976 1976static int __devinit pxafb_parse_options(struct device *dev, char *options)
817daf14 1977{
1da177e4 1978 char *this_opt;
817daf14 1979 int ret;
1da177e4 1980
817daf14 1981 if (!options || !*options)
1982 return 0;
1da177e4
LT		 1983
1984 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1985
1986 /* could be made table driven or similar?... */
817daf14 1987 while ((this_opt = strsep(&options, ",")) != NULL) {
1988 ret = parse_opt(dev, this_opt);
1989 if (ret)
1990 return ret;
1991 }
1992 return 0;
1da177e4 1993}
92ac73c1 1994
1995static char g_options[256] __devinitdata = "";
1996
f1edfc42 1997#ifndef MODULE
9e6c2976 1998static int __init pxafb_setup_options(void)
92ac73c1 1999{
2000 char *options = NULL;
2001
2002 if (fb_get_options("pxafb", &options))
2003 return -ENODEV;
2004
2005 if (options)
2006 strlcpy(g_options, options, sizeof(g_options));
2007
2008 return 0;
2009}
2010#else
2011#define pxafb_setup_options() (0)
2012
2013module_param_string(options, g_options, sizeof(g_options), 0);
2014MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
2015#endif
2016
2017#else
2018#define pxafb_parse_options(...) (0)
2019#define pxafb_setup_options() (0)
1da177e4
LT		 2020#endif
2021
1da177e4 2022#ifdef DEBUG_VAR
4f3e2664
EM		 2023/* Check for various illegal bit-combinations. Currently only
2024 * a warning is given. */
2025static void __devinit pxafb_check_options(struct device *dev,
2026 struct pxafb_mach_info *inf)
2027{
2028 if (inf->lcd_conn)
2029 return;
1da177e4 2030
b0086efb 2031 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
4f3e2664 2032 dev_warn(dev, "machine LCCR0 setting contains "
b0086efb 2033 "illegal bits: %08x\n",
2034 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2035 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
4f3e2664 2036 dev_warn(dev, "machine LCCR3 setting contains "
b0086efb 2037 "illegal bits: %08x\n",
2038 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2039 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 2040 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2041 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2042 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
4f3e2664 2043 dev_warn(dev, "Double Pixel Data (DPD) mode is "
b0086efb 2044 "only valid in passive mono"
2045 " single panel mode\n");
2046 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 2047 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
4f3e2664 2048 dev_warn(dev, "Dual panel only valid in passive mode\n");
b0086efb 2049 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2050 (inf->modes->upper_margin || inf->modes->lower_margin))
4f3e2664 2051 dev_warn(dev, "Upper and lower margins must be 0 in "
b0086efb 2052 "passive mode\n");
4f3e2664
EM		 2053}
2054#else
2055#define pxafb_check_options(...) do {} while (0)
1da177e4
LT		 2056#endif
2057
4f3e2664
EM		 2058static int __devinit pxafb_probe(struct platform_device *dev)
2059{
2060 struct pxafb_info *fbi;
2061 struct pxafb_mach_info *inf;
2062 struct resource *r;
2063 int irq, ret;
2064
2065 dev_dbg(&dev->dev, "pxafb_probe\n");
2066
2067 inf = dev->dev.platform_data;
2068 ret = -ENOMEM;
2069 fbi = NULL;
2070 if (!inf)
2071 goto failed;
2072
2073 ret = pxafb_parse_options(&dev->dev, g_options);
2074 if (ret < 0)
2075 goto failed;
2076
2077 pxafb_check_options(&dev->dev, inf);
2078
b0086efb 2079 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2080 inf->modes->xres,
2081 inf->modes->yres,
2082 inf->modes->bpp);
2083 if (inf->modes->xres == 0 ||
2084 inf->modes->yres == 0 ||
2085 inf->modes->bpp == 0) {
3ae5eaec 2086 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 2087 ret = -EINVAL;
2088 goto failed;
2089 }
a5718a14 2090
3ae5eaec 2091 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 2092 if (!fbi) {
b0086efb 2093 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 2094 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 2095 ret = -ENOMEM;
1da177e4
LT		 2096 goto failed;
2097 }
2098
52a7a1ce
DM		 2099 if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2100 fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2101
a5718a14
EM		 2102 fbi->backlight_power = inf->pxafb_backlight_power;
2103 fbi->lcd_power = inf->pxafb_lcd_power;
2104
ce4fb7b8 2105 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2106 if (r == NULL) {
2107 dev_err(&dev->dev, "no I/O memory resource defined\n");
2108 ret = -ENODEV;
ee98476b 2109 goto failed_fbi;
ce4fb7b8 2110 }
2111
53eff417 2112 r = request_mem_region(r->start, resource_size(r), dev->name);
ce4fb7b8 2113 if (r == NULL) {
2114 dev_err(&dev->dev, "failed to request I/O memory\n");
2115 ret = -EBUSY;
ee98476b 2116 goto failed_fbi;
ce4fb7b8 2117 }
2118
53eff417 2119 fbi->mmio_base = ioremap(r->start, resource_size(r));
ce4fb7b8 2120 if (fbi->mmio_base == NULL) {
2121 dev_err(&dev->dev, "failed to map I/O memory\n");
2122 ret = -EBUSY;
2123 goto failed_free_res;
2124 }
2125
77e19675
EM		 2126 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2127 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2128 &fbi->dma_buff_phys, GFP_KERNEL);
2129 if (fbi->dma_buff == NULL) {
2130 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2131 ret = -ENOMEM;
2132 goto failed_free_io;
2133 }
2134
2135 ret = pxafb_init_video_memory(fbi);
1da177e4 2136 if (ret) {
3ae5eaec 2137 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 2138 ret = -ENOMEM;
77e19675 2139 goto failed_free_dma;
1da177e4 2140 }
1da177e4 2141
ce4fb7b8 2142 irq = platform_get_irq(dev, 0);
2143 if (irq < 0) {
2144 dev_err(&dev->dev, "no IRQ defined\n");
2145 ret = -ENODEV;
2146 goto failed_free_mem;
2147 }
2148
2149 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1da177e4 2150 if (ret) {
3ae5eaec 2151 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 2152 ret = -EBUSY;
ce4fb7b8 2153 goto failed_free_mem;
1da177e4
LT		 2154 }
2155
3c42a449
EM		 2156 ret = pxafb_smart_init(fbi);
2157 if (ret) {
2158 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2159 goto failed_free_irq;
2160 }
07df1c4f 2161
1da177e4
LT		 2162 /*
2163 * This makes sure that our colour bitfield
2164 * descriptors are correctly initialised.
2165 */
ee98476b
JK		 2166 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2167 if (ret) {
2168 dev_err(&dev->dev, "failed to get suitable mode\n");
2169 goto failed_free_irq;
2170 }
2171
2172 ret = pxafb_set_par(&fbi->fb);
2173 if (ret) {
2174 dev_err(&dev->dev, "Failed to set parameters\n");
2175 goto failed_free_irq;
2176 }
1da177e4 2177
3ae5eaec 2178 platform_set_drvdata(dev, fbi);
1da177e4
LT		 2179
2180 ret = register_framebuffer(&fbi->fb);
2181 if (ret < 0) {
b0086efb 2182 dev_err(&dev->dev,
2183 "Failed to register framebuffer device: %d\n", ret);
ee98476b 2184 goto failed_free_cmap;
1da177e4
LT		 2185 }
2186
198fc108
EM		 2187 pxafb_overlay_init(fbi);
2188
1da177e4
LT		 2189#ifdef CONFIG_CPU_FREQ
2190 fbi->freq_transition.notifier_call = pxafb_freq_transition;
2191 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 2192 cpufreq_register_notifier(&fbi->freq_transition,
2193 CPUFREQ_TRANSITION_NOTIFIER);
2194 cpufreq_register_notifier(&fbi->freq_policy,
2195 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 2196#endif
2197
2198 /*
2199 * Ok, now enable the LCD controller
2200 */
2201 set_ctrlr_state(fbi, C_ENABLE);
2202
2203 return 0;
2204
ee98476b
JK		 2205failed_free_cmap:
2206 if (fbi->fb.cmap.len)
2207 fb_dealloc_cmap(&fbi->fb.cmap);
ce4fb7b8 2208failed_free_irq:
2209 free_irq(irq, fbi);
ce4fb7b8 2210failed_free_mem:
77e19675
EM		 2211 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2212failed_free_dma:
2213 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2214 fbi->dma_buff, fbi->dma_buff_phys);
ee98476b
JK		 2215failed_free_io:
2216 iounmap(fbi->mmio_base);
2217failed_free_res:
53eff417 2218 release_mem_region(r->start, resource_size(r));
ee98476b
JK		 2219failed_fbi:
2220 clk_put(fbi->clk);
3ae5eaec 2221 platform_set_drvdata(dev, NULL);
1da177e4 2222 kfree(fbi);
ee98476b 2223failed:
1da177e4
LT		 2224 return ret;
2225}
2226
9f17f287
JK		 2227static int __devexit pxafb_remove(struct platform_device *dev)
2228{
2229 struct pxafb_info *fbi = platform_get_drvdata(dev);
2230 struct resource *r;
2231 int irq;
2232 struct fb_info *info;
2233
2234 if (!fbi)
2235 return 0;
2236
2237 info = &fbi->fb;
2238
198fc108 2239 pxafb_overlay_exit(fbi);
9f17f287
JK		 2240 unregister_framebuffer(info);
2241
2242 pxafb_disable_controller(fbi);
2243
2244 if (fbi->fb.cmap.len)
2245 fb_dealloc_cmap(&fbi->fb.cmap);
2246
2247 irq = platform_get_irq(dev, 0);
2248 free_irq(irq, fbi);
2249
77e19675
EM		 2250 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2251
2252 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2253 fbi->dma_buff, fbi->dma_buff_phys);
9f17f287
JK		 2254
2255 iounmap(fbi->mmio_base);
2256
2257 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
53eff417 2258 release_mem_region(r->start, resource_size(r));
9f17f287
JK		 2259
2260 clk_put(fbi->clk);
2261 kfree(fbi);
2262
2263 return 0;
2264}
2265
3ae5eaec 2266static struct platform_driver pxafb_driver = {
1da177e4 2267 .probe = pxafb_probe,
bdf602bd 2268 .remove = __devexit_p(pxafb_remove),
3ae5eaec 2269 .driver = {
9f17f287 2270 .owner = THIS_MODULE,
3ae5eaec 2271 .name = "pxa2xx-fb",
4f3edfe3
MR		 2272#ifdef CONFIG_PM
2273 .pm = &pxafb_pm_ops,
2274#endif
3ae5eaec 2275 },
1da177e4
LT		 2276};
2277
9e6c2976 2278static int __init pxafb_init(void)
1da177e4 2279{
92ac73c1 2280 if (pxafb_setup_options())
2281 return -EINVAL;
1da177e4 2282
3ae5eaec 2283 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 2284}
2285
9f17f287
JK		 2286static void __exit pxafb_exit(void)
2287{
2288 platform_driver_unregister(&pxafb_driver);
2289}
2290
1da177e4 2291module_init(pxafb_init);
9f17f287 2292module_exit(pxafb_exit);
1da177e4
LT		 2293
2294MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2295MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)