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Merge branch 'for-2.6.28' of git://linux-nfs.org/~bfields/linux
[linux-2.6-block.git] / drivers / video / aty / radeon_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53#define RADEON_VERSION "0.2.0"
54
b0313f89
JD		 55#include "radeonfb.h"
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/moduleparam.h>
59#include <linux/kernel.h>
60#include <linux/errno.h>
61#include <linux/string.h>
e7a18c9c 62#include <linux/ctype.h>
1da177e4 63#include <linux/mm.h>
1da177e4
LT		 64#include <linux/slab.h>
65#include <linux/delay.h>
66#include <linux/time.h>
67#include <linux/fb.h>
68#include <linux/ioport.h>
69#include <linux/init.h>
70#include <linux/pci.h>
71#include <linux/vmalloc.h>
72#include <linux/device.h>
1da177e4
LT		 73
74#include <asm/io.h>
84902b7a 75#include <linux/uaccess.h>
1da177e4
LT		 76
77#ifdef CONFIG_PPC_OF
78
79#include <asm/pci-bridge.h>
80#include "../macmodes.h"
81
1da177e4
LT		 82#ifdef CONFIG_BOOTX_TEXT
83#include <asm/btext.h>
84#endif
85
86#endif /* CONFIG_PPC_OF */
87
88#ifdef CONFIG_MTRR
89#include <asm/mtrr.h>
90#endif
91
92#include <video/radeon.h>
93#include <linux/radeonfb.h>
94
95#include "../edid.h" // MOVE THAT TO include/video
96#include "ati_ids.h"
1da177e4
LT		 97
98#define MAX_MAPPED_VRAM (2048*2048*4)
99#define MIN_MAPPED_VRAM (1024*768*1)
100
101#define CHIP_DEF(id, family, flags) \
102 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
103
104static struct pci_device_id radeonfb_pci_table[] = {
dd144713 105 /* Radeon Xpress 200m */
106 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
106c4a9c 107 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
1da177e4
LT		 108 /* Mobility M6 */
109 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
110 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
111 /* Radeon VE/7000 */
112 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
113 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
183dee0f 114 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
1da177e4
LT		 115 /* Radeon IGP320M (U1) */
116 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* Radeon IGP320 (A3) */
118 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* IGP330M/340M/350M (U2) */
120 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121 /* IGP330/340/350 (A4) */
122 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123 /* Mobility 7000 IGP */
124 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
125 /* 7000 IGP (A4+) */
126 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
127 /* 8500 AIW */
128 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
130 /* 8700/8800 */
131 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
132 /* 8500 */
133 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
134 /* 9100 */
135 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
136 /* Mobility M7 */
137 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
138 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 /* 7500 */
140 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
141 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
142 /* Mobility M9 */
143 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 /* 9000/Pro */
148 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
149 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
0b693eaf
SB		 150
151 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
1da177e4
LT		 152 /* Mobility 9100 IGP (U3) */
153 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
155 /* 9100 IGP (A5) */
156 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
158 /* Mobility 9200 (M9+) */
159 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
161 /* 9200 */
162 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
165 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
166 /* 9500 */
167 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
169 /* 9600TX / FireGL Z1 */
170 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
172 /* 9700/9500/Pro/FireGL X1 */
173 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
176 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
177 /* Mobility M10/M11 */
178 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
184 /* 9600/FireGL T2 */
185 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
191 /* 9800/Pro/FileGL X2 */
192 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
200 /* Newer stuff */
201 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
205 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
3050d45c 207 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
1da177e4
LT		 208 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
212 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
219 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
226 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
227 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
228 /* Original Radeon/7200 */
229 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
231 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
232 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
233 { 0, }
234};
235MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
236
237
238typedef struct {
239 u16 reg;
240 u32 val;
241} reg_val;
242
243
244/* these common regs are cleared before mode setting so they do not
245 * interfere with anything
246 */
247static reg_val common_regs[] = {
248 { OVR_CLR, 0 },
249 { OVR_WID_LEFT_RIGHT, 0 },
250 { OVR_WID_TOP_BOTTOM, 0 },
251 { OV0_SCALE_CNTL, 0 },
252 { SUBPIC_CNTL, 0 },
253 { VIPH_CONTROL, 0 },
254 { I2C_CNTL_1, 0 },
255 { GEN_INT_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 },
257 { CAP1_TRIG_CNTL, 0 },
258};
259
260/*
261 * globals
262 */
263
264static char *mode_option;
265static char *monitor_layout;
266static int noaccel = 0;
267static int default_dynclk = -2;
268static int nomodeset = 0;
269static int ignore_edid = 0;
270static int mirror = 0;
271static int panel_yres = 0;
272static int force_dfp = 0;
273static int force_measure_pll = 0;
274#ifdef CONFIG_MTRR
275static int nomtrr = 0;
276#endif
994aad25
VB		 277static int force_sleep;
278static int ignore_devlist;
202d4e60
RP		 279#ifdef CONFIG_PMAC_BACKLIGHT
280static int backlight = 1;
281#else
282static int backlight = 0;
283#endif
1da177e4
LT		 284
285/*
286 * prototypes
287 */
288
1da177e4
LT		 289static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
290{
291 if (!rinfo->bios_seg)
292 return;
293 pci_unmap_rom(dev, rinfo->bios_seg);
294}
295
296static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
297{
298 void __iomem *rom;
299 u16 dptr;
300 u8 rom_type;
301 size_t rom_size;
302
303 /* If this is a primary card, there is a shadow copy of the
304 * ROM somewhere in the first meg. We will just ignore the copy
305 * and use the ROM directly.
306 */
307
308 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
309 unsigned int temp;
310 temp = INREG(MPP_TB_CONFIG);
311 temp &= 0x00ffffffu;
312 temp |= 0x04 << 24;
313 OUTREG(MPP_TB_CONFIG, temp);
314 temp = INREG(MPP_TB_CONFIG);
315
316 rom = pci_map_rom(dev, &rom_size);
317 if (!rom) {
318 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
319 pci_name(rinfo->pdev));
320 return -ENOMEM;
321 }
322
323 rinfo->bios_seg = rom;
324
325 /* Very simple test to make sure it appeared */
326 if (BIOS_IN16(0) != 0xaa55) {
3b4abffb
OH		 327 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
328 "should be 0xaa55\n",
329 pci_name(rinfo->pdev), BIOS_IN16(0));
1da177e4
LT		 330 goto failed;
331 }
332 /* Look for the PCI data to check the ROM type */
333 dptr = BIOS_IN16(0x18);
334
335 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
336 * for now, until I've verified this works everywhere. The goal here is more
337 * to phase out Open Firmware images.
338 *
339 * Currently, we only look at the first PCI data, we could iteratre and deal with
340 * them all, and we should use fb_bios_start relative to start of image and not
341 * relative start of ROM, but so far, I never found a dual-image ATI card
342 *
343 * typedef struct {
344 * u32 signature; + 0x00
345 * u16 vendor; + 0x04
346 * u16 device; + 0x06
347 * u16 reserved_1; + 0x08
348 * u16 dlen; + 0x0a
349 * u8 drevision; + 0x0c
350 * u8 class_hi; + 0x0d
351 * u16 class_lo; + 0x0e
352 * u16 ilen; + 0x10
353 * u16 irevision; + 0x12
354 * u8 type; + 0x14
355 * u8 indicator; + 0x15
356 * u16 reserved_2; + 0x16
357 * } pci_data_t;
358 */
359 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
360 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
361 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
362 goto anyway;
363 }
364 rom_type = BIOS_IN8(dptr + 0x14);
365 switch(rom_type) {
366 case 0:
367 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
368 break;
369 case 1:
370 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
371 goto failed;
372 case 2:
373 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
374 goto failed;
375 default:
376 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
377 goto failed;
378 }
379 anyway:
380 /* Locate the flat panel infos, do some sanity checking !!! */
381 rinfo->fp_bios_start = BIOS_IN16(0x48);
382 return 0;
383
384 failed:
385 rinfo->bios_seg = NULL;
386 radeon_unmap_ROM(rinfo, dev);
387 return -ENXIO;
388}
389
390#ifdef CONFIG_X86
391static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
392{
393 /* I simplified this code as we used to miss the signatures in
394 * a lot of case. It's now closer to XFree, we just don't check
395 * for signatures at all... Something better will have to be done
396 * if we end up having conflicts
397 */
398 u32 segstart;
399 void __iomem *rom_base = NULL;
400
401 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
402 rom_base = ioremap(segstart, 0x10000);
403 if (rom_base == NULL)
404 return -ENOMEM;
405 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
406 break;
407 iounmap(rom_base);
408 rom_base = NULL;
409 }
410 if (rom_base == NULL)
411 return -ENXIO;
412
413 /* Locate the flat panel infos, do some sanity checking !!! */
414 rinfo->bios_seg = rom_base;
415 rinfo->fp_bios_start = BIOS_IN16(0x48);
416
417 return 0;
418}
419#endif
420
9f47df26 421#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4
LT		 422/*
423 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
424 * tree. Hopefully, ATI OF driver is kind enough to fill these
425 */
426static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
427{
428 struct device_node *dp = rinfo->of_node;
b04e3dd4 429 const u32 *val;
1da177e4
LT		 430
431 if (dp == NULL)
432 return -ENODEV;
40cd3a45 433 val = of_get_property(dp, "ATY,RefCLK", NULL);
1da177e4
LT		 434 if (!val || !*val) {
435 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
436 return -EINVAL;
437 }
438
439 rinfo->pll.ref_clk = (*val) / 10;
440
40cd3a45 441 val = of_get_property(dp, "ATY,SCLK", NULL);
1da177e4
LT		 442 if (val && *val)
443 rinfo->pll.sclk = (*val) / 10;
444
40cd3a45 445 val = of_get_property(dp, "ATY,MCLK", NULL);
1da177e4
LT		 446 if (val && *val)
447 rinfo->pll.mclk = (*val) / 10;
448
449 return 0;
450}
9f47df26 451#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
1da177e4
LT		 452
453/*
454 * Read PLL infos from chip registers
455 */
456static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
457{
458 unsigned char ppll_div_sel;
459 unsigned Ns, Nm, M;
460 unsigned sclk, mclk, tmp, ref_div;
461 int hTotal, vTotal, num, denom, m, n;
462 unsigned long long hz, vclk;
463 long xtal;
464 struct timeval start_tv, stop_tv;
465 long total_secs, total_usecs;
466 int i;
467
468 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
469 * here, so... --BenH
470 */
471
472 /* Flush PCI buffers ? */
017fb98e 473 tmp = INREG16(DEVICE_ID);
1da177e4
LT		 474
475 local_irq_disable();
476
477 for(i=0; i<1000000; i++)
478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
479 break;
480
481 do_gettimeofday(&start_tv);
482
483 for(i=0; i<1000000; i++)
484 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
485 break;
486
487 for(i=0; i<1000000; i++)
488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
489 break;
490
491 do_gettimeofday(&stop_tv);
492
493 local_irq_enable();
494
495 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
496 if (total_secs > 10)
497 return -1;
498 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
499 total_usecs += total_secs * 1000000;
500 if (total_usecs < 0)
501 total_usecs = -total_usecs;
502 hz = 1000000/total_usecs;
503
504 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
505 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
506 vclk = (long long)hTotal * (long long)vTotal * hz;
507
508 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
509 case 0:
510 default:
511 num = 1;
512 denom = 1;
513 break;
514 case 1:
515 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
516 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
517 num = 2*n;
518 denom = 2*m;
519 break;
520 case 2:
521 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
522 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
523 num = 2*n;
524 denom = 2*m;
525 break;
526 }
527
528 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
529 radeon_pll_errata_after_index(rinfo);
530
531 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
532 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
533
534 num *= n;
535 denom *= m;
536
537 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
538 case 1:
539 denom *= 2;
540 break;
541 case 2:
542 denom *= 4;
543 break;
544 case 3:
545 denom *= 8;
546 break;
547 case 4:
548 denom *= 3;
549 break;
550 case 6:
551 denom *= 6;
552 break;
553 case 7:
554 denom *= 12;
555 break;
556 }
557
558 vclk *= denom;
559 do_div(vclk, 1000 * num);
560 xtal = vclk;
561
562 if ((xtal > 26900) && (xtal < 27100))
563 xtal = 2700;
564 else if ((xtal > 14200) && (xtal < 14400))
565 xtal = 1432;
566 else if ((xtal > 29400) && (xtal < 29600))
567 xtal = 2950;
568 else {
569 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
570 return -1;
571 }
572
573 tmp = INPLL(M_SPLL_REF_FB_DIV);
574 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
575
576 Ns = (tmp & 0xff0000) >> 16;
577 Nm = (tmp & 0xff00) >> 8;
578 M = (tmp & 0xff);
579 sclk = round_div((2 * Ns * xtal), (2 * M));
580 mclk = round_div((2 * Nm * xtal), (2 * M));
581
582 /* we're done, hopefully these are sane values */
583 rinfo->pll.ref_clk = xtal;
584 rinfo->pll.ref_div = ref_div;
585 rinfo->pll.sclk = sclk;
586 rinfo->pll.mclk = mclk;
587
588 return 0;
589}
590
591/*
4a4efbde 592 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
1da177e4
LT		 593 */
594static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
595{
596 /*
597 * In the case nothing works, these are defaults; they are mostly
598 * incomplete, however. It does provide ppll_max and _min values
599 * even for most other methods, however.
600 */
601 switch (rinfo->chipset) {
602 case PCI_DEVICE_ID_ATI_RADEON_QW:
603 case PCI_DEVICE_ID_ATI_RADEON_QX:
604 rinfo->pll.ppll_max = 35000;
605 rinfo->pll.ppll_min = 12000;
606 rinfo->pll.mclk = 23000;
607 rinfo->pll.sclk = 23000;
608 rinfo->pll.ref_clk = 2700;
609 break;
610 case PCI_DEVICE_ID_ATI_RADEON_QL:
611 case PCI_DEVICE_ID_ATI_RADEON_QN:
612 case PCI_DEVICE_ID_ATI_RADEON_QO:
613 case PCI_DEVICE_ID_ATI_RADEON_Ql:
614 case PCI_DEVICE_ID_ATI_RADEON_BB:
615 rinfo->pll.ppll_max = 35000;
616 rinfo->pll.ppll_min = 12000;
617 rinfo->pll.mclk = 27500;
618 rinfo->pll.sclk = 27500;
619 rinfo->pll.ref_clk = 2700;
620 break;
621 case PCI_DEVICE_ID_ATI_RADEON_Id:
622 case PCI_DEVICE_ID_ATI_RADEON_Ie:
623 case PCI_DEVICE_ID_ATI_RADEON_If:
624 case PCI_DEVICE_ID_ATI_RADEON_Ig:
625 rinfo->pll.ppll_max = 35000;
626 rinfo->pll.ppll_min = 12000;
627 rinfo->pll.mclk = 25000;
628 rinfo->pll.sclk = 25000;
629 rinfo->pll.ref_clk = 2700;
630 break;
631 case PCI_DEVICE_ID_ATI_RADEON_ND:
632 case PCI_DEVICE_ID_ATI_RADEON_NE:
633 case PCI_DEVICE_ID_ATI_RADEON_NF:
634 case PCI_DEVICE_ID_ATI_RADEON_NG:
635 rinfo->pll.ppll_max = 40000;
636 rinfo->pll.ppll_min = 20000;
637 rinfo->pll.mclk = 27000;
638 rinfo->pll.sclk = 27000;
639 rinfo->pll.ref_clk = 2700;
640 break;
641 case PCI_DEVICE_ID_ATI_RADEON_QD:
642 case PCI_DEVICE_ID_ATI_RADEON_QE:
643 case PCI_DEVICE_ID_ATI_RADEON_QF:
644 case PCI_DEVICE_ID_ATI_RADEON_QG:
645 default:
646 rinfo->pll.ppll_max = 35000;
647 rinfo->pll.ppll_min = 12000;
648 rinfo->pll.mclk = 16600;
649 rinfo->pll.sclk = 16600;
650 rinfo->pll.ref_clk = 2700;
651 break;
652 }
653 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
654
655
9f47df26 656#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4 657 /*
4a4efbde 658 * Retrieve PLL infos from Open Firmware first
1da177e4
LT		 659 */
660 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
4a4efbde 661 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
1da177e4
LT		 662 goto found;
663 }
9f47df26 664#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
1da177e4
LT		 665
666 /*
667 * Check out if we have an X86 which gave us some PLL informations
4a4efbde 668 * and if yes, retrieve them
1da177e4
LT		 669 */
670 if (!force_measure_pll && rinfo->bios_seg) {
671 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
672
673 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
674 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
675 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
676 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
677 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
678 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
679
4a4efbde 680 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
1da177e4
LT		 681 goto found;
682 }
683
684 /*
685 * We didn't get PLL parameters from either OF or BIOS, we try to
686 * probe them
687 */
688 if (radeon_probe_pll_params(rinfo) == 0) {
4a4efbde 689 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
1da177e4
LT		 690 goto found;
691 }
692
693 /*
694 * Fall back to already-set defaults...
695 */
696 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
697
698found:
699 /*
4a4efbde 700 * Some methods fail to retrieve SCLK and MCLK values, we apply default
1da177e4
LT		 701 * settings in this case (200Mhz). If that really happne often, we could
702 * fetch from registers instead...
703 */
704 if (rinfo->pll.mclk == 0)
705 rinfo->pll.mclk = 20000;
706 if (rinfo->pll.sclk == 0)
707 rinfo->pll.sclk = 20000;
708
709 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
710 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
711 rinfo->pll.ref_div,
712 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
713 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
714 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
715}
716
717static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
718{
719 struct radeonfb_info *rinfo = info->par;
720 struct fb_var_screeninfo v;
721 int nom, den;
722 unsigned int pitch;
723
724 if (radeon_match_mode(rinfo, &v, var))
725 return -EINVAL;
726
727 switch (v.bits_per_pixel) {
728 case 0 ... 8:
729 v.bits_per_pixel = 8;
730 break;
731 case 9 ... 16:
732 v.bits_per_pixel = 16;
733 break;
734 case 17 ... 24:
735#if 0 /* Doesn't seem to work */
736 v.bits_per_pixel = 24;
737 break;
738#endif
739 return -EINVAL;
740 case 25 ... 32:
741 v.bits_per_pixel = 32;
742 break;
743 default:
744 return -EINVAL;
745 }
746
747 switch (var_to_depth(&v)) {
748 case 8:
749 nom = den = 1;
750 v.red.offset = v.green.offset = v.blue.offset = 0;
751 v.red.length = v.green.length = v.blue.length = 8;
752 v.transp.offset = v.transp.length = 0;
753 break;
754 case 15:
755 nom = 2;
756 den = 1;
757 v.red.offset = 10;
758 v.green.offset = 5;
759 v.blue.offset = 0;
760 v.red.length = v.green.length = v.blue.length = 5;
761 v.transp.offset = v.transp.length = 0;
762 break;
763 case 16:
764 nom = 2;
765 den = 1;
766 v.red.offset = 11;
767 v.green.offset = 5;
768 v.blue.offset = 0;
769 v.red.length = 5;
770 v.green.length = 6;
771 v.blue.length = 5;
772 v.transp.offset = v.transp.length = 0;
773 break;
774 case 24:
775 nom = 4;
776 den = 1;
777 v.red.offset = 16;
778 v.green.offset = 8;
779 v.blue.offset = 0;
780 v.red.length = v.blue.length = v.green.length = 8;
781 v.transp.offset = v.transp.length = 0;
782 break;
783 case 32:
784 nom = 4;
785 den = 1;
786 v.red.offset = 16;
787 v.green.offset = 8;
788 v.blue.offset = 0;
789 v.red.length = v.blue.length = v.green.length = 8;
790 v.transp.offset = 24;
791 v.transp.length = 8;
792 break;
793 default:
794 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
795 var->xres, var->yres, var->bits_per_pixel);
796 return -EINVAL;
797 }
798
799 if (v.yres_virtual < v.yres)
800 v.yres_virtual = v.yres;
801 if (v.xres_virtual < v.xres)
802 v.xres_virtual = v.xres;
803
804
805 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
806 * with some panels, though I don't quite like this solution
807 */
808 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
809 v.xres_virtual = v.xres_virtual & ~7ul;
810 } else {
811 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
812 & ~(0x3f)) >> 6;
813 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
814 }
815
816 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
817 return -EINVAL;
818
819 if (v.xres_virtual < v.xres)
820 v.xres = v.xres_virtual;
821
822 if (v.xoffset < 0)
823 v.xoffset = 0;
824 if (v.yoffset < 0)
825 v.yoffset = 0;
826
827 if (v.xoffset > v.xres_virtual - v.xres)
828 v.xoffset = v.xres_virtual - v.xres - 1;
829
830 if (v.yoffset > v.yres_virtual - v.yres)
831 v.yoffset = v.yres_virtual - v.yres - 1;
832
833 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
834 v.transp.offset = v.transp.length =
835 v.transp.msb_right = 0;
836
837 memcpy(var, &v, sizeof(v));
838
839 return 0;
840}
841
842
843static int radeonfb_pan_display (struct fb_var_screeninfo *var,
844 struct fb_info *info)
845{
846 struct radeonfb_info *rinfo = info->par;
847
848 if ((var->xoffset + var->xres > var->xres_virtual)
849 || (var->yoffset + var->yres > var->yres_virtual))
850 return -EINVAL;
851
852 if (rinfo->asleep)
853 return 0;
854
1da177e4
LT		 855 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
856 * var->bits_per_pixel / 8) & ~7);
857 return 0;
858}
859
860
67a6680d
CH		 861static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
862 unsigned long arg)
1da177e4
LT		 863{
864 struct radeonfb_info *rinfo = info->par;
865 unsigned int tmp;
866 u32 value = 0;
867 int rc;
868
869 switch (cmd) {
870 /*
871 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
872 * and do something better using 2nd CRTC instead of just hackish
873 * routing to second output
874 */
875 case FBIO_RADEON_SET_MIRROR:
876 if (!rinfo->is_mobility)
877 return -EINVAL;
878
879 rc = get_user(value, (__u32 __user *)arg);
880
881 if (rc)
882 return rc;
883
1da177e4
LT		 884 if (value & 0x01) {
885 tmp = INREG(LVDS_GEN_CNTL);
886
887 tmp |= (LVDS_ON | LVDS_BLON);
888 } else {
889 tmp = INREG(LVDS_GEN_CNTL);
890
891 tmp &= ~(LVDS_ON | LVDS_BLON);
892 }
893
894 OUTREG(LVDS_GEN_CNTL, tmp);
895
896 if (value & 0x02) {
897 tmp = INREG(CRTC_EXT_CNTL);
898 tmp |= CRTC_CRT_ON;
899
900 mirror = 1;
901 } else {
902 tmp = INREG(CRTC_EXT_CNTL);
903 tmp &= ~CRTC_CRT_ON;
904
905 mirror = 0;
906 }
907
908 OUTREG(CRTC_EXT_CNTL, tmp);
909
910 return 0;
911 case FBIO_RADEON_GET_MIRROR:
912 if (!rinfo->is_mobility)
913 return -EINVAL;
914
915 tmp = INREG(LVDS_GEN_CNTL);
916 if ((LVDS_ON | LVDS_BLON) & tmp)
917 value |= 0x01;
918
919 tmp = INREG(CRTC_EXT_CNTL);
920 if (CRTC_CRT_ON & tmp)
921 value |= 0x02;
922
923 return put_user(value, (__u32 __user *)arg);
924 default:
925 return -EINVAL;
926 }
927
928 return -EINVAL;
929}
930
931
932int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
933{
934 u32 val;
935 u32 tmp_pix_clks;
936 int unblank = 0;
937
938 if (rinfo->lock_blank)
939 return 0;
940
b1ee26ba 941 radeon_engine_idle(rinfo);
1da177e4
LT		 942
943 val = INREG(CRTC_EXT_CNTL);
944 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
945 CRTC_VSYNC_DIS);
946 switch (blank) {
947 case FB_BLANK_VSYNC_SUSPEND:
948 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
949 break;
950 case FB_BLANK_HSYNC_SUSPEND:
951 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
952 break;
953 case FB_BLANK_POWERDOWN:
954 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
955 CRTC_HSYNC_DIS);
956 break;
957 case FB_BLANK_NORMAL:
958 val |= CRTC_DISPLAY_DIS;
959 break;
960 case FB_BLANK_UNBLANK:
961 default:
962 unblank = 1;
963 }
964 OUTREG(CRTC_EXT_CNTL, val);
965
966
967 switch (rinfo->mon1_type) {
968 case MT_DFP:
969 if (unblank)
970 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
971 ~(FP_FPON | FP_TMDS_EN));
972 else {
973 if (mode_switch || blank == FB_BLANK_NORMAL)
974 break;
975 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
976 }
977 break;
978 case MT_LCD:
979 del_timer_sync(&rinfo->lvds_timer);
980 val = INREG(LVDS_GEN_CNTL);
981 if (unblank) {
982 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
983 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
984 & (LVDS_DIGON | LVDS_BL_MOD_EN));
985 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
986 OUTREG(LVDS_GEN_CNTL, target_val);
987 else if ((val ^ target_val) != 0) {
988 OUTREG(LVDS_GEN_CNTL, target_val
989 & ~(LVDS_ON | LVDS_BL_MOD_EN));
990 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
991 rinfo->init_state.lvds_gen_cntl |=
992 target_val & LVDS_STATE_MASK;
993 if (mode_switch) {
994 radeon_msleep(rinfo->panel_info.pwr_delay);
995 OUTREG(LVDS_GEN_CNTL, target_val);
996 }
997 else {
998 rinfo->pending_lvds_gen_cntl = target_val;
999 mod_timer(&rinfo->lvds_timer,
1000 jiffies +
1001 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1002 }
1003 }
1004 } else {
1005 val |= LVDS_DISPLAY_DIS;
1006 OUTREG(LVDS_GEN_CNTL, val);
1007
1008 /* We don't do a full switch-off on a simple mode switch */
1009 if (mode_switch || blank == FB_BLANK_NORMAL)
1010 break;
1011
1012 /* Asic bug, when turning off LVDS_ON, we have to make sure
1013 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1014 */
1015 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1016 if (rinfo->is_mobility || rinfo->is_IGP)
1017 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1018 val &= ~(LVDS_BL_MOD_EN);
1019 OUTREG(LVDS_GEN_CNTL, val);
1020 udelay(100);
1021 val &= ~(LVDS_ON | LVDS_EN);
1022 OUTREG(LVDS_GEN_CNTL, val);
1023 val &= ~LVDS_DIGON;
1024 rinfo->pending_lvds_gen_cntl = val;
1025 mod_timer(&rinfo->lvds_timer,
1026 jiffies +
1027 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1028 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1029 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1030 if (rinfo->is_mobility || rinfo->is_IGP)
1031 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1032 }
1033 break;
1034 case MT_CRT:
1035 // todo: powerdown DAC
1036 default:
1037 break;
1038 }
1039
7ab87670 1040 return 0;
1da177e4
LT		 1041}
1042
1043static int radeonfb_blank (int blank, struct fb_info *info)
1044{
1045 struct radeonfb_info *rinfo = info->par;
1046
1047 if (rinfo->asleep)
1048 return 0;
b1ee26ba 1049
1da177e4
LT		 1050 return radeon_screen_blank(rinfo, blank, 0);
1051}
1052
71494376
BH		 1053static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1054 unsigned blue, unsigned transp,
1055 struct radeonfb_info *rinfo)
1da177e4 1056{
1da177e4
LT		 1057 u32 pindex;
1058 unsigned int i;
71494376
BH		 1059
1060
1da177e4 1061 if (regno > 255)
db77ec27 1062 return -EINVAL;
1da177e4
LT		 1063
1064 red >>= 8;
1065 green >>= 8;
1066 blue >>= 8;
1067 rinfo->palette[regno].red = red;
1068 rinfo->palette[regno].green = green;
1069 rinfo->palette[regno].blue = blue;
1070
1071 /* default */
1072 pindex = regno;
1073
1074 if (!rinfo->asleep) {
1da177e4
LT		 1075 if (rinfo->bpp == 16) {
1076 pindex = regno * 8;
1077
1078 if (rinfo->depth == 16 && regno > 63)
db77ec27 1079 return -EINVAL;
1da177e4 1080 if (rinfo->depth == 15 && regno > 31)
db77ec27 1081 return -EINVAL;
1da177e4 1082
71494376
BH		 1083 /* For 565, the green component is mixed one order
1084 * below
1085 */
1da177e4
LT		 1086 if (rinfo->depth == 16) {
1087 OUTREG(PALETTE_INDEX, pindex>>1);
71494376
BH		 1088 OUTREG(PALETTE_DATA,
1089 (rinfo->palette[regno>>1].red << 16) |
1090 (green << 8) |
1091 (rinfo->palette[regno>>1].blue));
1da177e4
LT		 1092 green = rinfo->palette[regno<<1].green;
1093 }
1094 }
1095
1096 if (rinfo->depth != 16 || regno < 32) {
1097 OUTREG(PALETTE_INDEX, pindex);
71494376
BH		 1098 OUTREG(PALETTE_DATA, (red << 16) |
1099 (green << 8) | blue);
1da177e4 1100 }
1da177e4
LT		 1101 }
1102 if (regno < 16) {
71494376 1103 u32 *pal = rinfo->info->pseudo_palette;
1da177e4
LT		 1104 switch (rinfo->depth) {
1105 case 15:
1106 pal[regno] = (regno << 10) | (regno << 5) | regno;
1107 break;
1108 case 16:
1109 pal[regno] = (regno << 11) | (regno << 5) | regno;
1110 break;
1111 case 24:
1112 pal[regno] = (regno << 16) | (regno << 8) | regno;
1113 break;
1114 case 32:
1115 i = (regno << 8) | regno;
1116 pal[regno] = (i << 16) | i;
1117 break;
1118 }
1119 }
1120 return 0;
1121}
1122
71494376
BH		 1123static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1124 unsigned blue, unsigned transp,
1125 struct fb_info *info)
1126{
1127 struct radeonfb_info *rinfo = info->par;
1128 u32 dac_cntl2, vclk_cntl = 0;
1129 int rc;
1130
1131 if (!rinfo->asleep) {
1132 if (rinfo->is_mobility) {
1133 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1134 OUTPLL(VCLK_ECP_CNTL,
1135 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1136 }
1137
1138 /* Make sure we are on first palette */
1139 if (rinfo->has_CRTC2) {
1140 dac_cntl2 = INREG(DAC_CNTL2);
1141 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1142 OUTREG(DAC_CNTL2, dac_cntl2);
1143 }
1144 }
1145
1146 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1147
1148 if (!rinfo->asleep && rinfo->is_mobility)
1149 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1150
1151 return rc;
1152}
1153
1154static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1155{
1156 struct radeonfb_info *rinfo = info->par;
1157 u16 *red, *green, *blue, *transp;
1158 u32 dac_cntl2, vclk_cntl = 0;
1159 int i, start, rc = 0;
1160
1161 if (!rinfo->asleep) {
1162 if (rinfo->is_mobility) {
1163 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1164 OUTPLL(VCLK_ECP_CNTL,
1165 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1166 }
1167
1168 /* Make sure we are on first palette */
1169 if (rinfo->has_CRTC2) {
1170 dac_cntl2 = INREG(DAC_CNTL2);
1171 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1172 OUTREG(DAC_CNTL2, dac_cntl2);
1173 }
1174 }
1175
1176 red = cmap->red;
1177 green = cmap->green;
1178 blue = cmap->blue;
1179 transp = cmap->transp;
1180 start = cmap->start;
1181
1182 for (i = 0; i < cmap->len; i++) {
1183 u_int hred, hgreen, hblue, htransp = 0xffff;
1184
1185 hred = *red++;
1186 hgreen = *green++;
1187 hblue = *blue++;
1188 if (transp)
1189 htransp = *transp++;
1190 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1191 rinfo);
1192 if (rc)
1193 break;
1194 }
1195
1196 if (!rinfo->asleep && rinfo->is_mobility)
1197 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1198
1199 return rc;
1200}
1da177e4
LT		 1201
1202static void radeon_save_state (struct radeonfb_info *rinfo,
1203 struct radeon_regs *save)
1204{
1205 /* CRTC regs */
1206 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1207 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1208 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1209 save->dac_cntl = INREG(DAC_CNTL);
1210 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1211 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1212 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1213 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1214 save->crtc_pitch = INREG(CRTC_PITCH);
1215 save->surface_cntl = INREG(SURFACE_CNTL);
1216
1217 /* FP regs */
1218 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1219 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1220 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1221 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1222 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1223 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1224 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1225 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1226 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1227 save->tmds_crc = INREG(TMDS_CRC);
1228 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1229 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1230
1231 /* PLL regs */
1232 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1233 radeon_pll_errata_after_index(rinfo);
1234 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1235 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1236}
1237
1238
1239static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1240{
1241 int i;
1242
1da177e4
LT		 1243 /* Workaround from XFree */
1244 if (rinfo->is_mobility) {
1245 /* A temporal workaround for the occational blanking on certain laptop
1246 * panels. This appears to related to the PLL divider registers
1247 * (fail to lock?). It occurs even when all dividers are the same
1248 * with their old settings. In this case we really don't need to
1249 * fiddle with PLL registers. By doing this we can avoid the blanking
1250 * problem with some panels.
1251 */
1252 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1253 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1254 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1255 /* We still have to force a switch to selected PPLL div thanks to
1256 * an XFree86 driver bug which will switch it away in some cases
1257 * even when using UseFDev */
1258 OUTREGP(CLOCK_CNTL_INDEX,
1259 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1260 ~PPLL_DIV_SEL_MASK);
1261 radeon_pll_errata_after_index(rinfo);
1262 radeon_pll_errata_after_data(rinfo);
1263 return;
1264 }
1265 }
1266
1267 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1268 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1269
1270 /* Reset PPLL & enable atomic update */
1271 OUTPLLP(PPLL_CNTL,
1272 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1273 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1274
1275 /* Switch to selected PPLL divider */
1276 OUTREGP(CLOCK_CNTL_INDEX,
1277 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1278 ~PPLL_DIV_SEL_MASK);
1279 radeon_pll_errata_after_index(rinfo);
1280 radeon_pll_errata_after_data(rinfo);
1281
1282 /* Set PPLL ref. div */
a6c0c37d 1283 if (IS_R300_VARIANT(rinfo) ||
1da177e4 1284 rinfo->family == CHIP_FAMILY_RS300 ||
a6c0c37d
BH		 1285 rinfo->family == CHIP_FAMILY_RS400 ||
1286 rinfo->family == CHIP_FAMILY_RS480) {
1da177e4
LT		 1287 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1288 /* When restoring console mode, use saved PPLL_REF_DIV
1289 * setting.
1290 */
1291 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1292 } else {
1293 /* R300 uses ref_div_acc field as real ref divider */
1294 OUTPLLP(PPLL_REF_DIV,
1295 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1296 ~R300_PPLL_REF_DIV_ACC_MASK);
1297 }
1298 } else
1299 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1300
1301 /* Set PPLL divider 3 & post divider*/
1302 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1303 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1304
1305 /* Write update */
1306 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1307 ;
1308 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1309
1310 /* Wait read update complete */
1311 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1312 the cause yet, but this workaround will mask the problem for now.
1313 Other chips usually will pass at the very first test, so the
1314 workaround shouldn't have any effect on them. */
1315 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1316 ;
1317
1318 OUTPLL(HTOTAL_CNTL, 0);
1319
1320 /* Clear reset & atomic update */
1321 OUTPLLP(PPLL_CNTL, 0,
1322 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1323
1324 /* We may want some locking ... oh well */
1325 radeon_msleep(5);
1326
1327 /* Switch back VCLK source to PPLL */
1328 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1329}
1330
1331/*
1332 * Timer function for delayed LVDS panel power up/down
1333 */
1334static void radeon_lvds_timer_func(unsigned long data)
1335{
1336 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1337
b1ee26ba 1338 radeon_engine_idle(rinfo);
1da177e4
LT		 1339
1340 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1341}
1342
1343/*
1344 * Apply a video mode. This will apply the whole register set, including
1345 * the PLL registers, to the card
1346 */
1347void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1348 int regs_only)
1349{
1350 int i;
1351 int primary_mon = PRIMARY_MONITOR(rinfo);
1352
1353 if (nomodeset)
1354 return;
1355
b1ee26ba
BH		 1356 radeon_engine_idle(rinfo);
1357
1da177e4
LT		 1358 if (!regs_only)
1359 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1360
1da177e4
LT		 1361 for (i=0; i<10; i++)
1362 OUTREG(common_regs[i].reg, common_regs[i].val);
1363
1364 /* Apply surface registers */
1365 for (i=0; i<8; i++) {
1366 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1367 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1368 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1369 }
1370
1371 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1372 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1373 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1374 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1375 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1376 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1377 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1378 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1379 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1380 OUTREG(CRTC_OFFSET, 0);
1381 OUTREG(CRTC_OFFSET_CNTL, 0);
1382 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1383 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1384
1385 radeon_write_pll_regs(rinfo, mode);
1386
1387 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1da177e4
LT		 1388 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1389 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1390 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1391 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1392 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1393 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1394 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1395 OUTREG(TMDS_CRC, mode->tmds_crc);
1396 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1397 }
1398
1399 if (!regs_only)
1400 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1401
1da177e4
LT		 1402 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1403
1404 return;
1405}
1406
1407/*
1408 * Calculate the PLL values for a given mode
1409 */
1410static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1411 unsigned long freq)
1412{
1413 const struct {
1414 int divider;
1415 int bitvalue;
1416 } *post_div,
1417 post_divs[] = {
1418 { 1, 0 },
1419 { 2, 1 },
1420 { 4, 2 },
1421 { 8, 3 },
1422 { 3, 4 },
1423 { 16, 5 },
1424 { 6, 6 },
1425 { 12, 7 },
1426 { 0, 0 },
1427 };
1428 int fb_div, pll_output_freq = 0;
1429 int uses_dvo = 0;
1430
1431 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1432 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1433 * recent than an r(v)100...
1434 */
1435#if 1
1436 /* XXX I had reports of flicker happening with the cinema display
1437 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1438 * this case. This could just be a bandwidth calculation issue, I
1439 * haven't implemented the bandwidth code yet, but in the meantime,
1440 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1441 * I haven't seen a case were were absolutely needed an odd PLL
1442 * divider. I'll find a better fix once I have more infos on the
1443 * real cause of the problem.
1444 */
1445 while (rinfo->has_CRTC2) {
1446 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1447 u32 disp_output_cntl;
1448 int source;
1449
1450 /* FP2 path not enabled */
1451 if ((fp2_gen_cntl & FP2_ON) == 0)
1452 break;
1453 /* Not all chip revs have the same format for this register,
1454 * extract the source selection
1455 */
a6c0c37d 1456 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1da177e4
LT		 1457 source = (fp2_gen_cntl >> 10) & 0x3;
1458 /* sourced from transform unit, check for transform unit
1459 * own source
1460 */
1461 if (source == 3) {
1462 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1463 source = (disp_output_cntl >> 12) & 0x3;
1464 }
1465 } else
1466 source = (fp2_gen_cntl >> 13) & 0x1;
1467 /* sourced from CRTC2 -> exit */
1468 if (source == 1)
1469 break;
1470
1471 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1472 uses_dvo = 1;
1473 break;
1474 }
1475#else
1476 uses_dvo = 1;
1477#endif
1478 if (freq > rinfo->pll.ppll_max)
1479 freq = rinfo->pll.ppll_max;
1480 if (freq*12 < rinfo->pll.ppll_min)
1481 freq = rinfo->pll.ppll_min / 12;
bc3bf466 1482 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1da177e4
LT		 1483 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1484
1485 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1486 pll_output_freq = post_div->divider * freq;
1487 /* If we output to the DVO port (external TMDS), we don't allow an
1488 * odd PLL divider as those aren't supported on this path
1489 */
1490 if (uses_dvo && (post_div->divider & 1))
1491 continue;
1492 if (pll_output_freq >= rinfo->pll.ppll_min &&
1493 pll_output_freq <= rinfo->pll.ppll_max)
1494 break;
1495 }
1496
1497 /* If we fall through the bottom, try the "default value"
1498 given by the terminal post_div->bitvalue */
1499 if ( !post_div->divider ) {
1500 post_div = &post_divs[post_div->bitvalue];
1501 pll_output_freq = post_div->divider * freq;
1502 }
bc3bf466 1503 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1da177e4
LT		 1504 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1505 pll_output_freq);
1506
1507 /* If we fall through the bottom, try the "default value"
1508 given by the terminal post_div->bitvalue */
1509 if ( !post_div->divider ) {
1510 post_div = &post_divs[post_div->bitvalue];
1511 pll_output_freq = post_div->divider * freq;
1512 }
bc3bf466 1513 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1da177e4
LT		 1514 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1515 pll_output_freq);
1516
1517 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1518 rinfo->pll.ref_clk);
1519 regs->ppll_ref_div = rinfo->pll.ref_div;
1520 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1521
bc3bf466
JD		 1522 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1523 pr_debug("fb_div = 0x%x\n", fb_div);
1524 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1da177e4
LT		 1525}
1526
1527static int radeonfb_set_par(struct fb_info *info)
1528{
1529 struct radeonfb_info *rinfo = info->par;
1530 struct fb_var_screeninfo *mode = &info->var;
1531 struct radeon_regs *newmode;
1532 int hTotal, vTotal, hSyncStart, hSyncEnd,
1533 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1534 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1535 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1536 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1537 int i, freq;
1538 int format = 0;
1539 int nopllcalc = 0;
1540 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1541 int primary_mon = PRIMARY_MONITOR(rinfo);
1542 int depth = var_to_depth(mode);
1543 int use_rmx = 0;
1544
1545 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1546 if (!newmode)
1547 return -ENOMEM;
1548
1549 /* We always want engine to be idle on a mode switch, even
1550 * if we won't actually change the mode
1551 */
b1ee26ba 1552 radeon_engine_idle(rinfo);
1da177e4
LT		 1553
1554 hSyncStart = mode->xres + mode->right_margin;
1555 hSyncEnd = hSyncStart + mode->hsync_len;
1556 hTotal = hSyncEnd + mode->left_margin;
1557
1558 vSyncStart = mode->yres + mode->lower_margin;
1559 vSyncEnd = vSyncStart + mode->vsync_len;
1560 vTotal = vSyncEnd + mode->upper_margin;
1561 pixClock = mode->pixclock;
1562
1563 sync = mode->sync;
1564 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1565 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1566
1567 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1568 if (rinfo->panel_info.xres < mode->xres)
1569 mode->xres = rinfo->panel_info.xres;
1570 if (rinfo->panel_info.yres < mode->yres)
1571 mode->yres = rinfo->panel_info.yres;
1572
1573 hTotal = mode->xres + rinfo->panel_info.hblank;
1574 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1575 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1576
1577 vTotal = mode->yres + rinfo->panel_info.vblank;
1578 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1579 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1580
1581 h_sync_pol = !rinfo->panel_info.hAct_high;
1582 v_sync_pol = !rinfo->panel_info.vAct_high;
1583
1584 pixClock = 100000000 / rinfo->panel_info.clock;
1585
1586 if (rinfo->panel_info.use_bios_dividers) {
1587 nopllcalc = 1;
1588 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1589 (rinfo->panel_info.post_divider << 16);
1590 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1591 }
1592 }
1593 dotClock = 1000000000 / pixClock;
1594 freq = dotClock / 10; /* x100 */
1595
bc3bf466 1596 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1da177e4 1597 hSyncStart, hSyncEnd, hTotal);
bc3bf466 1598 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1da177e4
LT		 1599 vSyncStart, vSyncEnd, vTotal);
1600
1601 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1602 vsync_wid = vSyncEnd - vSyncStart;
1603 if (hsync_wid == 0)
1604 hsync_wid = 1;
1605 else if (hsync_wid > 0x3f) /* max */
1606 hsync_wid = 0x3f;
1607
1608 if (vsync_wid == 0)
1609 vsync_wid = 1;
1610 else if (vsync_wid > 0x1f) /* max */
1611 vsync_wid = 0x1f;
1612
1613 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1614 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1615
1616 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1617
1618 format = radeon_get_dstbpp(depth);
1619 bytpp = mode->bits_per_pixel >> 3;
1620
1621 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1622 hsync_fudge = hsync_fudge_fp[format-1];
1623 else
1624 hsync_fudge = hsync_adj_tab[format-1];
1625
1626 hsync_start = hSyncStart - 8 + hsync_fudge;
1627
1628 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1629 (format << 8);
1630
1631 /* Clear auto-center etc... */
1632 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1633 newmode->crtc_more_cntl &= 0xfffffff0;
1634
1635 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1636 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1637 if (mirror)
1638 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1639
1640 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1641 CRTC_INTERLACE_EN);
1642 } else {
1643 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1644 CRTC_CRT_ON;
1645 }
1646
1647 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1648 DAC_8BIT_EN;
1649
1650 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1651 (((mode->xres / 8) - 1) << 16));
1652
1653 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1654 (hsync_wid << 16) | (h_sync_pol << 23));
1655
1656 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1657 ((mode->yres - 1) << 16);
1658
1659 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1660 (vsync_wid << 16) | (v_sync_pol << 23));
1661
1662 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1663 /* We first calculate the engine pitch */
1664 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1665 & ~(0x3f)) >> 6;
1666
1667 /* Then, re-multiply it to get the CRTC pitch */
1668 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1669 } else
1670 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1671
1672 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1673
1674 /*
1675 * It looks like recent chips have a problem with SURFACE_CNTL,
1676 * setting SURF_TRANSLATION_DIS completely disables the
1677 * swapper as well, so we leave it unset now.
1678 */
1679 newmode->surface_cntl = 0;
1680
1681#if defined(__BIG_ENDIAN)
1682
1683 /* Setup swapping on both apertures, though we currently
1684 * only use aperture 0, enabling swapper on aperture 1
1685 * won't harm
1686 */
1687 switch (mode->bits_per_pixel) {
1688 case 16:
1689 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1690 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1691 break;
1692 case 24:
1693 case 32:
1694 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1695 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1696 break;
1697 }
1698#endif
1699
1700 /* Clear surface registers */
1701 for (i=0; i<8; i++) {
1702 newmode->surf_lower_bound[i] = 0;
1703 newmode->surf_upper_bound[i] = 0x1f;
1704 newmode->surf_info[i] = 0;
1705 }
1706
bc3bf466 1707 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1da177e4 1708 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
bc3bf466 1709 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1da177e4
LT		 1710 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1711
1712 rinfo->bpp = mode->bits_per_pixel;
1713 rinfo->depth = depth;
1714
bc3bf466
JD		 1715 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1716 pr_debug("freq = %lu\n", (unsigned long)freq);
1da177e4
LT		 1717
1718 /* We use PPLL_DIV_3 */
1719 newmode->clk_cntl_index = 0x300;
1720
1721 /* Calculate PPLL value if necessary */
1722 if (!nopllcalc)
1723 radeon_calc_pll_regs(rinfo, newmode, freq);
1724
1725 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1726
1727 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1728 unsigned int hRatio, vRatio;
1729
1730 if (mode->xres > rinfo->panel_info.xres)
1731 mode->xres = rinfo->panel_info.xres;
1732 if (mode->yres > rinfo->panel_info.yres)
1733 mode->yres = rinfo->panel_info.yres;
1734
1735 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1736 << HORZ_PANEL_SHIFT);
1737 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1738 << VERT_PANEL_SHIFT);
1739
1740 if (mode->xres != rinfo->panel_info.xres) {
1741 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1742 rinfo->panel_info.xres);
1743 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1744 (newmode->fp_horz_stretch &
1745 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1746 HORZ_AUTO_RATIO_INC)));
1747 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1748 HORZ_STRETCH_ENABLE);
1749 use_rmx = 1;
1750 }
1751 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1752
1753 if (mode->yres != rinfo->panel_info.yres) {
1754 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1755 rinfo->panel_info.yres);
1756 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1757 (newmode->fp_vert_stretch &
1758 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1759 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1760 VERT_STRETCH_ENABLE);
1761 use_rmx = 1;
1762 }
1763 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1764
1765 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1766 ~(FP_SEL_CRTC2 |
1767 FP_RMX_HVSYNC_CONTROL_EN |
1768 FP_DFP_SYNC_SEL |
1769 FP_CRT_SYNC_SEL |
1770 FP_CRTC_LOCK_8DOT |
1771 FP_USE_SHADOW_EN |
1772 FP_CRTC_USE_SHADOW_VEND |
1773 FP_CRT_SYNC_ALT));
1774
1775 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1776 FP_CRTC_DONT_SHADOW_HEND |
1777 FP_PANEL_FORMAT);
1778
1779 if (IS_R300_VARIANT(rinfo) ||
1780 (rinfo->family == CHIP_FAMILY_R200)) {
1781 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1782 if (use_rmx)
1783 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1784 else
1785 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1786 } else
1787 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1788
1789 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1790 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1791 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1792 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1793
1794 if (primary_mon == MT_LCD) {
1795 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1796 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1797 } else {
1798 /* DFP */
1799 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1800 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1801 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1802 if (IS_R300_VARIANT(rinfo) ||
1803 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1804 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1805 else
1806 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1807 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1808 }
1809
1810 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1811 (((mode->xres / 8) - 1) << 16));
1812 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1813 ((mode->yres - 1) << 16);
1814 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1815 (hsync_wid << 16) | (h_sync_pol << 23));
1816 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1817 (vsync_wid << 16) | (v_sync_pol << 23));
1818 }
1819
1820 /* do it! */
1821 if (!rinfo->asleep) {
1822 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1823 radeon_write_mode (rinfo, newmode, 0);
1824 /* (re)initialize the engine */
1825 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1826 radeonfb_engine_init (rinfo);
1827 }
1828 /* Update fix */
1829 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1830 info->fix.line_length = rinfo->pitch*64;
1831 else
1832 info->fix.line_length = mode->xres_virtual
1833 * ((mode->bits_per_pixel + 1) / 8);
1834 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1835 : FB_VISUAL_DIRECTCOLOR;
1836
1837#ifdef CONFIG_BOOTX_TEXT
1838 /* Update debug text engine */
1839 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1840 rinfo->depth, info->fix.line_length);
1841#endif
1842
1843 kfree(newmode);
1844 return 0;
1845}
1846
1da177e4
LT		 1847static struct fb_ops radeonfb_ops = {
1848 .owner = THIS_MODULE,
1849 .fb_check_var = radeonfb_check_var,
1850 .fb_set_par = radeonfb_set_par,
1851 .fb_setcolreg = radeonfb_setcolreg,
71494376 1852 .fb_setcmap = radeonfb_setcmap,
1da177e4
LT		 1853 .fb_pan_display = radeonfb_pan_display,
1854 .fb_blank = radeonfb_blank,
1855 .fb_ioctl = radeonfb_ioctl,
1856 .fb_sync = radeonfb_sync,
1857 .fb_fillrect = radeonfb_fillrect,
1858 .fb_copyarea = radeonfb_copyarea,
1859 .fb_imageblit = radeonfb_imageblit,
1da177e4
LT		 1860};
1861
1862
1863static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1864{
1865 struct fb_info *info = rinfo->info;
1866
1867 info->par = rinfo;
1868 info->pseudo_palette = rinfo->pseudo_palette;
1869 info->flags = FBINFO_DEFAULT
b1ee26ba 1870 | FBINFO_HWACCEL_IMAGEBLIT
1da177e4
LT		 1871 | FBINFO_HWACCEL_COPYAREA
1872 | FBINFO_HWACCEL_FILLRECT
1873 | FBINFO_HWACCEL_XPAN
1874 | FBINFO_HWACCEL_YPAN;
1875 info->fbops = &radeonfb_ops;
1876 info->screen_base = rinfo->fb_base;
1877 info->screen_size = rinfo->mapped_vram;
c4c6fa98 1878
1da177e4
LT		 1879 /* Fill fix common fields */
1880 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1881 info->fix.smem_start = rinfo->fb_base_phys;
1882 info->fix.smem_len = rinfo->video_ram;
1883 info->fix.type = FB_TYPE_PACKED_PIXELS;
1884 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1885 info->fix.xpanstep = 8;
1886 info->fix.ypanstep = 1;
1887 info->fix.ywrapstep = 0;
1888 info->fix.type_aux = 0;
1889 info->fix.mmio_start = rinfo->mmio_base_phys;
1890 info->fix.mmio_len = RADEON_REGSIZE;
1891 info->fix.accel = FB_ACCEL_ATI_RADEON;
1892
c4c6fa98 1893 /* Allocate colormap */
1da177e4
LT		 1894 fb_alloc_cmap(&info->cmap, 256, 0);
1895
c4c6fa98
BH		 1896 /* Setup pixmap used for acceleration */
1897#define PIXMAP_SIZE (2048 * 4)
1898
1899 info->pixmap.addr = kmalloc(PIXMAP_SIZE, GFP_KERNEL);
1900 if (!info->pixmap.addr) {
1901 printk(KERN_ERR "radeonfb: Failed to allocate pixmap !\n");
1902 noaccel = 1;
1903 goto bail;
1904 }
1905 info->pixmap.size = PIXMAP_SIZE;
1906 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1907 info->pixmap.scan_align = 4;
1908 info->pixmap.buf_align = 4;
1909 info->pixmap.access_align = 32;
1910
1911bail:
1da177e4
LT		 1912 if (noaccel)
1913 info->flags |= FBINFO_HWACCEL_DISABLED;
1914
1915 return 0;
1916}
1917
1da177e4
LT		 1918/*
1919 * This reconfigure the card's internal memory map. In theory, we'd like
1920 * to setup the card's memory at the same address as it's PCI bus address,
1921 * and the AGP aperture right after that so that system RAM on 32 bits
1922 * machines at least, is directly accessible. However, doing so would
1923 * conflict with the current XFree drivers...
1924 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1925 * on the proper way to set this up and duplicate this here. In the meantime,
1926 * I put the card's memory at 0 in card space and AGP at some random high
1927 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1928 */
1929#ifdef CONFIG_PPC_OF
1930#undef SET_MC_FB_FROM_APERTURE
1931static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1932{
1933 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1934 u32 save_crtc_ext_cntl;
1935 u32 aper_base, aper_size;
1936 u32 agp_base;
1937
1938 /* First, we disable display to avoid interfering */
1939 if (rinfo->has_CRTC2) {
1940 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1941 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1942 }
1943 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1944 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1945
1946 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1947 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1948 mdelay(100);
1949
1950 aper_base = INREG(CONFIG_APER_0_BASE);
1951 aper_size = INREG(CONFIG_APER_SIZE);
1952
1953#ifdef SET_MC_FB_FROM_APERTURE
1954 /* Set framebuffer to be at the same address as set in PCI BAR */
1955 OUTREG(MC_FB_LOCATION,
1956 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1957 rinfo->fb_local_base = aper_base;
1958#else
1959 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1960 rinfo->fb_local_base = 0;
1961#endif
1962 agp_base = aper_base + aper_size;
1963 if (agp_base & 0xf0000000)
1964 agp_base = (aper_base | 0x0fffffff) + 1;
1965
1966 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1967 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1968 * always the case on PPCs afaik.
1969 */
1970#ifdef SET_MC_FB_FROM_APERTURE
1971 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1972#else
1973 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1974#endif
1975
1976 /* Fixup the display base addresses & engine offsets while we
1977 * are at it as well
1978 */
1979#ifdef SET_MC_FB_FROM_APERTURE
1980 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1981 if (rinfo->has_CRTC2)
1982 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1983 OUTREG(OV0_BASE_ADDR, aper_base);
1984#else
1985 OUTREG(DISPLAY_BASE_ADDR, 0);
1986 if (rinfo->has_CRTC2)
1987 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1988 OUTREG(OV0_BASE_ADDR, 0);
1989#endif
1990 mdelay(100);
1991
1992 /* Restore display settings */
1993 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1994 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1995 if (rinfo->has_CRTC2)
1996 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1997
bc3bf466 1998 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1da177e4
LT		 1999 aper_base,
2000 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2001 0xffff0000 | (agp_base >> 16));
2002}
2003#endif /* CONFIG_PPC_OF */
2004
2005
2006static void radeon_identify_vram(struct radeonfb_info *rinfo)
2007{
2008 u32 tmp;
2009
2010 /* framebuffer size */
2011 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2012 (rinfo->family == CHIP_FAMILY_RS200) ||
dd144713 2013 (rinfo->family == CHIP_FAMILY_RS300) ||
0b693eaf 2014 (rinfo->family == CHIP_FAMILY_RC410) ||
a6c0c37d 2015 (rinfo->family == CHIP_FAMILY_RS400) ||
dd144713 2016 (rinfo->family == CHIP_FAMILY_RS480) ) {
1da177e4
LT		 2017 u32 tom = INREG(NB_TOM);
2018 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2019
1da177e4
LT		 2020 OUTREG(MC_FB_LOCATION, tom);
2021 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2022 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2023 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2024
2025 /* This is supposed to fix the crtc2 noise problem. */
2026 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2027
2028 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2029 (rinfo->family == CHIP_FAMILY_RS200)) {
2030 /* This is to workaround the asic bug for RMX, some versions
2031 of BIOS dosen't have this register initialized correctly.
2032 */
2033 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2034 ~CRTC_H_CUTOFF_ACTIVE_EN);
2035 }
2036 } else {
2037 tmp = INREG(CONFIG_MEMSIZE);
2038 }
2039
2040 /* mem size is bits [28:0], mask off the rest */
2041 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2042
2043 /*
2044 * Hack to get around some busted production M6's
2045 * reporting no ram
2046 */
2047 if (rinfo->video_ram == 0) {
2048 switch (rinfo->pdev->device) {
2049 case PCI_CHIP_RADEON_LY:
2050 case PCI_CHIP_RADEON_LZ:
2051 rinfo->video_ram = 8192 * 1024;
2052 break;
2053 default:
2054 break;
2055 }
2056 }
2057
2058
2059 /*
2060 * Now try to identify VRAM type
2061 */
2062 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2063 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2064 rinfo->vram_ddr = 1;
2065 else
2066 rinfo->vram_ddr = 0;
2067
2068 tmp = INREG(MEM_CNTL);
2069 if (IS_R300_VARIANT(rinfo)) {
2070 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2071 switch (tmp) {
2072 case 0: rinfo->vram_width = 64; break;
2073 case 1: rinfo->vram_width = 128; break;
2074 case 2: rinfo->vram_width = 256; break;
2075 default: rinfo->vram_width = 128; break;
2076 }
2077 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2078 (rinfo->family == CHIP_FAMILY_RS100) ||
2079 (rinfo->family == CHIP_FAMILY_RS200)){
2080 if (tmp & RV100_MEM_HALF_MODE)
2081 rinfo->vram_width = 32;
2082 else
2083 rinfo->vram_width = 64;
2084 } else {
2085 if (tmp & MEM_NUM_CHANNELS_MASK)
2086 rinfo->vram_width = 128;
2087 else
2088 rinfo->vram_width = 64;
2089 }
2090
2091 /* This may not be correct, as some cards can have half of channel disabled
2092 * ToDo: identify these cases
2093 */
2094
bc3bf466 2095 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
1da177e4
LT		 2096 pci_name(rinfo->pdev),
2097 rinfo->video_ram / 1024,
2098 rinfo->vram_ddr ? "DDR" : "SDRAM",
2099 rinfo->vram_width);
2100}
2101
2102/*
2103 * Sysfs
2104 */
2105
2106static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2107{
a882ef47 2108 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
1da177e4
LT		 2109}
2110
2111
91a69029
ZR		 2112static ssize_t radeon_show_edid1(struct kobject *kobj,
2113 struct bin_attribute *bin_attr,
2114 char *buf, loff_t off, size_t count)
1da177e4
LT		 2115{
2116 struct device *dev = container_of(kobj, struct device, kobj);
2117 struct pci_dev *pdev = to_pci_dev(dev);
2118 struct fb_info *info = pci_get_drvdata(pdev);
2119 struct radeonfb_info *rinfo = info->par;
2120
2121 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2122}
2123
2124
91a69029
ZR		 2125static ssize_t radeon_show_edid2(struct kobject *kobj,
2126 struct bin_attribute *bin_attr,
2127 char *buf, loff_t off, size_t count)
1da177e4
LT		 2128{
2129 struct device *dev = container_of(kobj, struct device, kobj);
2130 struct pci_dev *pdev = to_pci_dev(dev);
2131 struct fb_info *info = pci_get_drvdata(pdev);
2132 struct radeonfb_info *rinfo = info->par;
2133
2134 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2135}
2136
2137static struct bin_attribute edid1_attr = {
2138 .attr = {
2139 .name = "edid1",
1da177e4
LT		 2140 .mode = 0444,
2141 },
2142 .size = EDID_LENGTH,
2143 .read = radeon_show_edid1,
2144};
2145
2146static struct bin_attribute edid2_attr = {
2147 .attr = {
2148 .name = "edid2",
1da177e4
LT		 2149 .mode = 0444,
2150 },
2151 .size = EDID_LENGTH,
2152 .read = radeon_show_edid2,
2153};
2154
2155
246846fc 2156static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
1da177e4
LT		 2157 const struct pci_device_id *ent)
2158{
2159 struct fb_info *info;
2160 struct radeonfb_info *rinfo;
2161 int ret;
e7a18c9c 2162 unsigned char c1, c2;
fcea8030 2163 int err = 0;
1da177e4 2164
bc3bf466 2165 pr_debug("radeonfb_pci_register BEGIN\n");
1da177e4
LT		 2166
2167 /* Enable device in PCI config */
2168 ret = pci_enable_device(pdev);
2169 if (ret < 0) {
2170 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2171 pci_name(pdev));
2172 goto err_out;
2173 }
2174
2175 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2176 if (!info) {
2177 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2178 pci_name(pdev));
2179 ret = -ENOMEM;
2180 goto err_disable;
2181 }
2182 rinfo = info->par;
2183 rinfo->info = info;
2184 rinfo->pdev = pdev;
2185
2186 spin_lock_init(&rinfo->reg_lock);
2187 init_timer(&rinfo->lvds_timer);
2188 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2189 rinfo->lvds_timer.data = (unsigned long)rinfo;
2190
e7a18c9c
AH		 2191 c1 = ent->device >> 8;
2192 c2 = ent->device & 0xff;
2193 if (isprint(c1) && isprint(c2))
2194 snprintf(rinfo->name, sizeof(rinfo->name),
2195 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2196 else
2197 snprintf(rinfo->name, sizeof(rinfo->name),
2198 "ATI Radeon %x", ent->device & 0xffff);
2199
1da177e4
LT		 2200 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2201 rinfo->chipset = pdev->device;
2202 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2203 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2204 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2205
2206 /* Set base addrs */
2207 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2208 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2209
2210 /* request the mem regions */
5251bffc 2211 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
1da177e4 2212 if (ret < 0) {
5251bffc
DB		 2213 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2214 pci_name(rinfo->pdev));
1da177e4
LT		 2215 goto err_release_fb;
2216 }
2217
5251bffc
DB		 2218 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2219 if (ret < 0) {
2220 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2221 pci_name(rinfo->pdev));
2222 goto err_release_pci0;
2223 }
2224
1da177e4
LT		 2225 /* map the regions */
2226 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2227 if (!rinfo->mmio_base) {
5251bffc
DB		 2228 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2229 pci_name(rinfo->pdev));
1da177e4 2230 ret = -EIO;
5251bffc 2231 goto err_release_pci2;
1da177e4
LT		 2232 }
2233
2234 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2235
2236 /*
2237 * Check for errata
2238 */
2239 rinfo->errata = 0;
2240 if (rinfo->family == CHIP_FAMILY_R300 &&
2241 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2242 == CFG_ATI_REV_A11)
2243 rinfo->errata |= CHIP_ERRATA_R300_CG;
2244
2245 if (rinfo->family == CHIP_FAMILY_RV200 ||
2246 rinfo->family == CHIP_FAMILY_RS200)
2247 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2248
2249 if (rinfo->family == CHIP_FAMILY_RV100 ||
2250 rinfo->family == CHIP_FAMILY_RS100 ||
2251 rinfo->family == CHIP_FAMILY_RS200)
2252 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2253
9f47df26 2254#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4
LT		 2255 /* On PPC, we obtain the OF device-node pointer to the firmware
2256 * data for this chip
2257 */
2258 rinfo->of_node = pci_device_to_OF_node(pdev);
2259 if (rinfo->of_node == NULL)
2260 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2261 pci_name(rinfo->pdev));
2262
9f47df26
DM		 2263#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2264#ifdef CONFIG_PPC_OF
1da177e4
LT		 2265 /* On PPC, the firmware sets up a memory mapping that tends
2266 * to cause lockups when enabling the engine. We reconfigure
2267 * the card internal memory mappings properly
2268 */
2269 fixup_memory_mappings(rinfo);
2270#endif /* CONFIG_PPC_OF */
2271
2272 /* Get VRAM size and type */
2273 radeon_identify_vram(rinfo);
2274
2275 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2276
2277 do {
2278 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2279 rinfo->mapped_vram);
5e2daeb3
HH		 2280 } while (rinfo->fb_base == NULL &&
2281 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
1da177e4 2282
8d5f7b43
BH		 2283 if (rinfo->fb_base == NULL) {
2284 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2285 pci_name(rinfo->pdev));
1da177e4
LT		 2286 ret = -EIO;
2287 goto err_unmap_rom;
2288 }
2289
bc3bf466 2290 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
1da177e4
LT		 2291 rinfo->mapped_vram/1024);
2292
2293 /*
4a4efbde 2294 * Map the BIOS ROM if any and retrieve PLL parameters from
1da177e4
LT		 2295 * the BIOS. We skip that on mobility chips as the real panel
2296 * values we need aren't in the ROM but in the BIOS image in
2297 * memory. This is definitely not the best meacnism though,
2298 * we really need the arch code to tell us which is the "primary"
2299 * video adapter to use the memory image (or better, the arch
2300 * should provide us a copy of the BIOS image to shield us from
2301 * archs who would store that elsewhere and/or could initialize
2302 * more than one adapter during boot).
2303 */
2304 if (!rinfo->is_mobility)
2305 radeon_map_ROM(rinfo, pdev);
2306
2307 /*
2308 * On x86, the primary display on laptop may have it's BIOS
2309 * ROM elsewhere, try to locate it at the legacy memory hole.
2310 * We probably need to make sure this is the primary display,
2311 * but that is difficult without some arch support.
2312 */
2313#ifdef CONFIG_X86
2314 if (rinfo->bios_seg == NULL)
2315 radeon_find_mem_vbios(rinfo);
2316#endif
2317
2318 /* If both above failed, try the BIOS ROM again for mobility
2319 * chips
2320 */
2321 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2322 radeon_map_ROM(rinfo, pdev);
2323
2324 /* Get informations about the board's PLL */
2325 radeon_get_pllinfo(rinfo);
2326
2327#ifdef CONFIG_FB_RADEON_I2C
2328 /* Register I2C bus */
2329 radeon_create_i2c_busses(rinfo);
2330#endif
2331
2332 /* set all the vital stuff */
2333 radeon_set_fbinfo (rinfo);
2334
2335 /* Probe screen types */
2336 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2337
2338 /* Build mode list, check out panel native model */
2339 radeon_check_modes(rinfo, mode_option);
2340
2341 /* Register some sysfs stuff (should be done better) */
2342 if (rinfo->mon1_EDID)
fcea8030
TB		 2343 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2344 &edid1_attr);
1da177e4 2345 if (rinfo->mon2_EDID)
fcea8030
TB		 2346 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2347 &edid2_attr);
2348 if (err)
2349 pr_warning("%s() Creating sysfs files failed, continuing\n",
2350 __func__);
1da177e4
LT		 2351
2352 /* save current mode regs before we switch into the new one
2353 * so we can restore this upon __exit
2354 */
2355 radeon_save_state (rinfo, &rinfo->init_state);
2356 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2357
2358 /* Setup Power Management capabilities */
2359 if (default_dynclk < -1) {
2360 /* -2 is special: means ON on mobility chips and do not
2361 * change on others
2362 */
994aad25 2363 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
1da177e4 2364 } else
994aad25 2365 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
1da177e4
LT		 2366
2367 pci_set_drvdata(pdev, info);
2368
2369 /* Register with fbdev layer */
2370 ret = register_framebuffer(info);
2371 if (ret < 0) {
2372 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2373 pci_name(rinfo->pdev));
2374 goto err_unmap_fb;
2375 }
2376
2377#ifdef CONFIG_MTRR
2378 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2379 rinfo->video_ram,
2380 MTRR_TYPE_WRCOMB, 1);
2381#endif
2382
202d4e60
RP		 2383 if (backlight)
2384 radeonfb_bl_init(rinfo);
1da177e4
LT		 2385
2386 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2387
2388 if (rinfo->bios_seg)
2389 radeon_unmap_ROM(rinfo, pdev);
bc3bf466 2390 pr_debug("radeonfb_pci_register END\n");
1da177e4
LT		 2391
2392 return 0;
2393err_unmap_fb:
2394 iounmap(rinfo->fb_base);
2395err_unmap_rom:
2396 kfree(rinfo->mon1_EDID);
2397 kfree(rinfo->mon2_EDID);
2398 if (rinfo->mon1_modedb)
2399 fb_destroy_modedb(rinfo->mon1_modedb);
2400 fb_dealloc_cmap(&info->cmap);
2401#ifdef CONFIG_FB_RADEON_I2C
2402 radeon_delete_i2c_busses(rinfo);
2403#endif
2404 if (rinfo->bios_seg)
2405 radeon_unmap_ROM(rinfo, pdev);
2406 iounmap(rinfo->mmio_base);
5251bffc
DB		 2407err_release_pci2:
2408 pci_release_region(pdev, 2);
2409err_release_pci0:
2410 pci_release_region(pdev, 0);
1da177e4 2411err_release_fb:
5251bffc 2412 framebuffer_release(info);
1da177e4 2413err_disable:
1da177e4
LT		 2414err_out:
2415 return ret;
2416}
2417
2418
2419
2420static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2421{
2422 struct fb_info *info = pci_get_drvdata(pdev);
2423 struct radeonfb_info *rinfo = info->par;
2424
2425 if (!rinfo)
2426 return;
5474c120 2427
1da177e4
LT		 2428 radeonfb_pm_exit(rinfo);
2429
3ca34fcb
JS		 2430 if (rinfo->mon1_EDID)
2431 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2432 if (rinfo->mon2_EDID)
2433 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2434
1da177e4
LT		 2435#if 0
2436 /* restore original state
2437 *
2438 * Doesn't quite work yet, I suspect if we come from a legacy
2439 * VGA mode (or worse, text mode), we need to do some VGA black
2440 * magic here that I know nothing about. --BenH
2441 */
2442 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2443 #endif
2444
2445 del_timer_sync(&rinfo->lvds_timer);
2446
2447#ifdef CONFIG_MTRR
2448 if (rinfo->mtrr_hdl >= 0)
2449 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2450#endif
2451
2452 unregister_framebuffer(info);
2453
37ce69a5
RP		 2454 radeonfb_bl_exit(rinfo);
2455
1da177e4
LT		 2456 iounmap(rinfo->mmio_base);
2457 iounmap(rinfo->fb_base);
2458
5251bffc
DB		 2459 pci_release_region(pdev, 2);
2460 pci_release_region(pdev, 0);
1da177e4
LT		 2461
2462 kfree(rinfo->mon1_EDID);
2463 kfree(rinfo->mon2_EDID);
2464 if (rinfo->mon1_modedb)
2465 fb_destroy_modedb(rinfo->mon1_modedb);
2466#ifdef CONFIG_FB_RADEON_I2C
2467 radeon_delete_i2c_busses(rinfo);
2468#endif
2469 fb_dealloc_cmap(&info->cmap);
2470 framebuffer_release(info);
1da177e4
LT		 2471}
2472
2473
2474static struct pci_driver radeonfb_driver = {
2475 .name = "radeonfb",
2476 .id_table = radeonfb_pci_table,
2477 .probe = radeonfb_pci_register,
2478 .remove = __devexit_p(radeonfb_pci_unregister),
2479#ifdef CONFIG_PM
2480 .suspend = radeonfb_pci_suspend,
2481 .resume = radeonfb_pci_resume,
2482#endif /* CONFIG_PM */
2483};
2484
2485#ifndef MODULE
2486static int __init radeonfb_setup (char *options)
2487{
2488 char *this_opt;
2489
2490 if (!options || !*options)
2491 return 0;
2492
2493 while ((this_opt = strsep (&options, ",")) != NULL) {
2494 if (!*this_opt)
2495 continue;
2496
2497 if (!strncmp(this_opt, "noaccel", 7)) {
2498 noaccel = 1;
2499 } else if (!strncmp(this_opt, "mirror", 6)) {
2500 mirror = 1;
2501 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2502 force_dfp = 1;
2503 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2504 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
202d4e60
RP		 2505 } else if (!strncmp(this_opt, "backlight:", 10)) {
2506 backlight = simple_strtoul(this_opt+10, NULL, 0);
1da177e4
LT		 2507#ifdef CONFIG_MTRR
2508 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2509 nomtrr = 1;
2510#endif
2511 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2512 nomodeset = 1;
2513 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2514 force_measure_pll = 1;
2515 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2516 ignore_edid = 1;
994aad25
VB		 2517#if defined(CONFIG_PM) && defined(CONFIG_X86)
2518 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2519 force_sleep = 1;
2520 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2521 ignore_devlist = 1;
2522#endif
1da177e4
LT		 2523 } else
2524 mode_option = this_opt;
2525 }
2526 return 0;
2527}
2528#endif /* MODULE */
2529
2530static int __init radeonfb_init (void)
2531{
2532#ifndef MODULE
2533 char *option = NULL;
2534
2535 if (fb_get_options("radeonfb", &option))
2536 return -ENODEV;
2537 radeonfb_setup(option);
2538#endif
2539 return pci_register_driver (&radeonfb_driver);
2540}
2541
2542
2543static void __exit radeonfb_exit (void)
2544{
2545 pci_unregister_driver (&radeonfb_driver);
2546}
2547
2548module_init(radeonfb_init);
2549module_exit(radeonfb_exit);
2550
2551MODULE_AUTHOR("Ani Joshi");
2552MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2553MODULE_LICENSE("GPL");
2554module_param(noaccel, bool, 0);
2555module_param(default_dynclk, int, 0);
2556MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2557MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2558module_param(nomodeset, bool, 0);
2559MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2560module_param(mirror, bool, 0);
2561MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2562module_param(force_dfp, bool, 0);
2563MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2564module_param(ignore_edid, bool, 0);
2565MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2566module_param(monitor_layout, charp, 0);
2567MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2568module_param(force_measure_pll, bool, 0);
2569MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2570#ifdef CONFIG_MTRR
2571module_param(nomtrr, bool, 0);
2572MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2573#endif
2574module_param(panel_yres, int, 0);
2575MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2576module_param(mode_option, charp, 0);
2577MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
994aad25
VB		 2578#if defined(CONFIG_PM) && defined(CONFIG_X86)
2579module_param(force_sleep, bool, 0);
2580MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2581module_param(ignore_devlist, bool, 0);
2582MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2583#endif
Linux 6.x block layer and io_uring tree(s)