projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
xhci: Don't enable/disable RWE on bus suspend/resume.
[linux-2.6-block.git] / drivers / usb / host / xhci.h
CommitLineData
74c68741
SS		 1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __LINUX_XHCI_HCD_H
24#define __LINUX_XHCI_HCD_H
25
26#include <linux/usb.h>
7f84eef0 27#include <linux/timer.h>
8e595a5d 28#include <linux/kernel.h>
27729aad 29#include <linux/usb/hcd.h>
74c68741 30
74c68741
SS		 31/* Code sharing between pci-quirks and xhci hcd */
32#include "xhci-ext-caps.h"
c41136b0 33#include "pci-quirks.h"
74c68741
SS		 34
35/* xHCI PCI Configuration Registers */
36#define XHCI_SBRN_OFFSET (0x60)
37
66d4eadd
SS		 38/* Max number of USB devices for any host controller - limit in section 6.1 */
39#define MAX_HC_SLOTS 256
0f2a7930
SS		 40/* Section 5.3.3 - MaxPorts */
41#define MAX_HC_PORTS 127
66d4eadd 42
74c68741
SS		 43/*
44 * xHCI register interface.
45 * This corresponds to the eXtensible Host Controller Interface (xHCI)
46 * Revision 0.95 specification
74c68741
SS		 47 */
48
49/**
50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
51 * @hc_capbase: length of the capabilities register and HC version number
52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
55 * @hcc_params: HCCPARAMS - Capability Parameters
56 * @db_off: DBOFF - Doorbell array offset
57 * @run_regs_off: RTSOFF - Runtime register space offset
58 */
59struct xhci_cap_regs {
28ccd296
ME		 60 __le32 hc_capbase;
61 __le32 hcs_params1;
62 __le32 hcs_params2;
63 __le32 hcs_params3;
64 __le32 hcc_params;
65 __le32 db_off;
66 __le32 run_regs_off;
74c68741 67 /* Reserved up to (CAPLENGTH - 0x1C) */
98441973 68};
74c68741
SS		 69
70/* hc_capbase bitmasks */
71/* bits 7:0 - how long is the Capabilities register */
72#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73/* bits 31:16 */
74#define HC_VERSION(p) (((p) >> 16) & 0xffff)
75
76/* HCSPARAMS1 - hcs_params1 - bitmasks */
77/* bits 0:7, Max Device Slots */
78#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
79#define HCS_SLOTS_MASK 0xff
80/* bits 8:18, Max Interrupters */
81#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
82/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
83#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84
85/* HCSPARAMS2 - hcs_params2 - bitmasks */
86/* bits 0:3, frames or uframes that SW needs to queue transactions
87 * ahead of the HW to meet periodic deadlines */
88#define HCS_IST(p) (((p) >> 0) & 0xf)
89/* bits 4:7, max number of Event Ring segments */
90#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
91/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
92/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
254c80a3 93#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
74c68741
SS		 94
95/* HCSPARAMS3 - hcs_params3 - bitmasks */
96/* bits 0:7, Max U1 to U0 latency for the roothub ports */
97#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
98/* bits 16:31, Max U2 to U0 latency for the roothub ports */
99#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100
101/* HCCPARAMS - hcc_params - bitmasks */
102/* true: HC can use 64-bit address pointers */
103#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
104/* true: HC can do bandwidth negotiation */
105#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
106/* true: HC uses 64-byte Device Context structures
107 * FIXME 64-byte context structures aren't supported yet.
108 */
109#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
110/* true: HC has port power switches */
111#define HCC_PPC(p) ((p) & (1 << 3))
112/* true: HC has port indicators */
113#define HCS_INDICATOR(p) ((p) & (1 << 4))
114/* true: HC has Light HC Reset Capability */
115#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
116/* true: HC supports latency tolerance messaging */
117#define HCC_LTC(p) ((p) & (1 << 6))
118/* true: no secondary Stream ID Support */
119#define HCC_NSS(p) ((p) & (1 << 7))
120/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
8df75f42 121#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
74c68741
SS		 122/* Extended Capabilities pointer from PCI base - section 5.3.6 */
123#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125/* db_off bitmask - bits 0:1 reserved */
126#define DBOFF_MASK (~0x3)
127
128/* run_regs_off bitmask - bits 0:4 reserved */
129#define RTSOFF_MASK (~0x1f)
130
131
132/* Number of registers per port */
133#define NUM_PORT_REGS 4
134
b6e76371
MN		 135#define PORTSC 0
136#define PORTPMSC 1
137#define PORTLI 2
138#define PORTHLPMC 3
139
74c68741
SS		 140/**
141 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
142 * @command: USBCMD - xHC command register
143 * @status: USBSTS - xHC status register
144 * @page_size: This indicates the page size that the host controller
145 * supports. If bit n is set, the HC supports a page size
146 * of 2^(n+12), up to a 128MB page size.
147 * 4K is the minimum page size.
148 * @cmd_ring: CRP - 64-bit Command Ring Pointer
149 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
150 * @config_reg: CONFIG - Configure Register
151 * @port_status_base: PORTSCn - base address for Port Status and Control
152 * Each port has a Port Status and Control register,
153 * followed by a Port Power Management Status and Control
154 * register, a Port Link Info register, and a reserved
155 * register.
156 * @port_power_base: PORTPMSCn - base address for
157 * Port Power Management Status and Control
158 * @port_link_base: PORTLIn - base address for Port Link Info (current
159 * Link PM state and control) for USB 2.1 and USB 3.0
160 * devices.
161 */
162struct xhci_op_regs {
28ccd296
ME		 163 __le32 command;
164 __le32 status;
165 __le32 page_size;
166 __le32 reserved1;
167 __le32 reserved2;
168 __le32 dev_notification;
169 __le64 cmd_ring;
74c68741 170 /* rsvd: offset 0x20-2F */
28ccd296
ME		 171 __le32 reserved3[4];
172 __le64 dcbaa_ptr;
173 __le32 config_reg;
74c68741 174 /* rsvd: offset 0x3C-3FF */
28ccd296 175 __le32 reserved4[241];
74c68741 176 /* port 1 registers, which serve as a base address for other ports */
28ccd296
ME		 177 __le32 port_status_base;
178 __le32 port_power_base;
179 __le32 port_link_base;
180 __le32 reserved5;
74c68741 181 /* registers for ports 2-255 */
28ccd296 182 __le32 reserved6[NUM_PORT_REGS*254];
98441973 183};
74c68741
SS		 184
185/* USBCMD - USB command - command bitmasks */
186/* start/stop HC execution - do not write unless HC is halted*/
187#define CMD_RUN XHCI_CMD_RUN
188/* Reset HC - resets internal HC state machine and all registers (except
189 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
190 * The xHCI driver must reinitialize the xHC after setting this bit.
191 */
192#define CMD_RESET (1 << 1)
193/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
194#define CMD_EIE XHCI_CMD_EIE
195/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
196#define CMD_HSEIE XHCI_CMD_HSEIE
197/* bits 4:6 are reserved (and should be preserved on writes). */
198/* light reset (port status stays unchanged) - reset completed when this is 0 */
199#define CMD_LRESET (1 << 7)
5535b1d5 200/* host controller save/restore state. */
74c68741
SS		 201#define CMD_CSS (1 << 8)
202#define CMD_CRS (1 << 9)
203/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
204#define CMD_EWE XHCI_CMD_EWE
205/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
206 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
207 * '0' means the xHC can power it off if all ports are in the disconnect,
208 * disabled, or powered-off state.
209 */
210#define CMD_PM_INDEX (1 << 11)
211/* bits 12:31 are reserved (and should be preserved on writes). */
212
4e833c0b 213/* IMAN - Interrupt Management Register */
f8264340
DT		 214#define IMAN_IE (1 << 1)
215#define IMAN_IP (1 << 0)
4e833c0b 216
74c68741
SS		 217/* USBSTS - USB status - status bitmasks */
218/* HC not running - set to 1 when run/stop bit is cleared. */
219#define STS_HALT XHCI_STS_HALT
220/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
221#define STS_FATAL (1 << 2)
222/* event interrupt - clear this prior to clearing any IP flags in IR set*/
223#define STS_EINT (1 << 3)
224/* port change detect */
225#define STS_PORT (1 << 4)
226/* bits 5:7 reserved and zeroed */
227/* save state status - '1' means xHC is saving state */
228#define STS_SAVE (1 << 8)
229/* restore state status - '1' means xHC is restoring state */
230#define STS_RESTORE (1 << 9)
231/* true: save or restore error */
232#define STS_SRE (1 << 10)
233/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
234#define STS_CNR XHCI_STS_CNR
235/* true: internal Host Controller Error - SW needs to reset and reinitialize */
236#define STS_HCE (1 << 12)
237/* bits 13:31 reserved and should be preserved */
238
239/*
240 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
241 * Generate a device notification event when the HC sees a transaction with a
242 * notification type that matches a bit set in this bit field.
243 */
244#define DEV_NOTE_MASK (0xffff)
5a6c2f3f 245#define ENABLE_DEV_NOTE(x) (1 << (x))
74c68741
SS		 246/* Most of the device notification types should only be used for debug.
247 * SW does need to pay attention to function wake notifications.
248 */
249#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
250
0ebbab37
SS		 251/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
252/* bit 0 is the command ring cycle state */
253/* stop ring operation after completion of the currently executing command */
254#define CMD_RING_PAUSE (1 << 1)
255/* stop ring immediately - abort the currently executing command */
256#define CMD_RING_ABORT (1 << 2)
257/* true: command ring is running */
258#define CMD_RING_RUNNING (1 << 3)
259/* bits 4:5 reserved and should be preserved */
260/* Command Ring pointer - bit mask for the lower 32 bits. */
8e595a5d 261#define CMD_RING_RSVD_BITS (0x3f)
0ebbab37 262
74c68741
SS		 263/* CONFIG - Configure Register - config_reg bitmasks */
264/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
265#define MAX_DEVS(p) ((p) & 0xff)
266/* bits 8:31 - reserved and should be preserved */
267
268/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
269/* true: device connected */
270#define PORT_CONNECT (1 << 0)
271/* true: port enabled */
272#define PORT_PE (1 << 1)
273/* bit 2 reserved and zeroed */
274/* true: port has an over-current condition */
275#define PORT_OC (1 << 3)
276/* true: port reset signaling asserted */
277#define PORT_RESET (1 << 4)
278/* Port Link State - bits 5:8
279 * A read gives the current link PM state of the port,
280 * a write with Link State Write Strobe set sets the link state.
281 */
be88fe4f
AX		 282#define PORT_PLS_MASK (0xf << 5)
283#define XDEV_U0 (0x0 << 5)
9574323c 284#define XDEV_U2 (0x2 << 5)
be88fe4f
AX		 285#define XDEV_U3 (0x3 << 5)
286#define XDEV_RESUME (0xf << 5)
74c68741
SS		 287/* true: port has power (see HCC_PPC) */
288#define PORT_POWER (1 << 9)
289/* bits 10:13 indicate device speed:
290 * 0 - undefined speed - port hasn't be initialized by a reset yet
291 * 1 - full speed
292 * 2 - low speed
293 * 3 - high speed
294 * 4 - super speed
295 * 5-15 reserved
296 */
3ffbba95
SS		 297#define DEV_SPEED_MASK (0xf << 10)
298#define XDEV_FS (0x1 << 10)
299#define XDEV_LS (0x2 << 10)
300#define XDEV_HS (0x3 << 10)
301#define XDEV_SS (0x4 << 10)
74c68741 302#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
3ffbba95
SS		 303#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
304#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
305#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
306#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
307/* Bits 20:23 in the Slot Context are the speed for the device */
308#define SLOT_SPEED_FS (XDEV_FS << 10)
309#define SLOT_SPEED_LS (XDEV_LS << 10)
310#define SLOT_SPEED_HS (XDEV_HS << 10)
311#define SLOT_SPEED_SS (XDEV_SS << 10)
74c68741
SS		 312/* Port Indicator Control */
313#define PORT_LED_OFF (0 << 14)
314#define PORT_LED_AMBER (1 << 14)
315#define PORT_LED_GREEN (2 << 14)
316#define PORT_LED_MASK (3 << 14)
317/* Port Link State Write Strobe - set this when changing link state */
318#define PORT_LINK_STROBE (1 << 16)
319/* true: connect status change */
320#define PORT_CSC (1 << 17)
321/* true: port enable change */
322#define PORT_PEC (1 << 18)
323/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
324 * into an enabled state, and the device into the default state. A "warm" reset
325 * also resets the link, forcing the device through the link training sequence.
326 * SW can also look at the Port Reset register to see when warm reset is done.
327 */
328#define PORT_WRC (1 << 19)
329/* true: over-current change */
330#define PORT_OCC (1 << 20)
331/* true: reset change - 1 to 0 transition of PORT_RESET */
332#define PORT_RC (1 << 21)
333/* port link status change - set on some port link state transitions:
334 * Transition Reason
335 * ------------------------------------------------------------------------------
336 * - U3 to Resume Wakeup signaling from a device
337 * - Resume to Recovery to U0 USB 3.0 device resume
338 * - Resume to U0 USB 2.0 device resume
339 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
340 * - U3 to U0 Software resume of USB 2.0 device complete
341 * - U2 to U0 L1 resume of USB 2.1 device complete
342 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
343 * - U0 to disabled L1 entry error with USB 2.1 device
344 * - Any state to inactive Error on USB 3.0 port
345 */
346#define PORT_PLC (1 << 22)
347/* port configure error change - port failed to configure its link partner */
348#define PORT_CEC (1 << 23)
8bea2bd3
SL		 349/* Cold Attach Status - xHC can set this bit to report device attached during
350 * Sx state. Warm port reset should be perfomed to clear this bit and move port
351 * to connected state.
352 */
353#define PORT_CAS (1 << 24)
74c68741
SS		 354/* wake on connect (enable) */
355#define PORT_WKCONN_E (1 << 25)
356/* wake on disconnect (enable) */
357#define PORT_WKDISC_E (1 << 26)
358/* wake on over-current (enable) */
359#define PORT_WKOC_E (1 << 27)
360/* bits 28:29 reserved */
361/* true: device is removable - for USB 3.0 roothub emulation */
362#define PORT_DEV_REMOVE (1 << 30)
363/* Initiate a warm port reset - complete when PORT_WRC is '1' */
364#define PORT_WR (1 << 31)
365
22e04870
DC		 366/* We mark duplicate entries with -1 */
367#define DUPLICATE_ENTRY ((u8)(-1))
368
74c68741
SS		 369/* Port Power Management Status and Control - port_power_base bitmasks */
370/* Inactivity timer value for transitions into U1, in microseconds.
371 * Timeout can be up to 127us. 0xFF means an infinite timeout.
372 */
373#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
797b0ca5 374#define PORT_U1_TIMEOUT_MASK 0xff
74c68741
SS		 375/* Inactivity timer value for transitions into U2 */
376#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
797b0ca5 377#define PORT_U2_TIMEOUT_MASK (0xff << 8)
74c68741
SS		 378/* Bits 24:31 for port testing */
379
9777e3ce 380/* USB2 Protocol PORTSPMSC */
9574323c
AX		 381#define PORT_L1S_MASK 7
382#define PORT_L1S_SUCCESS 1
383#define PORT_RWE (1 << 3)
384#define PORT_HIRD(p) (((p) & 0xf) << 4)
65580b43 385#define PORT_HIRD_MASK (0xf << 4)
9574323c 386#define PORT_L1DS(p) (((p) & 0xff) << 8)
65580b43 387#define PORT_HLE (1 << 16)
74c68741 388
a558ccdc
MN		 389
390/* USB2 Protocol PORTHLPMC */
391#define PORT_HIRDM(p)((p) & 3)
392#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
393#define PORT_BESLD(p)(((p) & 0xf) << 10)
394
395/* use 512 microseconds as USB2 LPM L1 default timeout. */
396#define XHCI_L1_TIMEOUT 512
397
398/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
399 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
400 * by other operating systems.
401 *
402 * XHCI 1.0 errata 8/14/12 Table 13 notes:
403 * "Software should choose xHC BESL/BESLD field values that do not violate a
404 * device's resume latency requirements,
405 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
406 * or not program values < '4' if BLC = '0' and a BESL device is attached.
407 */
408#define XHCI_DEFAULT_BESL 4
409
74c68741 410/**
98441973 411 * struct xhci_intr_reg - Interrupt Register Set
74c68741
SS		 412 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
413 * interrupts and check for pending interrupts.
414 * @irq_control: IMOD - Interrupt Moderation Register.
415 * Used to throttle interrupts.
416 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
417 * @erst_base: ERST base address.
418 * @erst_dequeue: Event ring dequeue pointer.
419 *
420 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
421 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
422 * multiple segments of the same size. The HC places events on the ring and
423 * "updates the Cycle bit in the TRBs to indicate to software the current
424 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
425 * updates the dequeue pointer.
426 */
98441973 427struct xhci_intr_reg {
28ccd296
ME		 428 __le32 irq_pending;
429 __le32 irq_control;
430 __le32 erst_size;
431 __le32 rsvd;
432 __le64 erst_base;
433 __le64 erst_dequeue;
98441973 434};
74c68741 435
66d4eadd 436/* irq_pending bitmasks */
74c68741 437#define ER_IRQ_PENDING(p) ((p) & 0x1)
66d4eadd 438/* bits 2:31 need to be preserved */
7f84eef0 439/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
66d4eadd
SS		 440#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
441#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
442#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
443
444/* irq_control bitmasks */
445/* Minimum interval between interrupts (in 250ns intervals). The interval
446 * between interrupts will be longer if there are no events on the event ring.
447 * Default is 4000 (1 ms).
448 */
449#define ER_IRQ_INTERVAL_MASK (0xffff)
450/* Counter used to count down the time to the next interrupt - HW use only */
451#define ER_IRQ_COUNTER_MASK (0xffff << 16)
452
453/* erst_size bitmasks */
74c68741 454/* Preserve bits 16:31 of erst_size */
66d4eadd
SS		 455#define ERST_SIZE_MASK (0xffff << 16)
456
457/* erst_dequeue bitmasks */
458/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
459 * where the current dequeue pointer lies. This is an optional HW hint.
460 */
461#define ERST_DESI_MASK (0x7)
462/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
463 * a work queue (or delayed service routine)?
464 */
465#define ERST_EHB (1 << 3)
0ebbab37 466#define ERST_PTR_MASK (0xf)
74c68741
SS		 467
468/**
469 * struct xhci_run_regs
470 * @microframe_index:
471 * MFINDEX - current microframe number
472 *
473 * Section 5.5 Host Controller Runtime Registers:
474 * "Software should read and write these registers using only Dword (32 bit)
475 * or larger accesses"
476 */
477struct xhci_run_regs {
28ccd296
ME		 478 __le32 microframe_index;
479 __le32 rsvd[7];
98441973
SS		 480 struct xhci_intr_reg ir_set[128];
481};
74c68741 482
0ebbab37
SS		 483/**
484 * struct doorbell_array
485 *
50d64676
MW		 486 * Bits 0 - 7: Endpoint target
487 * Bits 8 - 15: RsvdZ
488 * Bits 16 - 31: Stream ID
489 *
0ebbab37
SS		 490 * Section 5.6
491 */
492struct xhci_doorbell_array {
28ccd296 493 __le32 doorbell[256];
98441973 494};
0ebbab37 495
50d64676
MW		 496#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
497#define DB_VALUE_HOST 0x00000000
0ebbab37 498
da6699ce
SS		 499/**
500 * struct xhci_protocol_caps
501 * @revision: major revision, minor revision, capability ID,
502 * and next capability pointer.
503 * @name_string: Four ASCII characters to say which spec this xHC
504 * follows, typically "USB ".
505 * @port_info: Port offset, count, and protocol-defined information.
506 */
507struct xhci_protocol_caps {
508 u32 revision;
509 u32 name_string;
510 u32 port_info;
511};
512
513#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
514#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
515#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
516
d115b048
JY		 517/**
518 * struct xhci_container_ctx
519 * @type: Type of context. Used to calculated offsets to contained contexts.
520 * @size: Size of the context data
521 * @bytes: The raw context data given to HW
522 * @dma: dma address of the bytes
523 *
524 * Represents either a Device or Input context. Holds a pointer to the raw
525 * memory used for the context (bytes) and dma address of it (dma).
526 */
527struct xhci_container_ctx {
528 unsigned type;
529#define XHCI_CTX_TYPE_DEVICE 0x1
530#define XHCI_CTX_TYPE_INPUT 0x2
531
532 int size;
533
534 u8 *bytes;
535 dma_addr_t dma;
536};
537
a74588f9
SS		 538/**
539 * struct xhci_slot_ctx
540 * @dev_info: Route string, device speed, hub info, and last valid endpoint
541 * @dev_info2: Max exit latency for device number, root hub port number
542 * @tt_info: tt_info is used to construct split transaction tokens
543 * @dev_state: slot state and device address
544 *
545 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
546 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
547 * reserved at the end of the slot context for HC internal use.
548 */
549struct xhci_slot_ctx {
28ccd296
ME		 550 __le32 dev_info;
551 __le32 dev_info2;
552 __le32 tt_info;
553 __le32 dev_state;
a74588f9 554 /* offset 0x10 to 0x1f reserved for HC internal use */
28ccd296 555 __le32 reserved[4];
98441973 556};
a74588f9
SS		 557
558/* dev_info bitmasks */
559/* Route String - 0:19 */
560#define ROUTE_STRING_MASK (0xfffff)
561/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
562#define DEV_SPEED (0xf << 20)
563/* bit 24 reserved */
564/* Is this LS/FS device connected through a HS hub? - bit 25 */
565#define DEV_MTT (0x1 << 25)
566/* Set if the device is a hub - bit 26 */
567#define DEV_HUB (0x1 << 26)
568/* Index of the last valid endpoint context in this device context - 27:31 */
3ffbba95
SS		 569#define LAST_CTX_MASK (0x1f << 27)
570#define LAST_CTX(p) ((p) << 27)
571#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
3ffbba95
SS		 572#define SLOT_FLAG (1 << 0)
573#define EP0_FLAG (1 << 1)
a74588f9
SS		 574
575/* dev_info2 bitmasks */
576/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
577#define MAX_EXIT (0xffff)
578/* Root hub port number that is needed to access the USB device */
3ffbba95 579#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
be88fe4f 580#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
ac1c1b7f
SS		 581/* Maximum number of ports under a hub device */
582#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
a74588f9
SS		 583
584/* tt_info bitmasks */
585/*
586 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
587 * The Slot ID of the hub that isolates the high speed signaling from
588 * this low or full-speed device. '0' if attached to root hub port.
589 */
590#define TT_SLOT (0xff)
591/*
592 * The number of the downstream facing port of the high-speed hub
593 * '0' if the device is not low or full speed.
594 */
595#define TT_PORT (0xff << 8)
ac1c1b7f 596#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
a74588f9
SS		 597
598/* dev_state bitmasks */
599/* USB device address - assigned by the HC */
3ffbba95 600#define DEV_ADDR_MASK (0xff)
a74588f9
SS		 601/* bits 8:26 reserved */
602/* Slot state */
603#define SLOT_STATE (0x1f << 27)
ae636747 604#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
a74588f9 605
e2b02177
ML		 606#define SLOT_STATE_DISABLED 0
607#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
608#define SLOT_STATE_DEFAULT 1
609#define SLOT_STATE_ADDRESSED 2
610#define SLOT_STATE_CONFIGURED 3
a74588f9
SS		 611
612/**
613 * struct xhci_ep_ctx
614 * @ep_info: endpoint state, streams, mult, and interval information.
615 * @ep_info2: information on endpoint type, max packet size, max burst size,
616 * error count, and whether the HC will force an event for all
617 * transactions.
3ffbba95
SS		 618 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
619 * defines one stream, this points to the endpoint transfer ring.
620 * Otherwise, it points to a stream context array, which has a
621 * ring pointer for each flow.
622 * @tx_info:
623 * Average TRB lengths for the endpoint ring and
624 * max payload within an Endpoint Service Interval Time (ESIT).
a74588f9
SS		 625 *
626 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
627 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
628 * reserved at the end of the endpoint context for HC internal use.
629 */
630struct xhci_ep_ctx {
28ccd296
ME		 631 __le32 ep_info;
632 __le32 ep_info2;
633 __le64 deq;
634 __le32 tx_info;
a74588f9 635 /* offset 0x14 - 0x1f reserved for HC internal use */
28ccd296 636 __le32 reserved[3];
98441973 637};
a74588f9
SS		 638
639/* ep_info bitmasks */
640/*
641 * Endpoint State - bits 0:2
642 * 0 - disabled
643 * 1 - running
644 * 2 - halted due to halt condition - ok to manipulate endpoint ring
645 * 3 - stopped
646 * 4 - TRB error
647 * 5-7 - reserved
648 */
d0e96f5a
SS		 649#define EP_STATE_MASK (0xf)
650#define EP_STATE_DISABLED 0
651#define EP_STATE_RUNNING 1
652#define EP_STATE_HALTED 2
653#define EP_STATE_STOPPED 3
654#define EP_STATE_ERROR 4
a74588f9 655/* Mult - Max number of burtst within an interval, in EP companion desc. */
5a6c2f3f 656#define EP_MULT(p) (((p) & 0x3) << 8)
9af5d71d 657#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
a74588f9
SS		 658/* bits 10:14 are Max Primary Streams */
659/* bit 15 is Linear Stream Array */
660/* Interval - period between requests to an endpoint - 125u increments. */
5a6c2f3f 661#define EP_INTERVAL(p) (((p) & 0xff) << 16)
624defa1 662#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
9af5d71d 663#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
8df75f42
SS		 664#define EP_MAXPSTREAMS_MASK (0x1f << 10)
665#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
666/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
667#define EP_HAS_LSA (1 << 15)
a74588f9
SS		 668
669/* ep_info2 bitmasks */
670/*
671 * Force Event - generate transfer events for all TRBs for this endpoint
672 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
673 */
674#define FORCE_EVENT (0x1)
675#define ERROR_COUNT(p) (((p) & 0x3) << 1)
82d1009f 676#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
a74588f9
SS		 677#define EP_TYPE(p) ((p) << 3)
678#define ISOC_OUT_EP 1
679#define BULK_OUT_EP 2
680#define INT_OUT_EP 3
681#define CTRL_EP 4
682#define ISOC_IN_EP 5
683#define BULK_IN_EP 6
684#define INT_IN_EP 7
685/* bit 6 reserved */
686/* bit 7 is Host Initiate Disable - for disabling stream selection */
687#define MAX_BURST(p) (((p)&0xff) << 8)
9af5d71d 688#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
a74588f9 689#define MAX_PACKET(p) (((p)&0xffff) << 16)
2d3f1fac
SS		 690#define MAX_PACKET_MASK (0xffff << 16)
691#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
a74588f9 692
dc07c91b
AX		 693/* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
694 * USB2.0 spec 9.6.6.
695 */
696#define GET_MAX_PACKET(p) ((p) & 0x7ff)
697
9238f25d
SS		 698/* tx_info bitmasks */
699#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
700#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
9af5d71d 701#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
9238f25d 702
bf161e85
SS		 703/* deq bitmasks */
704#define EP_CTX_CYCLE_MASK (1 << 0)
705
a74588f9
SS		 706
707/**
d115b048
JY		 708 * struct xhci_input_control_context
709 * Input control context; see section 6.2.5.
a74588f9
SS		 710 *
711 * @drop_context: set the bit of the endpoint context you want to disable
712 * @add_context: set the bit of the endpoint context you want to enable
713 */
d115b048 714struct xhci_input_control_ctx {
28ccd296
ME		 715 __le32 drop_flags;
716 __le32 add_flags;
717 __le32 rsvd2[6];
98441973 718};
a74588f9 719
9af5d71d
SS		 720#define EP_IS_ADDED(ctrl_ctx, i) \
721 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
722#define EP_IS_DROPPED(ctrl_ctx, i) \
723 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
724
913a8a34
SS		 725/* Represents everything that is needed to issue a command on the command ring.
726 * It's useful to pre-allocate these for commands that cannot fail due to
727 * out-of-memory errors, like freeing streams.
728 */
729struct xhci_command {
730 /* Input context for changing device state */
731 struct xhci_container_ctx *in_ctx;
732 u32 status;
733 /* If completion is null, no one is waiting on this command
734 * and the structure can be freed after the command completes.
735 */
736 struct completion *completion;
737 union xhci_trb *command_trb;
738 struct list_head cmd_list;
739};
740
a74588f9
SS		 741/* drop context bitmasks */
742#define DROP_EP(x) (0x1 << x)
743/* add context bitmasks */
744#define ADD_EP(x) (0x1 << x)
745
8df75f42
SS		 746struct xhci_stream_ctx {
747 /* 64-bit stream ring address, cycle state, and stream type */
28ccd296 748 __le64 stream_ring;
8df75f42 749 /* offset 0x14 - 0x1f reserved for HC internal use */
28ccd296 750 __le32 reserved[2];
8df75f42
SS		 751};
752
753/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
754#define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
755/* Secondary stream array type, dequeue pointer is to a transfer ring */
756#define SCT_SEC_TR 0
757/* Primary stream array type, dequeue pointer is to a transfer ring */
758#define SCT_PRI_TR 1
759/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
760#define SCT_SSA_8 2
761#define SCT_SSA_16 3
762#define SCT_SSA_32 4
763#define SCT_SSA_64 5
764#define SCT_SSA_128 6
765#define SCT_SSA_256 7
766
767/* Assume no secondary streams for now */
768struct xhci_stream_info {
769 struct xhci_ring **stream_rings;
770 /* Number of streams, including stream 0 (which drivers can't use) */
771 unsigned int num_streams;
772 /* The stream context array may be bigger than
773 * the number of streams the driver asked for
774 */
775 struct xhci_stream_ctx *stream_ctx_array;
776 unsigned int num_stream_ctxs;
777 dma_addr_t ctx_array_dma;
778 /* For mapping physical TRB addresses to segments in stream rings */
779 struct radix_tree_root trb_address_map;
780 struct xhci_command *free_streams_command;
781};
782
783#define SMALL_STREAM_ARRAY_SIZE 256
784#define MEDIUM_STREAM_ARRAY_SIZE 1024
785
9af5d71d
SS		 786/* Some Intel xHCI host controllers need software to keep track of the bus
787 * bandwidth. Keep track of endpoint info here. Each root port is allocated
788 * the full bus bandwidth. We must also treat TTs (including each port under a
789 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
790 * (DMI) also limits the total bandwidth (across all domains) that can be used.
791 */
792struct xhci_bw_info {
170c0263 793 /* ep_interval is zero-based */
9af5d71d 794 unsigned int ep_interval;
170c0263 795 /* mult and num_packets are one-based */
9af5d71d
SS		 796 unsigned int mult;
797 unsigned int num_packets;
798 unsigned int max_packet_size;
799 unsigned int max_esit_payload;
800 unsigned int type;
801};
802
c29eea62
SS		 803/* "Block" sizes in bytes the hardware uses for different device speeds.
804 * The logic in this part of the hardware limits the number of bits the hardware
805 * can use, so must represent bandwidth in a less precise manner to mimic what
806 * the scheduler hardware computes.
807 */
808#define FS_BLOCK 1
809#define HS_BLOCK 4
810#define SS_BLOCK 16
811#define DMI_BLOCK 32
812
813/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
814 * with each byte transferred. SuperSpeed devices have an initial overhead to
815 * set up bursts. These are in blocks, see above. LS overhead has already been
816 * translated into FS blocks.
817 */
818#define DMI_OVERHEAD 8
819#define DMI_OVERHEAD_BURST 4
820#define SS_OVERHEAD 8
821#define SS_OVERHEAD_BURST 32
822#define HS_OVERHEAD 26
823#define FS_OVERHEAD 20
824#define LS_OVERHEAD 128
825/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
826 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
827 * of overhead associated with split transfers crossing microframe boundaries.
828 * 31 blocks is pure protocol overhead.
829 */
830#define TT_HS_OVERHEAD (31 + 94)
831#define TT_DMI_OVERHEAD (25 + 12)
832
833/* Bandwidth limits in blocks */
834#define FS_BW_LIMIT 1285
835#define TT_BW_LIMIT 1320
836#define HS_BW_LIMIT 1607
837#define SS_BW_LIMIT_IN 3906
838#define DMI_BW_LIMIT_IN 3906
839#define SS_BW_LIMIT_OUT 3906
840#define DMI_BW_LIMIT_OUT 3906
841
842/* Percentage of bus bandwidth reserved for non-periodic transfers */
843#define FS_BW_RESERVED 10
844#define HS_BW_RESERVED 20
2b698999 845#define SS_BW_RESERVED 10
c29eea62 846
63a0d9ab
SS		 847struct xhci_virt_ep {
848 struct xhci_ring *ring;
8df75f42
SS		 849 /* Related to endpoints that are configured to use stream IDs only */
850 struct xhci_stream_info *stream_info;
63a0d9ab
SS		 851 /* Temporary storage in case the configure endpoint command fails and we
852 * have to restore the device state to the previous state
853 */
854 struct xhci_ring *new_ring;
855 unsigned int ep_state;
856#define SET_DEQ_PENDING (1 << 0)
678539cf
SS		 857#define EP_HALTED (1 << 1) /* For stall handling */
858#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
8df75f42
SS		 859/* Transitioning the endpoint to using streams, don't enqueue URBs */
860#define EP_GETTING_STREAMS (1 << 3)
861#define EP_HAS_STREAMS (1 << 4)
862/* Transitioning the endpoint to not using streams, don't enqueue URBs */
863#define EP_GETTING_NO_STREAMS (1 << 5)
63a0d9ab
SS		 864 /* ---- Related to URB cancellation ---- */
865 struct list_head cancelled_td_list;
63a0d9ab
SS		 866 /* The TRB that was last reported in a stopped endpoint ring */
867 union xhci_trb *stopped_trb;
868 struct xhci_td *stopped_td;
e9df17eb 869 unsigned int stopped_stream;
6f5165cf
SS		 870 /* Watchdog timer for stop endpoint command to cancel URBs */
871 struct timer_list stop_cmd_timer;
872 int stop_cmds_pending;
873 struct xhci_hcd *xhci;
bf161e85
SS		 874 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
875 * command. We'll need to update the ring's dequeue segment and dequeue
876 * pointer after the command completes.
877 */
878 struct xhci_segment *queued_deq_seg;
879 union xhci_trb *queued_deq_ptr;
d18240db
AX		 880 /*
881 * Sometimes the xHC can not process isochronous endpoint ring quickly
882 * enough, and it will miss some isoc tds on the ring and generate
883 * a Missed Service Error Event.
884 * Set skip flag when receive a Missed Service Error Event and
885 * process the missed tds on the endpoint ring.
886 */
887 bool skip;
2e27980e 888 /* Bandwidth checking storage */
9af5d71d 889 struct xhci_bw_info bw_info;
2e27980e 890 struct list_head bw_endpoint_list;
63a0d9ab
SS		 891};
892
839c817c
SS		 893enum xhci_overhead_type {
894 LS_OVERHEAD_TYPE = 0,
895 FS_OVERHEAD_TYPE,
896 HS_OVERHEAD_TYPE,
897};
898
899struct xhci_interval_bw {
900 unsigned int num_packets;
2e27980e
SS		 901 /* Sorted by max packet size.
902 * Head of the list is the greatest max packet size.
903 */
904 struct list_head endpoints;
839c817c
SS		 905 /* How many endpoints of each speed are present. */
906 unsigned int overhead[3];
907};
908
909#define XHCI_MAX_INTERVAL 16
910
911struct xhci_interval_bw_table {
912 unsigned int interval0_esit_payload;
913 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
c29eea62
SS		 914 /* Includes reserved bandwidth for async endpoints */
915 unsigned int bw_used;
2b698999
SS		 916 unsigned int ss_bw_in;
917 unsigned int ss_bw_out;
839c817c
SS		 918};
919
920
3ffbba95 921struct xhci_virt_device {
64927730 922 struct usb_device *udev;
3ffbba95
SS		 923 /*
924 * Commands to the hardware are passed an "input context" that
925 * tells the hardware what to change in its data structures.
926 * The hardware will return changes in an "output context" that
927 * software must allocate for the hardware. We need to keep
928 * track of input and output contexts separately because
929 * these commands might fail and we don't trust the hardware.
930 */
d115b048 931 struct xhci_container_ctx *out_ctx;
3ffbba95 932 /* Used for addressing devices and configuration changes */
d115b048 933 struct xhci_container_ctx *in_ctx;
74f9fe21
SS		 934 /* Rings saved to ensure old alt settings can be re-instated */
935 struct xhci_ring **ring_cache;
936 int num_rings_cached;
c8d4af8e
AX		 937 /* Store xHC assigned device address */
938 int address;
74f9fe21 939#define XHCI_MAX_RINGS_CACHED 31
63a0d9ab 940 struct xhci_virt_ep eps[31];
f94e0186 941 struct completion cmd_completion;
3ffbba95
SS		 942 /* Status of the last command issued for this device */
943 u32 cmd_status;
913a8a34 944 struct list_head cmd_list;
fe30182c 945 u8 fake_port;
66381755 946 u8 real_port;
839c817c
SS		 947 struct xhci_interval_bw_table *bw_table;
948 struct xhci_tt_bw_info *tt_info;
3b3db026
SS		 949 /* The current max exit latency for the enabled USB3 link states. */
950 u16 current_mel;
839c817c
SS		 951};
952
953/*
954 * For each roothub, keep track of the bandwidth information for each periodic
955 * interval.
956 *
957 * If a high speed hub is attached to the roothub, each TT associated with that
958 * hub is a separate bandwidth domain. The interval information for the
959 * endpoints on the devices under that TT will appear in the TT structure.
960 */
961struct xhci_root_port_bw_info {
962 struct list_head tts;
963 unsigned int num_active_tts;
964 struct xhci_interval_bw_table bw_table;
965};
966
967struct xhci_tt_bw_info {
968 struct list_head tt_list;
969 int slot_id;
970 int ttport;
971 struct xhci_interval_bw_table bw_table;
972 int active_eps;
3ffbba95
SS		 973};
974
975
a74588f9
SS		 976/**
977 * struct xhci_device_context_array
978 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
979 */
980struct xhci_device_context_array {
981 /* 64-bit device addresses; we only write 32-bit addresses */
28ccd296 982 __le64 dev_context_ptrs[MAX_HC_SLOTS];
a74588f9
SS		 983 /* private xHCD pointers */
984 dma_addr_t dma;
98441973 985};
a74588f9
SS		 986/* TODO: write function to set the 64-bit device DMA address */
987/*
988 * TODO: change this to be dynamically sized at HC mem init time since the HC
989 * might not be able to handle the maximum number of devices possible.
990 */
991
992
0ebbab37
SS		 993struct xhci_transfer_event {
994 /* 64-bit buffer address, or immediate data */
28ccd296
ME		 995 __le64 buffer;
996 __le32 transfer_len;
0ebbab37 997 /* This field is interpreted differently based on the type of TRB */
28ccd296 998 __le32 flags;
98441973 999};
0ebbab37 1000
1c11a172
VG		 1001/* Transfer event TRB length bit mask */
1002/* bits 0:23 */
1003#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1004
d0e96f5a
SS		 1005/** Transfer Event bit fields **/
1006#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1007
0ebbab37
SS		 1008/* Completion Code - only applicable for some types of TRBs */
1009#define COMP_CODE_MASK (0xff << 24)
1010#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1011#define COMP_SUCCESS 1
1012/* Data Buffer Error */
1013#define COMP_DB_ERR 2
1014/* Babble Detected Error */
1015#define COMP_BABBLE 3
1016/* USB Transaction Error */
1017#define COMP_TX_ERR 4
1018/* TRB Error - some TRB field is invalid */
1019#define COMP_TRB_ERR 5
1020/* Stall Error - USB device is stalled */
1021#define COMP_STALL 6
1022/* Resource Error - HC doesn't have memory for that device configuration */
1023#define COMP_ENOMEM 7
1024/* Bandwidth Error - not enough room in schedule for this dev config */
1025#define COMP_BW_ERR 8
1026/* No Slots Available Error - HC ran out of device slots */
1027#define COMP_ENOSLOTS 9
1028/* Invalid Stream Type Error */
1029#define COMP_STREAM_ERR 10
1030/* Slot Not Enabled Error - doorbell rung for disabled device slot */
1031#define COMP_EBADSLT 11
1032/* Endpoint Not Enabled Error */
1033#define COMP_EBADEP 12
1034/* Short Packet */
1035#define COMP_SHORT_TX 13
1036/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1037#define COMP_UNDERRUN 14
1038/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1039#define COMP_OVERRUN 15
1040/* Virtual Function Event Ring Full Error */
1041#define COMP_VF_FULL 16
1042/* Parameter Error - Context parameter is invalid */
1043#define COMP_EINVAL 17
1044/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1045#define COMP_BW_OVER 18
1046/* Context State Error - illegal context state transition requested */
1047#define COMP_CTX_STATE 19
1048/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1049#define COMP_PING_ERR 20
1050/* Event Ring is full */
1051#define COMP_ER_FULL 21
f6ba6fe2
AH		 1052/* Incompatible Device Error */
1053#define COMP_DEV_ERR 22
0ebbab37
SS		 1054/* Missed Service Error - HC couldn't service an isoc ep within interval */
1055#define COMP_MISSED_INT 23
1056/* Successfully stopped command ring */
1057#define COMP_CMD_STOP 24
1058/* Successfully aborted current command and stopped command ring */
1059#define COMP_CMD_ABORT 25
1060/* Stopped - transfer was terminated by a stop endpoint command */
1061#define COMP_STOP 26
25985edc 1062/* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
0ebbab37
SS		 1063#define COMP_STOP_INVAL 27
1064/* Control Abort Error - Debug Capability - control pipe aborted */
1065#define COMP_DBG_ABORT 28
1bb73a88
AH		 1066/* Max Exit Latency Too Large Error */
1067#define COMP_MEL_ERR 29
1068/* TRB type 30 reserved */
0ebbab37
SS		 1069/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1070#define COMP_BUFF_OVER 31
1071/* Event Lost Error - xHC has an "internal event overrun condition" */
1072#define COMP_ISSUES 32
1073/* Undefined Error - reported when other error codes don't apply */
1074#define COMP_UNKNOWN 33
1075/* Invalid Stream ID Error */
1076#define COMP_STRID_ERR 34
1077/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
0ebbab37
SS		 1078#define COMP_2ND_BW_ERR 35
1079/* Split Transaction Error */
1080#define COMP_SPLIT_ERR 36
1081
1082struct xhci_link_trb {
1083 /* 64-bit segment pointer*/
28ccd296
ME		 1084 __le64 segment_ptr;
1085 __le32 intr_target;
1086 __le32 control;
98441973 1087};
0ebbab37
SS		 1088
1089/* control bitfields */
1090#define LINK_TOGGLE (0x1<<1)
1091
7f84eef0
SS		 1092/* Command completion event TRB */
1093struct xhci_event_cmd {
1094 /* Pointer to command TRB, or the value passed by the event data trb */
28ccd296
ME		 1095 __le64 cmd_trb;
1096 __le32 status;
1097 __le32 flags;
98441973 1098};
0ebbab37 1099
3ffbba95
SS		 1100/* flags bitmasks */
1101/* bits 16:23 are the virtual function ID */
1102/* bits 24:31 are the slot ID */
1103#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1104#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
0ebbab37 1105
ae636747
SS		 1106/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1107#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1108#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1109
be88fe4f
AX		 1110#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1111#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1112#define LAST_EP_INDEX 30
1113
e9df17eb
SS		 1114/* Set TR Dequeue Pointer command TRB fields */
1115#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1116#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1117
ae636747 1118
0f2a7930
SS		 1119/* Port Status Change Event TRB fields */
1120/* Port ID - bits 31:24 */
1121#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1122
0ebbab37
SS		 1123/* Normal TRB fields */
1124/* transfer_len bitmasks - bits 0:16 */
1125#define TRB_LEN(p) ((p) & 0x1ffff)
0ebbab37
SS		 1126/* Interrupter Target - which MSI-X vector to target the completion event at */
1127#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1128#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
5cd43e33 1129#define TRB_TBC(p) (((p) & 0x3) << 7)
b61d378f 1130#define TRB_TLBPC(p) (((p) & 0xf) << 16)
0ebbab37
SS		 1131
1132/* Cycle bit - indicates TRB ownership by HC or HCD */
1133#define TRB_CYCLE (1<<0)
1134/*
1135 * Force next event data TRB to be evaluated before task switch.
1136 * Used to pass OS data back after a TD completes.
1137 */
1138#define TRB_ENT (1<<1)
1139/* Interrupt on short packet */
1140#define TRB_ISP (1<<2)
1141/* Set PCIe no snoop attribute */
1142#define TRB_NO_SNOOP (1<<3)
1143/* Chain multiple TRBs into a TD */
1144#define TRB_CHAIN (1<<4)
1145/* Interrupt on completion */
1146#define TRB_IOC (1<<5)
1147/* The buffer pointer contains immediate data */
1148#define TRB_IDT (1<<6)
1149
ad106f29
AX		 1150/* Block Event Interrupt */
1151#define TRB_BEI (1<<9)
0ebbab37
SS		 1152
1153/* Control transfer TRB specific fields */
1154#define TRB_DIR_IN (1<<16)
b83cdc8f
AX		 1155#define TRB_TX_TYPE(p) ((p) << 16)
1156#define TRB_DATA_OUT 2
1157#define TRB_DATA_IN 3
0ebbab37 1158
04e51901
AX		 1159/* Isochronous TRB specific fields */
1160#define TRB_SIA (1<<31)
1161
7f84eef0 1162struct xhci_generic_trb {
28ccd296 1163 __le32 field[4];
98441973 1164};
7f84eef0
SS		 1165
1166union xhci_trb {
1167 struct xhci_link_trb link;
1168 struct xhci_transfer_event trans_event;
1169 struct xhci_event_cmd event_cmd;
1170 struct xhci_generic_trb generic;
1171};
1172
0ebbab37
SS		 1173/* TRB bit mask */
1174#define TRB_TYPE_BITMASK (0xfc00)
1175#define TRB_TYPE(p) ((p) << 10)
0238634d 1176#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
0ebbab37
SS		 1177/* TRB type IDs */
1178/* bulk, interrupt, isoc scatter/gather, and control data stage */
1179#define TRB_NORMAL 1
1180/* setup stage for control transfers */
1181#define TRB_SETUP 2
1182/* data stage for control transfers */
1183#define TRB_DATA 3
1184/* status stage for control transfers */
1185#define TRB_STATUS 4
1186/* isoc transfers */
1187#define TRB_ISOC 5
1188/* TRB for linking ring segments */
1189#define TRB_LINK 6
1190#define TRB_EVENT_DATA 7
1191/* Transfer Ring No-op (not for the command ring) */
1192#define TRB_TR_NOOP 8
1193/* Command TRBs */
1194/* Enable Slot Command */
1195#define TRB_ENABLE_SLOT 9
1196/* Disable Slot Command */
1197#define TRB_DISABLE_SLOT 10
1198/* Address Device Command */
1199#define TRB_ADDR_DEV 11
1200/* Configure Endpoint Command */
1201#define TRB_CONFIG_EP 12
1202/* Evaluate Context Command */
1203#define TRB_EVAL_CONTEXT 13
a1587d97
SS		 1204/* Reset Endpoint Command */
1205#define TRB_RESET_EP 14
0ebbab37
SS		 1206/* Stop Transfer Ring Command */
1207#define TRB_STOP_RING 15
1208/* Set Transfer Ring Dequeue Pointer Command */
1209#define TRB_SET_DEQ 16
1210/* Reset Device Command */
1211#define TRB_RESET_DEV 17
1212/* Force Event Command (opt) */
1213#define TRB_FORCE_EVENT 18
1214/* Negotiate Bandwidth Command (opt) */
1215#define TRB_NEG_BANDWIDTH 19
1216/* Set Latency Tolerance Value Command (opt) */
1217#define TRB_SET_LT 20
1218/* Get port bandwidth Command */
1219#define TRB_GET_BW 21
1220/* Force Header Command - generate a transaction or link management packet */
1221#define TRB_FORCE_HEADER 22
1222/* No-op Command - not for transfer rings */
1223#define TRB_CMD_NOOP 23
1224/* TRB IDs 24-31 reserved */
1225/* Event TRBS */
1226/* Transfer Event */
1227#define TRB_TRANSFER 32
1228/* Command Completion Event */
1229#define TRB_COMPLETION 33
1230/* Port Status Change Event */
1231#define TRB_PORT_STATUS 34
1232/* Bandwidth Request Event (opt) */
1233#define TRB_BANDWIDTH_EVENT 35
1234/* Doorbell Event (opt) */
1235#define TRB_DOORBELL 36
1236/* Host Controller Event */
1237#define TRB_HC_EVENT 37
1238/* Device Notification Event - device sent function wake notification */
1239#define TRB_DEV_NOTE 38
1240/* MFINDEX Wrap Event - microframe counter wrapped */
1241#define TRB_MFINDEX_WRAP 39
1242/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1243
0238634d
SS		 1244/* Nec vendor-specific command completion event. */
1245#define TRB_NEC_CMD_COMP 48
1246/* Get NEC firmware revision. */
1247#define TRB_NEC_GET_FW 49
1248
f5960b69
ME		 1249#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1250/* Above, but for __le32 types -- can avoid work by swapping constants: */
1251#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1252 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1253#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1254 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1255
0238634d
SS		 1256#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1257#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1258
0ebbab37
SS		 1259/*
1260 * TRBS_PER_SEGMENT must be a multiple of 4,
1261 * since the command ring is 64-byte aligned.
1262 * It must also be greater than 16.
1263 */
1264#define TRBS_PER_SEGMENT 64
913a8a34
SS		 1265/* Allow two commands + a link TRB, along with any reserved command TRBs */
1266#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
eb8ccd2b
DH		 1267#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1268#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
b10de142
SS		 1269/* TRB buffer pointers can't cross 64KB boundaries */
1270#define TRB_MAX_BUFF_SHIFT 16
1271#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
0ebbab37
SS		 1272
1273struct xhci_segment {
1274 union xhci_trb *trbs;
1275 /* private to HCD */
1276 struct xhci_segment *next;
1277 dma_addr_t dma;
98441973 1278};
0ebbab37 1279
ae636747
SS		 1280struct xhci_td {
1281 struct list_head td_list;
1282 struct list_head cancelled_td_list;
1283 struct urb *urb;
1284 struct xhci_segment *start_seg;
1285 union xhci_trb *first_trb;
1286 union xhci_trb *last_trb;
1287};
1288
6e4468b9
EF		 1289/* xHCI command default timeout value */
1290#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1291
b92cc66c
EF		 1292/* command descriptor */
1293struct xhci_cd {
1294 struct list_head cancel_cmd_list;
1295 struct xhci_command *command;
1296 union xhci_trb *cmd_trb;
1297};
1298
ac9d8fe7
SS		 1299struct xhci_dequeue_state {
1300 struct xhci_segment *new_deq_seg;
1301 union xhci_trb *new_deq_ptr;
1302 int new_cycle_state;
1303};
1304
3b72fca0
AX		 1305enum xhci_ring_type {
1306 TYPE_CTRL = 0,
1307 TYPE_ISOC,
1308 TYPE_BULK,
1309 TYPE_INTR,
1310 TYPE_STREAM,
1311 TYPE_COMMAND,
1312 TYPE_EVENT,
1313};
1314
0ebbab37
SS		 1315struct xhci_ring {
1316 struct xhci_segment *first_seg;
3fe4fe08 1317 struct xhci_segment *last_seg;
0ebbab37 1318 union xhci_trb *enqueue;
7f84eef0
SS		 1319 struct xhci_segment *enq_seg;
1320 unsigned int enq_updates;
0ebbab37 1321 union xhci_trb *dequeue;
7f84eef0
SS		 1322 struct xhci_segment *deq_seg;
1323 unsigned int deq_updates;
d0e96f5a 1324 struct list_head td_list;
0ebbab37
SS		 1325 /*
1326 * Write the cycle state into the TRB cycle field to give ownership of
1327 * the TRB to the host controller (if we are the producer), or to check
1328 * if we own the TRB (if we are the consumer). See section 4.9.1.
1329 */
1330 u32 cycle_state;
e9df17eb 1331 unsigned int stream_id;
3fe4fe08 1332 unsigned int num_segs;
b008df60
AX		 1333 unsigned int num_trbs_free;
1334 unsigned int num_trbs_free_temp;
3b72fca0 1335 enum xhci_ring_type type;
ad808333 1336 bool last_td_was_short;
0ebbab37
SS		 1337};
1338
1339struct xhci_erst_entry {
1340 /* 64-bit event ring segment address */
28ccd296
ME		 1341 __le64 seg_addr;
1342 __le32 seg_size;
0ebbab37 1343 /* Set to zero */
28ccd296 1344 __le32 rsvd;
98441973 1345};
0ebbab37
SS		 1346
1347struct xhci_erst {
1348 struct xhci_erst_entry *entries;
1349 unsigned int num_entries;
1350 /* xhci->event_ring keeps track of segment dma addresses */
1351 dma_addr_t erst_dma_addr;
1352 /* Num entries the ERST can contain */
1353 unsigned int erst_size;
1354};
1355
254c80a3
JY		 1356struct xhci_scratchpad {
1357 u64 *sp_array;
1358 dma_addr_t sp_dma;
1359 void **sp_buffers;
1360 dma_addr_t *sp_dma_buffers;
1361};
1362
8e51adcc
AX		 1363struct urb_priv {
1364 int length;
1365 int td_cnt;
1366 struct xhci_td *td[0];
1367};
1368
0ebbab37
SS		 1369/*
1370 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1371 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1372 * meaning 64 ring segments.
1373 * Initial allocated size of the ERST, in number of entries */
1374#define ERST_NUM_SEGS 1
1375/* Initial allocated size of the ERST, in number of entries */
1376#define ERST_SIZE 64
1377/* Initial number of event segment rings allocated */
1378#define ERST_ENTRIES 1
7f84eef0
SS		 1379/* Poll every 60 seconds */
1380#define POLL_TIMEOUT 60
6f5165cf
SS		 1381/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1382#define XHCI_STOP_EP_CMD_TIMEOUT 5
0ebbab37
SS		 1383/* XXX: Make these module parameters */
1384
5535b1d5
AX		 1385struct s3_save {
1386 u32 command;
1387 u32 dev_nt;
1388 u64 dcbaa_ptr;
1389 u32 config_reg;
1390 u32 irq_pending;
1391 u32 irq_control;
1392 u32 erst_size;
1393 u64 erst_base;
1394 u64 erst_dequeue;
1395};
74c68741 1396
9574323c
AX		 1397/* Use for lpm */
1398struct dev_info {
1399 u32 dev_id;
1400 struct list_head list;
1401};
1402
20b67cf5
SS		 1403struct xhci_bus_state {
1404 unsigned long bus_suspended;
1405 unsigned long next_statechange;
1406
1407 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1408 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1409 u32 port_c_suspend;
1410 u32 suspended_ports;
4ee823b8 1411 u32 port_remote_wakeup;
20b67cf5 1412 unsigned long resume_done[USB_MAXCHILDREN];
f370b996
AX		 1413 /* which ports have started to resume */
1414 unsigned long resuming_ports;
8b3d4570
SS		 1415 /* Which ports are waiting on RExit to U0 transition. */
1416 unsigned long rexit_ports;
1417 struct completion rexit_done[USB_MAXCHILDREN];
20b67cf5
SS		 1418};
1419
8b3d4570
SS		 1420
1421/*
1422 * It can take up to 20 ms to transition from RExit to U0 on the
1423 * Intel Lynx Point LP xHCI host.
1424 */
1425#define XHCI_MAX_REXIT_TIMEOUT (20 * 1000)
1426
20b67cf5
SS		 1427static inline unsigned int hcd_index(struct usb_hcd *hcd)
1428{
f6ff0ac8
SS		 1429 if (hcd->speed == HCD_USB3)
1430 return 0;
1431 else
1432 return 1;
20b67cf5
SS		 1433}
1434
05103114 1435/* There is one xhci_hcd structure per controller */
74c68741 1436struct xhci_hcd {
b02d0ed6 1437 struct usb_hcd *main_hcd;
f6ff0ac8 1438 struct usb_hcd *shared_hcd;
74c68741
SS		 1439 /* glue to PCI and HCD framework */
1440 struct xhci_cap_regs __iomem *cap_regs;
1441 struct xhci_op_regs __iomem *op_regs;
1442 struct xhci_run_regs __iomem *run_regs;
0ebbab37 1443 struct xhci_doorbell_array __iomem *dba;
66d4eadd 1444 /* Our HCD's current interrupter register set */
98441973 1445 struct xhci_intr_reg __iomem *ir_set;
74c68741
SS		 1446
1447 /* Cached register copies of read-only HC data */
1448 __u32 hcs_params1;
1449 __u32 hcs_params2;
1450 __u32 hcs_params3;
1451 __u32 hcc_params;
1452
1453 spinlock_t lock;
1454
1455 /* packed release number */
1456 u8 sbrn;
1457 u16 hci_version;
1458 u8 max_slots;
1459 u8 max_interrupters;
1460 u8 max_ports;
1461 u8 isoc_threshold;
1462 int event_ring_max;
1463 int addr_64;
66d4eadd 1464 /* 4KB min, 128MB max */
74c68741 1465 int page_size;
66d4eadd
SS		 1466 /* Valid values are 12 to 20, inclusive */
1467 int page_shift;
43b86af8 1468 /* msi-x vectors */
66d4eadd
SS		 1469 int msix_count;
1470 struct msix_entry *msix_entries;
0ebbab37 1471 /* data structures */
a74588f9 1472 struct xhci_device_context_array *dcbaa;
0ebbab37 1473 struct xhci_ring *cmd_ring;
c181bc5b
EF		 1474 unsigned int cmd_ring_state;
1475#define CMD_RING_STATE_RUNNING (1 << 0)
1476#define CMD_RING_STATE_ABORTED (1 << 1)
1477#define CMD_RING_STATE_STOPPED (1 << 2)
b92cc66c 1478 struct list_head cancel_cmd_list;
913a8a34 1479 unsigned int cmd_ring_reserved_trbs;
0ebbab37
SS		 1480 struct xhci_ring *event_ring;
1481 struct xhci_erst erst;
254c80a3
JY		 1482 /* Scratchpad */
1483 struct xhci_scratchpad *scratchpad;
9574323c
AX		 1484 /* Store LPM test failed devices' information */
1485 struct list_head lpm_failed_devs;
254c80a3 1486
3ffbba95
SS		 1487 /* slot enabling and address device helpers */
1488 struct completion addr_dev;
1489 int slot_id;
dbc33303
SS		 1490 /* For USB 3.0 LPM enable/disable. */
1491 struct xhci_command *lpm_command;
3ffbba95
SS		 1492 /* Internal mirror of the HW's dcbaa */
1493 struct xhci_virt_device *devs[MAX_HC_SLOTS];
839c817c
SS		 1494 /* For keeping track of bandwidth domains per roothub. */
1495 struct xhci_root_port_bw_info *rh_bw;
0ebbab37
SS		 1496
1497 /* DMA pools */
1498 struct dma_pool *device_pool;
1499 struct dma_pool *segment_pool;
8df75f42
SS		 1500 struct dma_pool *small_streams_pool;
1501 struct dma_pool *medium_streams_pool;
7f84eef0 1502
6f5165cf
SS		 1503 /* Host controller watchdog timer structures */
1504 unsigned int xhc_state;
9777e3ce 1505
9777e3ce 1506 u32 command;
5535b1d5 1507 struct s3_save s3;
6f5165cf
SS		 1508/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1509 *
1510 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1511 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1512 * that sees this status (other than the timer that set it) should stop touching
1513 * hardware immediately. Interrupt handlers should return immediately when
1514 * they see this status (any time they drop and re-acquire xhci->lock).
1515 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1516 * putting the TD on the canceled list, etc.
1517 *
1518 * There are no reports of xHCI host controllers that display this issue.
1519 */
1520#define XHCI_STATE_DYING (1 << 0)
c6cc27c7 1521#define XHCI_STATE_HALTED (1 << 1)
7f84eef0 1522 /* Statistics */
7f84eef0 1523 int error_bitmask;
b0567b3f
SS		 1524 unsigned int quirks;
1525#define XHCI_LINK_TRB_QUIRK (1 << 0)
ac9d8fe7 1526#define XHCI_RESET_EP_QUIRK (1 << 1)
0238634d 1527#define XHCI_NEC_HOST (1 << 2)
c41136b0 1528#define XHCI_AMD_PLL_FIX (1 << 3)
ad808333 1529#define XHCI_SPURIOUS_SUCCESS (1 << 4)
2cf95c18
SS		 1530/*
1531 * Certain Intel host controllers have a limit to the number of endpoint
1532 * contexts they can handle. Ideally, they would signal that they can't handle
1533 * anymore endpoint contexts by returning a Resource Error for the Configure
1534 * Endpoint command, but they don't. Instead they expect software to keep track
1535 * of the number of active endpoints for them, across configure endpoint
1536 * commands, reset device commands, disable slot commands, and address device
1537 * commands.
1538 */
1539#define XHCI_EP_LIMIT_QUIRK (1 << 5)
f5182b41 1540#define XHCI_BROKEN_MSI (1 << 6)
c877b3b2 1541#define XHCI_RESET_ON_RESUME (1 << 7)
c29eea62 1542#define XHCI_SW_BW_CHECKING (1 << 8)
7e393a83 1543#define XHCI_AMD_0x96_HOST (1 << 9)
1530bbc6 1544#define XHCI_TRUST_TX_LENGTH (1 << 10)
3b3db026 1545#define XHCI_LPM_SUPPORT (1 << 11)
e3567d2c 1546#define XHCI_INTEL_HOST (1 << 12)
e95829f4 1547#define XHCI_SPURIOUS_REBOOT (1 << 13)
71c731a2 1548#define XHCI_COMP_MODE_QUIRK (1 << 14)
80fab3b2 1549#define XHCI_AVOID_BEI (1 << 15)
52fb6125 1550#define XHCI_PLAT (1 << 16)
2cf95c18
SS		 1551 unsigned int num_active_eps;
1552 unsigned int limit_active_eps;
f6ff0ac8
SS		 1553 /* There are two roothubs to keep track of bus suspend info for */
1554 struct xhci_bus_state bus_state[2];
da6699ce
SS		 1555 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1556 u8 *port_array;
1557 /* Array of pointers to USB 3.0 PORTSC registers */
28ccd296 1558 __le32 __iomem **usb3_ports;
da6699ce
SS		 1559 unsigned int num_usb3_ports;
1560 /* Array of pointers to USB 2.0 PORTSC registers */
28ccd296 1561 __le32 __iomem **usb2_ports;
da6699ce 1562 unsigned int num_usb2_ports;
fc71ff75
AX		 1563 /* support xHCI 0.96 spec USB2 software LPM */
1564 unsigned sw_lpm_support:1;
1565 /* support xHCI 1.0 spec USB2 hardware LPM */
1566 unsigned hw_lpm_support:1;
b630d4b9
MN		 1567 /* cached usb2 extened protocol capabilites */
1568 u32 *ext_caps;
1569 unsigned int num_ext_caps;
71c731a2
AC		 1570 /* Compliance Mode Recovery Data */
1571 struct timer_list comp_mode_recovery_timer;
1572 u32 port_status_u0;
1573/* Compliance Mode Timer Triggered every 2 seconds */
1574#define COMP_MODE_RCVRY_MSECS 2000
74c68741
SS		 1575};
1576
1577/* convert between an HCD pointer and the corresponding EHCI_HCD */
1578static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1579{
b02d0ed6 1580 return *((struct xhci_hcd **) (hcd->hcd_priv));
74c68741
SS		 1581}
1582
1583static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1584{
b02d0ed6 1585 return xhci->main_hcd;
74c68741
SS		 1586}
1587
74c68741 1588#define xhci_dbg(xhci, fmt, args...) \
b2497509 1589 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
74c68741
SS		 1590#define xhci_err(xhci, fmt, args...) \
1591 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1592#define xhci_warn(xhci, fmt, args...) \
1593 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
8202ce2e
SS		 1594#define xhci_warn_ratelimited(xhci, fmt, args...) \
1595 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
74c68741
SS		 1596
1597/* TODO: copied from ehci.h - can be refactored? */
1598/* xHCI spec says all registers are little endian */
1599static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
28ccd296 1600 __le32 __iomem *regs)
74c68741
SS		 1601{
1602 return readl(regs);
1603}
045f123d 1604static inline void xhci_writel(struct xhci_hcd *xhci,
28ccd296 1605 const unsigned int val, __le32 __iomem *regs)
74c68741 1606{
74c68741
SS		 1607 writel(val, regs);
1608}
1609
8e595a5d
SS		 1610/*
1611 * Registers should always be accessed with double word or quad word accesses.
1612 *
1613 * Some xHCI implementations may support 64-bit address pointers. Registers
1614 * with 64-bit address pointers should be written to with dword accesses by
1615 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1616 * xHCI implementations that do not support 64-bit address pointers will ignore
1617 * the high dword, and write order is irrelevant.
1618 */
1619static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
28ccd296 1620 __le64 __iomem *regs)
8e595a5d
SS		 1621{
1622 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1623 u64 val_lo = readl(ptr);
1624 u64 val_hi = readl(ptr + 1);
1625 return val_lo + (val_hi << 32);
1626}
1627static inline void xhci_write_64(struct xhci_hcd *xhci,
28ccd296 1628 const u64 val, __le64 __iomem *regs)
8e595a5d
SS		 1629{
1630 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1631 u32 val_lo = lower_32_bits(val);
1632 u32 val_hi = upper_32_bits(val);
1633
8e595a5d
SS		 1634 writel(val_lo, ptr);
1635 writel(val_hi, ptr + 1);
1636}
1637
b0567b3f
SS		 1638static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1639{
d7826599 1640 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
b0567b3f
SS		 1641}
1642
66d4eadd 1643/* xHCI debugging */
09ece30e 1644void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
66d4eadd 1645void xhci_print_registers(struct xhci_hcd *xhci);
0ebbab37
SS		 1646void xhci_dbg_regs(struct xhci_hcd *xhci);
1647void xhci_print_run_regs(struct xhci_hcd *xhci);
d0e96f5a
SS		 1648void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1649void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
7f84eef0 1650void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
0ebbab37
SS		 1651void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1652void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1653void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
7f84eef0 1654void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
d115b048 1655void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
9c9a7dbf 1656char *xhci_get_slot_state(struct xhci_hcd *xhci,
2a8f82c4 1657 struct xhci_container_ctx *ctx);
e9df17eb
SS		 1658void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1659 unsigned int slot_id, unsigned int ep_index,
1660 struct xhci_virt_ep *ep);
84a99f6f
XR		 1661void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1662 const char *fmt, ...);
66d4eadd 1663
3dbda77e 1664/* xHCI memory management */
66d4eadd
SS		 1665void xhci_mem_cleanup(struct xhci_hcd *xhci);
1666int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
3ffbba95
SS		 1667void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1668int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1669int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2d1ee590
SS		 1670void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1671 struct usb_device *udev);
d0e96f5a 1672unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
01c5f447 1673unsigned int xhci_get_endpoint_address(unsigned int ep_index);
f94e0186 1674unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
ac9d8fe7
SS		 1675unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1676unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
f94e0186 1677void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2e27980e
SS		 1678void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1679 struct xhci_bw_info *ep_bw,
1680 struct xhci_interval_bw_table *bw_table,
1681 struct usb_device *udev,
1682 struct xhci_virt_ep *virt_ep,
1683 struct xhci_tt_bw_info *tt_info);
1684void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1685 struct xhci_virt_device *virt_dev,
1686 int old_active_eps);
9af5d71d
SS		 1687void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1688void xhci_update_bw_info(struct xhci_hcd *xhci,
1689 struct xhci_container_ctx *in_ctx,
1690 struct xhci_input_control_ctx *ctrl_ctx,
1691 struct xhci_virt_device *virt_dev);
f2217e8e 1692void xhci_endpoint_copy(struct xhci_hcd *xhci,
913a8a34
SS		 1693 struct xhci_container_ctx *in_ctx,
1694 struct xhci_container_ctx *out_ctx,
1695 unsigned int ep_index);
1696void xhci_slot_copy(struct xhci_hcd *xhci,
1697 struct xhci_container_ctx *in_ctx,
1698 struct xhci_container_ctx *out_ctx);
f88ba78d
SS		 1699int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1700 struct usb_device *udev, struct usb_host_endpoint *ep,
1701 gfp_t mem_flags);
f94e0186 1702void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
8dfec614
AX		 1703int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1704 unsigned int num_trbs, gfp_t flags);
412566bd
SS		 1705void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1706 struct xhci_virt_device *virt_dev,
1707 unsigned int ep_index);
8df75f42
SS		 1708struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1709 unsigned int num_stream_ctxs,
1710 unsigned int num_streams, gfp_t flags);
1711void xhci_free_stream_info(struct xhci_hcd *xhci,
1712 struct xhci_stream_info *stream_info);
1713void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1714 struct xhci_ep_ctx *ep_ctx,
1715 struct xhci_stream_info *stream_info);
1716void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1717 struct xhci_ep_ctx *ep_ctx,
1718 struct xhci_virt_ep *ep);
2cf95c18
SS		 1719void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1720 struct xhci_virt_device *virt_dev, bool drop_control_ep);
e9df17eb
SS		 1721struct xhci_ring *xhci_dma_to_transfer_ring(
1722 struct xhci_virt_ep *ep,
1723 u64 address);
e9df17eb
SS		 1724struct xhci_ring *xhci_stream_id_to_ring(
1725 struct xhci_virt_device *dev,
1726 unsigned int ep_index,
1727 unsigned int stream_id);
913a8a34 1728struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
a1d78c16
SS		 1729 bool allocate_in_ctx, bool allocate_completion,
1730 gfp_t mem_flags);
8e51adcc 1731void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
913a8a34
SS		 1732void xhci_free_command(struct xhci_hcd *xhci,
1733 struct xhci_command *command);
66d4eadd
SS		 1734
1735#ifdef CONFIG_PCI
1736/* xHCI PCI glue */
1737int xhci_register_pci(void);
1738void xhci_unregister_pci(void);
0cc47d54
SAS		 1739#else
1740static inline int xhci_register_pci(void) { return 0; }
1741static inline void xhci_unregister_pci(void) {}
66d4eadd
SS		 1742#endif
1743
3429e91a
SAS		 1744#if defined(CONFIG_USB_XHCI_PLATFORM) \
1745 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1746int xhci_register_plat(void);
1747void xhci_unregister_plat(void);
1748#else
1749static inline int xhci_register_plat(void)
1750{ return 0; }
1751static inline void xhci_unregister_plat(void)
1752{ }
1753#endif
1754
66d4eadd 1755/* xHCI host controller glue */
552e0c4f 1756typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2611bd18 1757int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
b92cc66c 1758 u32 mask, u32 done, int usec);
4f0f0bae 1759void xhci_quiesce(struct xhci_hcd *xhci);
66d4eadd
SS		 1760int xhci_halt(struct xhci_hcd *xhci);
1761int xhci_reset(struct xhci_hcd *xhci);
1762int xhci_init(struct usb_hcd *hcd);
1763int xhci_run(struct usb_hcd *hcd);
1764void xhci_stop(struct usb_hcd *hcd);
1765void xhci_shutdown(struct usb_hcd *hcd);
552e0c4f 1766int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
436a3890
SS		 1767
1768#ifdef CONFIG_PM
5535b1d5
AX		 1769int xhci_suspend(struct xhci_hcd *xhci);
1770int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
436a3890
SS		 1771#else
1772#define xhci_suspend NULL
1773#define xhci_resume NULL
1774#endif
1775
66d4eadd 1776int xhci_get_frame(struct usb_hcd *hcd);
7f84eef0 1777irqreturn_t xhci_irq(struct usb_hcd *hcd);
851ec164 1778irqreturn_t xhci_msi_irq(int irq, void *hcd);
3ffbba95
SS		 1779int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1780void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
839c817c
SS		 1781int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1782 struct xhci_virt_device *virt_dev,
1783 struct usb_device *hdev,
1784 struct usb_tt *tt, gfp_t mem_flags);
8df75f42
SS		 1785int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1786 struct usb_host_endpoint **eps, unsigned int num_eps,
1787 unsigned int num_streams, gfp_t mem_flags);
1788int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1789 struct usb_host_endpoint **eps, unsigned int num_eps,
1790 gfp_t mem_flags);
3ffbba95 1791int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
9574323c 1792int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
65580b43
AX		 1793int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1794 struct usb_device *udev, int enable);
ac1c1b7f
SS		 1795int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1796 struct usb_tt *tt, gfp_t mem_flags);
d0e96f5a
SS		 1797int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1798int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
f94e0186
SS		 1799int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1800int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
a1587d97 1801void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
f0615c45 1802int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
f94e0186
SS		 1803int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1804void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
7f84eef0
SS		 1805
1806/* xHCI ring, segment, TRB, and TD functions */
23e3be11 1807dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
6648f29d
SS		 1808struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1809 union xhci_trb *start_trb, union xhci_trb *end_trb,
1810 dma_addr_t suspect_dma);
b45b5069 1811int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
23e3be11 1812void xhci_ring_cmd_db(struct xhci_hcd *xhci);
23e3be11
SS		 1813int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1814int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1815 u32 slot_id);
0238634d
SS		 1816int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1817 u32 field1, u32 field2, u32 field3, u32 field4);
23e3be11 1818int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
be88fe4f 1819 unsigned int ep_index, int suspend);
23e3be11
SS		 1820int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1821 int slot_id, unsigned int ep_index);
1822int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1823 int slot_id, unsigned int ep_index);
624defa1
SS		 1824int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1825 int slot_id, unsigned int ep_index);
04e51901
AX		 1826int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1827 struct urb *urb, int slot_id, unsigned int ep_index);
23e3be11 1828int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
913a8a34 1829 u32 slot_id, bool command_must_succeed);
f2217e8e 1830int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4b266541 1831 u32 slot_id, bool command_must_succeed);
a1587d97
SS		 1832int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1833 unsigned int ep_index);
2a8f82c4 1834int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
c92bcfa7
SS		 1835void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1836 unsigned int slot_id, unsigned int ep_index,
e9df17eb
SS		 1837 unsigned int stream_id, struct xhci_td *cur_td,
1838 struct xhci_dequeue_state *state);
c92bcfa7 1839void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
63a0d9ab 1840 unsigned int slot_id, unsigned int ep_index,
e9df17eb 1841 unsigned int stream_id,
63a0d9ab 1842 struct xhci_dequeue_state *deq_state);
82d1009f 1843void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
63a0d9ab 1844 struct usb_device *udev, unsigned int ep_index);
ac9d8fe7
SS		 1845void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1846 unsigned int slot_id, unsigned int ep_index,
1847 struct xhci_dequeue_state *deq_state);
6f5165cf 1848void xhci_stop_endpoint_command_watchdog(unsigned long arg);
b92cc66c
EF		 1849int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
1850 union xhci_trb *cmd_trb);
be88fe4f
AX		 1851void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1852 unsigned int ep_index, unsigned int stream_id);
ec7e43e2 1853union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring);
66d4eadd 1854
0f2a7930 1855/* xHCI roothub code */
c9682dff
AX		 1856void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1857 int port_id, u32 link_state);
3b3db026
SS		 1858int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1859 struct usb_device *udev, enum usb3_link_state state);
1860int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1861 struct usb_device *udev, enum usb3_link_state state);
d2f52c9e
AX		 1862void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1863 int port_id, u32 port_bit);
0f2a7930
SS		 1864int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1865 char *buf, u16 wLength);
1866int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
3f5eb141 1867int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
436a3890
SS		 1868
1869#ifdef CONFIG_PM
9777e3ce
AX		 1870int xhci_bus_suspend(struct usb_hcd *hcd);
1871int xhci_bus_resume(struct usb_hcd *hcd);
436a3890
SS		 1872#else
1873#define xhci_bus_suspend NULL
1874#define xhci_bus_resume NULL
1875#endif /* CONFIG_PM */
1876
56192531 1877u32 xhci_port_state_to_neutral(u32 state);
5233630f
SS		 1878int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1879 u16 port);
56192531 1880void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
0f2a7930 1881
d115b048
JY		 1882/* xHCI contexts */
1883struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1884struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1885struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1886
c3897aa5
SS		 1887/* xHCI quirks */
1888bool xhci_compliance_mode_recovery_timer_quirk_check(void);
1889
74c68741 1890#endif /* __LINUX_XHCI_HCD_H */
Linux 6.x block layer and io_uring tree(s)