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USB: xhci: Wait for host to start running.
[linux-2.6-block.git] / drivers / usb / host / xhci.h
CommitLineData
74c68741
SS		 1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __LINUX_XHCI_HCD_H
24#define __LINUX_XHCI_HCD_H
25
26#include <linux/usb.h>
7f84eef0 27#include <linux/timer.h>
8e595a5d 28#include <linux/kernel.h>
27729aad 29#include <linux/usb/hcd.h>
74c68741 30
74c68741
SS		 31/* Code sharing between pci-quirks and xhci hcd */
32#include "xhci-ext-caps.h"
33
34/* xHCI PCI Configuration Registers */
35#define XHCI_SBRN_OFFSET (0x60)
36
66d4eadd
SS		 37/* Max number of USB devices for any host controller - limit in section 6.1 */
38#define MAX_HC_SLOTS 256
0f2a7930
SS		 39/* Section 5.3.3 - MaxPorts */
40#define MAX_HC_PORTS 127
66d4eadd 41
74c68741
SS		 42/*
43 * xHCI register interface.
44 * This corresponds to the eXtensible Host Controller Interface (xHCI)
45 * Revision 0.95 specification
74c68741
SS		 46 */
47
48/**
49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
50 * @hc_capbase: length of the capabilities register and HC version number
51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
54 * @hcc_params: HCCPARAMS - Capability Parameters
55 * @db_off: DBOFF - Doorbell array offset
56 * @run_regs_off: RTSOFF - Runtime register space offset
57 */
58struct xhci_cap_regs {
59 u32 hc_capbase;
60 u32 hcs_params1;
61 u32 hcs_params2;
62 u32 hcs_params3;
63 u32 hcc_params;
64 u32 db_off;
65 u32 run_regs_off;
66 /* Reserved up to (CAPLENGTH - 0x1C) */
98441973 67};
74c68741
SS		 68
69/* hc_capbase bitmasks */
70/* bits 7:0 - how long is the Capabilities register */
71#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
72/* bits 31:16 */
73#define HC_VERSION(p) (((p) >> 16) & 0xffff)
74
75/* HCSPARAMS1 - hcs_params1 - bitmasks */
76/* bits 0:7, Max Device Slots */
77#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
78#define HCS_SLOTS_MASK 0xff
79/* bits 8:18, Max Interrupters */
80#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
81/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
82#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
83
84/* HCSPARAMS2 - hcs_params2 - bitmasks */
85/* bits 0:3, frames or uframes that SW needs to queue transactions
86 * ahead of the HW to meet periodic deadlines */
87#define HCS_IST(p) (((p) >> 0) & 0xf)
88/* bits 4:7, max number of Event Ring segments */
89#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
90/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
254c80a3 92#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
74c68741
SS		 93
94/* HCSPARAMS3 - hcs_params3 - bitmasks */
95/* bits 0:7, Max U1 to U0 latency for the roothub ports */
96#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
97/* bits 16:31, Max U2 to U0 latency for the roothub ports */
98#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
99
100/* HCCPARAMS - hcc_params - bitmasks */
101/* true: HC can use 64-bit address pointers */
102#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
103/* true: HC can do bandwidth negotiation */
104#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
105/* true: HC uses 64-byte Device Context structures
106 * FIXME 64-byte context structures aren't supported yet.
107 */
108#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
109/* true: HC has port power switches */
110#define HCC_PPC(p) ((p) & (1 << 3))
111/* true: HC has port indicators */
112#define HCS_INDICATOR(p) ((p) & (1 << 4))
113/* true: HC has Light HC Reset Capability */
114#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
115/* true: HC supports latency tolerance messaging */
116#define HCC_LTC(p) ((p) & (1 << 6))
117/* true: no secondary Stream ID Support */
118#define HCC_NSS(p) ((p) & (1 << 7))
119/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
8df75f42 120#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
74c68741
SS		 121/* Extended Capabilities pointer from PCI base - section 5.3.6 */
122#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
123
124/* db_off bitmask - bits 0:1 reserved */
125#define DBOFF_MASK (~0x3)
126
127/* run_regs_off bitmask - bits 0:4 reserved */
128#define RTSOFF_MASK (~0x1f)
129
130
131/* Number of registers per port */
132#define NUM_PORT_REGS 4
133
134/**
135 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
136 * @command: USBCMD - xHC command register
137 * @status: USBSTS - xHC status register
138 * @page_size: This indicates the page size that the host controller
139 * supports. If bit n is set, the HC supports a page size
140 * of 2^(n+12), up to a 128MB page size.
141 * 4K is the minimum page size.
142 * @cmd_ring: CRP - 64-bit Command Ring Pointer
143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
144 * @config_reg: CONFIG - Configure Register
145 * @port_status_base: PORTSCn - base address for Port Status and Control
146 * Each port has a Port Status and Control register,
147 * followed by a Port Power Management Status and Control
148 * register, a Port Link Info register, and a reserved
149 * register.
150 * @port_power_base: PORTPMSCn - base address for
151 * Port Power Management Status and Control
152 * @port_link_base: PORTLIn - base address for Port Link Info (current
153 * Link PM state and control) for USB 2.1 and USB 3.0
154 * devices.
155 */
156struct xhci_op_regs {
157 u32 command;
158 u32 status;
159 u32 page_size;
160 u32 reserved1;
161 u32 reserved2;
162 u32 dev_notification;
8e595a5d 163 u64 cmd_ring;
74c68741
SS		 164 /* rsvd: offset 0x20-2F */
165 u32 reserved3[4];
8e595a5d 166 u64 dcbaa_ptr;
74c68741
SS		 167 u32 config_reg;
168 /* rsvd: offset 0x3C-3FF */
169 u32 reserved4[241];
170 /* port 1 registers, which serve as a base address for other ports */
171 u32 port_status_base;
172 u32 port_power_base;
173 u32 port_link_base;
174 u32 reserved5;
175 /* registers for ports 2-255 */
176 u32 reserved6[NUM_PORT_REGS*254];
98441973 177};
74c68741
SS		 178
179/* USBCMD - USB command - command bitmasks */
180/* start/stop HC execution - do not write unless HC is halted*/
181#define CMD_RUN XHCI_CMD_RUN
182/* Reset HC - resets internal HC state machine and all registers (except
183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
184 * The xHCI driver must reinitialize the xHC after setting this bit.
185 */
186#define CMD_RESET (1 << 1)
187/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
188#define CMD_EIE XHCI_CMD_EIE
189/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
190#define CMD_HSEIE XHCI_CMD_HSEIE
191/* bits 4:6 are reserved (and should be preserved on writes). */
192/* light reset (port status stays unchanged) - reset completed when this is 0 */
193#define CMD_LRESET (1 << 7)
194/* FIXME: ignoring host controller save/restore state for now. */
195#define CMD_CSS (1 << 8)
196#define CMD_CRS (1 << 9)
197/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
198#define CMD_EWE XHCI_CMD_EWE
199/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
201 * '0' means the xHC can power it off if all ports are in the disconnect,
202 * disabled, or powered-off state.
203 */
204#define CMD_PM_INDEX (1 << 11)
205/* bits 12:31 are reserved (and should be preserved on writes). */
206
207/* USBSTS - USB status - status bitmasks */
208/* HC not running - set to 1 when run/stop bit is cleared. */
209#define STS_HALT XHCI_STS_HALT
210/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
211#define STS_FATAL (1 << 2)
212/* event interrupt - clear this prior to clearing any IP flags in IR set*/
213#define STS_EINT (1 << 3)
214/* port change detect */
215#define STS_PORT (1 << 4)
216/* bits 5:7 reserved and zeroed */
217/* save state status - '1' means xHC is saving state */
218#define STS_SAVE (1 << 8)
219/* restore state status - '1' means xHC is restoring state */
220#define STS_RESTORE (1 << 9)
221/* true: save or restore error */
222#define STS_SRE (1 << 10)
223/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
224#define STS_CNR XHCI_STS_CNR
225/* true: internal Host Controller Error - SW needs to reset and reinitialize */
226#define STS_HCE (1 << 12)
227/* bits 13:31 reserved and should be preserved */
228
229/*
230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
231 * Generate a device notification event when the HC sees a transaction with a
232 * notification type that matches a bit set in this bit field.
233 */
234#define DEV_NOTE_MASK (0xffff)
235#define ENABLE_DEV_NOTE(x) (1 << x)
236/* Most of the device notification types should only be used for debug.
237 * SW does need to pay attention to function wake notifications.
238 */
239#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
240
0ebbab37
SS		 241/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
242/* bit 0 is the command ring cycle state */
243/* stop ring operation after completion of the currently executing command */
244#define CMD_RING_PAUSE (1 << 1)
245/* stop ring immediately - abort the currently executing command */
246#define CMD_RING_ABORT (1 << 2)
247/* true: command ring is running */
248#define CMD_RING_RUNNING (1 << 3)
249/* bits 4:5 reserved and should be preserved */
250/* Command Ring pointer - bit mask for the lower 32 bits. */
8e595a5d 251#define CMD_RING_RSVD_BITS (0x3f)
0ebbab37 252
74c68741
SS		 253/* CONFIG - Configure Register - config_reg bitmasks */
254/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
255#define MAX_DEVS(p) ((p) & 0xff)
256/* bits 8:31 - reserved and should be preserved */
257
258/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
259/* true: device connected */
260#define PORT_CONNECT (1 << 0)
261/* true: port enabled */
262#define PORT_PE (1 << 1)
263/* bit 2 reserved and zeroed */
264/* true: port has an over-current condition */
265#define PORT_OC (1 << 3)
266/* true: port reset signaling asserted */
267#define PORT_RESET (1 << 4)
268/* Port Link State - bits 5:8
269 * A read gives the current link PM state of the port,
270 * a write with Link State Write Strobe set sets the link state.
271 */
272/* true: port has power (see HCC_PPC) */
273#define PORT_POWER (1 << 9)
274/* bits 10:13 indicate device speed:
275 * 0 - undefined speed - port hasn't be initialized by a reset yet
276 * 1 - full speed
277 * 2 - low speed
278 * 3 - high speed
279 * 4 - super speed
280 * 5-15 reserved
281 */
3ffbba95
SS		 282#define DEV_SPEED_MASK (0xf << 10)
283#define XDEV_FS (0x1 << 10)
284#define XDEV_LS (0x2 << 10)
285#define XDEV_HS (0x3 << 10)
286#define XDEV_SS (0x4 << 10)
74c68741 287#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
3ffbba95
SS		 288#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
289#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
290#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
291#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
292/* Bits 20:23 in the Slot Context are the speed for the device */
293#define SLOT_SPEED_FS (XDEV_FS << 10)
294#define SLOT_SPEED_LS (XDEV_LS << 10)
295#define SLOT_SPEED_HS (XDEV_HS << 10)
296#define SLOT_SPEED_SS (XDEV_SS << 10)
74c68741
SS		 297/* Port Indicator Control */
298#define PORT_LED_OFF (0 << 14)
299#define PORT_LED_AMBER (1 << 14)
300#define PORT_LED_GREEN (2 << 14)
301#define PORT_LED_MASK (3 << 14)
302/* Port Link State Write Strobe - set this when changing link state */
303#define PORT_LINK_STROBE (1 << 16)
304/* true: connect status change */
305#define PORT_CSC (1 << 17)
306/* true: port enable change */
307#define PORT_PEC (1 << 18)
308/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
309 * into an enabled state, and the device into the default state. A "warm" reset
310 * also resets the link, forcing the device through the link training sequence.
311 * SW can also look at the Port Reset register to see when warm reset is done.
312 */
313#define PORT_WRC (1 << 19)
314/* true: over-current change */
315#define PORT_OCC (1 << 20)
316/* true: reset change - 1 to 0 transition of PORT_RESET */
317#define PORT_RC (1 << 21)
318/* port link status change - set on some port link state transitions:
319 * Transition Reason
320 * ------------------------------------------------------------------------------
321 * - U3 to Resume Wakeup signaling from a device
322 * - Resume to Recovery to U0 USB 3.0 device resume
323 * - Resume to U0 USB 2.0 device resume
324 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
325 * - U3 to U0 Software resume of USB 2.0 device complete
326 * - U2 to U0 L1 resume of USB 2.1 device complete
327 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
328 * - U0 to disabled L1 entry error with USB 2.1 device
329 * - Any state to inactive Error on USB 3.0 port
330 */
331#define PORT_PLC (1 << 22)
332/* port configure error change - port failed to configure its link partner */
333#define PORT_CEC (1 << 23)
334/* bit 24 reserved */
335/* wake on connect (enable) */
336#define PORT_WKCONN_E (1 << 25)
337/* wake on disconnect (enable) */
338#define PORT_WKDISC_E (1 << 26)
339/* wake on over-current (enable) */
340#define PORT_WKOC_E (1 << 27)
341/* bits 28:29 reserved */
342/* true: device is removable - for USB 3.0 roothub emulation */
343#define PORT_DEV_REMOVE (1 << 30)
344/* Initiate a warm port reset - complete when PORT_WRC is '1' */
345#define PORT_WR (1 << 31)
346
347/* Port Power Management Status and Control - port_power_base bitmasks */
348/* Inactivity timer value for transitions into U1, in microseconds.
349 * Timeout can be up to 127us. 0xFF means an infinite timeout.
350 */
351#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
352/* Inactivity timer value for transitions into U2 */
353#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
354/* Bits 24:31 for port testing */
355
356
357/**
98441973 358 * struct xhci_intr_reg - Interrupt Register Set
74c68741
SS		 359 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
360 * interrupts and check for pending interrupts.
361 * @irq_control: IMOD - Interrupt Moderation Register.
362 * Used to throttle interrupts.
363 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
364 * @erst_base: ERST base address.
365 * @erst_dequeue: Event ring dequeue pointer.
366 *
367 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
368 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
369 * multiple segments of the same size. The HC places events on the ring and
370 * "updates the Cycle bit in the TRBs to indicate to software the current
371 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
372 * updates the dequeue pointer.
373 */
98441973 374struct xhci_intr_reg {
74c68741
SS		 375 u32 irq_pending;
376 u32 irq_control;
377 u32 erst_size;
378 u32 rsvd;
8e595a5d
SS		 379 u64 erst_base;
380 u64 erst_dequeue;
98441973 381};
74c68741 382
66d4eadd 383/* irq_pending bitmasks */
74c68741 384#define ER_IRQ_PENDING(p) ((p) & 0x1)
66d4eadd 385/* bits 2:31 need to be preserved */
7f84eef0 386/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
66d4eadd
SS		 387#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
388#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
389#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
390
391/* irq_control bitmasks */
392/* Minimum interval between interrupts (in 250ns intervals). The interval
393 * between interrupts will be longer if there are no events on the event ring.
394 * Default is 4000 (1 ms).
395 */
396#define ER_IRQ_INTERVAL_MASK (0xffff)
397/* Counter used to count down the time to the next interrupt - HW use only */
398#define ER_IRQ_COUNTER_MASK (0xffff << 16)
399
400/* erst_size bitmasks */
74c68741 401/* Preserve bits 16:31 of erst_size */
66d4eadd
SS		 402#define ERST_SIZE_MASK (0xffff << 16)
403
404/* erst_dequeue bitmasks */
405/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
406 * where the current dequeue pointer lies. This is an optional HW hint.
407 */
408#define ERST_DESI_MASK (0x7)
409/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
410 * a work queue (or delayed service routine)?
411 */
412#define ERST_EHB (1 << 3)
0ebbab37 413#define ERST_PTR_MASK (0xf)
74c68741
SS		 414
415/**
416 * struct xhci_run_regs
417 * @microframe_index:
418 * MFINDEX - current microframe number
419 *
420 * Section 5.5 Host Controller Runtime Registers:
421 * "Software should read and write these registers using only Dword (32 bit)
422 * or larger accesses"
423 */
424struct xhci_run_regs {
98441973
SS		 425 u32 microframe_index;
426 u32 rsvd[7];
427 struct xhci_intr_reg ir_set[128];
428};
74c68741 429
0ebbab37
SS		 430/**
431 * struct doorbell_array
432 *
433 * Section 5.6
434 */
435struct xhci_doorbell_array {
436 u32 doorbell[256];
98441973 437};
0ebbab37
SS		 438
439#define DB_TARGET_MASK 0xFFFFFF00
440#define DB_STREAM_ID_MASK 0x0000FFFF
441#define DB_TARGET_HOST 0x0
442#define DB_STREAM_ID_HOST 0x0
443#define DB_MASK (0xff << 8)
444
d0e96f5a
SS		 445/* Endpoint Target - bits 0:7 */
446#define EPI_TO_DB(p) (((p) + 1) & 0xff)
e9df17eb 447#define STREAM_ID_TO_DB(p) (((p) & 0xffff) << 16)
d0e96f5a 448
0ebbab37 449
d115b048
JY		 450/**
451 * struct xhci_container_ctx
452 * @type: Type of context. Used to calculated offsets to contained contexts.
453 * @size: Size of the context data
454 * @bytes: The raw context data given to HW
455 * @dma: dma address of the bytes
456 *
457 * Represents either a Device or Input context. Holds a pointer to the raw
458 * memory used for the context (bytes) and dma address of it (dma).
459 */
460struct xhci_container_ctx {
461 unsigned type;
462#define XHCI_CTX_TYPE_DEVICE 0x1
463#define XHCI_CTX_TYPE_INPUT 0x2
464
465 int size;
466
467 u8 *bytes;
468 dma_addr_t dma;
469};
470
a74588f9
SS		 471/**
472 * struct xhci_slot_ctx
473 * @dev_info: Route string, device speed, hub info, and last valid endpoint
474 * @dev_info2: Max exit latency for device number, root hub port number
475 * @tt_info: tt_info is used to construct split transaction tokens
476 * @dev_state: slot state and device address
477 *
478 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
479 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
480 * reserved at the end of the slot context for HC internal use.
481 */
482struct xhci_slot_ctx {
483 u32 dev_info;
484 u32 dev_info2;
485 u32 tt_info;
486 u32 dev_state;
487 /* offset 0x10 to 0x1f reserved for HC internal use */
488 u32 reserved[4];
98441973 489};
a74588f9
SS		 490
491/* dev_info bitmasks */
492/* Route String - 0:19 */
493#define ROUTE_STRING_MASK (0xfffff)
494/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
495#define DEV_SPEED (0xf << 20)
496/* bit 24 reserved */
497/* Is this LS/FS device connected through a HS hub? - bit 25 */
498#define DEV_MTT (0x1 << 25)
499/* Set if the device is a hub - bit 26 */
500#define DEV_HUB (0x1 << 26)
501/* Index of the last valid endpoint context in this device context - 27:31 */
3ffbba95
SS		 502#define LAST_CTX_MASK (0x1f << 27)
503#define LAST_CTX(p) ((p) << 27)
504#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
3ffbba95
SS		 505#define SLOT_FLAG (1 << 0)
506#define EP0_FLAG (1 << 1)
a74588f9
SS		 507
508/* dev_info2 bitmasks */
509/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
510#define MAX_EXIT (0xffff)
511/* Root hub port number that is needed to access the USB device */
3ffbba95 512#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
ac1c1b7f
SS		 513/* Maximum number of ports under a hub device */
514#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
a74588f9
SS		 515
516/* tt_info bitmasks */
517/*
518 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
519 * The Slot ID of the hub that isolates the high speed signaling from
520 * this low or full-speed device. '0' if attached to root hub port.
521 */
522#define TT_SLOT (0xff)
523/*
524 * The number of the downstream facing port of the high-speed hub
525 * '0' if the device is not low or full speed.
526 */
527#define TT_PORT (0xff << 8)
ac1c1b7f 528#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
a74588f9
SS		 529
530/* dev_state bitmasks */
531/* USB device address - assigned by the HC */
3ffbba95 532#define DEV_ADDR_MASK (0xff)
a74588f9
SS		 533/* bits 8:26 reserved */
534/* Slot state */
535#define SLOT_STATE (0x1f << 27)
ae636747 536#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
a74588f9
SS		 537
538
539/**
540 * struct xhci_ep_ctx
541 * @ep_info: endpoint state, streams, mult, and interval information.
542 * @ep_info2: information on endpoint type, max packet size, max burst size,
543 * error count, and whether the HC will force an event for all
544 * transactions.
3ffbba95
SS		 545 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
546 * defines one stream, this points to the endpoint transfer ring.
547 * Otherwise, it points to a stream context array, which has a
548 * ring pointer for each flow.
549 * @tx_info:
550 * Average TRB lengths for the endpoint ring and
551 * max payload within an Endpoint Service Interval Time (ESIT).
a74588f9
SS		 552 *
553 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
554 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
555 * reserved at the end of the endpoint context for HC internal use.
556 */
557struct xhci_ep_ctx {
558 u32 ep_info;
559 u32 ep_info2;
8e595a5d 560 u64 deq;
3ffbba95 561 u32 tx_info;
a74588f9 562 /* offset 0x14 - 0x1f reserved for HC internal use */
3ffbba95 563 u32 reserved[3];
98441973 564};
a74588f9
SS		 565
566/* ep_info bitmasks */
567/*
568 * Endpoint State - bits 0:2
569 * 0 - disabled
570 * 1 - running
571 * 2 - halted due to halt condition - ok to manipulate endpoint ring
572 * 3 - stopped
573 * 4 - TRB error
574 * 5-7 - reserved
575 */
d0e96f5a
SS		 576#define EP_STATE_MASK (0xf)
577#define EP_STATE_DISABLED 0
578#define EP_STATE_RUNNING 1
579#define EP_STATE_HALTED 2
580#define EP_STATE_STOPPED 3
581#define EP_STATE_ERROR 4
a74588f9
SS		 582/* Mult - Max number of burtst within an interval, in EP companion desc. */
583#define EP_MULT(p) ((p & 0x3) << 8)
584/* bits 10:14 are Max Primary Streams */
585/* bit 15 is Linear Stream Array */
586/* Interval - period between requests to an endpoint - 125u increments. */
f94e0186 587#define EP_INTERVAL(p) ((p & 0xff) << 16)
624defa1 588#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
8df75f42
SS		 589#define EP_MAXPSTREAMS_MASK (0x1f << 10)
590#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
591/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
592#define EP_HAS_LSA (1 << 15)
a74588f9
SS		 593
594/* ep_info2 bitmasks */
595/*
596 * Force Event - generate transfer events for all TRBs for this endpoint
597 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
598 */
599#define FORCE_EVENT (0x1)
600#define ERROR_COUNT(p) (((p) & 0x3) << 1)
82d1009f 601#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
a74588f9
SS		 602#define EP_TYPE(p) ((p) << 3)
603#define ISOC_OUT_EP 1
604#define BULK_OUT_EP 2
605#define INT_OUT_EP 3
606#define CTRL_EP 4
607#define ISOC_IN_EP 5
608#define BULK_IN_EP 6
609#define INT_IN_EP 7
610/* bit 6 reserved */
611/* bit 7 is Host Initiate Disable - for disabling stream selection */
612#define MAX_BURST(p) (((p)&0xff) << 8)
613#define MAX_PACKET(p) (((p)&0xffff) << 16)
2d3f1fac
SS		 614#define MAX_PACKET_MASK (0xffff << 16)
615#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
a74588f9 616
9238f25d
SS		 617/* tx_info bitmasks */
618#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
619#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
620
a74588f9
SS		 621
622/**
d115b048
JY		 623 * struct xhci_input_control_context
624 * Input control context; see section 6.2.5.
a74588f9
SS		 625 *
626 * @drop_context: set the bit of the endpoint context you want to disable
627 * @add_context: set the bit of the endpoint context you want to enable
628 */
d115b048 629struct xhci_input_control_ctx {
a74588f9
SS		 630 u32 drop_flags;
631 u32 add_flags;
d115b048 632 u32 rsvd2[6];
98441973 633};
a74588f9 634
913a8a34
SS		 635/* Represents everything that is needed to issue a command on the command ring.
636 * It's useful to pre-allocate these for commands that cannot fail due to
637 * out-of-memory errors, like freeing streams.
638 */
639struct xhci_command {
640 /* Input context for changing device state */
641 struct xhci_container_ctx *in_ctx;
642 u32 status;
643 /* If completion is null, no one is waiting on this command
644 * and the structure can be freed after the command completes.
645 */
646 struct completion *completion;
647 union xhci_trb *command_trb;
648 struct list_head cmd_list;
649};
650
a74588f9
SS		 651/* drop context bitmasks */
652#define DROP_EP(x) (0x1 << x)
653/* add context bitmasks */
654#define ADD_EP(x) (0x1 << x)
655
8df75f42
SS		 656struct xhci_stream_ctx {
657 /* 64-bit stream ring address, cycle state, and stream type */
658 u64 stream_ring;
659 /* offset 0x14 - 0x1f reserved for HC internal use */
660 u32 reserved[2];
661};
662
663/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
664#define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
665/* Secondary stream array type, dequeue pointer is to a transfer ring */
666#define SCT_SEC_TR 0
667/* Primary stream array type, dequeue pointer is to a transfer ring */
668#define SCT_PRI_TR 1
669/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
670#define SCT_SSA_8 2
671#define SCT_SSA_16 3
672#define SCT_SSA_32 4
673#define SCT_SSA_64 5
674#define SCT_SSA_128 6
675#define SCT_SSA_256 7
676
677/* Assume no secondary streams for now */
678struct xhci_stream_info {
679 struct xhci_ring **stream_rings;
680 /* Number of streams, including stream 0 (which drivers can't use) */
681 unsigned int num_streams;
682 /* The stream context array may be bigger than
683 * the number of streams the driver asked for
684 */
685 struct xhci_stream_ctx *stream_ctx_array;
686 unsigned int num_stream_ctxs;
687 dma_addr_t ctx_array_dma;
688 /* For mapping physical TRB addresses to segments in stream rings */
689 struct radix_tree_root trb_address_map;
690 struct xhci_command *free_streams_command;
691};
692
693#define SMALL_STREAM_ARRAY_SIZE 256
694#define MEDIUM_STREAM_ARRAY_SIZE 1024
695
63a0d9ab
SS		 696struct xhci_virt_ep {
697 struct xhci_ring *ring;
8df75f42
SS		 698 /* Related to endpoints that are configured to use stream IDs only */
699 struct xhci_stream_info *stream_info;
63a0d9ab
SS		 700 /* Temporary storage in case the configure endpoint command fails and we
701 * have to restore the device state to the previous state
702 */
703 struct xhci_ring *new_ring;
704 unsigned int ep_state;
705#define SET_DEQ_PENDING (1 << 0)
678539cf
SS		 706#define EP_HALTED (1 << 1) /* For stall handling */
707#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
8df75f42
SS		 708/* Transitioning the endpoint to using streams, don't enqueue URBs */
709#define EP_GETTING_STREAMS (1 << 3)
710#define EP_HAS_STREAMS (1 << 4)
711/* Transitioning the endpoint to not using streams, don't enqueue URBs */
712#define EP_GETTING_NO_STREAMS (1 << 5)
63a0d9ab
SS		 713 /* ---- Related to URB cancellation ---- */
714 struct list_head cancelled_td_list;
63a0d9ab
SS		 715 /* The TRB that was last reported in a stopped endpoint ring */
716 union xhci_trb *stopped_trb;
717 struct xhci_td *stopped_td;
e9df17eb 718 unsigned int stopped_stream;
6f5165cf
SS		 719 /* Watchdog timer for stop endpoint command to cancel URBs */
720 struct timer_list stop_cmd_timer;
721 int stop_cmds_pending;
722 struct xhci_hcd *xhci;
63a0d9ab
SS		 723};
724
3ffbba95
SS		 725struct xhci_virt_device {
726 /*
727 * Commands to the hardware are passed an "input context" that
728 * tells the hardware what to change in its data structures.
729 * The hardware will return changes in an "output context" that
730 * software must allocate for the hardware. We need to keep
731 * track of input and output contexts separately because
732 * these commands might fail and we don't trust the hardware.
733 */
d115b048 734 struct xhci_container_ctx *out_ctx;
3ffbba95 735 /* Used for addressing devices and configuration changes */
d115b048 736 struct xhci_container_ctx *in_ctx;
74f9fe21
SS		 737 /* Rings saved to ensure old alt settings can be re-instated */
738 struct xhci_ring **ring_cache;
739 int num_rings_cached;
740#define XHCI_MAX_RINGS_CACHED 31
63a0d9ab 741 struct xhci_virt_ep eps[31];
f94e0186 742 struct completion cmd_completion;
3ffbba95
SS		 743 /* Status of the last command issued for this device */
744 u32 cmd_status;
913a8a34 745 struct list_head cmd_list;
3ffbba95
SS		 746};
747
748
a74588f9
SS		 749/**
750 * struct xhci_device_context_array
751 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
752 */
753struct xhci_device_context_array {
754 /* 64-bit device addresses; we only write 32-bit addresses */
8e595a5d 755 u64 dev_context_ptrs[MAX_HC_SLOTS];
a74588f9
SS		 756 /* private xHCD pointers */
757 dma_addr_t dma;
98441973 758};
a74588f9
SS		 759/* TODO: write function to set the 64-bit device DMA address */
760/*
761 * TODO: change this to be dynamically sized at HC mem init time since the HC
762 * might not be able to handle the maximum number of devices possible.
763 */
764
765
0ebbab37
SS		 766struct xhci_transfer_event {
767 /* 64-bit buffer address, or immediate data */
8e595a5d 768 u64 buffer;
0ebbab37
SS		 769 u32 transfer_len;
770 /* This field is interpreted differently based on the type of TRB */
771 u32 flags;
98441973 772};
0ebbab37 773
d0e96f5a
SS		 774/** Transfer Event bit fields **/
775#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
776
0ebbab37
SS		 777/* Completion Code - only applicable for some types of TRBs */
778#define COMP_CODE_MASK (0xff << 24)
779#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
780#define COMP_SUCCESS 1
781/* Data Buffer Error */
782#define COMP_DB_ERR 2
783/* Babble Detected Error */
784#define COMP_BABBLE 3
785/* USB Transaction Error */
786#define COMP_TX_ERR 4
787/* TRB Error - some TRB field is invalid */
788#define COMP_TRB_ERR 5
789/* Stall Error - USB device is stalled */
790#define COMP_STALL 6
791/* Resource Error - HC doesn't have memory for that device configuration */
792#define COMP_ENOMEM 7
793/* Bandwidth Error - not enough room in schedule for this dev config */
794#define COMP_BW_ERR 8
795/* No Slots Available Error - HC ran out of device slots */
796#define COMP_ENOSLOTS 9
797/* Invalid Stream Type Error */
798#define COMP_STREAM_ERR 10
799/* Slot Not Enabled Error - doorbell rung for disabled device slot */
800#define COMP_EBADSLT 11
801/* Endpoint Not Enabled Error */
802#define COMP_EBADEP 12
803/* Short Packet */
804#define COMP_SHORT_TX 13
805/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
806#define COMP_UNDERRUN 14
807/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
808#define COMP_OVERRUN 15
809/* Virtual Function Event Ring Full Error */
810#define COMP_VF_FULL 16
811/* Parameter Error - Context parameter is invalid */
812#define COMP_EINVAL 17
813/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
814#define COMP_BW_OVER 18
815/* Context State Error - illegal context state transition requested */
816#define COMP_CTX_STATE 19
817/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
818#define COMP_PING_ERR 20
819/* Event Ring is full */
820#define COMP_ER_FULL 21
821/* Missed Service Error - HC couldn't service an isoc ep within interval */
822#define COMP_MISSED_INT 23
823/* Successfully stopped command ring */
824#define COMP_CMD_STOP 24
825/* Successfully aborted current command and stopped command ring */
826#define COMP_CMD_ABORT 25
827/* Stopped - transfer was terminated by a stop endpoint command */
828#define COMP_STOP 26
829/* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */
830#define COMP_STOP_INVAL 27
831/* Control Abort Error - Debug Capability - control pipe aborted */
832#define COMP_DBG_ABORT 28
833/* TRB type 29 and 30 reserved */
834/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
835#define COMP_BUFF_OVER 31
836/* Event Lost Error - xHC has an "internal event overrun condition" */
837#define COMP_ISSUES 32
838/* Undefined Error - reported when other error codes don't apply */
839#define COMP_UNKNOWN 33
840/* Invalid Stream ID Error */
841#define COMP_STRID_ERR 34
842/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
843/* FIXME - check for this */
844#define COMP_2ND_BW_ERR 35
845/* Split Transaction Error */
846#define COMP_SPLIT_ERR 36
847
848struct xhci_link_trb {
849 /* 64-bit segment pointer*/
8e595a5d 850 u64 segment_ptr;
0ebbab37
SS		 851 u32 intr_target;
852 u32 control;
98441973 853};
0ebbab37
SS		 854
855/* control bitfields */
856#define LINK_TOGGLE (0x1<<1)
857
7f84eef0
SS		 858/* Command completion event TRB */
859struct xhci_event_cmd {
860 /* Pointer to command TRB, or the value passed by the event data trb */
8e595a5d 861 u64 cmd_trb;
7f84eef0
SS		 862 u32 status;
863 u32 flags;
98441973 864};
0ebbab37 865
3ffbba95
SS		 866/* flags bitmasks */
867/* bits 16:23 are the virtual function ID */
868/* bits 24:31 are the slot ID */
869#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
870#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
0ebbab37 871
ae636747
SS		 872/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
873#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
874#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
875
e9df17eb
SS		 876/* Set TR Dequeue Pointer command TRB fields */
877#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
878#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
879
ae636747 880
0f2a7930
SS		 881/* Port Status Change Event TRB fields */
882/* Port ID - bits 31:24 */
883#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
884
0ebbab37
SS		 885/* Normal TRB fields */
886/* transfer_len bitmasks - bits 0:16 */
887#define TRB_LEN(p) ((p) & 0x1ffff)
0ebbab37
SS		 888/* Interrupter Target - which MSI-X vector to target the completion event at */
889#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
890#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
891
892/* Cycle bit - indicates TRB ownership by HC or HCD */
893#define TRB_CYCLE (1<<0)
894/*
895 * Force next event data TRB to be evaluated before task switch.
896 * Used to pass OS data back after a TD completes.
897 */
898#define TRB_ENT (1<<1)
899/* Interrupt on short packet */
900#define TRB_ISP (1<<2)
901/* Set PCIe no snoop attribute */
902#define TRB_NO_SNOOP (1<<3)
903/* Chain multiple TRBs into a TD */
904#define TRB_CHAIN (1<<4)
905/* Interrupt on completion */
906#define TRB_IOC (1<<5)
907/* The buffer pointer contains immediate data */
908#define TRB_IDT (1<<6)
909
910
911/* Control transfer TRB specific fields */
912#define TRB_DIR_IN (1<<16)
913
7f84eef0
SS		 914struct xhci_generic_trb {
915 u32 field[4];
98441973 916};
7f84eef0
SS		 917
918union xhci_trb {
919 struct xhci_link_trb link;
920 struct xhci_transfer_event trans_event;
921 struct xhci_event_cmd event_cmd;
922 struct xhci_generic_trb generic;
923};
924
0ebbab37
SS		 925/* TRB bit mask */
926#define TRB_TYPE_BITMASK (0xfc00)
927#define TRB_TYPE(p) ((p) << 10)
928/* TRB type IDs */
929/* bulk, interrupt, isoc scatter/gather, and control data stage */
930#define TRB_NORMAL 1
931/* setup stage for control transfers */
932#define TRB_SETUP 2
933/* data stage for control transfers */
934#define TRB_DATA 3
935/* status stage for control transfers */
936#define TRB_STATUS 4
937/* isoc transfers */
938#define TRB_ISOC 5
939/* TRB for linking ring segments */
940#define TRB_LINK 6
941#define TRB_EVENT_DATA 7
942/* Transfer Ring No-op (not for the command ring) */
943#define TRB_TR_NOOP 8
944/* Command TRBs */
945/* Enable Slot Command */
946#define TRB_ENABLE_SLOT 9
947/* Disable Slot Command */
948#define TRB_DISABLE_SLOT 10
949/* Address Device Command */
950#define TRB_ADDR_DEV 11
951/* Configure Endpoint Command */
952#define TRB_CONFIG_EP 12
953/* Evaluate Context Command */
954#define TRB_EVAL_CONTEXT 13
a1587d97
SS		 955/* Reset Endpoint Command */
956#define TRB_RESET_EP 14
0ebbab37
SS		 957/* Stop Transfer Ring Command */
958#define TRB_STOP_RING 15
959/* Set Transfer Ring Dequeue Pointer Command */
960#define TRB_SET_DEQ 16
961/* Reset Device Command */
962#define TRB_RESET_DEV 17
963/* Force Event Command (opt) */
964#define TRB_FORCE_EVENT 18
965/* Negotiate Bandwidth Command (opt) */
966#define TRB_NEG_BANDWIDTH 19
967/* Set Latency Tolerance Value Command (opt) */
968#define TRB_SET_LT 20
969/* Get port bandwidth Command */
970#define TRB_GET_BW 21
971/* Force Header Command - generate a transaction or link management packet */
972#define TRB_FORCE_HEADER 22
973/* No-op Command - not for transfer rings */
974#define TRB_CMD_NOOP 23
975/* TRB IDs 24-31 reserved */
976/* Event TRBS */
977/* Transfer Event */
978#define TRB_TRANSFER 32
979/* Command Completion Event */
980#define TRB_COMPLETION 33
981/* Port Status Change Event */
982#define TRB_PORT_STATUS 34
983/* Bandwidth Request Event (opt) */
984#define TRB_BANDWIDTH_EVENT 35
985/* Doorbell Event (opt) */
986#define TRB_DOORBELL 36
987/* Host Controller Event */
988#define TRB_HC_EVENT 37
989/* Device Notification Event - device sent function wake notification */
990#define TRB_DEV_NOTE 38
991/* MFINDEX Wrap Event - microframe counter wrapped */
992#define TRB_MFINDEX_WRAP 39
993/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
994
995/*
996 * TRBS_PER_SEGMENT must be a multiple of 4,
997 * since the command ring is 64-byte aligned.
998 * It must also be greater than 16.
999 */
1000#define TRBS_PER_SEGMENT 64
913a8a34
SS		 1001/* Allow two commands + a link TRB, along with any reserved command TRBs */
1002#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
0ebbab37 1003#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
8df75f42
SS		 1004/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
1005 * Change this if you change TRBS_PER_SEGMENT!
1006 */
1007#define SEGMENT_SHIFT 10
b10de142
SS		 1008/* TRB buffer pointers can't cross 64KB boundaries */
1009#define TRB_MAX_BUFF_SHIFT 16
1010#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
0ebbab37
SS		 1011
1012struct xhci_segment {
1013 union xhci_trb *trbs;
1014 /* private to HCD */
1015 struct xhci_segment *next;
1016 dma_addr_t dma;
98441973 1017};
0ebbab37 1018
ae636747
SS		 1019struct xhci_td {
1020 struct list_head td_list;
1021 struct list_head cancelled_td_list;
1022 struct urb *urb;
1023 struct xhci_segment *start_seg;
1024 union xhci_trb *first_trb;
1025 union xhci_trb *last_trb;
1026};
1027
ac9d8fe7
SS		 1028struct xhci_dequeue_state {
1029 struct xhci_segment *new_deq_seg;
1030 union xhci_trb *new_deq_ptr;
1031 int new_cycle_state;
1032};
1033
0ebbab37
SS		 1034struct xhci_ring {
1035 struct xhci_segment *first_seg;
1036 union xhci_trb *enqueue;
7f84eef0
SS		 1037 struct xhci_segment *enq_seg;
1038 unsigned int enq_updates;
0ebbab37 1039 union xhci_trb *dequeue;
7f84eef0
SS		 1040 struct xhci_segment *deq_seg;
1041 unsigned int deq_updates;
d0e96f5a 1042 struct list_head td_list;
0ebbab37
SS		 1043 /*
1044 * Write the cycle state into the TRB cycle field to give ownership of
1045 * the TRB to the host controller (if we are the producer), or to check
1046 * if we own the TRB (if we are the consumer). See section 4.9.1.
1047 */
1048 u32 cycle_state;
e9df17eb 1049 unsigned int stream_id;
0ebbab37
SS		 1050};
1051
1052struct xhci_erst_entry {
1053 /* 64-bit event ring segment address */
8e595a5d 1054 u64 seg_addr;
0ebbab37
SS		 1055 u32 seg_size;
1056 /* Set to zero */
1057 u32 rsvd;
98441973 1058};
0ebbab37
SS		 1059
1060struct xhci_erst {
1061 struct xhci_erst_entry *entries;
1062 unsigned int num_entries;
1063 /* xhci->event_ring keeps track of segment dma addresses */
1064 dma_addr_t erst_dma_addr;
1065 /* Num entries the ERST can contain */
1066 unsigned int erst_size;
1067};
1068
254c80a3
JY		 1069struct xhci_scratchpad {
1070 u64 *sp_array;
1071 dma_addr_t sp_dma;
1072 void **sp_buffers;
1073 dma_addr_t *sp_dma_buffers;
1074};
1075
0ebbab37
SS		 1076/*
1077 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1078 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1079 * meaning 64 ring segments.
1080 * Initial allocated size of the ERST, in number of entries */
1081#define ERST_NUM_SEGS 1
1082/* Initial allocated size of the ERST, in number of entries */
1083#define ERST_SIZE 64
1084/* Initial number of event segment rings allocated */
1085#define ERST_ENTRIES 1
7f84eef0
SS		 1086/* Poll every 60 seconds */
1087#define POLL_TIMEOUT 60
6f5165cf
SS		 1088/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1089#define XHCI_STOP_EP_CMD_TIMEOUT 5
0ebbab37
SS		 1090/* XXX: Make these module parameters */
1091
74c68741
SS		 1092
1093/* There is one ehci_hci structure per controller */
1094struct xhci_hcd {
1095 /* glue to PCI and HCD framework */
1096 struct xhci_cap_regs __iomem *cap_regs;
1097 struct xhci_op_regs __iomem *op_regs;
1098 struct xhci_run_regs __iomem *run_regs;
0ebbab37 1099 struct xhci_doorbell_array __iomem *dba;
66d4eadd 1100 /* Our HCD's current interrupter register set */
98441973 1101 struct xhci_intr_reg __iomem *ir_set;
74c68741
SS		 1102
1103 /* Cached register copies of read-only HC data */
1104 __u32 hcs_params1;
1105 __u32 hcs_params2;
1106 __u32 hcs_params3;
1107 __u32 hcc_params;
1108
1109 spinlock_t lock;
1110
1111 /* packed release number */
1112 u8 sbrn;
1113 u16 hci_version;
1114 u8 max_slots;
1115 u8 max_interrupters;
1116 u8 max_ports;
1117 u8 isoc_threshold;
1118 int event_ring_max;
1119 int addr_64;
66d4eadd 1120 /* 4KB min, 128MB max */
74c68741 1121 int page_size;
66d4eadd
SS		 1122 /* Valid values are 12 to 20, inclusive */
1123 int page_shift;
1124 /* only one MSI vector for now, but might need more later */
1125 int msix_count;
1126 struct msix_entry *msix_entries;
0ebbab37 1127 /* data structures */
a74588f9 1128 struct xhci_device_context_array *dcbaa;
0ebbab37 1129 struct xhci_ring *cmd_ring;
913a8a34 1130 unsigned int cmd_ring_reserved_trbs;
0ebbab37
SS		 1131 struct xhci_ring *event_ring;
1132 struct xhci_erst erst;
254c80a3
JY		 1133 /* Scratchpad */
1134 struct xhci_scratchpad *scratchpad;
1135
3ffbba95
SS		 1136 /* slot enabling and address device helpers */
1137 struct completion addr_dev;
1138 int slot_id;
1139 /* Internal mirror of the HW's dcbaa */
1140 struct xhci_virt_device *devs[MAX_HC_SLOTS];
0ebbab37
SS		 1141
1142 /* DMA pools */
1143 struct dma_pool *device_pool;
1144 struct dma_pool *segment_pool;
8df75f42
SS		 1145 struct dma_pool *small_streams_pool;
1146 struct dma_pool *medium_streams_pool;
7f84eef0
SS		 1147
1148#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1149 /* Poll the rings - for debugging */
1150 struct timer_list event_ring_timer;
1151 int zombie;
1152#endif
6f5165cf
SS		 1153 /* Host controller watchdog timer structures */
1154 unsigned int xhc_state;
1155/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1156 *
1157 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1158 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1159 * that sees this status (other than the timer that set it) should stop touching
1160 * hardware immediately. Interrupt handlers should return immediately when
1161 * they see this status (any time they drop and re-acquire xhci->lock).
1162 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1163 * putting the TD on the canceled list, etc.
1164 *
1165 * There are no reports of xHCI host controllers that display this issue.
1166 */
1167#define XHCI_STATE_DYING (1 << 0)
7f84eef0
SS		 1168 /* Statistics */
1169 int noops_submitted;
1170 int noops_handled;
1171 int error_bitmask;
b0567b3f
SS		 1172 unsigned int quirks;
1173#define XHCI_LINK_TRB_QUIRK (1 << 0)
ac9d8fe7 1174#define XHCI_RESET_EP_QUIRK (1 << 1)
74c68741
SS		 1175};
1176
7f84eef0
SS		 1177/* For testing purposes */
1178#define NUM_TEST_NOOPS 0
1179
74c68741
SS		 1180/* convert between an HCD pointer and the corresponding EHCI_HCD */
1181static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1182{
1183 return (struct xhci_hcd *) (hcd->hcd_priv);
1184}
1185
1186static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1187{
1188 return container_of((void *) xhci, struct usb_hcd, hcd_priv);
1189}
1190
1191#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1192#define XHCI_DEBUG 1
1193#else
1194#define XHCI_DEBUG 0
1195#endif
1196
1197#define xhci_dbg(xhci, fmt, args...) \
1198 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1199#define xhci_info(xhci, fmt, args...) \
1200 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1201#define xhci_err(xhci, fmt, args...) \
1202 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1203#define xhci_warn(xhci, fmt, args...) \
1204 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1205
1206/* TODO: copied from ehci.h - can be refactored? */
1207/* xHCI spec says all registers are little endian */
1208static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1209 __u32 __iomem *regs)
1210{
1211 return readl(regs);
1212}
045f123d 1213static inline void xhci_writel(struct xhci_hcd *xhci,
74c68741
SS		 1214 const unsigned int val, __u32 __iomem *regs)
1215{
66e49d87
SS		 1216 xhci_dbg(xhci,
1217 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
1218 regs, val);
74c68741
SS		 1219 writel(val, regs);
1220}
1221
8e595a5d
SS		 1222/*
1223 * Registers should always be accessed with double word or quad word accesses.
1224 *
1225 * Some xHCI implementations may support 64-bit address pointers. Registers
1226 * with 64-bit address pointers should be written to with dword accesses by
1227 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1228 * xHCI implementations that do not support 64-bit address pointers will ignore
1229 * the high dword, and write order is irrelevant.
1230 */
1231static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1232 __u64 __iomem *regs)
1233{
1234 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1235 u64 val_lo = readl(ptr);
1236 u64 val_hi = readl(ptr + 1);
1237 return val_lo + (val_hi << 32);
1238}
1239static inline void xhci_write_64(struct xhci_hcd *xhci,
1240 const u64 val, __u64 __iomem *regs)
1241{
1242 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1243 u32 val_lo = lower_32_bits(val);
1244 u32 val_hi = upper_32_bits(val);
1245
66e49d87
SS		 1246 xhci_dbg(xhci,
1247 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
1248 regs, (long unsigned int) val);
8e595a5d
SS		 1249 writel(val_lo, ptr);
1250 writel(val_hi, ptr + 1);
1251}
1252
b0567b3f
SS		 1253static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1254{
1255 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
1256 return ((HC_VERSION(temp) == 0x95) &&
1257 (xhci->quirks & XHCI_LINK_TRB_QUIRK));
1258}
1259
66d4eadd 1260/* xHCI debugging */
98441973 1261void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
66d4eadd 1262void xhci_print_registers(struct xhci_hcd *xhci);
0ebbab37
SS		 1263void xhci_dbg_regs(struct xhci_hcd *xhci);
1264void xhci_print_run_regs(struct xhci_hcd *xhci);
d0e96f5a
SS		 1265void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1266void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
7f84eef0 1267void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
0ebbab37
SS		 1268void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1269void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1270void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
7f84eef0 1271void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
d115b048 1272void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
9c9a7dbf 1273char *xhci_get_slot_state(struct xhci_hcd *xhci,
2a8f82c4 1274 struct xhci_container_ctx *ctx);
e9df17eb
SS		 1275void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1276 unsigned int slot_id, unsigned int ep_index,
1277 struct xhci_virt_ep *ep);
66d4eadd 1278
3dbda77e 1279/* xHCI memory management */
66d4eadd
SS		 1280void xhci_mem_cleanup(struct xhci_hcd *xhci);
1281int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
3ffbba95
SS		 1282void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1283int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1284int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
d0e96f5a 1285unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
f94e0186 1286unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
ac9d8fe7
SS		 1287unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1288unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
f94e0186 1289void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
f2217e8e 1290void xhci_endpoint_copy(struct xhci_hcd *xhci,
913a8a34
SS		 1291 struct xhci_container_ctx *in_ctx,
1292 struct xhci_container_ctx *out_ctx,
1293 unsigned int ep_index);
1294void xhci_slot_copy(struct xhci_hcd *xhci,
1295 struct xhci_container_ctx *in_ctx,
1296 struct xhci_container_ctx *out_ctx);
f88ba78d
SS		 1297int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1298 struct usb_device *udev, struct usb_host_endpoint *ep,
1299 gfp_t mem_flags);
f94e0186 1300void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
412566bd
SS		 1301void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1302 struct xhci_virt_device *virt_dev,
1303 unsigned int ep_index);
8df75f42
SS		 1304struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1305 unsigned int num_stream_ctxs,
1306 unsigned int num_streams, gfp_t flags);
1307void xhci_free_stream_info(struct xhci_hcd *xhci,
1308 struct xhci_stream_info *stream_info);
1309void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1310 struct xhci_ep_ctx *ep_ctx,
1311 struct xhci_stream_info *stream_info);
1312void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1313 struct xhci_ep_ctx *ep_ctx,
1314 struct xhci_virt_ep *ep);
e9df17eb
SS		 1315struct xhci_ring *xhci_dma_to_transfer_ring(
1316 struct xhci_virt_ep *ep,
1317 u64 address);
1318struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1319 struct urb *urb);
1320struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1321 unsigned int slot_id, unsigned int ep_index,
1322 unsigned int stream_id);
1323struct xhci_ring *xhci_stream_id_to_ring(
1324 struct xhci_virt_device *dev,
1325 unsigned int ep_index,
1326 unsigned int stream_id);
913a8a34 1327struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
a1d78c16
SS		 1328 bool allocate_in_ctx, bool allocate_completion,
1329 gfp_t mem_flags);
913a8a34
SS		 1330void xhci_free_command(struct xhci_hcd *xhci,
1331 struct xhci_command *command);
66d4eadd
SS		 1332
1333#ifdef CONFIG_PCI
1334/* xHCI PCI glue */
1335int xhci_register_pci(void);
1336void xhci_unregister_pci(void);
1337#endif
1338
1339/* xHCI host controller glue */
4f0f0bae 1340void xhci_quiesce(struct xhci_hcd *xhci);
66d4eadd
SS		 1341int xhci_halt(struct xhci_hcd *xhci);
1342int xhci_reset(struct xhci_hcd *xhci);
1343int xhci_init(struct usb_hcd *hcd);
1344int xhci_run(struct usb_hcd *hcd);
1345void xhci_stop(struct usb_hcd *hcd);
1346void xhci_shutdown(struct usb_hcd *hcd);
1347int xhci_get_frame(struct usb_hcd *hcd);
7f84eef0 1348irqreturn_t xhci_irq(struct usb_hcd *hcd);
3ffbba95
SS		 1349int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1350void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
8df75f42
SS		 1351int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1352 struct usb_host_endpoint **eps, unsigned int num_eps,
1353 unsigned int num_streams, gfp_t mem_flags);
1354int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1355 struct usb_host_endpoint **eps, unsigned int num_eps,
1356 gfp_t mem_flags);
3ffbba95 1357int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
ac1c1b7f
SS		 1358int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1359 struct usb_tt *tt, gfp_t mem_flags);
d0e96f5a
SS		 1360int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1361int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
f94e0186
SS		 1362int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1363int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
a1587d97 1364void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
a5f0efab 1365int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
f94e0186
SS		 1366int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1367void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
7f84eef0
SS		 1368
1369/* xHCI ring, segment, TRB, and TD functions */
23e3be11 1370dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
6648f29d
SS		 1371struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1372 union xhci_trb *start_trb, union xhci_trb *end_trb,
1373 dma_addr_t suspect_dma);
b45b5069 1374int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
23e3be11
SS		 1375void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1376void *xhci_setup_one_noop(struct xhci_hcd *xhci);
b7258a4a 1377void xhci_handle_event(struct xhci_hcd *xhci);
23e3be11
SS		 1378void xhci_set_hc_event_deq(struct xhci_hcd *xhci);
1379int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1380int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1381 u32 slot_id);
1382int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
ae636747 1383 unsigned int ep_index);
23e3be11
SS		 1384int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1385 int slot_id, unsigned int ep_index);
1386int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1387 int slot_id, unsigned int ep_index);
624defa1
SS		 1388int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1389 int slot_id, unsigned int ep_index);
23e3be11 1390int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
913a8a34 1391 u32 slot_id, bool command_must_succeed);
f2217e8e 1392int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
23e3be11 1393 u32 slot_id);
a1587d97
SS		 1394int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1395 unsigned int ep_index);
2a8f82c4 1396int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
c92bcfa7
SS		 1397void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1398 unsigned int slot_id, unsigned int ep_index,
e9df17eb
SS		 1399 unsigned int stream_id, struct xhci_td *cur_td,
1400 struct xhci_dequeue_state *state);
c92bcfa7 1401void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
63a0d9ab 1402 unsigned int slot_id, unsigned int ep_index,
e9df17eb 1403 unsigned int stream_id,
63a0d9ab 1404 struct xhci_dequeue_state *deq_state);
82d1009f 1405void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
63a0d9ab 1406 struct usb_device *udev, unsigned int ep_index);
ac9d8fe7
SS		 1407void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1408 unsigned int slot_id, unsigned int ep_index,
1409 struct xhci_dequeue_state *deq_state);
6f5165cf 1410void xhci_stop_endpoint_command_watchdog(unsigned long arg);
66d4eadd 1411
0f2a7930
SS		 1412/* xHCI roothub code */
1413int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1414 char *buf, u16 wLength);
1415int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1416
d115b048
JY		 1417/* xHCI contexts */
1418struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1419struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1420struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1421
74c68741 1422#endif /* __LINUX_XHCI_HCD_H */
Linux 6.x block layer and io_uring tree(s)