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xHCI: set link state
[linux-2.6-block.git] / drivers / usb / host / xhci.h
CommitLineData
74c68741
SS		 1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __LINUX_XHCI_HCD_H
24#define __LINUX_XHCI_HCD_H
25
26#include <linux/usb.h>
7f84eef0 27#include <linux/timer.h>
8e595a5d 28#include <linux/kernel.h>
27729aad 29#include <linux/usb/hcd.h>
74c68741 30
74c68741
SS		 31/* Code sharing between pci-quirks and xhci hcd */
32#include "xhci-ext-caps.h"
c41136b0 33#include "pci-quirks.h"
74c68741
SS		 34
35/* xHCI PCI Configuration Registers */
36#define XHCI_SBRN_OFFSET (0x60)
37
66d4eadd
SS		 38/* Max number of USB devices for any host controller - limit in section 6.1 */
39#define MAX_HC_SLOTS 256
0f2a7930
SS		 40/* Section 5.3.3 - MaxPorts */
41#define MAX_HC_PORTS 127
66d4eadd 42
74c68741
SS		 43/*
44 * xHCI register interface.
45 * This corresponds to the eXtensible Host Controller Interface (xHCI)
46 * Revision 0.95 specification
74c68741
SS		 47 */
48
49/**
50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
51 * @hc_capbase: length of the capabilities register and HC version number
52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
55 * @hcc_params: HCCPARAMS - Capability Parameters
56 * @db_off: DBOFF - Doorbell array offset
57 * @run_regs_off: RTSOFF - Runtime register space offset
58 */
59struct xhci_cap_regs {
28ccd296
ME		 60 __le32 hc_capbase;
61 __le32 hcs_params1;
62 __le32 hcs_params2;
63 __le32 hcs_params3;
64 __le32 hcc_params;
65 __le32 db_off;
66 __le32 run_regs_off;
74c68741 67 /* Reserved up to (CAPLENGTH - 0x1C) */
98441973 68};
74c68741
SS		 69
70/* hc_capbase bitmasks */
71/* bits 7:0 - how long is the Capabilities register */
72#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73/* bits 31:16 */
74#define HC_VERSION(p) (((p) >> 16) & 0xffff)
75
76/* HCSPARAMS1 - hcs_params1 - bitmasks */
77/* bits 0:7, Max Device Slots */
78#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
79#define HCS_SLOTS_MASK 0xff
80/* bits 8:18, Max Interrupters */
81#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
82/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
83#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84
85/* HCSPARAMS2 - hcs_params2 - bitmasks */
86/* bits 0:3, frames or uframes that SW needs to queue transactions
87 * ahead of the HW to meet periodic deadlines */
88#define HCS_IST(p) (((p) >> 0) & 0xf)
89/* bits 4:7, max number of Event Ring segments */
90#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
91/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
92/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
254c80a3 93#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
74c68741
SS		 94
95/* HCSPARAMS3 - hcs_params3 - bitmasks */
96/* bits 0:7, Max U1 to U0 latency for the roothub ports */
97#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
98/* bits 16:31, Max U2 to U0 latency for the roothub ports */
99#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100
101/* HCCPARAMS - hcc_params - bitmasks */
102/* true: HC can use 64-bit address pointers */
103#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
104/* true: HC can do bandwidth negotiation */
105#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
106/* true: HC uses 64-byte Device Context structures
107 * FIXME 64-byte context structures aren't supported yet.
108 */
109#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
110/* true: HC has port power switches */
111#define HCC_PPC(p) ((p) & (1 << 3))
112/* true: HC has port indicators */
113#define HCS_INDICATOR(p) ((p) & (1 << 4))
114/* true: HC has Light HC Reset Capability */
115#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
116/* true: HC supports latency tolerance messaging */
117#define HCC_LTC(p) ((p) & (1 << 6))
118/* true: no secondary Stream ID Support */
119#define HCC_NSS(p) ((p) & (1 << 7))
120/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
8df75f42 121#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
74c68741
SS		 122/* Extended Capabilities pointer from PCI base - section 5.3.6 */
123#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125/* db_off bitmask - bits 0:1 reserved */
126#define DBOFF_MASK (~0x3)
127
128/* run_regs_off bitmask - bits 0:4 reserved */
129#define RTSOFF_MASK (~0x1f)
130
131
132/* Number of registers per port */
133#define NUM_PORT_REGS 4
134
135/**
136 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
137 * @command: USBCMD - xHC command register
138 * @status: USBSTS - xHC status register
139 * @page_size: This indicates the page size that the host controller
140 * supports. If bit n is set, the HC supports a page size
141 * of 2^(n+12), up to a 128MB page size.
142 * 4K is the minimum page size.
143 * @cmd_ring: CRP - 64-bit Command Ring Pointer
144 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
145 * @config_reg: CONFIG - Configure Register
146 * @port_status_base: PORTSCn - base address for Port Status and Control
147 * Each port has a Port Status and Control register,
148 * followed by a Port Power Management Status and Control
149 * register, a Port Link Info register, and a reserved
150 * register.
151 * @port_power_base: PORTPMSCn - base address for
152 * Port Power Management Status and Control
153 * @port_link_base: PORTLIn - base address for Port Link Info (current
154 * Link PM state and control) for USB 2.1 and USB 3.0
155 * devices.
156 */
157struct xhci_op_regs {
28ccd296
ME		 158 __le32 command;
159 __le32 status;
160 __le32 page_size;
161 __le32 reserved1;
162 __le32 reserved2;
163 __le32 dev_notification;
164 __le64 cmd_ring;
74c68741 165 /* rsvd: offset 0x20-2F */
28ccd296
ME		 166 __le32 reserved3[4];
167 __le64 dcbaa_ptr;
168 __le32 config_reg;
74c68741 169 /* rsvd: offset 0x3C-3FF */
28ccd296 170 __le32 reserved4[241];
74c68741 171 /* port 1 registers, which serve as a base address for other ports */
28ccd296
ME		 172 __le32 port_status_base;
173 __le32 port_power_base;
174 __le32 port_link_base;
175 __le32 reserved5;
74c68741 176 /* registers for ports 2-255 */
28ccd296 177 __le32 reserved6[NUM_PORT_REGS*254];
98441973 178};
74c68741
SS		 179
180/* USBCMD - USB command - command bitmasks */
181/* start/stop HC execution - do not write unless HC is halted*/
182#define CMD_RUN XHCI_CMD_RUN
183/* Reset HC - resets internal HC state machine and all registers (except
184 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
185 * The xHCI driver must reinitialize the xHC after setting this bit.
186 */
187#define CMD_RESET (1 << 1)
188/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
189#define CMD_EIE XHCI_CMD_EIE
190/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
191#define CMD_HSEIE XHCI_CMD_HSEIE
192/* bits 4:6 are reserved (and should be preserved on writes). */
193/* light reset (port status stays unchanged) - reset completed when this is 0 */
194#define CMD_LRESET (1 << 7)
5535b1d5 195/* host controller save/restore state. */
74c68741
SS		 196#define CMD_CSS (1 << 8)
197#define CMD_CRS (1 << 9)
198/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
199#define CMD_EWE XHCI_CMD_EWE
200/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
201 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
202 * '0' means the xHC can power it off if all ports are in the disconnect,
203 * disabled, or powered-off state.
204 */
205#define CMD_PM_INDEX (1 << 11)
206/* bits 12:31 are reserved (and should be preserved on writes). */
207
208/* USBSTS - USB status - status bitmasks */
209/* HC not running - set to 1 when run/stop bit is cleared. */
210#define STS_HALT XHCI_STS_HALT
211/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
212#define STS_FATAL (1 << 2)
213/* event interrupt - clear this prior to clearing any IP flags in IR set*/
214#define STS_EINT (1 << 3)
215/* port change detect */
216#define STS_PORT (1 << 4)
217/* bits 5:7 reserved and zeroed */
218/* save state status - '1' means xHC is saving state */
219#define STS_SAVE (1 << 8)
220/* restore state status - '1' means xHC is restoring state */
221#define STS_RESTORE (1 << 9)
222/* true: save or restore error */
223#define STS_SRE (1 << 10)
224/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
225#define STS_CNR XHCI_STS_CNR
226/* true: internal Host Controller Error - SW needs to reset and reinitialize */
227#define STS_HCE (1 << 12)
228/* bits 13:31 reserved and should be preserved */
229
230/*
231 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
232 * Generate a device notification event when the HC sees a transaction with a
233 * notification type that matches a bit set in this bit field.
234 */
235#define DEV_NOTE_MASK (0xffff)
5a6c2f3f 236#define ENABLE_DEV_NOTE(x) (1 << (x))
74c68741
SS		 237/* Most of the device notification types should only be used for debug.
238 * SW does need to pay attention to function wake notifications.
239 */
240#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
241
0ebbab37
SS		 242/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
243/* bit 0 is the command ring cycle state */
244/* stop ring operation after completion of the currently executing command */
245#define CMD_RING_PAUSE (1 << 1)
246/* stop ring immediately - abort the currently executing command */
247#define CMD_RING_ABORT (1 << 2)
248/* true: command ring is running */
249#define CMD_RING_RUNNING (1 << 3)
250/* bits 4:5 reserved and should be preserved */
251/* Command Ring pointer - bit mask for the lower 32 bits. */
8e595a5d 252#define CMD_RING_RSVD_BITS (0x3f)
0ebbab37 253
74c68741
SS		 254/* CONFIG - Configure Register - config_reg bitmasks */
255/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
256#define MAX_DEVS(p) ((p) & 0xff)
257/* bits 8:31 - reserved and should be preserved */
258
259/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
260/* true: device connected */
261#define PORT_CONNECT (1 << 0)
262/* true: port enabled */
263#define PORT_PE (1 << 1)
264/* bit 2 reserved and zeroed */
265/* true: port has an over-current condition */
266#define PORT_OC (1 << 3)
267/* true: port reset signaling asserted */
268#define PORT_RESET (1 << 4)
269/* Port Link State - bits 5:8
270 * A read gives the current link PM state of the port,
271 * a write with Link State Write Strobe set sets the link state.
272 */
be88fe4f
AX		 273#define PORT_PLS_MASK (0xf << 5)
274#define XDEV_U0 (0x0 << 5)
275#define XDEV_U3 (0x3 << 5)
276#define XDEV_RESUME (0xf << 5)
74c68741
SS		 277/* true: port has power (see HCC_PPC) */
278#define PORT_POWER (1 << 9)
279/* bits 10:13 indicate device speed:
280 * 0 - undefined speed - port hasn't be initialized by a reset yet
281 * 1 - full speed
282 * 2 - low speed
283 * 3 - high speed
284 * 4 - super speed
285 * 5-15 reserved
286 */
3ffbba95
SS		 287#define DEV_SPEED_MASK (0xf << 10)
288#define XDEV_FS (0x1 << 10)
289#define XDEV_LS (0x2 << 10)
290#define XDEV_HS (0x3 << 10)
291#define XDEV_SS (0x4 << 10)
74c68741 292#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
3ffbba95
SS		 293#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
294#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
295#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
296#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
297/* Bits 20:23 in the Slot Context are the speed for the device */
298#define SLOT_SPEED_FS (XDEV_FS << 10)
299#define SLOT_SPEED_LS (XDEV_LS << 10)
300#define SLOT_SPEED_HS (XDEV_HS << 10)
301#define SLOT_SPEED_SS (XDEV_SS << 10)
74c68741
SS		 302/* Port Indicator Control */
303#define PORT_LED_OFF (0 << 14)
304#define PORT_LED_AMBER (1 << 14)
305#define PORT_LED_GREEN (2 << 14)
306#define PORT_LED_MASK (3 << 14)
307/* Port Link State Write Strobe - set this when changing link state */
308#define PORT_LINK_STROBE (1 << 16)
309/* true: connect status change */
310#define PORT_CSC (1 << 17)
311/* true: port enable change */
312#define PORT_PEC (1 << 18)
313/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
314 * into an enabled state, and the device into the default state. A "warm" reset
315 * also resets the link, forcing the device through the link training sequence.
316 * SW can also look at the Port Reset register to see when warm reset is done.
317 */
318#define PORT_WRC (1 << 19)
319/* true: over-current change */
320#define PORT_OCC (1 << 20)
321/* true: reset change - 1 to 0 transition of PORT_RESET */
322#define PORT_RC (1 << 21)
323/* port link status change - set on some port link state transitions:
324 * Transition Reason
325 * ------------------------------------------------------------------------------
326 * - U3 to Resume Wakeup signaling from a device
327 * - Resume to Recovery to U0 USB 3.0 device resume
328 * - Resume to U0 USB 2.0 device resume
329 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
330 * - U3 to U0 Software resume of USB 2.0 device complete
331 * - U2 to U0 L1 resume of USB 2.1 device complete
332 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
333 * - U0 to disabled L1 entry error with USB 2.1 device
334 * - Any state to inactive Error on USB 3.0 port
335 */
336#define PORT_PLC (1 << 22)
337/* port configure error change - port failed to configure its link partner */
338#define PORT_CEC (1 << 23)
339/* bit 24 reserved */
340/* wake on connect (enable) */
341#define PORT_WKCONN_E (1 << 25)
342/* wake on disconnect (enable) */
343#define PORT_WKDISC_E (1 << 26)
344/* wake on over-current (enable) */
345#define PORT_WKOC_E (1 << 27)
346/* bits 28:29 reserved */
347/* true: device is removable - for USB 3.0 roothub emulation */
348#define PORT_DEV_REMOVE (1 << 30)
349/* Initiate a warm port reset - complete when PORT_WRC is '1' */
350#define PORT_WR (1 << 31)
351
22e04870
DC		 352/* We mark duplicate entries with -1 */
353#define DUPLICATE_ENTRY ((u8)(-1))
354
74c68741
SS		 355/* Port Power Management Status and Control - port_power_base bitmasks */
356/* Inactivity timer value for transitions into U1, in microseconds.
357 * Timeout can be up to 127us. 0xFF means an infinite timeout.
358 */
359#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
360/* Inactivity timer value for transitions into U2 */
361#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
362/* Bits 24:31 for port testing */
363
9777e3ce
AX		 364/* USB2 Protocol PORTSPMSC */
365#define PORT_RWE (1 << 0x3)
74c68741
SS		 366
367/**
98441973 368 * struct xhci_intr_reg - Interrupt Register Set
74c68741
SS		 369 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
370 * interrupts and check for pending interrupts.
371 * @irq_control: IMOD - Interrupt Moderation Register.
372 * Used to throttle interrupts.
373 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
374 * @erst_base: ERST base address.
375 * @erst_dequeue: Event ring dequeue pointer.
376 *
377 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
378 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
379 * multiple segments of the same size. The HC places events on the ring and
380 * "updates the Cycle bit in the TRBs to indicate to software the current
381 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
382 * updates the dequeue pointer.
383 */
98441973 384struct xhci_intr_reg {
28ccd296
ME		 385 __le32 irq_pending;
386 __le32 irq_control;
387 __le32 erst_size;
388 __le32 rsvd;
389 __le64 erst_base;
390 __le64 erst_dequeue;
98441973 391};
74c68741 392
66d4eadd 393/* irq_pending bitmasks */
74c68741 394#define ER_IRQ_PENDING(p) ((p) & 0x1)
66d4eadd 395/* bits 2:31 need to be preserved */
7f84eef0 396/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
66d4eadd
SS		 397#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
398#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
399#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
400
401/* irq_control bitmasks */
402/* Minimum interval between interrupts (in 250ns intervals). The interval
403 * between interrupts will be longer if there are no events on the event ring.
404 * Default is 4000 (1 ms).
405 */
406#define ER_IRQ_INTERVAL_MASK (0xffff)
407/* Counter used to count down the time to the next interrupt - HW use only */
408#define ER_IRQ_COUNTER_MASK (0xffff << 16)
409
410/* erst_size bitmasks */
74c68741 411/* Preserve bits 16:31 of erst_size */
66d4eadd
SS		 412#define ERST_SIZE_MASK (0xffff << 16)
413
414/* erst_dequeue bitmasks */
415/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
416 * where the current dequeue pointer lies. This is an optional HW hint.
417 */
418#define ERST_DESI_MASK (0x7)
419/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
420 * a work queue (or delayed service routine)?
421 */
422#define ERST_EHB (1 << 3)
0ebbab37 423#define ERST_PTR_MASK (0xf)
74c68741
SS		 424
425/**
426 * struct xhci_run_regs
427 * @microframe_index:
428 * MFINDEX - current microframe number
429 *
430 * Section 5.5 Host Controller Runtime Registers:
431 * "Software should read and write these registers using only Dword (32 bit)
432 * or larger accesses"
433 */
434struct xhci_run_regs {
28ccd296
ME		 435 __le32 microframe_index;
436 __le32 rsvd[7];
98441973
SS		 437 struct xhci_intr_reg ir_set[128];
438};
74c68741 439
0ebbab37
SS		 440/**
441 * struct doorbell_array
442 *
50d64676
MW		 443 * Bits 0 - 7: Endpoint target
444 * Bits 8 - 15: RsvdZ
445 * Bits 16 - 31: Stream ID
446 *
0ebbab37
SS		 447 * Section 5.6
448 */
449struct xhci_doorbell_array {
28ccd296 450 __le32 doorbell[256];
98441973 451};
0ebbab37 452
50d64676
MW		 453#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
454#define DB_VALUE_HOST 0x00000000
0ebbab37 455
da6699ce
SS		 456/**
457 * struct xhci_protocol_caps
458 * @revision: major revision, minor revision, capability ID,
459 * and next capability pointer.
460 * @name_string: Four ASCII characters to say which spec this xHC
461 * follows, typically "USB ".
462 * @port_info: Port offset, count, and protocol-defined information.
463 */
464struct xhci_protocol_caps {
465 u32 revision;
466 u32 name_string;
467 u32 port_info;
468};
469
470#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
471#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
472#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
473
d115b048
JY		 474/**
475 * struct xhci_container_ctx
476 * @type: Type of context. Used to calculated offsets to contained contexts.
477 * @size: Size of the context data
478 * @bytes: The raw context data given to HW
479 * @dma: dma address of the bytes
480 *
481 * Represents either a Device or Input context. Holds a pointer to the raw
482 * memory used for the context (bytes) and dma address of it (dma).
483 */
484struct xhci_container_ctx {
485 unsigned type;
486#define XHCI_CTX_TYPE_DEVICE 0x1
487#define XHCI_CTX_TYPE_INPUT 0x2
488
489 int size;
490
491 u8 *bytes;
492 dma_addr_t dma;
493};
494
a74588f9
SS		 495/**
496 * struct xhci_slot_ctx
497 * @dev_info: Route string, device speed, hub info, and last valid endpoint
498 * @dev_info2: Max exit latency for device number, root hub port number
499 * @tt_info: tt_info is used to construct split transaction tokens
500 * @dev_state: slot state and device address
501 *
502 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
503 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
504 * reserved at the end of the slot context for HC internal use.
505 */
506struct xhci_slot_ctx {
28ccd296
ME		 507 __le32 dev_info;
508 __le32 dev_info2;
509 __le32 tt_info;
510 __le32 dev_state;
a74588f9 511 /* offset 0x10 to 0x1f reserved for HC internal use */
28ccd296 512 __le32 reserved[4];
98441973 513};
a74588f9
SS		 514
515/* dev_info bitmasks */
516/* Route String - 0:19 */
517#define ROUTE_STRING_MASK (0xfffff)
518/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
519#define DEV_SPEED (0xf << 20)
520/* bit 24 reserved */
521/* Is this LS/FS device connected through a HS hub? - bit 25 */
522#define DEV_MTT (0x1 << 25)
523/* Set if the device is a hub - bit 26 */
524#define DEV_HUB (0x1 << 26)
525/* Index of the last valid endpoint context in this device context - 27:31 */
3ffbba95
SS		 526#define LAST_CTX_MASK (0x1f << 27)
527#define LAST_CTX(p) ((p) << 27)
528#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
3ffbba95
SS		 529#define SLOT_FLAG (1 << 0)
530#define EP0_FLAG (1 << 1)
a74588f9
SS		 531
532/* dev_info2 bitmasks */
533/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
534#define MAX_EXIT (0xffff)
535/* Root hub port number that is needed to access the USB device */
3ffbba95 536#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
be88fe4f 537#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
ac1c1b7f
SS		 538/* Maximum number of ports under a hub device */
539#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
a74588f9
SS		 540
541/* tt_info bitmasks */
542/*
543 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
544 * The Slot ID of the hub that isolates the high speed signaling from
545 * this low or full-speed device. '0' if attached to root hub port.
546 */
547#define TT_SLOT (0xff)
548/*
549 * The number of the downstream facing port of the high-speed hub
550 * '0' if the device is not low or full speed.
551 */
552#define TT_PORT (0xff << 8)
ac1c1b7f 553#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
a74588f9
SS		 554
555/* dev_state bitmasks */
556/* USB device address - assigned by the HC */
3ffbba95 557#define DEV_ADDR_MASK (0xff)
a74588f9
SS		 558/* bits 8:26 reserved */
559/* Slot state */
560#define SLOT_STATE (0x1f << 27)
ae636747 561#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
a74588f9 562
e2b02177
ML		 563#define SLOT_STATE_DISABLED 0
564#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
565#define SLOT_STATE_DEFAULT 1
566#define SLOT_STATE_ADDRESSED 2
567#define SLOT_STATE_CONFIGURED 3
a74588f9
SS		 568
569/**
570 * struct xhci_ep_ctx
571 * @ep_info: endpoint state, streams, mult, and interval information.
572 * @ep_info2: information on endpoint type, max packet size, max burst size,
573 * error count, and whether the HC will force an event for all
574 * transactions.
3ffbba95
SS		 575 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
576 * defines one stream, this points to the endpoint transfer ring.
577 * Otherwise, it points to a stream context array, which has a
578 * ring pointer for each flow.
579 * @tx_info:
580 * Average TRB lengths for the endpoint ring and
581 * max payload within an Endpoint Service Interval Time (ESIT).
a74588f9
SS		 582 *
583 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
584 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
585 * reserved at the end of the endpoint context for HC internal use.
586 */
587struct xhci_ep_ctx {
28ccd296
ME		 588 __le32 ep_info;
589 __le32 ep_info2;
590 __le64 deq;
591 __le32 tx_info;
a74588f9 592 /* offset 0x14 - 0x1f reserved for HC internal use */
28ccd296 593 __le32 reserved[3];
98441973 594};
a74588f9
SS		 595
596/* ep_info bitmasks */
597/*
598 * Endpoint State - bits 0:2
599 * 0 - disabled
600 * 1 - running
601 * 2 - halted due to halt condition - ok to manipulate endpoint ring
602 * 3 - stopped
603 * 4 - TRB error
604 * 5-7 - reserved
605 */
d0e96f5a
SS		 606#define EP_STATE_MASK (0xf)
607#define EP_STATE_DISABLED 0
608#define EP_STATE_RUNNING 1
609#define EP_STATE_HALTED 2
610#define EP_STATE_STOPPED 3
611#define EP_STATE_ERROR 4
a74588f9 612/* Mult - Max number of burtst within an interval, in EP companion desc. */
5a6c2f3f 613#define EP_MULT(p) (((p) & 0x3) << 8)
9af5d71d 614#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
a74588f9
SS		 615/* bits 10:14 are Max Primary Streams */
616/* bit 15 is Linear Stream Array */
617/* Interval - period between requests to an endpoint - 125u increments. */
5a6c2f3f 618#define EP_INTERVAL(p) (((p) & 0xff) << 16)
624defa1 619#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
9af5d71d 620#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
8df75f42
SS		 621#define EP_MAXPSTREAMS_MASK (0x1f << 10)
622#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
623/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
624#define EP_HAS_LSA (1 << 15)
a74588f9
SS		 625
626/* ep_info2 bitmasks */
627/*
628 * Force Event - generate transfer events for all TRBs for this endpoint
629 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
630 */
631#define FORCE_EVENT (0x1)
632#define ERROR_COUNT(p) (((p) & 0x3) << 1)
82d1009f 633#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
a74588f9
SS		 634#define EP_TYPE(p) ((p) << 3)
635#define ISOC_OUT_EP 1
636#define BULK_OUT_EP 2
637#define INT_OUT_EP 3
638#define CTRL_EP 4
639#define ISOC_IN_EP 5
640#define BULK_IN_EP 6
641#define INT_IN_EP 7
642/* bit 6 reserved */
643/* bit 7 is Host Initiate Disable - for disabling stream selection */
644#define MAX_BURST(p) (((p)&0xff) << 8)
9af5d71d 645#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
a74588f9 646#define MAX_PACKET(p) (((p)&0xffff) << 16)
2d3f1fac
SS		 647#define MAX_PACKET_MASK (0xffff << 16)
648#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
a74588f9 649
dc07c91b
AX		 650/* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
651 * USB2.0 spec 9.6.6.
652 */
653#define GET_MAX_PACKET(p) ((p) & 0x7ff)
654
9238f25d
SS		 655/* tx_info bitmasks */
656#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
657#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
9af5d71d 658#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
9238f25d 659
bf161e85
SS		 660/* deq bitmasks */
661#define EP_CTX_CYCLE_MASK (1 << 0)
662
a74588f9
SS		 663
664/**
d115b048
JY		 665 * struct xhci_input_control_context
666 * Input control context; see section 6.2.5.
a74588f9
SS		 667 *
668 * @drop_context: set the bit of the endpoint context you want to disable
669 * @add_context: set the bit of the endpoint context you want to enable
670 */
d115b048 671struct xhci_input_control_ctx {
28ccd296
ME		 672 __le32 drop_flags;
673 __le32 add_flags;
674 __le32 rsvd2[6];
98441973 675};
a74588f9 676
9af5d71d
SS		 677#define EP_IS_ADDED(ctrl_ctx, i) \
678 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
679#define EP_IS_DROPPED(ctrl_ctx, i) \
680 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
681
913a8a34
SS		 682/* Represents everything that is needed to issue a command on the command ring.
683 * It's useful to pre-allocate these for commands that cannot fail due to
684 * out-of-memory errors, like freeing streams.
685 */
686struct xhci_command {
687 /* Input context for changing device state */
688 struct xhci_container_ctx *in_ctx;
689 u32 status;
690 /* If completion is null, no one is waiting on this command
691 * and the structure can be freed after the command completes.
692 */
693 struct completion *completion;
694 union xhci_trb *command_trb;
695 struct list_head cmd_list;
696};
697
a74588f9
SS		 698/* drop context bitmasks */
699#define DROP_EP(x) (0x1 << x)
700/* add context bitmasks */
701#define ADD_EP(x) (0x1 << x)
702
8df75f42
SS		 703struct xhci_stream_ctx {
704 /* 64-bit stream ring address, cycle state, and stream type */
28ccd296 705 __le64 stream_ring;
8df75f42 706 /* offset 0x14 - 0x1f reserved for HC internal use */
28ccd296 707 __le32 reserved[2];
8df75f42
SS		 708};
709
710/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
711#define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
712/* Secondary stream array type, dequeue pointer is to a transfer ring */
713#define SCT_SEC_TR 0
714/* Primary stream array type, dequeue pointer is to a transfer ring */
715#define SCT_PRI_TR 1
716/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
717#define SCT_SSA_8 2
718#define SCT_SSA_16 3
719#define SCT_SSA_32 4
720#define SCT_SSA_64 5
721#define SCT_SSA_128 6
722#define SCT_SSA_256 7
723
724/* Assume no secondary streams for now */
725struct xhci_stream_info {
726 struct xhci_ring **stream_rings;
727 /* Number of streams, including stream 0 (which drivers can't use) */
728 unsigned int num_streams;
729 /* The stream context array may be bigger than
730 * the number of streams the driver asked for
731 */
732 struct xhci_stream_ctx *stream_ctx_array;
733 unsigned int num_stream_ctxs;
734 dma_addr_t ctx_array_dma;
735 /* For mapping physical TRB addresses to segments in stream rings */
736 struct radix_tree_root trb_address_map;
737 struct xhci_command *free_streams_command;
738};
739
740#define SMALL_STREAM_ARRAY_SIZE 256
741#define MEDIUM_STREAM_ARRAY_SIZE 1024
742
9af5d71d
SS		 743/* Some Intel xHCI host controllers need software to keep track of the bus
744 * bandwidth. Keep track of endpoint info here. Each root port is allocated
745 * the full bus bandwidth. We must also treat TTs (including each port under a
746 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
747 * (DMI) also limits the total bandwidth (across all domains) that can be used.
748 */
749struct xhci_bw_info {
170c0263 750 /* ep_interval is zero-based */
9af5d71d 751 unsigned int ep_interval;
170c0263 752 /* mult and num_packets are one-based */
9af5d71d
SS		 753 unsigned int mult;
754 unsigned int num_packets;
755 unsigned int max_packet_size;
756 unsigned int max_esit_payload;
757 unsigned int type;
758};
759
c29eea62
SS		 760/* "Block" sizes in bytes the hardware uses for different device speeds.
761 * The logic in this part of the hardware limits the number of bits the hardware
762 * can use, so must represent bandwidth in a less precise manner to mimic what
763 * the scheduler hardware computes.
764 */
765#define FS_BLOCK 1
766#define HS_BLOCK 4
767#define SS_BLOCK 16
768#define DMI_BLOCK 32
769
770/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
771 * with each byte transferred. SuperSpeed devices have an initial overhead to
772 * set up bursts. These are in blocks, see above. LS overhead has already been
773 * translated into FS blocks.
774 */
775#define DMI_OVERHEAD 8
776#define DMI_OVERHEAD_BURST 4
777#define SS_OVERHEAD 8
778#define SS_OVERHEAD_BURST 32
779#define HS_OVERHEAD 26
780#define FS_OVERHEAD 20
781#define LS_OVERHEAD 128
782/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
783 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
784 * of overhead associated with split transfers crossing microframe boundaries.
785 * 31 blocks is pure protocol overhead.
786 */
787#define TT_HS_OVERHEAD (31 + 94)
788#define TT_DMI_OVERHEAD (25 + 12)
789
790/* Bandwidth limits in blocks */
791#define FS_BW_LIMIT 1285
792#define TT_BW_LIMIT 1320
793#define HS_BW_LIMIT 1607
794#define SS_BW_LIMIT_IN 3906
795#define DMI_BW_LIMIT_IN 3906
796#define SS_BW_LIMIT_OUT 3906
797#define DMI_BW_LIMIT_OUT 3906
798
799/* Percentage of bus bandwidth reserved for non-periodic transfers */
800#define FS_BW_RESERVED 10
801#define HS_BW_RESERVED 20
2b698999 802#define SS_BW_RESERVED 10
c29eea62 803
63a0d9ab
SS		 804struct xhci_virt_ep {
805 struct xhci_ring *ring;
8df75f42
SS		 806 /* Related to endpoints that are configured to use stream IDs only */
807 struct xhci_stream_info *stream_info;
63a0d9ab
SS		 808 /* Temporary storage in case the configure endpoint command fails and we
809 * have to restore the device state to the previous state
810 */
811 struct xhci_ring *new_ring;
812 unsigned int ep_state;
813#define SET_DEQ_PENDING (1 << 0)
678539cf
SS		 814#define EP_HALTED (1 << 1) /* For stall handling */
815#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
8df75f42
SS		 816/* Transitioning the endpoint to using streams, don't enqueue URBs */
817#define EP_GETTING_STREAMS (1 << 3)
818#define EP_HAS_STREAMS (1 << 4)
819/* Transitioning the endpoint to not using streams, don't enqueue URBs */
820#define EP_GETTING_NO_STREAMS (1 << 5)
63a0d9ab
SS		 821 /* ---- Related to URB cancellation ---- */
822 struct list_head cancelled_td_list;
63a0d9ab
SS		 823 /* The TRB that was last reported in a stopped endpoint ring */
824 union xhci_trb *stopped_trb;
825 struct xhci_td *stopped_td;
e9df17eb 826 unsigned int stopped_stream;
6f5165cf
SS		 827 /* Watchdog timer for stop endpoint command to cancel URBs */
828 struct timer_list stop_cmd_timer;
829 int stop_cmds_pending;
830 struct xhci_hcd *xhci;
bf161e85
SS		 831 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
832 * command. We'll need to update the ring's dequeue segment and dequeue
833 * pointer after the command completes.
834 */
835 struct xhci_segment *queued_deq_seg;
836 union xhci_trb *queued_deq_ptr;
d18240db
AX		 837 /*
838 * Sometimes the xHC can not process isochronous endpoint ring quickly
839 * enough, and it will miss some isoc tds on the ring and generate
840 * a Missed Service Error Event.
841 * Set skip flag when receive a Missed Service Error Event and
842 * process the missed tds on the endpoint ring.
843 */
844 bool skip;
2e27980e 845 /* Bandwidth checking storage */
9af5d71d 846 struct xhci_bw_info bw_info;
2e27980e 847 struct list_head bw_endpoint_list;
63a0d9ab
SS		 848};
849
839c817c
SS		 850enum xhci_overhead_type {
851 LS_OVERHEAD_TYPE = 0,
852 FS_OVERHEAD_TYPE,
853 HS_OVERHEAD_TYPE,
854};
855
856struct xhci_interval_bw {
857 unsigned int num_packets;
2e27980e
SS		 858 /* Sorted by max packet size.
859 * Head of the list is the greatest max packet size.
860 */
861 struct list_head endpoints;
839c817c
SS		 862 /* How many endpoints of each speed are present. */
863 unsigned int overhead[3];
864};
865
866#define XHCI_MAX_INTERVAL 16
867
868struct xhci_interval_bw_table {
869 unsigned int interval0_esit_payload;
870 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
c29eea62
SS		 871 /* Includes reserved bandwidth for async endpoints */
872 unsigned int bw_used;
2b698999
SS		 873 unsigned int ss_bw_in;
874 unsigned int ss_bw_out;
839c817c
SS		 875};
876
877
3ffbba95 878struct xhci_virt_device {
64927730 879 struct usb_device *udev;
3ffbba95
SS		 880 /*
881 * Commands to the hardware are passed an "input context" that
882 * tells the hardware what to change in its data structures.
883 * The hardware will return changes in an "output context" that
884 * software must allocate for the hardware. We need to keep
885 * track of input and output contexts separately because
886 * these commands might fail and we don't trust the hardware.
887 */
d115b048 888 struct xhci_container_ctx *out_ctx;
3ffbba95 889 /* Used for addressing devices and configuration changes */
d115b048 890 struct xhci_container_ctx *in_ctx;
74f9fe21
SS		 891 /* Rings saved to ensure old alt settings can be re-instated */
892 struct xhci_ring **ring_cache;
893 int num_rings_cached;
c8d4af8e
AX		 894 /* Store xHC assigned device address */
895 int address;
74f9fe21 896#define XHCI_MAX_RINGS_CACHED 31
63a0d9ab 897 struct xhci_virt_ep eps[31];
f94e0186 898 struct completion cmd_completion;
3ffbba95
SS		 899 /* Status of the last command issued for this device */
900 u32 cmd_status;
913a8a34 901 struct list_head cmd_list;
fe30182c 902 u8 fake_port;
66381755 903 u8 real_port;
839c817c
SS		 904 struct xhci_interval_bw_table *bw_table;
905 struct xhci_tt_bw_info *tt_info;
906};
907
908/*
909 * For each roothub, keep track of the bandwidth information for each periodic
910 * interval.
911 *
912 * If a high speed hub is attached to the roothub, each TT associated with that
913 * hub is a separate bandwidth domain. The interval information for the
914 * endpoints on the devices under that TT will appear in the TT structure.
915 */
916struct xhci_root_port_bw_info {
917 struct list_head tts;
918 unsigned int num_active_tts;
919 struct xhci_interval_bw_table bw_table;
920};
921
922struct xhci_tt_bw_info {
923 struct list_head tt_list;
924 int slot_id;
925 int ttport;
926 struct xhci_interval_bw_table bw_table;
927 int active_eps;
3ffbba95
SS		 928};
929
930
a74588f9
SS		 931/**
932 * struct xhci_device_context_array
933 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
934 */
935struct xhci_device_context_array {
936 /* 64-bit device addresses; we only write 32-bit addresses */
28ccd296 937 __le64 dev_context_ptrs[MAX_HC_SLOTS];
a74588f9
SS		 938 /* private xHCD pointers */
939 dma_addr_t dma;
98441973 940};
a74588f9
SS		 941/* TODO: write function to set the 64-bit device DMA address */
942/*
943 * TODO: change this to be dynamically sized at HC mem init time since the HC
944 * might not be able to handle the maximum number of devices possible.
945 */
946
947
0ebbab37
SS		 948struct xhci_transfer_event {
949 /* 64-bit buffer address, or immediate data */
28ccd296
ME		 950 __le64 buffer;
951 __le32 transfer_len;
0ebbab37 952 /* This field is interpreted differently based on the type of TRB */
28ccd296 953 __le32 flags;
98441973 954};
0ebbab37 955
d0e96f5a
SS		 956/** Transfer Event bit fields **/
957#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
958
0ebbab37
SS		 959/* Completion Code - only applicable for some types of TRBs */
960#define COMP_CODE_MASK (0xff << 24)
961#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
962#define COMP_SUCCESS 1
963/* Data Buffer Error */
964#define COMP_DB_ERR 2
965/* Babble Detected Error */
966#define COMP_BABBLE 3
967/* USB Transaction Error */
968#define COMP_TX_ERR 4
969/* TRB Error - some TRB field is invalid */
970#define COMP_TRB_ERR 5
971/* Stall Error - USB device is stalled */
972#define COMP_STALL 6
973/* Resource Error - HC doesn't have memory for that device configuration */
974#define COMP_ENOMEM 7
975/* Bandwidth Error - not enough room in schedule for this dev config */
976#define COMP_BW_ERR 8
977/* No Slots Available Error - HC ran out of device slots */
978#define COMP_ENOSLOTS 9
979/* Invalid Stream Type Error */
980#define COMP_STREAM_ERR 10
981/* Slot Not Enabled Error - doorbell rung for disabled device slot */
982#define COMP_EBADSLT 11
983/* Endpoint Not Enabled Error */
984#define COMP_EBADEP 12
985/* Short Packet */
986#define COMP_SHORT_TX 13
987/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
988#define COMP_UNDERRUN 14
989/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
990#define COMP_OVERRUN 15
991/* Virtual Function Event Ring Full Error */
992#define COMP_VF_FULL 16
993/* Parameter Error - Context parameter is invalid */
994#define COMP_EINVAL 17
995/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
996#define COMP_BW_OVER 18
997/* Context State Error - illegal context state transition requested */
998#define COMP_CTX_STATE 19
999/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1000#define COMP_PING_ERR 20
1001/* Event Ring is full */
1002#define COMP_ER_FULL 21
f6ba6fe2
AH		 1003/* Incompatible Device Error */
1004#define COMP_DEV_ERR 22
0ebbab37
SS		 1005/* Missed Service Error - HC couldn't service an isoc ep within interval */
1006#define COMP_MISSED_INT 23
1007/* Successfully stopped command ring */
1008#define COMP_CMD_STOP 24
1009/* Successfully aborted current command and stopped command ring */
1010#define COMP_CMD_ABORT 25
1011/* Stopped - transfer was terminated by a stop endpoint command */
1012#define COMP_STOP 26
25985edc 1013/* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
0ebbab37
SS		 1014#define COMP_STOP_INVAL 27
1015/* Control Abort Error - Debug Capability - control pipe aborted */
1016#define COMP_DBG_ABORT 28
1bb73a88
AH		 1017/* Max Exit Latency Too Large Error */
1018#define COMP_MEL_ERR 29
1019/* TRB type 30 reserved */
0ebbab37
SS		 1020/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1021#define COMP_BUFF_OVER 31
1022/* Event Lost Error - xHC has an "internal event overrun condition" */
1023#define COMP_ISSUES 32
1024/* Undefined Error - reported when other error codes don't apply */
1025#define COMP_UNKNOWN 33
1026/* Invalid Stream ID Error */
1027#define COMP_STRID_ERR 34
1028/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1029/* FIXME - check for this */
1030#define COMP_2ND_BW_ERR 35
1031/* Split Transaction Error */
1032#define COMP_SPLIT_ERR 36
1033
1034struct xhci_link_trb {
1035 /* 64-bit segment pointer*/
28ccd296
ME		 1036 __le64 segment_ptr;
1037 __le32 intr_target;
1038 __le32 control;
98441973 1039};
0ebbab37
SS		 1040
1041/* control bitfields */
1042#define LINK_TOGGLE (0x1<<1)
1043
7f84eef0
SS		 1044/* Command completion event TRB */
1045struct xhci_event_cmd {
1046 /* Pointer to command TRB, or the value passed by the event data trb */
28ccd296
ME		 1047 __le64 cmd_trb;
1048 __le32 status;
1049 __le32 flags;
98441973 1050};
0ebbab37 1051
3ffbba95
SS		 1052/* flags bitmasks */
1053/* bits 16:23 are the virtual function ID */
1054/* bits 24:31 are the slot ID */
1055#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1056#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
0ebbab37 1057
ae636747
SS		 1058/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1059#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1060#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1061
be88fe4f
AX		 1062#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1063#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1064#define LAST_EP_INDEX 30
1065
e9df17eb
SS		 1066/* Set TR Dequeue Pointer command TRB fields */
1067#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1068#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1069
ae636747 1070
0f2a7930
SS		 1071/* Port Status Change Event TRB fields */
1072/* Port ID - bits 31:24 */
1073#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1074
0ebbab37
SS		 1075/* Normal TRB fields */
1076/* transfer_len bitmasks - bits 0:16 */
1077#define TRB_LEN(p) ((p) & 0x1ffff)
0ebbab37
SS		 1078/* Interrupter Target - which MSI-X vector to target the completion event at */
1079#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1080#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
5cd43e33 1081#define TRB_TBC(p) (((p) & 0x3) << 7)
b61d378f 1082#define TRB_TLBPC(p) (((p) & 0xf) << 16)
0ebbab37
SS		 1083
1084/* Cycle bit - indicates TRB ownership by HC or HCD */
1085#define TRB_CYCLE (1<<0)
1086/*
1087 * Force next event data TRB to be evaluated before task switch.
1088 * Used to pass OS data back after a TD completes.
1089 */
1090#define TRB_ENT (1<<1)
1091/* Interrupt on short packet */
1092#define TRB_ISP (1<<2)
1093/* Set PCIe no snoop attribute */
1094#define TRB_NO_SNOOP (1<<3)
1095/* Chain multiple TRBs into a TD */
1096#define TRB_CHAIN (1<<4)
1097/* Interrupt on completion */
1098#define TRB_IOC (1<<5)
1099/* The buffer pointer contains immediate data */
1100#define TRB_IDT (1<<6)
1101
ad106f29
AX		 1102/* Block Event Interrupt */
1103#define TRB_BEI (1<<9)
0ebbab37
SS		 1104
1105/* Control transfer TRB specific fields */
1106#define TRB_DIR_IN (1<<16)
b83cdc8f
AX		 1107#define TRB_TX_TYPE(p) ((p) << 16)
1108#define TRB_DATA_OUT 2
1109#define TRB_DATA_IN 3
0ebbab37 1110
04e51901
AX		 1111/* Isochronous TRB specific fields */
1112#define TRB_SIA (1<<31)
1113
7f84eef0 1114struct xhci_generic_trb {
28ccd296 1115 __le32 field[4];
98441973 1116};
7f84eef0
SS		 1117
1118union xhci_trb {
1119 struct xhci_link_trb link;
1120 struct xhci_transfer_event trans_event;
1121 struct xhci_event_cmd event_cmd;
1122 struct xhci_generic_trb generic;
1123};
1124
0ebbab37
SS		 1125/* TRB bit mask */
1126#define TRB_TYPE_BITMASK (0xfc00)
1127#define TRB_TYPE(p) ((p) << 10)
0238634d 1128#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
0ebbab37
SS		 1129/* TRB type IDs */
1130/* bulk, interrupt, isoc scatter/gather, and control data stage */
1131#define TRB_NORMAL 1
1132/* setup stage for control transfers */
1133#define TRB_SETUP 2
1134/* data stage for control transfers */
1135#define TRB_DATA 3
1136/* status stage for control transfers */
1137#define TRB_STATUS 4
1138/* isoc transfers */
1139#define TRB_ISOC 5
1140/* TRB for linking ring segments */
1141#define TRB_LINK 6
1142#define TRB_EVENT_DATA 7
1143/* Transfer Ring No-op (not for the command ring) */
1144#define TRB_TR_NOOP 8
1145/* Command TRBs */
1146/* Enable Slot Command */
1147#define TRB_ENABLE_SLOT 9
1148/* Disable Slot Command */
1149#define TRB_DISABLE_SLOT 10
1150/* Address Device Command */
1151#define TRB_ADDR_DEV 11
1152/* Configure Endpoint Command */
1153#define TRB_CONFIG_EP 12
1154/* Evaluate Context Command */
1155#define TRB_EVAL_CONTEXT 13
a1587d97
SS		 1156/* Reset Endpoint Command */
1157#define TRB_RESET_EP 14
0ebbab37
SS		 1158/* Stop Transfer Ring Command */
1159#define TRB_STOP_RING 15
1160/* Set Transfer Ring Dequeue Pointer Command */
1161#define TRB_SET_DEQ 16
1162/* Reset Device Command */
1163#define TRB_RESET_DEV 17
1164/* Force Event Command (opt) */
1165#define TRB_FORCE_EVENT 18
1166/* Negotiate Bandwidth Command (opt) */
1167#define TRB_NEG_BANDWIDTH 19
1168/* Set Latency Tolerance Value Command (opt) */
1169#define TRB_SET_LT 20
1170/* Get port bandwidth Command */
1171#define TRB_GET_BW 21
1172/* Force Header Command - generate a transaction or link management packet */
1173#define TRB_FORCE_HEADER 22
1174/* No-op Command - not for transfer rings */
1175#define TRB_CMD_NOOP 23
1176/* TRB IDs 24-31 reserved */
1177/* Event TRBS */
1178/* Transfer Event */
1179#define TRB_TRANSFER 32
1180/* Command Completion Event */
1181#define TRB_COMPLETION 33
1182/* Port Status Change Event */
1183#define TRB_PORT_STATUS 34
1184/* Bandwidth Request Event (opt) */
1185#define TRB_BANDWIDTH_EVENT 35
1186/* Doorbell Event (opt) */
1187#define TRB_DOORBELL 36
1188/* Host Controller Event */
1189#define TRB_HC_EVENT 37
1190/* Device Notification Event - device sent function wake notification */
1191#define TRB_DEV_NOTE 38
1192/* MFINDEX Wrap Event - microframe counter wrapped */
1193#define TRB_MFINDEX_WRAP 39
1194/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1195
0238634d
SS		 1196/* Nec vendor-specific command completion event. */
1197#define TRB_NEC_CMD_COMP 48
1198/* Get NEC firmware revision. */
1199#define TRB_NEC_GET_FW 49
1200
f5960b69
ME		 1201#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1202/* Above, but for __le32 types -- can avoid work by swapping constants: */
1203#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1204 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1205#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1206 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1207
0238634d
SS		 1208#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1209#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1210
0ebbab37
SS		 1211/*
1212 * TRBS_PER_SEGMENT must be a multiple of 4,
1213 * since the command ring is 64-byte aligned.
1214 * It must also be greater than 16.
1215 */
1216#define TRBS_PER_SEGMENT 64
913a8a34
SS		 1217/* Allow two commands + a link TRB, along with any reserved command TRBs */
1218#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
0ebbab37 1219#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
8df75f42
SS		 1220/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
1221 * Change this if you change TRBS_PER_SEGMENT!
1222 */
1223#define SEGMENT_SHIFT 10
b10de142
SS		 1224/* TRB buffer pointers can't cross 64KB boundaries */
1225#define TRB_MAX_BUFF_SHIFT 16
1226#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
0ebbab37
SS		 1227
1228struct xhci_segment {
1229 union xhci_trb *trbs;
1230 /* private to HCD */
1231 struct xhci_segment *next;
1232 dma_addr_t dma;
98441973 1233};
0ebbab37 1234
ae636747
SS		 1235struct xhci_td {
1236 struct list_head td_list;
1237 struct list_head cancelled_td_list;
1238 struct urb *urb;
1239 struct xhci_segment *start_seg;
1240 union xhci_trb *first_trb;
1241 union xhci_trb *last_trb;
1242};
1243
ac9d8fe7
SS		 1244struct xhci_dequeue_state {
1245 struct xhci_segment *new_deq_seg;
1246 union xhci_trb *new_deq_ptr;
1247 int new_cycle_state;
1248};
1249
0ebbab37
SS		 1250struct xhci_ring {
1251 struct xhci_segment *first_seg;
1252 union xhci_trb *enqueue;
7f84eef0
SS		 1253 struct xhci_segment *enq_seg;
1254 unsigned int enq_updates;
0ebbab37 1255 union xhci_trb *dequeue;
7f84eef0
SS		 1256 struct xhci_segment *deq_seg;
1257 unsigned int deq_updates;
d0e96f5a 1258 struct list_head td_list;
0ebbab37
SS		 1259 /*
1260 * Write the cycle state into the TRB cycle field to give ownership of
1261 * the TRB to the host controller (if we are the producer), or to check
1262 * if we own the TRB (if we are the consumer). See section 4.9.1.
1263 */
1264 u32 cycle_state;
e9df17eb 1265 unsigned int stream_id;
ad808333 1266 bool last_td_was_short;
0ebbab37
SS		 1267};
1268
1269struct xhci_erst_entry {
1270 /* 64-bit event ring segment address */
28ccd296
ME		 1271 __le64 seg_addr;
1272 __le32 seg_size;
0ebbab37 1273 /* Set to zero */
28ccd296 1274 __le32 rsvd;
98441973 1275};
0ebbab37
SS		 1276
1277struct xhci_erst {
1278 struct xhci_erst_entry *entries;
1279 unsigned int num_entries;
1280 /* xhci->event_ring keeps track of segment dma addresses */
1281 dma_addr_t erst_dma_addr;
1282 /* Num entries the ERST can contain */
1283 unsigned int erst_size;
1284};
1285
254c80a3
JY		 1286struct xhci_scratchpad {
1287 u64 *sp_array;
1288 dma_addr_t sp_dma;
1289 void **sp_buffers;
1290 dma_addr_t *sp_dma_buffers;
1291};
1292
8e51adcc
AX		 1293struct urb_priv {
1294 int length;
1295 int td_cnt;
1296 struct xhci_td *td[0];
1297};
1298
0ebbab37
SS		 1299/*
1300 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1301 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1302 * meaning 64 ring segments.
1303 * Initial allocated size of the ERST, in number of entries */
1304#define ERST_NUM_SEGS 1
1305/* Initial allocated size of the ERST, in number of entries */
1306#define ERST_SIZE 64
1307/* Initial number of event segment rings allocated */
1308#define ERST_ENTRIES 1
7f84eef0
SS		 1309/* Poll every 60 seconds */
1310#define POLL_TIMEOUT 60
6f5165cf
SS		 1311/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1312#define XHCI_STOP_EP_CMD_TIMEOUT 5
0ebbab37
SS		 1313/* XXX: Make these module parameters */
1314
5535b1d5
AX		 1315struct s3_save {
1316 u32 command;
1317 u32 dev_nt;
1318 u64 dcbaa_ptr;
1319 u32 config_reg;
1320 u32 irq_pending;
1321 u32 irq_control;
1322 u32 erst_size;
1323 u64 erst_base;
1324 u64 erst_dequeue;
1325};
74c68741 1326
20b67cf5
SS		 1327struct xhci_bus_state {
1328 unsigned long bus_suspended;
1329 unsigned long next_statechange;
1330
1331 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1332 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1333 u32 port_c_suspend;
1334 u32 suspended_ports;
1335 unsigned long resume_done[USB_MAXCHILDREN];
1336};
1337
1338static inline unsigned int hcd_index(struct usb_hcd *hcd)
1339{
f6ff0ac8
SS		 1340 if (hcd->speed == HCD_USB3)
1341 return 0;
1342 else
1343 return 1;
20b67cf5
SS		 1344}
1345
74c68741
SS		 1346/* There is one ehci_hci structure per controller */
1347struct xhci_hcd {
b02d0ed6 1348 struct usb_hcd *main_hcd;
f6ff0ac8 1349 struct usb_hcd *shared_hcd;
74c68741
SS		 1350 /* glue to PCI and HCD framework */
1351 struct xhci_cap_regs __iomem *cap_regs;
1352 struct xhci_op_regs __iomem *op_regs;
1353 struct xhci_run_regs __iomem *run_regs;
0ebbab37 1354 struct xhci_doorbell_array __iomem *dba;
66d4eadd 1355 /* Our HCD's current interrupter register set */
98441973 1356 struct xhci_intr_reg __iomem *ir_set;
74c68741
SS		 1357
1358 /* Cached register copies of read-only HC data */
1359 __u32 hcs_params1;
1360 __u32 hcs_params2;
1361 __u32 hcs_params3;
1362 __u32 hcc_params;
1363
1364 spinlock_t lock;
1365
1366 /* packed release number */
1367 u8 sbrn;
1368 u16 hci_version;
1369 u8 max_slots;
1370 u8 max_interrupters;
1371 u8 max_ports;
1372 u8 isoc_threshold;
1373 int event_ring_max;
1374 int addr_64;
66d4eadd 1375 /* 4KB min, 128MB max */
74c68741 1376 int page_size;
66d4eadd
SS		 1377 /* Valid values are 12 to 20, inclusive */
1378 int page_shift;
43b86af8 1379 /* msi-x vectors */
66d4eadd
SS		 1380 int msix_count;
1381 struct msix_entry *msix_entries;
0ebbab37 1382 /* data structures */
a74588f9 1383 struct xhci_device_context_array *dcbaa;
0ebbab37 1384 struct xhci_ring *cmd_ring;
913a8a34 1385 unsigned int cmd_ring_reserved_trbs;
0ebbab37
SS		 1386 struct xhci_ring *event_ring;
1387 struct xhci_erst erst;
254c80a3
JY		 1388 /* Scratchpad */
1389 struct xhci_scratchpad *scratchpad;
1390
3ffbba95
SS		 1391 /* slot enabling and address device helpers */
1392 struct completion addr_dev;
1393 int slot_id;
1394 /* Internal mirror of the HW's dcbaa */
1395 struct xhci_virt_device *devs[MAX_HC_SLOTS];
839c817c
SS		 1396 /* For keeping track of bandwidth domains per roothub. */
1397 struct xhci_root_port_bw_info *rh_bw;
0ebbab37
SS		 1398
1399 /* DMA pools */
1400 struct dma_pool *device_pool;
1401 struct dma_pool *segment_pool;
8df75f42
SS		 1402 struct dma_pool *small_streams_pool;
1403 struct dma_pool *medium_streams_pool;
7f84eef0
SS		 1404
1405#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1406 /* Poll the rings - for debugging */
1407 struct timer_list event_ring_timer;
1408 int zombie;
1409#endif
6f5165cf
SS		 1410 /* Host controller watchdog timer structures */
1411 unsigned int xhc_state;
9777e3ce 1412
9777e3ce 1413 u32 command;
5535b1d5 1414 struct s3_save s3;
6f5165cf
SS		 1415/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1416 *
1417 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1418 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1419 * that sees this status (other than the timer that set it) should stop touching
1420 * hardware immediately. Interrupt handlers should return immediately when
1421 * they see this status (any time they drop and re-acquire xhci->lock).
1422 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1423 * putting the TD on the canceled list, etc.
1424 *
1425 * There are no reports of xHCI host controllers that display this issue.
1426 */
1427#define XHCI_STATE_DYING (1 << 0)
c6cc27c7 1428#define XHCI_STATE_HALTED (1 << 1)
7f84eef0 1429 /* Statistics */
7f84eef0 1430 int error_bitmask;
b0567b3f
SS		 1431 unsigned int quirks;
1432#define XHCI_LINK_TRB_QUIRK (1 << 0)
ac9d8fe7 1433#define XHCI_RESET_EP_QUIRK (1 << 1)
0238634d 1434#define XHCI_NEC_HOST (1 << 2)
c41136b0 1435#define XHCI_AMD_PLL_FIX (1 << 3)
ad808333 1436#define XHCI_SPURIOUS_SUCCESS (1 << 4)
2cf95c18
SS		 1437/*
1438 * Certain Intel host controllers have a limit to the number of endpoint
1439 * contexts they can handle. Ideally, they would signal that they can't handle
1440 * anymore endpoint contexts by returning a Resource Error for the Configure
1441 * Endpoint command, but they don't. Instead they expect software to keep track
1442 * of the number of active endpoints for them, across configure endpoint
1443 * commands, reset device commands, disable slot commands, and address device
1444 * commands.
1445 */
1446#define XHCI_EP_LIMIT_QUIRK (1 << 5)
f5182b41 1447#define XHCI_BROKEN_MSI (1 << 6)
c877b3b2 1448#define XHCI_RESET_ON_RESUME (1 << 7)
c29eea62 1449#define XHCI_SW_BW_CHECKING (1 << 8)
2cf95c18
SS		 1450 unsigned int num_active_eps;
1451 unsigned int limit_active_eps;
f6ff0ac8
SS		 1452 /* There are two roothubs to keep track of bus suspend info for */
1453 struct xhci_bus_state bus_state[2];
da6699ce
SS		 1454 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1455 u8 *port_array;
1456 /* Array of pointers to USB 3.0 PORTSC registers */
28ccd296 1457 __le32 __iomem **usb3_ports;
da6699ce
SS		 1458 unsigned int num_usb3_ports;
1459 /* Array of pointers to USB 2.0 PORTSC registers */
28ccd296 1460 __le32 __iomem **usb2_ports;
da6699ce 1461 unsigned int num_usb2_ports;
74c68741
SS		 1462};
1463
1464/* convert between an HCD pointer and the corresponding EHCI_HCD */
1465static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1466{
b02d0ed6 1467 return *((struct xhci_hcd **) (hcd->hcd_priv));
74c68741
SS		 1468}
1469
1470static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1471{
b02d0ed6 1472 return xhci->main_hcd;
74c68741
SS		 1473}
1474
1475#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1476#define XHCI_DEBUG 1
1477#else
1478#define XHCI_DEBUG 0
1479#endif
1480
1481#define xhci_dbg(xhci, fmt, args...) \
1482 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1483#define xhci_info(xhci, fmt, args...) \
1484 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1485#define xhci_err(xhci, fmt, args...) \
1486 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1487#define xhci_warn(xhci, fmt, args...) \
1488 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1489
1490/* TODO: copied from ehci.h - can be refactored? */
1491/* xHCI spec says all registers are little endian */
1492static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
28ccd296 1493 __le32 __iomem *regs)
74c68741
SS		 1494{
1495 return readl(regs);
1496}
045f123d 1497static inline void xhci_writel(struct xhci_hcd *xhci,
28ccd296 1498 const unsigned int val, __le32 __iomem *regs)
74c68741 1499{
74c68741
SS		 1500 writel(val, regs);
1501}
1502
8e595a5d
SS		 1503/*
1504 * Registers should always be accessed with double word or quad word accesses.
1505 *
1506 * Some xHCI implementations may support 64-bit address pointers. Registers
1507 * with 64-bit address pointers should be written to with dword accesses by
1508 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1509 * xHCI implementations that do not support 64-bit address pointers will ignore
1510 * the high dword, and write order is irrelevant.
1511 */
1512static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
28ccd296 1513 __le64 __iomem *regs)
8e595a5d
SS		 1514{
1515 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1516 u64 val_lo = readl(ptr);
1517 u64 val_hi = readl(ptr + 1);
1518 return val_lo + (val_hi << 32);
1519}
1520static inline void xhci_write_64(struct xhci_hcd *xhci,
28ccd296 1521 const u64 val, __le64 __iomem *regs)
8e595a5d
SS		 1522{
1523 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1524 u32 val_lo = lower_32_bits(val);
1525 u32 val_hi = upper_32_bits(val);
1526
8e595a5d
SS		 1527 writel(val_lo, ptr);
1528 writel(val_hi, ptr + 1);
1529}
1530
b0567b3f
SS		 1531static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1532{
d7826599 1533 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
b0567b3f
SS		 1534}
1535
66d4eadd 1536/* xHCI debugging */
09ece30e 1537void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
66d4eadd 1538void xhci_print_registers(struct xhci_hcd *xhci);
0ebbab37
SS		 1539void xhci_dbg_regs(struct xhci_hcd *xhci);
1540void xhci_print_run_regs(struct xhci_hcd *xhci);
d0e96f5a
SS		 1541void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1542void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
7f84eef0 1543void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
0ebbab37
SS		 1544void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1545void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1546void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
7f84eef0 1547void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
d115b048 1548void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
9c9a7dbf 1549char *xhci_get_slot_state(struct xhci_hcd *xhci,
2a8f82c4 1550 struct xhci_container_ctx *ctx);
e9df17eb
SS		 1551void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1552 unsigned int slot_id, unsigned int ep_index,
1553 struct xhci_virt_ep *ep);
66d4eadd 1554
3dbda77e 1555/* xHCI memory management */
66d4eadd
SS		 1556void xhci_mem_cleanup(struct xhci_hcd *xhci);
1557int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
3ffbba95
SS		 1558void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1559int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1560int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2d1ee590
SS		 1561void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1562 struct usb_device *udev);
d0e96f5a 1563unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
f94e0186 1564unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
ac9d8fe7
SS		 1565unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1566unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
f94e0186 1567void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2e27980e
SS		 1568void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1569 struct xhci_bw_info *ep_bw,
1570 struct xhci_interval_bw_table *bw_table,
1571 struct usb_device *udev,
1572 struct xhci_virt_ep *virt_ep,
1573 struct xhci_tt_bw_info *tt_info);
1574void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1575 struct xhci_virt_device *virt_dev,
1576 int old_active_eps);
9af5d71d
SS		 1577void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1578void xhci_update_bw_info(struct xhci_hcd *xhci,
1579 struct xhci_container_ctx *in_ctx,
1580 struct xhci_input_control_ctx *ctrl_ctx,
1581 struct xhci_virt_device *virt_dev);
f2217e8e 1582void xhci_endpoint_copy(struct xhci_hcd *xhci,
913a8a34
SS		 1583 struct xhci_container_ctx *in_ctx,
1584 struct xhci_container_ctx *out_ctx,
1585 unsigned int ep_index);
1586void xhci_slot_copy(struct xhci_hcd *xhci,
1587 struct xhci_container_ctx *in_ctx,
1588 struct xhci_container_ctx *out_ctx);
f88ba78d
SS		 1589int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1590 struct usb_device *udev, struct usb_host_endpoint *ep,
1591 gfp_t mem_flags);
f94e0186 1592void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
412566bd
SS		 1593void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1594 struct xhci_virt_device *virt_dev,
1595 unsigned int ep_index);
8df75f42
SS		 1596struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1597 unsigned int num_stream_ctxs,
1598 unsigned int num_streams, gfp_t flags);
1599void xhci_free_stream_info(struct xhci_hcd *xhci,
1600 struct xhci_stream_info *stream_info);
1601void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1602 struct xhci_ep_ctx *ep_ctx,
1603 struct xhci_stream_info *stream_info);
1604void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1605 struct xhci_ep_ctx *ep_ctx,
1606 struct xhci_virt_ep *ep);
2cf95c18
SS		 1607void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1608 struct xhci_virt_device *virt_dev, bool drop_control_ep);
e9df17eb
SS		 1609struct xhci_ring *xhci_dma_to_transfer_ring(
1610 struct xhci_virt_ep *ep,
1611 u64 address);
e9df17eb
SS		 1612struct xhci_ring *xhci_stream_id_to_ring(
1613 struct xhci_virt_device *dev,
1614 unsigned int ep_index,
1615 unsigned int stream_id);
913a8a34 1616struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
a1d78c16
SS		 1617 bool allocate_in_ctx, bool allocate_completion,
1618 gfp_t mem_flags);
8e51adcc 1619void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
913a8a34
SS		 1620void xhci_free_command(struct xhci_hcd *xhci,
1621 struct xhci_command *command);
66d4eadd
SS		 1622
1623#ifdef CONFIG_PCI
1624/* xHCI PCI glue */
1625int xhci_register_pci(void);
1626void xhci_unregister_pci(void);
1627#endif
1628
1629/* xHCI host controller glue */
4f0f0bae 1630void xhci_quiesce(struct xhci_hcd *xhci);
66d4eadd
SS		 1631int xhci_halt(struct xhci_hcd *xhci);
1632int xhci_reset(struct xhci_hcd *xhci);
1633int xhci_init(struct usb_hcd *hcd);
1634int xhci_run(struct usb_hcd *hcd);
1635void xhci_stop(struct usb_hcd *hcd);
1636void xhci_shutdown(struct usb_hcd *hcd);
436a3890
SS		 1637
1638#ifdef CONFIG_PM
5535b1d5
AX		 1639int xhci_suspend(struct xhci_hcd *xhci);
1640int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
436a3890
SS		 1641#else
1642#define xhci_suspend NULL
1643#define xhci_resume NULL
1644#endif
1645
66d4eadd 1646int xhci_get_frame(struct usb_hcd *hcd);
7f84eef0 1647irqreturn_t xhci_irq(struct usb_hcd *hcd);
9032cd52 1648irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
3ffbba95
SS		 1649int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1650void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
839c817c
SS		 1651int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1652 struct xhci_virt_device *virt_dev,
1653 struct usb_device *hdev,
1654 struct usb_tt *tt, gfp_t mem_flags);
8df75f42
SS		 1655int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1656 struct usb_host_endpoint **eps, unsigned int num_eps,
1657 unsigned int num_streams, gfp_t mem_flags);
1658int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1659 struct usb_host_endpoint **eps, unsigned int num_eps,
1660 gfp_t mem_flags);
3ffbba95 1661int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
ac1c1b7f
SS		 1662int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1663 struct usb_tt *tt, gfp_t mem_flags);
d0e96f5a
SS		 1664int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1665int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
f94e0186
SS		 1666int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1667int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
a1587d97 1668void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
f0615c45 1669int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
f94e0186
SS		 1670int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1671void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
7f84eef0
SS		 1672
1673/* xHCI ring, segment, TRB, and TD functions */
23e3be11 1674dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
6648f29d
SS		 1675struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1676 union xhci_trb *start_trb, union xhci_trb *end_trb,
1677 dma_addr_t suspect_dma);
b45b5069 1678int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
23e3be11 1679void xhci_ring_cmd_db(struct xhci_hcd *xhci);
23e3be11
SS		 1680int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1681int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1682 u32 slot_id);
0238634d
SS		 1683int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1684 u32 field1, u32 field2, u32 field3, u32 field4);
23e3be11 1685int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
be88fe4f 1686 unsigned int ep_index, int suspend);
23e3be11
SS		 1687int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1688 int slot_id, unsigned int ep_index);
1689int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1690 int slot_id, unsigned int ep_index);
624defa1
SS		 1691int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1692 int slot_id, unsigned int ep_index);
04e51901
AX		 1693int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1694 struct urb *urb, int slot_id, unsigned int ep_index);
23e3be11 1695int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
913a8a34 1696 u32 slot_id, bool command_must_succeed);
f2217e8e 1697int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
23e3be11 1698 u32 slot_id);
a1587d97
SS		 1699int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1700 unsigned int ep_index);
2a8f82c4 1701int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
c92bcfa7
SS		 1702void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1703 unsigned int slot_id, unsigned int ep_index,
e9df17eb
SS		 1704 unsigned int stream_id, struct xhci_td *cur_td,
1705 struct xhci_dequeue_state *state);
c92bcfa7 1706void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
63a0d9ab 1707 unsigned int slot_id, unsigned int ep_index,
e9df17eb 1708 unsigned int stream_id,
63a0d9ab 1709 struct xhci_dequeue_state *deq_state);
82d1009f 1710void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
63a0d9ab 1711 struct usb_device *udev, unsigned int ep_index);
ac9d8fe7
SS		 1712void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1713 unsigned int slot_id, unsigned int ep_index,
1714 struct xhci_dequeue_state *deq_state);
6f5165cf 1715void xhci_stop_endpoint_command_watchdog(unsigned long arg);
be88fe4f
AX		 1716void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1717 unsigned int ep_index, unsigned int stream_id);
66d4eadd 1718
0f2a7930 1719/* xHCI roothub code */
c9682dff
AX		 1720void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1721 int port_id, u32 link_state);
0f2a7930
SS		 1722int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1723 char *buf, u16 wLength);
1724int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
436a3890
SS		 1725
1726#ifdef CONFIG_PM
9777e3ce
AX		 1727int xhci_bus_suspend(struct usb_hcd *hcd);
1728int xhci_bus_resume(struct usb_hcd *hcd);
436a3890
SS		 1729#else
1730#define xhci_bus_suspend NULL
1731#define xhci_bus_resume NULL
1732#endif /* CONFIG_PM */
1733
56192531 1734u32 xhci_port_state_to_neutral(u32 state);
5233630f
SS		 1735int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1736 u16 port);
56192531 1737void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
0f2a7930 1738
d115b048
JY		 1739/* xHCI contexts */
1740struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1741struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1742struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1743
74c68741 1744#endif /* __LINUX_XHCI_HCD_H */
Linux 6.x block layer and io_uring tree(s)