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USB: usbtmc: Use usb_clear_halt() instead of custom code.
[linux-2.6-block.git] / drivers / usb / host / xhci.h
CommitLineData
74c68741
SS		 1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __LINUX_XHCI_HCD_H
24#define __LINUX_XHCI_HCD_H
25
26#include <linux/usb.h>
7f84eef0 27#include <linux/timer.h>
8e595a5d 28#include <linux/kernel.h>
74c68741
SS		 29
30#include "../core/hcd.h"
31/* Code sharing between pci-quirks and xhci hcd */
32#include "xhci-ext-caps.h"
33
34/* xHCI PCI Configuration Registers */
35#define XHCI_SBRN_OFFSET (0x60)
36
66d4eadd
SS		 37/* Max number of USB devices for any host controller - limit in section 6.1 */
38#define MAX_HC_SLOTS 256
0f2a7930
SS		 39/* Section 5.3.3 - MaxPorts */
40#define MAX_HC_PORTS 127
66d4eadd 41
74c68741
SS		 42/*
43 * xHCI register interface.
44 * This corresponds to the eXtensible Host Controller Interface (xHCI)
45 * Revision 0.95 specification
74c68741
SS		 46 */
47
48/**
49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
50 * @hc_capbase: length of the capabilities register and HC version number
51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
54 * @hcc_params: HCCPARAMS - Capability Parameters
55 * @db_off: DBOFF - Doorbell array offset
56 * @run_regs_off: RTSOFF - Runtime register space offset
57 */
58struct xhci_cap_regs {
59 u32 hc_capbase;
60 u32 hcs_params1;
61 u32 hcs_params2;
62 u32 hcs_params3;
63 u32 hcc_params;
64 u32 db_off;
65 u32 run_regs_off;
66 /* Reserved up to (CAPLENGTH - 0x1C) */
98441973 67};
74c68741
SS		 68
69/* hc_capbase bitmasks */
70/* bits 7:0 - how long is the Capabilities register */
71#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
72/* bits 31:16 */
73#define HC_VERSION(p) (((p) >> 16) & 0xffff)
74
75/* HCSPARAMS1 - hcs_params1 - bitmasks */
76/* bits 0:7, Max Device Slots */
77#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
78#define HCS_SLOTS_MASK 0xff
79/* bits 8:18, Max Interrupters */
80#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
81/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
82#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
83
84/* HCSPARAMS2 - hcs_params2 - bitmasks */
85/* bits 0:3, frames or uframes that SW needs to queue transactions
86 * ahead of the HW to meet periodic deadlines */
87#define HCS_IST(p) (((p) >> 0) & 0xf)
88/* bits 4:7, max number of Event Ring segments */
89#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
90/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
254c80a3 92#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
74c68741
SS		 93
94/* HCSPARAMS3 - hcs_params3 - bitmasks */
95/* bits 0:7, Max U1 to U0 latency for the roothub ports */
96#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
97/* bits 16:31, Max U2 to U0 latency for the roothub ports */
98#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
99
100/* HCCPARAMS - hcc_params - bitmasks */
101/* true: HC can use 64-bit address pointers */
102#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
103/* true: HC can do bandwidth negotiation */
104#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
105/* true: HC uses 64-byte Device Context structures
106 * FIXME 64-byte context structures aren't supported yet.
107 */
108#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
109/* true: HC has port power switches */
110#define HCC_PPC(p) ((p) & (1 << 3))
111/* true: HC has port indicators */
112#define HCS_INDICATOR(p) ((p) & (1 << 4))
113/* true: HC has Light HC Reset Capability */
114#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
115/* true: HC supports latency tolerance messaging */
116#define HCC_LTC(p) ((p) & (1 << 6))
117/* true: no secondary Stream ID Support */
118#define HCC_NSS(p) ((p) & (1 << 7))
119/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
120#define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1))
121/* Extended Capabilities pointer from PCI base - section 5.3.6 */
122#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
123
124/* db_off bitmask - bits 0:1 reserved */
125#define DBOFF_MASK (~0x3)
126
127/* run_regs_off bitmask - bits 0:4 reserved */
128#define RTSOFF_MASK (~0x1f)
129
130
131/* Number of registers per port */
132#define NUM_PORT_REGS 4
133
134/**
135 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
136 * @command: USBCMD - xHC command register
137 * @status: USBSTS - xHC status register
138 * @page_size: This indicates the page size that the host controller
139 * supports. If bit n is set, the HC supports a page size
140 * of 2^(n+12), up to a 128MB page size.
141 * 4K is the minimum page size.
142 * @cmd_ring: CRP - 64-bit Command Ring Pointer
143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
144 * @config_reg: CONFIG - Configure Register
145 * @port_status_base: PORTSCn - base address for Port Status and Control
146 * Each port has a Port Status and Control register,
147 * followed by a Port Power Management Status and Control
148 * register, a Port Link Info register, and a reserved
149 * register.
150 * @port_power_base: PORTPMSCn - base address for
151 * Port Power Management Status and Control
152 * @port_link_base: PORTLIn - base address for Port Link Info (current
153 * Link PM state and control) for USB 2.1 and USB 3.0
154 * devices.
155 */
156struct xhci_op_regs {
157 u32 command;
158 u32 status;
159 u32 page_size;
160 u32 reserved1;
161 u32 reserved2;
162 u32 dev_notification;
8e595a5d 163 u64 cmd_ring;
74c68741
SS		 164 /* rsvd: offset 0x20-2F */
165 u32 reserved3[4];
8e595a5d 166 u64 dcbaa_ptr;
74c68741
SS		 167 u32 config_reg;
168 /* rsvd: offset 0x3C-3FF */
169 u32 reserved4[241];
170 /* port 1 registers, which serve as a base address for other ports */
171 u32 port_status_base;
172 u32 port_power_base;
173 u32 port_link_base;
174 u32 reserved5;
175 /* registers for ports 2-255 */
176 u32 reserved6[NUM_PORT_REGS*254];
98441973 177};
74c68741
SS		 178
179/* USBCMD - USB command - command bitmasks */
180/* start/stop HC execution - do not write unless HC is halted*/
181#define CMD_RUN XHCI_CMD_RUN
182/* Reset HC - resets internal HC state machine and all registers (except
183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
184 * The xHCI driver must reinitialize the xHC after setting this bit.
185 */
186#define CMD_RESET (1 << 1)
187/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
188#define CMD_EIE XHCI_CMD_EIE
189/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
190#define CMD_HSEIE XHCI_CMD_HSEIE
191/* bits 4:6 are reserved (and should be preserved on writes). */
192/* light reset (port status stays unchanged) - reset completed when this is 0 */
193#define CMD_LRESET (1 << 7)
194/* FIXME: ignoring host controller save/restore state for now. */
195#define CMD_CSS (1 << 8)
196#define CMD_CRS (1 << 9)
197/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
198#define CMD_EWE XHCI_CMD_EWE
199/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
201 * '0' means the xHC can power it off if all ports are in the disconnect,
202 * disabled, or powered-off state.
203 */
204#define CMD_PM_INDEX (1 << 11)
205/* bits 12:31 are reserved (and should be preserved on writes). */
206
207/* USBSTS - USB status - status bitmasks */
208/* HC not running - set to 1 when run/stop bit is cleared. */
209#define STS_HALT XHCI_STS_HALT
210/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
211#define STS_FATAL (1 << 2)
212/* event interrupt - clear this prior to clearing any IP flags in IR set*/
213#define STS_EINT (1 << 3)
214/* port change detect */
215#define STS_PORT (1 << 4)
216/* bits 5:7 reserved and zeroed */
217/* save state status - '1' means xHC is saving state */
218#define STS_SAVE (1 << 8)
219/* restore state status - '1' means xHC is restoring state */
220#define STS_RESTORE (1 << 9)
221/* true: save or restore error */
222#define STS_SRE (1 << 10)
223/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
224#define STS_CNR XHCI_STS_CNR
225/* true: internal Host Controller Error - SW needs to reset and reinitialize */
226#define STS_HCE (1 << 12)
227/* bits 13:31 reserved and should be preserved */
228
229/*
230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
231 * Generate a device notification event when the HC sees a transaction with a
232 * notification type that matches a bit set in this bit field.
233 */
234#define DEV_NOTE_MASK (0xffff)
235#define ENABLE_DEV_NOTE(x) (1 << x)
236/* Most of the device notification types should only be used for debug.
237 * SW does need to pay attention to function wake notifications.
238 */
239#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
240
0ebbab37
SS		 241/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
242/* bit 0 is the command ring cycle state */
243/* stop ring operation after completion of the currently executing command */
244#define CMD_RING_PAUSE (1 << 1)
245/* stop ring immediately - abort the currently executing command */
246#define CMD_RING_ABORT (1 << 2)
247/* true: command ring is running */
248#define CMD_RING_RUNNING (1 << 3)
249/* bits 4:5 reserved and should be preserved */
250/* Command Ring pointer - bit mask for the lower 32 bits. */
8e595a5d 251#define CMD_RING_RSVD_BITS (0x3f)
0ebbab37 252
74c68741
SS		 253/* CONFIG - Configure Register - config_reg bitmasks */
254/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
255#define MAX_DEVS(p) ((p) & 0xff)
256/* bits 8:31 - reserved and should be preserved */
257
258/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
259/* true: device connected */
260#define PORT_CONNECT (1 << 0)
261/* true: port enabled */
262#define PORT_PE (1 << 1)
263/* bit 2 reserved and zeroed */
264/* true: port has an over-current condition */
265#define PORT_OC (1 << 3)
266/* true: port reset signaling asserted */
267#define PORT_RESET (1 << 4)
268/* Port Link State - bits 5:8
269 * A read gives the current link PM state of the port,
270 * a write with Link State Write Strobe set sets the link state.
271 */
272/* true: port has power (see HCC_PPC) */
273#define PORT_POWER (1 << 9)
274/* bits 10:13 indicate device speed:
275 * 0 - undefined speed - port hasn't be initialized by a reset yet
276 * 1 - full speed
277 * 2 - low speed
278 * 3 - high speed
279 * 4 - super speed
280 * 5-15 reserved
281 */
3ffbba95
SS		 282#define DEV_SPEED_MASK (0xf << 10)
283#define XDEV_FS (0x1 << 10)
284#define XDEV_LS (0x2 << 10)
285#define XDEV_HS (0x3 << 10)
286#define XDEV_SS (0x4 << 10)
74c68741 287#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
3ffbba95
SS		 288#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
289#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
290#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
291#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
292/* Bits 20:23 in the Slot Context are the speed for the device */
293#define SLOT_SPEED_FS (XDEV_FS << 10)
294#define SLOT_SPEED_LS (XDEV_LS << 10)
295#define SLOT_SPEED_HS (XDEV_HS << 10)
296#define SLOT_SPEED_SS (XDEV_SS << 10)
74c68741
SS		 297/* Port Indicator Control */
298#define PORT_LED_OFF (0 << 14)
299#define PORT_LED_AMBER (1 << 14)
300#define PORT_LED_GREEN (2 << 14)
301#define PORT_LED_MASK (3 << 14)
302/* Port Link State Write Strobe - set this when changing link state */
303#define PORT_LINK_STROBE (1 << 16)
304/* true: connect status change */
305#define PORT_CSC (1 << 17)
306/* true: port enable change */
307#define PORT_PEC (1 << 18)
308/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
309 * into an enabled state, and the device into the default state. A "warm" reset
310 * also resets the link, forcing the device through the link training sequence.
311 * SW can also look at the Port Reset register to see when warm reset is done.
312 */
313#define PORT_WRC (1 << 19)
314/* true: over-current change */
315#define PORT_OCC (1 << 20)
316/* true: reset change - 1 to 0 transition of PORT_RESET */
317#define PORT_RC (1 << 21)
318/* port link status change - set on some port link state transitions:
319 * Transition Reason
320 * ------------------------------------------------------------------------------
321 * - U3 to Resume Wakeup signaling from a device
322 * - Resume to Recovery to U0 USB 3.0 device resume
323 * - Resume to U0 USB 2.0 device resume
324 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
325 * - U3 to U0 Software resume of USB 2.0 device complete
326 * - U2 to U0 L1 resume of USB 2.1 device complete
327 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
328 * - U0 to disabled L1 entry error with USB 2.1 device
329 * - Any state to inactive Error on USB 3.0 port
330 */
331#define PORT_PLC (1 << 22)
332/* port configure error change - port failed to configure its link partner */
333#define PORT_CEC (1 << 23)
334/* bit 24 reserved */
335/* wake on connect (enable) */
336#define PORT_WKCONN_E (1 << 25)
337/* wake on disconnect (enable) */
338#define PORT_WKDISC_E (1 << 26)
339/* wake on over-current (enable) */
340#define PORT_WKOC_E (1 << 27)
341/* bits 28:29 reserved */
342/* true: device is removable - for USB 3.0 roothub emulation */
343#define PORT_DEV_REMOVE (1 << 30)
344/* Initiate a warm port reset - complete when PORT_WRC is '1' */
345#define PORT_WR (1 << 31)
346
347/* Port Power Management Status and Control - port_power_base bitmasks */
348/* Inactivity timer value for transitions into U1, in microseconds.
349 * Timeout can be up to 127us. 0xFF means an infinite timeout.
350 */
351#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
352/* Inactivity timer value for transitions into U2 */
353#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
354/* Bits 24:31 for port testing */
355
356
357/**
98441973 358 * struct xhci_intr_reg - Interrupt Register Set
74c68741
SS		 359 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
360 * interrupts and check for pending interrupts.
361 * @irq_control: IMOD - Interrupt Moderation Register.
362 * Used to throttle interrupts.
363 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
364 * @erst_base: ERST base address.
365 * @erst_dequeue: Event ring dequeue pointer.
366 *
367 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
368 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
369 * multiple segments of the same size. The HC places events on the ring and
370 * "updates the Cycle bit in the TRBs to indicate to software the current
371 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
372 * updates the dequeue pointer.
373 */
98441973 374struct xhci_intr_reg {
74c68741
SS		 375 u32 irq_pending;
376 u32 irq_control;
377 u32 erst_size;
378 u32 rsvd;
8e595a5d
SS		 379 u64 erst_base;
380 u64 erst_dequeue;
98441973 381};
74c68741 382
66d4eadd 383/* irq_pending bitmasks */
74c68741 384#define ER_IRQ_PENDING(p) ((p) & 0x1)
66d4eadd 385/* bits 2:31 need to be preserved */
7f84eef0 386/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
66d4eadd
SS		 387#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
388#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
389#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
390
391/* irq_control bitmasks */
392/* Minimum interval between interrupts (in 250ns intervals). The interval
393 * between interrupts will be longer if there are no events on the event ring.
394 * Default is 4000 (1 ms).
395 */
396#define ER_IRQ_INTERVAL_MASK (0xffff)
397/* Counter used to count down the time to the next interrupt - HW use only */
398#define ER_IRQ_COUNTER_MASK (0xffff << 16)
399
400/* erst_size bitmasks */
74c68741 401/* Preserve bits 16:31 of erst_size */
66d4eadd
SS		 402#define ERST_SIZE_MASK (0xffff << 16)
403
404/* erst_dequeue bitmasks */
405/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
406 * where the current dequeue pointer lies. This is an optional HW hint.
407 */
408#define ERST_DESI_MASK (0x7)
409/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
410 * a work queue (or delayed service routine)?
411 */
412#define ERST_EHB (1 << 3)
0ebbab37 413#define ERST_PTR_MASK (0xf)
74c68741
SS		 414
415/**
416 * struct xhci_run_regs
417 * @microframe_index:
418 * MFINDEX - current microframe number
419 *
420 * Section 5.5 Host Controller Runtime Registers:
421 * "Software should read and write these registers using only Dword (32 bit)
422 * or larger accesses"
423 */
424struct xhci_run_regs {
98441973
SS		 425 u32 microframe_index;
426 u32 rsvd[7];
427 struct xhci_intr_reg ir_set[128];
428};
74c68741 429
0ebbab37
SS		 430/**
431 * struct doorbell_array
432 *
433 * Section 5.6
434 */
435struct xhci_doorbell_array {
436 u32 doorbell[256];
98441973 437};
0ebbab37
SS		 438
439#define DB_TARGET_MASK 0xFFFFFF00
440#define DB_STREAM_ID_MASK 0x0000FFFF
441#define DB_TARGET_HOST 0x0
442#define DB_STREAM_ID_HOST 0x0
443#define DB_MASK (0xff << 8)
444
d0e96f5a
SS		 445/* Endpoint Target - bits 0:7 */
446#define EPI_TO_DB(p) (((p) + 1) & 0xff)
447
0ebbab37 448
d115b048
JY		 449/**
450 * struct xhci_container_ctx
451 * @type: Type of context. Used to calculated offsets to contained contexts.
452 * @size: Size of the context data
453 * @bytes: The raw context data given to HW
454 * @dma: dma address of the bytes
455 *
456 * Represents either a Device or Input context. Holds a pointer to the raw
457 * memory used for the context (bytes) and dma address of it (dma).
458 */
459struct xhci_container_ctx {
460 unsigned type;
461#define XHCI_CTX_TYPE_DEVICE 0x1
462#define XHCI_CTX_TYPE_INPUT 0x2
463
464 int size;
465
466 u8 *bytes;
467 dma_addr_t dma;
468};
469
a74588f9
SS		 470/**
471 * struct xhci_slot_ctx
472 * @dev_info: Route string, device speed, hub info, and last valid endpoint
473 * @dev_info2: Max exit latency for device number, root hub port number
474 * @tt_info: tt_info is used to construct split transaction tokens
475 * @dev_state: slot state and device address
476 *
477 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
478 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
479 * reserved at the end of the slot context for HC internal use.
480 */
481struct xhci_slot_ctx {
482 u32 dev_info;
483 u32 dev_info2;
484 u32 tt_info;
485 u32 dev_state;
486 /* offset 0x10 to 0x1f reserved for HC internal use */
487 u32 reserved[4];
98441973 488};
a74588f9
SS		 489
490/* dev_info bitmasks */
491/* Route String - 0:19 */
492#define ROUTE_STRING_MASK (0xfffff)
493/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
494#define DEV_SPEED (0xf << 20)
495/* bit 24 reserved */
496/* Is this LS/FS device connected through a HS hub? - bit 25 */
497#define DEV_MTT (0x1 << 25)
498/* Set if the device is a hub - bit 26 */
499#define DEV_HUB (0x1 << 26)
500/* Index of the last valid endpoint context in this device context - 27:31 */
3ffbba95
SS		 501#define LAST_CTX_MASK (0x1f << 27)
502#define LAST_CTX(p) ((p) << 27)
503#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
3ffbba95
SS		 504#define SLOT_FLAG (1 << 0)
505#define EP0_FLAG (1 << 1)
a74588f9
SS		 506
507/* dev_info2 bitmasks */
508/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
509#define MAX_EXIT (0xffff)
510/* Root hub port number that is needed to access the USB device */
3ffbba95 511#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
ac1c1b7f
SS		 512/* Maximum number of ports under a hub device */
513#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
a74588f9
SS		 514
515/* tt_info bitmasks */
516/*
517 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
518 * The Slot ID of the hub that isolates the high speed signaling from
519 * this low or full-speed device. '0' if attached to root hub port.
520 */
521#define TT_SLOT (0xff)
522/*
523 * The number of the downstream facing port of the high-speed hub
524 * '0' if the device is not low or full speed.
525 */
526#define TT_PORT (0xff << 8)
ac1c1b7f 527#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
a74588f9
SS		 528
529/* dev_state bitmasks */
530/* USB device address - assigned by the HC */
3ffbba95 531#define DEV_ADDR_MASK (0xff)
a74588f9
SS		 532/* bits 8:26 reserved */
533/* Slot state */
534#define SLOT_STATE (0x1f << 27)
ae636747 535#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
a74588f9
SS		 536
537
538/**
539 * struct xhci_ep_ctx
540 * @ep_info: endpoint state, streams, mult, and interval information.
541 * @ep_info2: information on endpoint type, max packet size, max burst size,
542 * error count, and whether the HC will force an event for all
543 * transactions.
3ffbba95
SS		 544 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
545 * defines one stream, this points to the endpoint transfer ring.
546 * Otherwise, it points to a stream context array, which has a
547 * ring pointer for each flow.
548 * @tx_info:
549 * Average TRB lengths for the endpoint ring and
550 * max payload within an Endpoint Service Interval Time (ESIT).
a74588f9
SS		 551 *
552 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
553 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
554 * reserved at the end of the endpoint context for HC internal use.
555 */
556struct xhci_ep_ctx {
557 u32 ep_info;
558 u32 ep_info2;
8e595a5d 559 u64 deq;
3ffbba95 560 u32 tx_info;
a74588f9 561 /* offset 0x14 - 0x1f reserved for HC internal use */
3ffbba95 562 u32 reserved[3];
98441973 563};
a74588f9
SS		 564
565/* ep_info bitmasks */
566/*
567 * Endpoint State - bits 0:2
568 * 0 - disabled
569 * 1 - running
570 * 2 - halted due to halt condition - ok to manipulate endpoint ring
571 * 3 - stopped
572 * 4 - TRB error
573 * 5-7 - reserved
574 */
d0e96f5a
SS		 575#define EP_STATE_MASK (0xf)
576#define EP_STATE_DISABLED 0
577#define EP_STATE_RUNNING 1
578#define EP_STATE_HALTED 2
579#define EP_STATE_STOPPED 3
580#define EP_STATE_ERROR 4
a74588f9
SS		 581/* Mult - Max number of burtst within an interval, in EP companion desc. */
582#define EP_MULT(p) ((p & 0x3) << 8)
583/* bits 10:14 are Max Primary Streams */
584/* bit 15 is Linear Stream Array */
585/* Interval - period between requests to an endpoint - 125u increments. */
f94e0186 586#define EP_INTERVAL(p) ((p & 0xff) << 16)
624defa1 587#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
a74588f9
SS		 588
589/* ep_info2 bitmasks */
590/*
591 * Force Event - generate transfer events for all TRBs for this endpoint
592 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
593 */
594#define FORCE_EVENT (0x1)
595#define ERROR_COUNT(p) (((p) & 0x3) << 1)
82d1009f 596#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
a74588f9
SS		 597#define EP_TYPE(p) ((p) << 3)
598#define ISOC_OUT_EP 1
599#define BULK_OUT_EP 2
600#define INT_OUT_EP 3
601#define CTRL_EP 4
602#define ISOC_IN_EP 5
603#define BULK_IN_EP 6
604#define INT_IN_EP 7
605/* bit 6 reserved */
606/* bit 7 is Host Initiate Disable - for disabling stream selection */
607#define MAX_BURST(p) (((p)&0xff) << 8)
608#define MAX_PACKET(p) (((p)&0xffff) << 16)
2d3f1fac
SS		 609#define MAX_PACKET_MASK (0xffff << 16)
610#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
a74588f9
SS		 611
612
613/**
d115b048
JY		 614 * struct xhci_input_control_context
615 * Input control context; see section 6.2.5.
a74588f9
SS		 616 *
617 * @drop_context: set the bit of the endpoint context you want to disable
618 * @add_context: set the bit of the endpoint context you want to enable
619 */
d115b048 620struct xhci_input_control_ctx {
a74588f9
SS		 621 u32 drop_flags;
622 u32 add_flags;
d115b048 623 u32 rsvd2[6];
98441973 624};
a74588f9 625
913a8a34
SS		 626/* Represents everything that is needed to issue a command on the command ring.
627 * It's useful to pre-allocate these for commands that cannot fail due to
628 * out-of-memory errors, like freeing streams.
629 */
630struct xhci_command {
631 /* Input context for changing device state */
632 struct xhci_container_ctx *in_ctx;
633 u32 status;
634 /* If completion is null, no one is waiting on this command
635 * and the structure can be freed after the command completes.
636 */
637 struct completion *completion;
638 union xhci_trb *command_trb;
639 struct list_head cmd_list;
640};
641
a74588f9
SS		 642/* drop context bitmasks */
643#define DROP_EP(x) (0x1 << x)
644/* add context bitmasks */
645#define ADD_EP(x) (0x1 << x)
646
63a0d9ab
SS		 647struct xhci_virt_ep {
648 struct xhci_ring *ring;
649 /* Temporary storage in case the configure endpoint command fails and we
650 * have to restore the device state to the previous state
651 */
652 struct xhci_ring *new_ring;
653 unsigned int ep_state;
654#define SET_DEQ_PENDING (1 << 0)
678539cf
SS		 655#define EP_HALTED (1 << 1) /* For stall handling */
656#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
63a0d9ab
SS		 657 /* ---- Related to URB cancellation ---- */
658 struct list_head cancelled_td_list;
63a0d9ab
SS		 659 /* The TRB that was last reported in a stopped endpoint ring */
660 union xhci_trb *stopped_trb;
661 struct xhci_td *stopped_td;
6f5165cf
SS		 662 /* Watchdog timer for stop endpoint command to cancel URBs */
663 struct timer_list stop_cmd_timer;
664 int stop_cmds_pending;
665 struct xhci_hcd *xhci;
63a0d9ab
SS		 666};
667
3ffbba95
SS		 668struct xhci_virt_device {
669 /*
670 * Commands to the hardware are passed an "input context" that
671 * tells the hardware what to change in its data structures.
672 * The hardware will return changes in an "output context" that
673 * software must allocate for the hardware. We need to keep
674 * track of input and output contexts separately because
675 * these commands might fail and we don't trust the hardware.
676 */
d115b048 677 struct xhci_container_ctx *out_ctx;
3ffbba95 678 /* Used for addressing devices and configuration changes */
d115b048 679 struct xhci_container_ctx *in_ctx;
63a0d9ab 680 struct xhci_virt_ep eps[31];
f94e0186 681 struct completion cmd_completion;
3ffbba95
SS		 682 /* Status of the last command issued for this device */
683 u32 cmd_status;
913a8a34 684 struct list_head cmd_list;
3ffbba95
SS		 685};
686
687
a74588f9
SS		 688/**
689 * struct xhci_device_context_array
690 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
691 */
692struct xhci_device_context_array {
693 /* 64-bit device addresses; we only write 32-bit addresses */
8e595a5d 694 u64 dev_context_ptrs[MAX_HC_SLOTS];
a74588f9
SS		 695 /* private xHCD pointers */
696 dma_addr_t dma;
98441973 697};
a74588f9
SS		 698/* TODO: write function to set the 64-bit device DMA address */
699/*
700 * TODO: change this to be dynamically sized at HC mem init time since the HC
701 * might not be able to handle the maximum number of devices possible.
702 */
703
704
705struct xhci_stream_ctx {
706 /* 64-bit stream ring address, cycle state, and stream type */
8e595a5d 707 u64 stream_ring;
a74588f9
SS		 708 /* offset 0x14 - 0x1f reserved for HC internal use */
709 u32 reserved[2];
98441973 710};
a74588f9
SS		 711
712
0ebbab37
SS		 713struct xhci_transfer_event {
714 /* 64-bit buffer address, or immediate data */
8e595a5d 715 u64 buffer;
0ebbab37
SS		 716 u32 transfer_len;
717 /* This field is interpreted differently based on the type of TRB */
718 u32 flags;
98441973 719};
0ebbab37 720
d0e96f5a
SS		 721/** Transfer Event bit fields **/
722#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
723
0ebbab37
SS		 724/* Completion Code - only applicable for some types of TRBs */
725#define COMP_CODE_MASK (0xff << 24)
726#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
727#define COMP_SUCCESS 1
728/* Data Buffer Error */
729#define COMP_DB_ERR 2
730/* Babble Detected Error */
731#define COMP_BABBLE 3
732/* USB Transaction Error */
733#define COMP_TX_ERR 4
734/* TRB Error - some TRB field is invalid */
735#define COMP_TRB_ERR 5
736/* Stall Error - USB device is stalled */
737#define COMP_STALL 6
738/* Resource Error - HC doesn't have memory for that device configuration */
739#define COMP_ENOMEM 7
740/* Bandwidth Error - not enough room in schedule for this dev config */
741#define COMP_BW_ERR 8
742/* No Slots Available Error - HC ran out of device slots */
743#define COMP_ENOSLOTS 9
744/* Invalid Stream Type Error */
745#define COMP_STREAM_ERR 10
746/* Slot Not Enabled Error - doorbell rung for disabled device slot */
747#define COMP_EBADSLT 11
748/* Endpoint Not Enabled Error */
749#define COMP_EBADEP 12
750/* Short Packet */
751#define COMP_SHORT_TX 13
752/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
753#define COMP_UNDERRUN 14
754/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
755#define COMP_OVERRUN 15
756/* Virtual Function Event Ring Full Error */
757#define COMP_VF_FULL 16
758/* Parameter Error - Context parameter is invalid */
759#define COMP_EINVAL 17
760/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
761#define COMP_BW_OVER 18
762/* Context State Error - illegal context state transition requested */
763#define COMP_CTX_STATE 19
764/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
765#define COMP_PING_ERR 20
766/* Event Ring is full */
767#define COMP_ER_FULL 21
768/* Missed Service Error - HC couldn't service an isoc ep within interval */
769#define COMP_MISSED_INT 23
770/* Successfully stopped command ring */
771#define COMP_CMD_STOP 24
772/* Successfully aborted current command and stopped command ring */
773#define COMP_CMD_ABORT 25
774/* Stopped - transfer was terminated by a stop endpoint command */
775#define COMP_STOP 26
776/* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */
777#define COMP_STOP_INVAL 27
778/* Control Abort Error - Debug Capability - control pipe aborted */
779#define COMP_DBG_ABORT 28
780/* TRB type 29 and 30 reserved */
781/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
782#define COMP_BUFF_OVER 31
783/* Event Lost Error - xHC has an "internal event overrun condition" */
784#define COMP_ISSUES 32
785/* Undefined Error - reported when other error codes don't apply */
786#define COMP_UNKNOWN 33
787/* Invalid Stream ID Error */
788#define COMP_STRID_ERR 34
789/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
790/* FIXME - check for this */
791#define COMP_2ND_BW_ERR 35
792/* Split Transaction Error */
793#define COMP_SPLIT_ERR 36
794
795struct xhci_link_trb {
796 /* 64-bit segment pointer*/
8e595a5d 797 u64 segment_ptr;
0ebbab37
SS		 798 u32 intr_target;
799 u32 control;
98441973 800};
0ebbab37
SS		 801
802/* control bitfields */
803#define LINK_TOGGLE (0x1<<1)
804
7f84eef0
SS		 805/* Command completion event TRB */
806struct xhci_event_cmd {
807 /* Pointer to command TRB, or the value passed by the event data trb */
8e595a5d 808 u64 cmd_trb;
7f84eef0
SS		 809 u32 status;
810 u32 flags;
98441973 811};
0ebbab37 812
3ffbba95
SS		 813/* flags bitmasks */
814/* bits 16:23 are the virtual function ID */
815/* bits 24:31 are the slot ID */
816#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
817#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
0ebbab37 818
ae636747
SS		 819/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
820#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
821#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
822
823
0f2a7930
SS		 824/* Port Status Change Event TRB fields */
825/* Port ID - bits 31:24 */
826#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
827
0ebbab37
SS		 828/* Normal TRB fields */
829/* transfer_len bitmasks - bits 0:16 */
830#define TRB_LEN(p) ((p) & 0x1ffff)
0ebbab37
SS		 831/* Interrupter Target - which MSI-X vector to target the completion event at */
832#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
833#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
834
835/* Cycle bit - indicates TRB ownership by HC or HCD */
836#define TRB_CYCLE (1<<0)
837/*
838 * Force next event data TRB to be evaluated before task switch.
839 * Used to pass OS data back after a TD completes.
840 */
841#define TRB_ENT (1<<1)
842/* Interrupt on short packet */
843#define TRB_ISP (1<<2)
844/* Set PCIe no snoop attribute */
845#define TRB_NO_SNOOP (1<<3)
846/* Chain multiple TRBs into a TD */
847#define TRB_CHAIN (1<<4)
848/* Interrupt on completion */
849#define TRB_IOC (1<<5)
850/* The buffer pointer contains immediate data */
851#define TRB_IDT (1<<6)
852
853
854/* Control transfer TRB specific fields */
855#define TRB_DIR_IN (1<<16)
856
7f84eef0
SS		 857struct xhci_generic_trb {
858 u32 field[4];
98441973 859};
7f84eef0
SS		 860
861union xhci_trb {
862 struct xhci_link_trb link;
863 struct xhci_transfer_event trans_event;
864 struct xhci_event_cmd event_cmd;
865 struct xhci_generic_trb generic;
866};
867
0ebbab37
SS		 868/* TRB bit mask */
869#define TRB_TYPE_BITMASK (0xfc00)
870#define TRB_TYPE(p) ((p) << 10)
871/* TRB type IDs */
872/* bulk, interrupt, isoc scatter/gather, and control data stage */
873#define TRB_NORMAL 1
874/* setup stage for control transfers */
875#define TRB_SETUP 2
876/* data stage for control transfers */
877#define TRB_DATA 3
878/* status stage for control transfers */
879#define TRB_STATUS 4
880/* isoc transfers */
881#define TRB_ISOC 5
882/* TRB for linking ring segments */
883#define TRB_LINK 6
884#define TRB_EVENT_DATA 7
885/* Transfer Ring No-op (not for the command ring) */
886#define TRB_TR_NOOP 8
887/* Command TRBs */
888/* Enable Slot Command */
889#define TRB_ENABLE_SLOT 9
890/* Disable Slot Command */
891#define TRB_DISABLE_SLOT 10
892/* Address Device Command */
893#define TRB_ADDR_DEV 11
894/* Configure Endpoint Command */
895#define TRB_CONFIG_EP 12
896/* Evaluate Context Command */
897#define TRB_EVAL_CONTEXT 13
a1587d97
SS		 898/* Reset Endpoint Command */
899#define TRB_RESET_EP 14
0ebbab37
SS		 900/* Stop Transfer Ring Command */
901#define TRB_STOP_RING 15
902/* Set Transfer Ring Dequeue Pointer Command */
903#define TRB_SET_DEQ 16
904/* Reset Device Command */
905#define TRB_RESET_DEV 17
906/* Force Event Command (opt) */
907#define TRB_FORCE_EVENT 18
908/* Negotiate Bandwidth Command (opt) */
909#define TRB_NEG_BANDWIDTH 19
910/* Set Latency Tolerance Value Command (opt) */
911#define TRB_SET_LT 20
912/* Get port bandwidth Command */
913#define TRB_GET_BW 21
914/* Force Header Command - generate a transaction or link management packet */
915#define TRB_FORCE_HEADER 22
916/* No-op Command - not for transfer rings */
917#define TRB_CMD_NOOP 23
918/* TRB IDs 24-31 reserved */
919/* Event TRBS */
920/* Transfer Event */
921#define TRB_TRANSFER 32
922/* Command Completion Event */
923#define TRB_COMPLETION 33
924/* Port Status Change Event */
925#define TRB_PORT_STATUS 34
926/* Bandwidth Request Event (opt) */
927#define TRB_BANDWIDTH_EVENT 35
928/* Doorbell Event (opt) */
929#define TRB_DOORBELL 36
930/* Host Controller Event */
931#define TRB_HC_EVENT 37
932/* Device Notification Event - device sent function wake notification */
933#define TRB_DEV_NOTE 38
934/* MFINDEX Wrap Event - microframe counter wrapped */
935#define TRB_MFINDEX_WRAP 39
936/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
937
938/*
939 * TRBS_PER_SEGMENT must be a multiple of 4,
940 * since the command ring is 64-byte aligned.
941 * It must also be greater than 16.
942 */
943#define TRBS_PER_SEGMENT 64
913a8a34
SS		 944/* Allow two commands + a link TRB, along with any reserved command TRBs */
945#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
0ebbab37 946#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
b10de142
SS		 947/* TRB buffer pointers can't cross 64KB boundaries */
948#define TRB_MAX_BUFF_SHIFT 16
949#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
0ebbab37
SS		 950
951struct xhci_segment {
952 union xhci_trb *trbs;
953 /* private to HCD */
954 struct xhci_segment *next;
955 dma_addr_t dma;
98441973 956};
0ebbab37 957
ae636747
SS		 958struct xhci_td {
959 struct list_head td_list;
960 struct list_head cancelled_td_list;
961 struct urb *urb;
962 struct xhci_segment *start_seg;
963 union xhci_trb *first_trb;
964 union xhci_trb *last_trb;
965};
966
ac9d8fe7
SS		 967struct xhci_dequeue_state {
968 struct xhci_segment *new_deq_seg;
969 union xhci_trb *new_deq_ptr;
970 int new_cycle_state;
971};
972
0ebbab37
SS		 973struct xhci_ring {
974 struct xhci_segment *first_seg;
975 union xhci_trb *enqueue;
7f84eef0
SS		 976 struct xhci_segment *enq_seg;
977 unsigned int enq_updates;
0ebbab37 978 union xhci_trb *dequeue;
7f84eef0
SS		 979 struct xhci_segment *deq_seg;
980 unsigned int deq_updates;
d0e96f5a 981 struct list_head td_list;
0ebbab37
SS		 982 /*
983 * Write the cycle state into the TRB cycle field to give ownership of
984 * the TRB to the host controller (if we are the producer), or to check
985 * if we own the TRB (if we are the consumer). See section 4.9.1.
986 */
987 u32 cycle_state;
988};
989
990struct xhci_erst_entry {
991 /* 64-bit event ring segment address */
8e595a5d 992 u64 seg_addr;
0ebbab37
SS		 993 u32 seg_size;
994 /* Set to zero */
995 u32 rsvd;
98441973 996};
0ebbab37
SS		 997
998struct xhci_erst {
999 struct xhci_erst_entry *entries;
1000 unsigned int num_entries;
1001 /* xhci->event_ring keeps track of segment dma addresses */
1002 dma_addr_t erst_dma_addr;
1003 /* Num entries the ERST can contain */
1004 unsigned int erst_size;
1005};
1006
254c80a3
JY		 1007struct xhci_scratchpad {
1008 u64 *sp_array;
1009 dma_addr_t sp_dma;
1010 void **sp_buffers;
1011 dma_addr_t *sp_dma_buffers;
1012};
1013
0ebbab37
SS		 1014/*
1015 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1016 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1017 * meaning 64 ring segments.
1018 * Initial allocated size of the ERST, in number of entries */
1019#define ERST_NUM_SEGS 1
1020/* Initial allocated size of the ERST, in number of entries */
1021#define ERST_SIZE 64
1022/* Initial number of event segment rings allocated */
1023#define ERST_ENTRIES 1
7f84eef0
SS		 1024/* Poll every 60 seconds */
1025#define POLL_TIMEOUT 60
6f5165cf
SS		 1026/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1027#define XHCI_STOP_EP_CMD_TIMEOUT 5
0ebbab37
SS		 1028/* XXX: Make these module parameters */
1029
74c68741
SS		 1030
1031/* There is one ehci_hci structure per controller */
1032struct xhci_hcd {
1033 /* glue to PCI and HCD framework */
1034 struct xhci_cap_regs __iomem *cap_regs;
1035 struct xhci_op_regs __iomem *op_regs;
1036 struct xhci_run_regs __iomem *run_regs;
0ebbab37 1037 struct xhci_doorbell_array __iomem *dba;
66d4eadd 1038 /* Our HCD's current interrupter register set */
98441973 1039 struct xhci_intr_reg __iomem *ir_set;
74c68741
SS		 1040
1041 /* Cached register copies of read-only HC data */
1042 __u32 hcs_params1;
1043 __u32 hcs_params2;
1044 __u32 hcs_params3;
1045 __u32 hcc_params;
1046
1047 spinlock_t lock;
1048
1049 /* packed release number */
1050 u8 sbrn;
1051 u16 hci_version;
1052 u8 max_slots;
1053 u8 max_interrupters;
1054 u8 max_ports;
1055 u8 isoc_threshold;
1056 int event_ring_max;
1057 int addr_64;
66d4eadd 1058 /* 4KB min, 128MB max */
74c68741 1059 int page_size;
66d4eadd
SS		 1060 /* Valid values are 12 to 20, inclusive */
1061 int page_shift;
1062 /* only one MSI vector for now, but might need more later */
1063 int msix_count;
1064 struct msix_entry *msix_entries;
0ebbab37 1065 /* data structures */
a74588f9 1066 struct xhci_device_context_array *dcbaa;
0ebbab37 1067 struct xhci_ring *cmd_ring;
913a8a34 1068 unsigned int cmd_ring_reserved_trbs;
0ebbab37
SS		 1069 struct xhci_ring *event_ring;
1070 struct xhci_erst erst;
254c80a3
JY		 1071 /* Scratchpad */
1072 struct xhci_scratchpad *scratchpad;
1073
3ffbba95
SS		 1074 /* slot enabling and address device helpers */
1075 struct completion addr_dev;
1076 int slot_id;
1077 /* Internal mirror of the HW's dcbaa */
1078 struct xhci_virt_device *devs[MAX_HC_SLOTS];
0ebbab37
SS		 1079
1080 /* DMA pools */
1081 struct dma_pool *device_pool;
1082 struct dma_pool *segment_pool;
7f84eef0
SS		 1083
1084#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1085 /* Poll the rings - for debugging */
1086 struct timer_list event_ring_timer;
1087 int zombie;
1088#endif
6f5165cf
SS		 1089 /* Host controller watchdog timer structures */
1090 unsigned int xhc_state;
1091/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1092 *
1093 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1094 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1095 * that sees this status (other than the timer that set it) should stop touching
1096 * hardware immediately. Interrupt handlers should return immediately when
1097 * they see this status (any time they drop and re-acquire xhci->lock).
1098 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1099 * putting the TD on the canceled list, etc.
1100 *
1101 * There are no reports of xHCI host controllers that display this issue.
1102 */
1103#define XHCI_STATE_DYING (1 << 0)
7f84eef0
SS		 1104 /* Statistics */
1105 int noops_submitted;
1106 int noops_handled;
1107 int error_bitmask;
b0567b3f
SS		 1108 unsigned int quirks;
1109#define XHCI_LINK_TRB_QUIRK (1 << 0)
ac9d8fe7 1110#define XHCI_RESET_EP_QUIRK (1 << 1)
74c68741
SS		 1111};
1112
7f84eef0
SS		 1113/* For testing purposes */
1114#define NUM_TEST_NOOPS 0
1115
74c68741
SS		 1116/* convert between an HCD pointer and the corresponding EHCI_HCD */
1117static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1118{
1119 return (struct xhci_hcd *) (hcd->hcd_priv);
1120}
1121
1122static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1123{
1124 return container_of((void *) xhci, struct usb_hcd, hcd_priv);
1125}
1126
1127#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1128#define XHCI_DEBUG 1
1129#else
1130#define XHCI_DEBUG 0
1131#endif
1132
1133#define xhci_dbg(xhci, fmt, args...) \
1134 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1135#define xhci_info(xhci, fmt, args...) \
1136 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1137#define xhci_err(xhci, fmt, args...) \
1138 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1139#define xhci_warn(xhci, fmt, args...) \
1140 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1141
1142/* TODO: copied from ehci.h - can be refactored? */
1143/* xHCI spec says all registers are little endian */
1144static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1145 __u32 __iomem *regs)
1146{
1147 return readl(regs);
1148}
045f123d 1149static inline void xhci_writel(struct xhci_hcd *xhci,
74c68741
SS		 1150 const unsigned int val, __u32 __iomem *regs)
1151{
66e49d87
SS		 1152 xhci_dbg(xhci,
1153 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
1154 regs, val);
74c68741
SS		 1155 writel(val, regs);
1156}
1157
8e595a5d
SS		 1158/*
1159 * Registers should always be accessed with double word or quad word accesses.
1160 *
1161 * Some xHCI implementations may support 64-bit address pointers. Registers
1162 * with 64-bit address pointers should be written to with dword accesses by
1163 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1164 * xHCI implementations that do not support 64-bit address pointers will ignore
1165 * the high dword, and write order is irrelevant.
1166 */
1167static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1168 __u64 __iomem *regs)
1169{
1170 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1171 u64 val_lo = readl(ptr);
1172 u64 val_hi = readl(ptr + 1);
1173 return val_lo + (val_hi << 32);
1174}
1175static inline void xhci_write_64(struct xhci_hcd *xhci,
1176 const u64 val, __u64 __iomem *regs)
1177{
1178 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1179 u32 val_lo = lower_32_bits(val);
1180 u32 val_hi = upper_32_bits(val);
1181
66e49d87
SS		 1182 xhci_dbg(xhci,
1183 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
1184 regs, (long unsigned int) val);
8e595a5d
SS		 1185 writel(val_lo, ptr);
1186 writel(val_hi, ptr + 1);
1187}
1188
b0567b3f
SS		 1189static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1190{
1191 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
1192 return ((HC_VERSION(temp) == 0x95) &&
1193 (xhci->quirks & XHCI_LINK_TRB_QUIRK));
1194}
1195
66d4eadd 1196/* xHCI debugging */
98441973 1197void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
66d4eadd 1198void xhci_print_registers(struct xhci_hcd *xhci);
0ebbab37
SS		 1199void xhci_dbg_regs(struct xhci_hcd *xhci);
1200void xhci_print_run_regs(struct xhci_hcd *xhci);
d0e96f5a
SS		 1201void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1202void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
7f84eef0 1203void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
0ebbab37
SS		 1204void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1205void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1206void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
7f84eef0 1207void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
d115b048 1208void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
66d4eadd 1209
3dbda77e 1210/* xHCI memory management */
66d4eadd
SS		 1211void xhci_mem_cleanup(struct xhci_hcd *xhci);
1212int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
3ffbba95
SS		 1213void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1214int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1215int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
d0e96f5a 1216unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
f94e0186 1217unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
ac9d8fe7
SS		 1218unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1219unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
f94e0186 1220void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
f2217e8e 1221void xhci_endpoint_copy(struct xhci_hcd *xhci,
913a8a34
SS		 1222 struct xhci_container_ctx *in_ctx,
1223 struct xhci_container_ctx *out_ctx,
1224 unsigned int ep_index);
1225void xhci_slot_copy(struct xhci_hcd *xhci,
1226 struct xhci_container_ctx *in_ctx,
1227 struct xhci_container_ctx *out_ctx);
f88ba78d
SS		 1228int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1229 struct usb_device *udev, struct usb_host_endpoint *ep,
1230 gfp_t mem_flags);
f94e0186 1231void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
913a8a34
SS		 1232struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1233 bool allocate_completion, gfp_t mem_flags);
1234void xhci_free_command(struct xhci_hcd *xhci,
1235 struct xhci_command *command);
66d4eadd
SS		 1236
1237#ifdef CONFIG_PCI
1238/* xHCI PCI glue */
1239int xhci_register_pci(void);
1240void xhci_unregister_pci(void);
1241#endif
1242
1243/* xHCI host controller glue */
4f0f0bae 1244void xhci_quiesce(struct xhci_hcd *xhci);
66d4eadd
SS		 1245int xhci_halt(struct xhci_hcd *xhci);
1246int xhci_reset(struct xhci_hcd *xhci);
1247int xhci_init(struct usb_hcd *hcd);
1248int xhci_run(struct usb_hcd *hcd);
1249void xhci_stop(struct usb_hcd *hcd);
1250void xhci_shutdown(struct usb_hcd *hcd);
1251int xhci_get_frame(struct usb_hcd *hcd);
7f84eef0 1252irqreturn_t xhci_irq(struct usb_hcd *hcd);
3ffbba95
SS		 1253int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1254void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1255int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
ac1c1b7f
SS		 1256int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1257 struct usb_tt *tt, gfp_t mem_flags);
d0e96f5a
SS		 1258int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1259int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
f94e0186
SS		 1260int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1261int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
a1587d97 1262void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
f94e0186
SS		 1263int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1264void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
7f84eef0
SS		 1265
1266/* xHCI ring, segment, TRB, and TD functions */
23e3be11 1267dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
6648f29d
SS		 1268struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1269 union xhci_trb *start_trb, union xhci_trb *end_trb,
1270 dma_addr_t suspect_dma);
23e3be11
SS		 1271void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1272void *xhci_setup_one_noop(struct xhci_hcd *xhci);
b7258a4a 1273void xhci_handle_event(struct xhci_hcd *xhci);
23e3be11
SS		 1274void xhci_set_hc_event_deq(struct xhci_hcd *xhci);
1275int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1276int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1277 u32 slot_id);
1278int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
ae636747 1279 unsigned int ep_index);
23e3be11
SS		 1280int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1281 int slot_id, unsigned int ep_index);
1282int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1283 int slot_id, unsigned int ep_index);
624defa1
SS		 1284int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1285 int slot_id, unsigned int ep_index);
23e3be11 1286int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
913a8a34 1287 u32 slot_id, bool command_must_succeed);
f2217e8e 1288int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
23e3be11 1289 u32 slot_id);
a1587d97
SS		 1290int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1291 unsigned int ep_index);
c92bcfa7
SS		 1292void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1293 unsigned int slot_id, unsigned int ep_index,
1294 struct xhci_td *cur_td, struct xhci_dequeue_state *state);
1295void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
63a0d9ab
SS		 1296 unsigned int slot_id, unsigned int ep_index,
1297 struct xhci_dequeue_state *deq_state);
82d1009f 1298void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
63a0d9ab 1299 struct usb_device *udev, unsigned int ep_index);
ac9d8fe7
SS		 1300void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1301 unsigned int slot_id, unsigned int ep_index,
1302 struct xhci_dequeue_state *deq_state);
6f5165cf 1303void xhci_stop_endpoint_command_watchdog(unsigned long arg);
66d4eadd 1304
0f2a7930
SS		 1305/* xHCI roothub code */
1306int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1307 char *buf, u16 wLength);
1308int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1309
d115b048
JY		 1310/* xHCI contexts */
1311struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1312struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1313struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1314
74c68741 1315#endif /* __LINUX_XHCI_HCD_H */
Linux 6.x block layer and io_uring tree(s)