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trivial: media/video/cx88: add __init/__exit macros to cx88 drivers
[linux-2.6-block.git] / drivers / usb / host / xhci.h
CommitLineData
74c68741
SS		 1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __LINUX_XHCI_HCD_H
24#define __LINUX_XHCI_HCD_H
25
26#include <linux/usb.h>
7f84eef0 27#include <linux/timer.h>
8e595a5d 28#include <linux/kernel.h>
74c68741
SS		 29
30#include "../core/hcd.h"
31/* Code sharing between pci-quirks and xhci hcd */
32#include "xhci-ext-caps.h"
33
34/* xHCI PCI Configuration Registers */
35#define XHCI_SBRN_OFFSET (0x60)
36
66d4eadd
SS		 37/* Max number of USB devices for any host controller - limit in section 6.1 */
38#define MAX_HC_SLOTS 256
0f2a7930
SS		 39/* Section 5.3.3 - MaxPorts */
40#define MAX_HC_PORTS 127
66d4eadd 41
74c68741
SS		 42/*
43 * xHCI register interface.
44 * This corresponds to the eXtensible Host Controller Interface (xHCI)
45 * Revision 0.95 specification
74c68741
SS		 46 */
47
48/**
49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
50 * @hc_capbase: length of the capabilities register and HC version number
51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
54 * @hcc_params: HCCPARAMS - Capability Parameters
55 * @db_off: DBOFF - Doorbell array offset
56 * @run_regs_off: RTSOFF - Runtime register space offset
57 */
58struct xhci_cap_regs {
59 u32 hc_capbase;
60 u32 hcs_params1;
61 u32 hcs_params2;
62 u32 hcs_params3;
63 u32 hcc_params;
64 u32 db_off;
65 u32 run_regs_off;
66 /* Reserved up to (CAPLENGTH - 0x1C) */
98441973 67};
74c68741
SS		 68
69/* hc_capbase bitmasks */
70/* bits 7:0 - how long is the Capabilities register */
71#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
72/* bits 31:16 */
73#define HC_VERSION(p) (((p) >> 16) & 0xffff)
74
75/* HCSPARAMS1 - hcs_params1 - bitmasks */
76/* bits 0:7, Max Device Slots */
77#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
78#define HCS_SLOTS_MASK 0xff
79/* bits 8:18, Max Interrupters */
80#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
81/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
82#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
83
84/* HCSPARAMS2 - hcs_params2 - bitmasks */
85/* bits 0:3, frames or uframes that SW needs to queue transactions
86 * ahead of the HW to meet periodic deadlines */
87#define HCS_IST(p) (((p) >> 0) & 0xf)
88/* bits 4:7, max number of Event Ring segments */
89#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
90/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
254c80a3 92#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
74c68741
SS		 93
94/* HCSPARAMS3 - hcs_params3 - bitmasks */
95/* bits 0:7, Max U1 to U0 latency for the roothub ports */
96#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
97/* bits 16:31, Max U2 to U0 latency for the roothub ports */
98#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
99
100/* HCCPARAMS - hcc_params - bitmasks */
101/* true: HC can use 64-bit address pointers */
102#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
103/* true: HC can do bandwidth negotiation */
104#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
105/* true: HC uses 64-byte Device Context structures
106 * FIXME 64-byte context structures aren't supported yet.
107 */
108#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
109/* true: HC has port power switches */
110#define HCC_PPC(p) ((p) & (1 << 3))
111/* true: HC has port indicators */
112#define HCS_INDICATOR(p) ((p) & (1 << 4))
113/* true: HC has Light HC Reset Capability */
114#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
115/* true: HC supports latency tolerance messaging */
116#define HCC_LTC(p) ((p) & (1 << 6))
117/* true: no secondary Stream ID Support */
118#define HCC_NSS(p) ((p) & (1 << 7))
119/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
120#define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1))
121/* Extended Capabilities pointer from PCI base - section 5.3.6 */
122#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
123
124/* db_off bitmask - bits 0:1 reserved */
125#define DBOFF_MASK (~0x3)
126
127/* run_regs_off bitmask - bits 0:4 reserved */
128#define RTSOFF_MASK (~0x1f)
129
130
131/* Number of registers per port */
132#define NUM_PORT_REGS 4
133
134/**
135 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
136 * @command: USBCMD - xHC command register
137 * @status: USBSTS - xHC status register
138 * @page_size: This indicates the page size that the host controller
139 * supports. If bit n is set, the HC supports a page size
140 * of 2^(n+12), up to a 128MB page size.
141 * 4K is the minimum page size.
142 * @cmd_ring: CRP - 64-bit Command Ring Pointer
143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
144 * @config_reg: CONFIG - Configure Register
145 * @port_status_base: PORTSCn - base address for Port Status and Control
146 * Each port has a Port Status and Control register,
147 * followed by a Port Power Management Status and Control
148 * register, a Port Link Info register, and a reserved
149 * register.
150 * @port_power_base: PORTPMSCn - base address for
151 * Port Power Management Status and Control
152 * @port_link_base: PORTLIn - base address for Port Link Info (current
153 * Link PM state and control) for USB 2.1 and USB 3.0
154 * devices.
155 */
156struct xhci_op_regs {
157 u32 command;
158 u32 status;
159 u32 page_size;
160 u32 reserved1;
161 u32 reserved2;
162 u32 dev_notification;
8e595a5d 163 u64 cmd_ring;
74c68741
SS		 164 /* rsvd: offset 0x20-2F */
165 u32 reserved3[4];
8e595a5d 166 u64 dcbaa_ptr;
74c68741
SS		 167 u32 config_reg;
168 /* rsvd: offset 0x3C-3FF */
169 u32 reserved4[241];
170 /* port 1 registers, which serve as a base address for other ports */
171 u32 port_status_base;
172 u32 port_power_base;
173 u32 port_link_base;
174 u32 reserved5;
175 /* registers for ports 2-255 */
176 u32 reserved6[NUM_PORT_REGS*254];
98441973 177};
74c68741
SS		 178
179/* USBCMD - USB command - command bitmasks */
180/* start/stop HC execution - do not write unless HC is halted*/
181#define CMD_RUN XHCI_CMD_RUN
182/* Reset HC - resets internal HC state machine and all registers (except
183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
184 * The xHCI driver must reinitialize the xHC after setting this bit.
185 */
186#define CMD_RESET (1 << 1)
187/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
188#define CMD_EIE XHCI_CMD_EIE
189/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
190#define CMD_HSEIE XHCI_CMD_HSEIE
191/* bits 4:6 are reserved (and should be preserved on writes). */
192/* light reset (port status stays unchanged) - reset completed when this is 0 */
193#define CMD_LRESET (1 << 7)
194/* FIXME: ignoring host controller save/restore state for now. */
195#define CMD_CSS (1 << 8)
196#define CMD_CRS (1 << 9)
197/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
198#define CMD_EWE XHCI_CMD_EWE
199/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
201 * '0' means the xHC can power it off if all ports are in the disconnect,
202 * disabled, or powered-off state.
203 */
204#define CMD_PM_INDEX (1 << 11)
205/* bits 12:31 are reserved (and should be preserved on writes). */
206
207/* USBSTS - USB status - status bitmasks */
208/* HC not running - set to 1 when run/stop bit is cleared. */
209#define STS_HALT XHCI_STS_HALT
210/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
211#define STS_FATAL (1 << 2)
212/* event interrupt - clear this prior to clearing any IP flags in IR set*/
213#define STS_EINT (1 << 3)
214/* port change detect */
215#define STS_PORT (1 << 4)
216/* bits 5:7 reserved and zeroed */
217/* save state status - '1' means xHC is saving state */
218#define STS_SAVE (1 << 8)
219/* restore state status - '1' means xHC is restoring state */
220#define STS_RESTORE (1 << 9)
221/* true: save or restore error */
222#define STS_SRE (1 << 10)
223/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
224#define STS_CNR XHCI_STS_CNR
225/* true: internal Host Controller Error - SW needs to reset and reinitialize */
226#define STS_HCE (1 << 12)
227/* bits 13:31 reserved and should be preserved */
228
229/*
230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
231 * Generate a device notification event when the HC sees a transaction with a
232 * notification type that matches a bit set in this bit field.
233 */
234#define DEV_NOTE_MASK (0xffff)
235#define ENABLE_DEV_NOTE(x) (1 << x)
236/* Most of the device notification types should only be used for debug.
237 * SW does need to pay attention to function wake notifications.
238 */
239#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
240
0ebbab37
SS		 241/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
242/* bit 0 is the command ring cycle state */
243/* stop ring operation after completion of the currently executing command */
244#define CMD_RING_PAUSE (1 << 1)
245/* stop ring immediately - abort the currently executing command */
246#define CMD_RING_ABORT (1 << 2)
247/* true: command ring is running */
248#define CMD_RING_RUNNING (1 << 3)
249/* bits 4:5 reserved and should be preserved */
250/* Command Ring pointer - bit mask for the lower 32 bits. */
8e595a5d 251#define CMD_RING_RSVD_BITS (0x3f)
0ebbab37 252
74c68741
SS		 253/* CONFIG - Configure Register - config_reg bitmasks */
254/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
255#define MAX_DEVS(p) ((p) & 0xff)
256/* bits 8:31 - reserved and should be preserved */
257
258/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
259/* true: device connected */
260#define PORT_CONNECT (1 << 0)
261/* true: port enabled */
262#define PORT_PE (1 << 1)
263/* bit 2 reserved and zeroed */
264/* true: port has an over-current condition */
265#define PORT_OC (1 << 3)
266/* true: port reset signaling asserted */
267#define PORT_RESET (1 << 4)
268/* Port Link State - bits 5:8
269 * A read gives the current link PM state of the port,
270 * a write with Link State Write Strobe set sets the link state.
271 */
272/* true: port has power (see HCC_PPC) */
273#define PORT_POWER (1 << 9)
274/* bits 10:13 indicate device speed:
275 * 0 - undefined speed - port hasn't be initialized by a reset yet
276 * 1 - full speed
277 * 2 - low speed
278 * 3 - high speed
279 * 4 - super speed
280 * 5-15 reserved
281 */
3ffbba95
SS		 282#define DEV_SPEED_MASK (0xf << 10)
283#define XDEV_FS (0x1 << 10)
284#define XDEV_LS (0x2 << 10)
285#define XDEV_HS (0x3 << 10)
286#define XDEV_SS (0x4 << 10)
74c68741 287#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
3ffbba95
SS		 288#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
289#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
290#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
291#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
292/* Bits 20:23 in the Slot Context are the speed for the device */
293#define SLOT_SPEED_FS (XDEV_FS << 10)
294#define SLOT_SPEED_LS (XDEV_LS << 10)
295#define SLOT_SPEED_HS (XDEV_HS << 10)
296#define SLOT_SPEED_SS (XDEV_SS << 10)
74c68741
SS		 297/* Port Indicator Control */
298#define PORT_LED_OFF (0 << 14)
299#define PORT_LED_AMBER (1 << 14)
300#define PORT_LED_GREEN (2 << 14)
301#define PORT_LED_MASK (3 << 14)
302/* Port Link State Write Strobe - set this when changing link state */
303#define PORT_LINK_STROBE (1 << 16)
304/* true: connect status change */
305#define PORT_CSC (1 << 17)
306/* true: port enable change */
307#define PORT_PEC (1 << 18)
308/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
309 * into an enabled state, and the device into the default state. A "warm" reset
310 * also resets the link, forcing the device through the link training sequence.
311 * SW can also look at the Port Reset register to see when warm reset is done.
312 */
313#define PORT_WRC (1 << 19)
314/* true: over-current change */
315#define PORT_OCC (1 << 20)
316/* true: reset change - 1 to 0 transition of PORT_RESET */
317#define PORT_RC (1 << 21)
318/* port link status change - set on some port link state transitions:
319 * Transition Reason
320 * ------------------------------------------------------------------------------
321 * - U3 to Resume Wakeup signaling from a device
322 * - Resume to Recovery to U0 USB 3.0 device resume
323 * - Resume to U0 USB 2.0 device resume
324 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
325 * - U3 to U0 Software resume of USB 2.0 device complete
326 * - U2 to U0 L1 resume of USB 2.1 device complete
327 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
328 * - U0 to disabled L1 entry error with USB 2.1 device
329 * - Any state to inactive Error on USB 3.0 port
330 */
331#define PORT_PLC (1 << 22)
332/* port configure error change - port failed to configure its link partner */
333#define PORT_CEC (1 << 23)
334/* bit 24 reserved */
335/* wake on connect (enable) */
336#define PORT_WKCONN_E (1 << 25)
337/* wake on disconnect (enable) */
338#define PORT_WKDISC_E (1 << 26)
339/* wake on over-current (enable) */
340#define PORT_WKOC_E (1 << 27)
341/* bits 28:29 reserved */
342/* true: device is removable - for USB 3.0 roothub emulation */
343#define PORT_DEV_REMOVE (1 << 30)
344/* Initiate a warm port reset - complete when PORT_WRC is '1' */
345#define PORT_WR (1 << 31)
346
347/* Port Power Management Status and Control - port_power_base bitmasks */
348/* Inactivity timer value for transitions into U1, in microseconds.
349 * Timeout can be up to 127us. 0xFF means an infinite timeout.
350 */
351#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
352/* Inactivity timer value for transitions into U2 */
353#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
354/* Bits 24:31 for port testing */
355
356
357/**
98441973 358 * struct xhci_intr_reg - Interrupt Register Set
74c68741
SS		 359 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
360 * interrupts and check for pending interrupts.
361 * @irq_control: IMOD - Interrupt Moderation Register.
362 * Used to throttle interrupts.
363 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
364 * @erst_base: ERST base address.
365 * @erst_dequeue: Event ring dequeue pointer.
366 *
367 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
368 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
369 * multiple segments of the same size. The HC places events on the ring and
370 * "updates the Cycle bit in the TRBs to indicate to software the current
371 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
372 * updates the dequeue pointer.
373 */
98441973 374struct xhci_intr_reg {
74c68741
SS		 375 u32 irq_pending;
376 u32 irq_control;
377 u32 erst_size;
378 u32 rsvd;
8e595a5d
SS		 379 u64 erst_base;
380 u64 erst_dequeue;
98441973 381};
74c68741 382
66d4eadd 383/* irq_pending bitmasks */
74c68741 384#define ER_IRQ_PENDING(p) ((p) & 0x1)
66d4eadd 385/* bits 2:31 need to be preserved */
7f84eef0 386/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
66d4eadd
SS		 387#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
388#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
389#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
390
391/* irq_control bitmasks */
392/* Minimum interval between interrupts (in 250ns intervals). The interval
393 * between interrupts will be longer if there are no events on the event ring.
394 * Default is 4000 (1 ms).
395 */
396#define ER_IRQ_INTERVAL_MASK (0xffff)
397/* Counter used to count down the time to the next interrupt - HW use only */
398#define ER_IRQ_COUNTER_MASK (0xffff << 16)
399
400/* erst_size bitmasks */
74c68741 401/* Preserve bits 16:31 of erst_size */
66d4eadd
SS		 402#define ERST_SIZE_MASK (0xffff << 16)
403
404/* erst_dequeue bitmasks */
405/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
406 * where the current dequeue pointer lies. This is an optional HW hint.
407 */
408#define ERST_DESI_MASK (0x7)
409/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
410 * a work queue (or delayed service routine)?
411 */
412#define ERST_EHB (1 << 3)
0ebbab37 413#define ERST_PTR_MASK (0xf)
74c68741
SS		 414
415/**
416 * struct xhci_run_regs
417 * @microframe_index:
418 * MFINDEX - current microframe number
419 *
420 * Section 5.5 Host Controller Runtime Registers:
421 * "Software should read and write these registers using only Dword (32 bit)
422 * or larger accesses"
423 */
424struct xhci_run_regs {
98441973
SS		 425 u32 microframe_index;
426 u32 rsvd[7];
427 struct xhci_intr_reg ir_set[128];
428};
74c68741 429
0ebbab37
SS		 430/**
431 * struct doorbell_array
432 *
433 * Section 5.6
434 */
435struct xhci_doorbell_array {
436 u32 doorbell[256];
98441973 437};
0ebbab37
SS		 438
439#define DB_TARGET_MASK 0xFFFFFF00
440#define DB_STREAM_ID_MASK 0x0000FFFF
441#define DB_TARGET_HOST 0x0
442#define DB_STREAM_ID_HOST 0x0
443#define DB_MASK (0xff << 8)
444
d0e96f5a
SS		 445/* Endpoint Target - bits 0:7 */
446#define EPI_TO_DB(p) (((p) + 1) & 0xff)
447
0ebbab37 448
d115b048
JY		 449/**
450 * struct xhci_container_ctx
451 * @type: Type of context. Used to calculated offsets to contained contexts.
452 * @size: Size of the context data
453 * @bytes: The raw context data given to HW
454 * @dma: dma address of the bytes
455 *
456 * Represents either a Device or Input context. Holds a pointer to the raw
457 * memory used for the context (bytes) and dma address of it (dma).
458 */
459struct xhci_container_ctx {
460 unsigned type;
461#define XHCI_CTX_TYPE_DEVICE 0x1
462#define XHCI_CTX_TYPE_INPUT 0x2
463
464 int size;
465
466 u8 *bytes;
467 dma_addr_t dma;
468};
469
a74588f9
SS		 470/**
471 * struct xhci_slot_ctx
472 * @dev_info: Route string, device speed, hub info, and last valid endpoint
473 * @dev_info2: Max exit latency for device number, root hub port number
474 * @tt_info: tt_info is used to construct split transaction tokens
475 * @dev_state: slot state and device address
476 *
477 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
478 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
479 * reserved at the end of the slot context for HC internal use.
480 */
481struct xhci_slot_ctx {
482 u32 dev_info;
483 u32 dev_info2;
484 u32 tt_info;
485 u32 dev_state;
486 /* offset 0x10 to 0x1f reserved for HC internal use */
487 u32 reserved[4];
98441973 488};
a74588f9
SS		 489
490/* dev_info bitmasks */
491/* Route String - 0:19 */
492#define ROUTE_STRING_MASK (0xfffff)
493/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
494#define DEV_SPEED (0xf << 20)
495/* bit 24 reserved */
496/* Is this LS/FS device connected through a HS hub? - bit 25 */
497#define DEV_MTT (0x1 << 25)
498/* Set if the device is a hub - bit 26 */
499#define DEV_HUB (0x1 << 26)
500/* Index of the last valid endpoint context in this device context - 27:31 */
3ffbba95
SS		 501#define LAST_CTX_MASK (0x1f << 27)
502#define LAST_CTX(p) ((p) << 27)
503#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
3ffbba95
SS		 504#define SLOT_FLAG (1 << 0)
505#define EP0_FLAG (1 << 1)
a74588f9
SS		 506
507/* dev_info2 bitmasks */
508/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
509#define MAX_EXIT (0xffff)
510/* Root hub port number that is needed to access the USB device */
3ffbba95 511#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
a74588f9
SS		 512
513/* tt_info bitmasks */
514/*
515 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
516 * The Slot ID of the hub that isolates the high speed signaling from
517 * this low or full-speed device. '0' if attached to root hub port.
518 */
519#define TT_SLOT (0xff)
520/*
521 * The number of the downstream facing port of the high-speed hub
522 * '0' if the device is not low or full speed.
523 */
524#define TT_PORT (0xff << 8)
525
526/* dev_state bitmasks */
527/* USB device address - assigned by the HC */
3ffbba95 528#define DEV_ADDR_MASK (0xff)
a74588f9
SS		 529/* bits 8:26 reserved */
530/* Slot state */
531#define SLOT_STATE (0x1f << 27)
ae636747 532#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
a74588f9
SS		 533
534
535/**
536 * struct xhci_ep_ctx
537 * @ep_info: endpoint state, streams, mult, and interval information.
538 * @ep_info2: information on endpoint type, max packet size, max burst size,
539 * error count, and whether the HC will force an event for all
540 * transactions.
3ffbba95
SS		 541 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
542 * defines one stream, this points to the endpoint transfer ring.
543 * Otherwise, it points to a stream context array, which has a
544 * ring pointer for each flow.
545 * @tx_info:
546 * Average TRB lengths for the endpoint ring and
547 * max payload within an Endpoint Service Interval Time (ESIT).
a74588f9
SS		 548 *
549 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
550 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
551 * reserved at the end of the endpoint context for HC internal use.
552 */
553struct xhci_ep_ctx {
554 u32 ep_info;
555 u32 ep_info2;
8e595a5d 556 u64 deq;
3ffbba95 557 u32 tx_info;
a74588f9 558 /* offset 0x14 - 0x1f reserved for HC internal use */
3ffbba95 559 u32 reserved[3];
98441973 560};
a74588f9
SS		 561
562/* ep_info bitmasks */
563/*
564 * Endpoint State - bits 0:2
565 * 0 - disabled
566 * 1 - running
567 * 2 - halted due to halt condition - ok to manipulate endpoint ring
568 * 3 - stopped
569 * 4 - TRB error
570 * 5-7 - reserved
571 */
d0e96f5a
SS		 572#define EP_STATE_MASK (0xf)
573#define EP_STATE_DISABLED 0
574#define EP_STATE_RUNNING 1
575#define EP_STATE_HALTED 2
576#define EP_STATE_STOPPED 3
577#define EP_STATE_ERROR 4
a74588f9
SS		 578/* Mult - Max number of burtst within an interval, in EP companion desc. */
579#define EP_MULT(p) ((p & 0x3) << 8)
580/* bits 10:14 are Max Primary Streams */
581/* bit 15 is Linear Stream Array */
582/* Interval - period between requests to an endpoint - 125u increments. */
f94e0186 583#define EP_INTERVAL(p) ((p & 0xff) << 16)
a74588f9
SS		 584
585/* ep_info2 bitmasks */
586/*
587 * Force Event - generate transfer events for all TRBs for this endpoint
588 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
589 */
590#define FORCE_EVENT (0x1)
591#define ERROR_COUNT(p) (((p) & 0x3) << 1)
592#define EP_TYPE(p) ((p) << 3)
593#define ISOC_OUT_EP 1
594#define BULK_OUT_EP 2
595#define INT_OUT_EP 3
596#define CTRL_EP 4
597#define ISOC_IN_EP 5
598#define BULK_IN_EP 6
599#define INT_IN_EP 7
600/* bit 6 reserved */
601/* bit 7 is Host Initiate Disable - for disabling stream selection */
602#define MAX_BURST(p) (((p)&0xff) << 8)
603#define MAX_PACKET(p) (((p)&0xffff) << 16)
604
605
606/**
d115b048
JY		 607 * struct xhci_input_control_context
608 * Input control context; see section 6.2.5.
a74588f9
SS		 609 *
610 * @drop_context: set the bit of the endpoint context you want to disable
611 * @add_context: set the bit of the endpoint context you want to enable
612 */
d115b048 613struct xhci_input_control_ctx {
a74588f9
SS		 614 u32 drop_flags;
615 u32 add_flags;
d115b048 616 u32 rsvd2[6];
98441973 617};
a74588f9
SS		 618
619/* drop context bitmasks */
620#define DROP_EP(x) (0x1 << x)
621/* add context bitmasks */
622#define ADD_EP(x) (0x1 << x)
623
3ffbba95
SS		 624struct xhci_virt_device {
625 /*
626 * Commands to the hardware are passed an "input context" that
627 * tells the hardware what to change in its data structures.
628 * The hardware will return changes in an "output context" that
629 * software must allocate for the hardware. We need to keep
630 * track of input and output contexts separately because
631 * these commands might fail and we don't trust the hardware.
632 */
d115b048 633 struct xhci_container_ctx *out_ctx;
3ffbba95 634 /* Used for addressing devices and configuration changes */
d115b048
JY		 635 struct xhci_container_ctx *in_ctx;
636
3ffbba95
SS		 637 /* FIXME when stream support is added */
638 struct xhci_ring *ep_rings[31];
f94e0186
SS		 639 /* Temporary storage in case the configure endpoint command fails and we
640 * have to restore the device state to the previous state
641 */
642 struct xhci_ring *new_ep_rings[31];
643 struct completion cmd_completion;
3ffbba95
SS		 644 /* Status of the last command issued for this device */
645 u32 cmd_status;
646};
647
648
a74588f9
SS		 649/**
650 * struct xhci_device_context_array
651 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
652 */
653struct xhci_device_context_array {
654 /* 64-bit device addresses; we only write 32-bit addresses */
8e595a5d 655 u64 dev_context_ptrs[MAX_HC_SLOTS];
a74588f9
SS		 656 /* private xHCD pointers */
657 dma_addr_t dma;
98441973 658};
a74588f9
SS		 659/* TODO: write function to set the 64-bit device DMA address */
660/*
661 * TODO: change this to be dynamically sized at HC mem init time since the HC
662 * might not be able to handle the maximum number of devices possible.
663 */
664
665
666struct xhci_stream_ctx {
667 /* 64-bit stream ring address, cycle state, and stream type */
8e595a5d 668 u64 stream_ring;
a74588f9
SS		 669 /* offset 0x14 - 0x1f reserved for HC internal use */
670 u32 reserved[2];
98441973 671};
a74588f9
SS		 672
673
0ebbab37
SS		 674struct xhci_transfer_event {
675 /* 64-bit buffer address, or immediate data */
8e595a5d 676 u64 buffer;
0ebbab37
SS		 677 u32 transfer_len;
678 /* This field is interpreted differently based on the type of TRB */
679 u32 flags;
98441973 680};
0ebbab37 681
d0e96f5a
SS		 682/** Transfer Event bit fields **/
683#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
684
0ebbab37
SS		 685/* Completion Code - only applicable for some types of TRBs */
686#define COMP_CODE_MASK (0xff << 24)
687#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
688#define COMP_SUCCESS 1
689/* Data Buffer Error */
690#define COMP_DB_ERR 2
691/* Babble Detected Error */
692#define COMP_BABBLE 3
693/* USB Transaction Error */
694#define COMP_TX_ERR 4
695/* TRB Error - some TRB field is invalid */
696#define COMP_TRB_ERR 5
697/* Stall Error - USB device is stalled */
698#define COMP_STALL 6
699/* Resource Error - HC doesn't have memory for that device configuration */
700#define COMP_ENOMEM 7
701/* Bandwidth Error - not enough room in schedule for this dev config */
702#define COMP_BW_ERR 8
703/* No Slots Available Error - HC ran out of device slots */
704#define COMP_ENOSLOTS 9
705/* Invalid Stream Type Error */
706#define COMP_STREAM_ERR 10
707/* Slot Not Enabled Error - doorbell rung for disabled device slot */
708#define COMP_EBADSLT 11
709/* Endpoint Not Enabled Error */
710#define COMP_EBADEP 12
711/* Short Packet */
712#define COMP_SHORT_TX 13
713/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
714#define COMP_UNDERRUN 14
715/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
716#define COMP_OVERRUN 15
717/* Virtual Function Event Ring Full Error */
718#define COMP_VF_FULL 16
719/* Parameter Error - Context parameter is invalid */
720#define COMP_EINVAL 17
721/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
722#define COMP_BW_OVER 18
723/* Context State Error - illegal context state transition requested */
724#define COMP_CTX_STATE 19
725/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
726#define COMP_PING_ERR 20
727/* Event Ring is full */
728#define COMP_ER_FULL 21
729/* Missed Service Error - HC couldn't service an isoc ep within interval */
730#define COMP_MISSED_INT 23
731/* Successfully stopped command ring */
732#define COMP_CMD_STOP 24
733/* Successfully aborted current command and stopped command ring */
734#define COMP_CMD_ABORT 25
735/* Stopped - transfer was terminated by a stop endpoint command */
736#define COMP_STOP 26
737/* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */
738#define COMP_STOP_INVAL 27
739/* Control Abort Error - Debug Capability - control pipe aborted */
740#define COMP_DBG_ABORT 28
741/* TRB type 29 and 30 reserved */
742/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
743#define COMP_BUFF_OVER 31
744/* Event Lost Error - xHC has an "internal event overrun condition" */
745#define COMP_ISSUES 32
746/* Undefined Error - reported when other error codes don't apply */
747#define COMP_UNKNOWN 33
748/* Invalid Stream ID Error */
749#define COMP_STRID_ERR 34
750/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
751/* FIXME - check for this */
752#define COMP_2ND_BW_ERR 35
753/* Split Transaction Error */
754#define COMP_SPLIT_ERR 36
755
756struct xhci_link_trb {
757 /* 64-bit segment pointer*/
8e595a5d 758 u64 segment_ptr;
0ebbab37
SS		 759 u32 intr_target;
760 u32 control;
98441973 761};
0ebbab37
SS		 762
763/* control bitfields */
764#define LINK_TOGGLE (0x1<<1)
765
7f84eef0
SS		 766/* Command completion event TRB */
767struct xhci_event_cmd {
768 /* Pointer to command TRB, or the value passed by the event data trb */
8e595a5d 769 u64 cmd_trb;
7f84eef0
SS		 770 u32 status;
771 u32 flags;
98441973 772};
0ebbab37 773
3ffbba95
SS		 774/* flags bitmasks */
775/* bits 16:23 are the virtual function ID */
776/* bits 24:31 are the slot ID */
777#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
778#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
0ebbab37 779
ae636747
SS		 780/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
781#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
782#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
783
784
0f2a7930
SS		 785/* Port Status Change Event TRB fields */
786/* Port ID - bits 31:24 */
787#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
788
0ebbab37
SS		 789/* Normal TRB fields */
790/* transfer_len bitmasks - bits 0:16 */
791#define TRB_LEN(p) ((p) & 0x1ffff)
792/* TD size - number of bytes remaining in the TD (including this TRB):
793 * bits 17 - 21. Shift the number of bytes by 10. */
794#define TD_REMAINDER(p) ((((p) >> 10) & 0x1f) << 17)
795/* Interrupter Target - which MSI-X vector to target the completion event at */
796#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
797#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
798
799/* Cycle bit - indicates TRB ownership by HC or HCD */
800#define TRB_CYCLE (1<<0)
801/*
802 * Force next event data TRB to be evaluated before task switch.
803 * Used to pass OS data back after a TD completes.
804 */
805#define TRB_ENT (1<<1)
806/* Interrupt on short packet */
807#define TRB_ISP (1<<2)
808/* Set PCIe no snoop attribute */
809#define TRB_NO_SNOOP (1<<3)
810/* Chain multiple TRBs into a TD */
811#define TRB_CHAIN (1<<4)
812/* Interrupt on completion */
813#define TRB_IOC (1<<5)
814/* The buffer pointer contains immediate data */
815#define TRB_IDT (1<<6)
816
817
818/* Control transfer TRB specific fields */
819#define TRB_DIR_IN (1<<16)
820
7f84eef0
SS		 821struct xhci_generic_trb {
822 u32 field[4];
98441973 823};
7f84eef0
SS		 824
825union xhci_trb {
826 struct xhci_link_trb link;
827 struct xhci_transfer_event trans_event;
828 struct xhci_event_cmd event_cmd;
829 struct xhci_generic_trb generic;
830};
831
0ebbab37
SS		 832/* TRB bit mask */
833#define TRB_TYPE_BITMASK (0xfc00)
834#define TRB_TYPE(p) ((p) << 10)
835/* TRB type IDs */
836/* bulk, interrupt, isoc scatter/gather, and control data stage */
837#define TRB_NORMAL 1
838/* setup stage for control transfers */
839#define TRB_SETUP 2
840/* data stage for control transfers */
841#define TRB_DATA 3
842/* status stage for control transfers */
843#define TRB_STATUS 4
844/* isoc transfers */
845#define TRB_ISOC 5
846/* TRB for linking ring segments */
847#define TRB_LINK 6
848#define TRB_EVENT_DATA 7
849/* Transfer Ring No-op (not for the command ring) */
850#define TRB_TR_NOOP 8
851/* Command TRBs */
852/* Enable Slot Command */
853#define TRB_ENABLE_SLOT 9
854/* Disable Slot Command */
855#define TRB_DISABLE_SLOT 10
856/* Address Device Command */
857#define TRB_ADDR_DEV 11
858/* Configure Endpoint Command */
859#define TRB_CONFIG_EP 12
860/* Evaluate Context Command */
861#define TRB_EVAL_CONTEXT 13
a1587d97
SS		 862/* Reset Endpoint Command */
863#define TRB_RESET_EP 14
0ebbab37
SS		 864/* Stop Transfer Ring Command */
865#define TRB_STOP_RING 15
866/* Set Transfer Ring Dequeue Pointer Command */
867#define TRB_SET_DEQ 16
868/* Reset Device Command */
869#define TRB_RESET_DEV 17
870/* Force Event Command (opt) */
871#define TRB_FORCE_EVENT 18
872/* Negotiate Bandwidth Command (opt) */
873#define TRB_NEG_BANDWIDTH 19
874/* Set Latency Tolerance Value Command (opt) */
875#define TRB_SET_LT 20
876/* Get port bandwidth Command */
877#define TRB_GET_BW 21
878/* Force Header Command - generate a transaction or link management packet */
879#define TRB_FORCE_HEADER 22
880/* No-op Command - not for transfer rings */
881#define TRB_CMD_NOOP 23
882/* TRB IDs 24-31 reserved */
883/* Event TRBS */
884/* Transfer Event */
885#define TRB_TRANSFER 32
886/* Command Completion Event */
887#define TRB_COMPLETION 33
888/* Port Status Change Event */
889#define TRB_PORT_STATUS 34
890/* Bandwidth Request Event (opt) */
891#define TRB_BANDWIDTH_EVENT 35
892/* Doorbell Event (opt) */
893#define TRB_DOORBELL 36
894/* Host Controller Event */
895#define TRB_HC_EVENT 37
896/* Device Notification Event - device sent function wake notification */
897#define TRB_DEV_NOTE 38
898/* MFINDEX Wrap Event - microframe counter wrapped */
899#define TRB_MFINDEX_WRAP 39
900/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
901
902/*
903 * TRBS_PER_SEGMENT must be a multiple of 4,
904 * since the command ring is 64-byte aligned.
905 * It must also be greater than 16.
906 */
907#define TRBS_PER_SEGMENT 64
908#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
b10de142
SS		 909/* TRB buffer pointers can't cross 64KB boundaries */
910#define TRB_MAX_BUFF_SHIFT 16
911#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
0ebbab37
SS		 912
913struct xhci_segment {
914 union xhci_trb *trbs;
915 /* private to HCD */
916 struct xhci_segment *next;
917 dma_addr_t dma;
98441973 918};
0ebbab37 919
ae636747
SS		 920struct xhci_td {
921 struct list_head td_list;
922 struct list_head cancelled_td_list;
923 struct urb *urb;
924 struct xhci_segment *start_seg;
925 union xhci_trb *first_trb;
926 union xhci_trb *last_trb;
927};
928
0ebbab37
SS		 929struct xhci_ring {
930 struct xhci_segment *first_seg;
931 union xhci_trb *enqueue;
7f84eef0
SS		 932 struct xhci_segment *enq_seg;
933 unsigned int enq_updates;
0ebbab37 934 union xhci_trb *dequeue;
7f84eef0
SS		 935 struct xhci_segment *deq_seg;
936 unsigned int deq_updates;
d0e96f5a 937 struct list_head td_list;
ae636747
SS		 938 /* ---- Related to URB cancellation ---- */
939 struct list_head cancelled_td_list;
940 unsigned int cancels_pending;
941 unsigned int state;
942#define SET_DEQ_PENDING (1 << 0)
a1587d97 943#define EP_HALTED (1 << 1)
ae636747
SS		 944 /* The TRB that was last reported in a stopped endpoint ring */
945 union xhci_trb *stopped_trb;
946 struct xhci_td *stopped_td;
0ebbab37
SS		 947 /*
948 * Write the cycle state into the TRB cycle field to give ownership of
949 * the TRB to the host controller (if we are the producer), or to check
950 * if we own the TRB (if we are the consumer). See section 4.9.1.
951 */
952 u32 cycle_state;
953};
954
c92bcfa7
SS		 955struct xhci_dequeue_state {
956 struct xhci_segment *new_deq_seg;
957 union xhci_trb *new_deq_ptr;
958 int new_cycle_state;
959};
960
0ebbab37
SS		 961struct xhci_erst_entry {
962 /* 64-bit event ring segment address */
8e595a5d 963 u64 seg_addr;
0ebbab37
SS		 964 u32 seg_size;
965 /* Set to zero */
966 u32 rsvd;
98441973 967};
0ebbab37
SS		 968
969struct xhci_erst {
970 struct xhci_erst_entry *entries;
971 unsigned int num_entries;
972 /* xhci->event_ring keeps track of segment dma addresses */
973 dma_addr_t erst_dma_addr;
974 /* Num entries the ERST can contain */
975 unsigned int erst_size;
976};
977
254c80a3
JY		 978struct xhci_scratchpad {
979 u64 *sp_array;
980 dma_addr_t sp_dma;
981 void **sp_buffers;
982 dma_addr_t *sp_dma_buffers;
983};
984
0ebbab37
SS		 985/*
986 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
987 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
988 * meaning 64 ring segments.
989 * Initial allocated size of the ERST, in number of entries */
990#define ERST_NUM_SEGS 1
991/* Initial allocated size of the ERST, in number of entries */
992#define ERST_SIZE 64
993/* Initial number of event segment rings allocated */
994#define ERST_ENTRIES 1
7f84eef0
SS		 995/* Poll every 60 seconds */
996#define POLL_TIMEOUT 60
0ebbab37
SS		 997/* XXX: Make these module parameters */
998
74c68741
SS		 999
1000/* There is one ehci_hci structure per controller */
1001struct xhci_hcd {
1002 /* glue to PCI and HCD framework */
1003 struct xhci_cap_regs __iomem *cap_regs;
1004 struct xhci_op_regs __iomem *op_regs;
1005 struct xhci_run_regs __iomem *run_regs;
0ebbab37 1006 struct xhci_doorbell_array __iomem *dba;
66d4eadd 1007 /* Our HCD's current interrupter register set */
98441973 1008 struct xhci_intr_reg __iomem *ir_set;
74c68741
SS		 1009
1010 /* Cached register copies of read-only HC data */
1011 __u32 hcs_params1;
1012 __u32 hcs_params2;
1013 __u32 hcs_params3;
1014 __u32 hcc_params;
1015
1016 spinlock_t lock;
1017
1018 /* packed release number */
1019 u8 sbrn;
1020 u16 hci_version;
1021 u8 max_slots;
1022 u8 max_interrupters;
1023 u8 max_ports;
1024 u8 isoc_threshold;
1025 int event_ring_max;
1026 int addr_64;
66d4eadd 1027 /* 4KB min, 128MB max */
74c68741 1028 int page_size;
66d4eadd
SS		 1029 /* Valid values are 12 to 20, inclusive */
1030 int page_shift;
1031 /* only one MSI vector for now, but might need more later */
1032 int msix_count;
1033 struct msix_entry *msix_entries;
0ebbab37 1034 /* data structures */
a74588f9 1035 struct xhci_device_context_array *dcbaa;
0ebbab37
SS		 1036 struct xhci_ring *cmd_ring;
1037 struct xhci_ring *event_ring;
1038 struct xhci_erst erst;
254c80a3
JY		 1039 /* Scratchpad */
1040 struct xhci_scratchpad *scratchpad;
1041
3ffbba95
SS		 1042 /* slot enabling and address device helpers */
1043 struct completion addr_dev;
1044 int slot_id;
1045 /* Internal mirror of the HW's dcbaa */
1046 struct xhci_virt_device *devs[MAX_HC_SLOTS];
0ebbab37
SS		 1047
1048 /* DMA pools */
1049 struct dma_pool *device_pool;
1050 struct dma_pool *segment_pool;
7f84eef0
SS		 1051
1052#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1053 /* Poll the rings - for debugging */
1054 struct timer_list event_ring_timer;
1055 int zombie;
1056#endif
1057 /* Statistics */
1058 int noops_submitted;
1059 int noops_handled;
1060 int error_bitmask;
74c68741
SS		 1061};
1062
7f84eef0
SS		 1063/* For testing purposes */
1064#define NUM_TEST_NOOPS 0
1065
74c68741
SS		 1066/* convert between an HCD pointer and the corresponding EHCI_HCD */
1067static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1068{
1069 return (struct xhci_hcd *) (hcd->hcd_priv);
1070}
1071
1072static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1073{
1074 return container_of((void *) xhci, struct usb_hcd, hcd_priv);
1075}
1076
1077#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1078#define XHCI_DEBUG 1
1079#else
1080#define XHCI_DEBUG 0
1081#endif
1082
1083#define xhci_dbg(xhci, fmt, args...) \
1084 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1085#define xhci_info(xhci, fmt, args...) \
1086 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1087#define xhci_err(xhci, fmt, args...) \
1088 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1089#define xhci_warn(xhci, fmt, args...) \
1090 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1091
1092/* TODO: copied from ehci.h - can be refactored? */
1093/* xHCI spec says all registers are little endian */
1094static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1095 __u32 __iomem *regs)
1096{
1097 return readl(regs);
1098}
045f123d 1099static inline void xhci_writel(struct xhci_hcd *xhci,
74c68741
SS		 1100 const unsigned int val, __u32 __iomem *regs)
1101{
66e49d87
SS		 1102 xhci_dbg(xhci,
1103 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
1104 regs, val);
74c68741
SS		 1105 writel(val, regs);
1106}
1107
8e595a5d
SS		 1108/*
1109 * Registers should always be accessed with double word or quad word accesses.
1110 *
1111 * Some xHCI implementations may support 64-bit address pointers. Registers
1112 * with 64-bit address pointers should be written to with dword accesses by
1113 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1114 * xHCI implementations that do not support 64-bit address pointers will ignore
1115 * the high dword, and write order is irrelevant.
1116 */
1117static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1118 __u64 __iomem *regs)
1119{
1120 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1121 u64 val_lo = readl(ptr);
1122 u64 val_hi = readl(ptr + 1);
1123 return val_lo + (val_hi << 32);
1124}
1125static inline void xhci_write_64(struct xhci_hcd *xhci,
1126 const u64 val, __u64 __iomem *regs)
1127{
1128 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1129 u32 val_lo = lower_32_bits(val);
1130 u32 val_hi = upper_32_bits(val);
1131
66e49d87
SS		 1132 xhci_dbg(xhci,
1133 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
1134 regs, (long unsigned int) val);
8e595a5d
SS		 1135 writel(val_lo, ptr);
1136 writel(val_hi, ptr + 1);
1137}
1138
66d4eadd 1139/* xHCI debugging */
98441973 1140void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
66d4eadd 1141void xhci_print_registers(struct xhci_hcd *xhci);
0ebbab37
SS		 1142void xhci_dbg_regs(struct xhci_hcd *xhci);
1143void xhci_print_run_regs(struct xhci_hcd *xhci);
d0e96f5a
SS		 1144void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1145void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
7f84eef0 1146void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
0ebbab37
SS		 1147void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1148void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1149void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
7f84eef0 1150void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
d115b048 1151void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
66d4eadd
SS		 1152
1153/* xHCI memory managment */
1154void xhci_mem_cleanup(struct xhci_hcd *xhci);
1155int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
3ffbba95
SS		 1156void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1157int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1158int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
d0e96f5a 1159unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
f94e0186
SS		 1160unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1161void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
f88ba78d
SS		 1162int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1163 struct usb_device *udev, struct usb_host_endpoint *ep,
1164 gfp_t mem_flags);
f94e0186 1165void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
66d4eadd
SS		 1166
1167#ifdef CONFIG_PCI
1168/* xHCI PCI glue */
1169int xhci_register_pci(void);
1170void xhci_unregister_pci(void);
1171#endif
1172
1173/* xHCI host controller glue */
1174int xhci_halt(struct xhci_hcd *xhci);
1175int xhci_reset(struct xhci_hcd *xhci);
1176int xhci_init(struct usb_hcd *hcd);
1177int xhci_run(struct usb_hcd *hcd);
1178void xhci_stop(struct usb_hcd *hcd);
1179void xhci_shutdown(struct usb_hcd *hcd);
1180int xhci_get_frame(struct usb_hcd *hcd);
7f84eef0 1181irqreturn_t xhci_irq(struct usb_hcd *hcd);
3ffbba95
SS		 1182int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1183void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1184int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
d0e96f5a
SS		 1185int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1186int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
f94e0186
SS		 1187int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1188int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
a1587d97 1189void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
f94e0186
SS		 1190int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1191void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
7f84eef0
SS		 1192
1193/* xHCI ring, segment, TRB, and TD functions */
23e3be11
SS		 1194dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1195void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1196void *xhci_setup_one_noop(struct xhci_hcd *xhci);
b7258a4a 1197void xhci_handle_event(struct xhci_hcd *xhci);
23e3be11
SS		 1198void xhci_set_hc_event_deq(struct xhci_hcd *xhci);
1199int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1200int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1201 u32 slot_id);
1202int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
ae636747 1203 unsigned int ep_index);
23e3be11
SS		 1204int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1205 int slot_id, unsigned int ep_index);
1206int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1207 int slot_id, unsigned int ep_index);
1208int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1209 u32 slot_id);
a1587d97
SS		 1210int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1211 unsigned int ep_index);
c92bcfa7
SS		 1212void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1213 unsigned int slot_id, unsigned int ep_index,
1214 struct xhci_td *cur_td, struct xhci_dequeue_state *state);
1215void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1216 struct xhci_ring *ep_ring, unsigned int slot_id,
1217 unsigned int ep_index, struct xhci_dequeue_state *deq_state);
66d4eadd 1218
0f2a7930
SS		 1219/* xHCI roothub code */
1220int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1221 char *buf, u16 wLength);
1222int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1223
d115b048
JY		 1224/* xHCI contexts */
1225struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1226struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1227struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1228
74c68741 1229#endif /* __LINUX_XHCI_HCD_H */
Linux 6.x block layer and io_uring tree(s)