Commit | Line | Data |
---|---|---|
74c68741 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #ifndef __LINUX_XHCI_HCD_H | |
24 | #define __LINUX_XHCI_HCD_H | |
25 | ||
26 | #include <linux/usb.h> | |
27 | ||
28 | #include "../core/hcd.h" | |
29 | /* Code sharing between pci-quirks and xhci hcd */ | |
30 | #include "xhci-ext-caps.h" | |
31 | ||
32 | /* xHCI PCI Configuration Registers */ | |
33 | #define XHCI_SBRN_OFFSET (0x60) | |
34 | ||
66d4eadd SS |
35 | /* Max number of USB devices for any host controller - limit in section 6.1 */ |
36 | #define MAX_HC_SLOTS 256 | |
37 | ||
74c68741 SS |
38 | /* |
39 | * xHCI register interface. | |
40 | * This corresponds to the eXtensible Host Controller Interface (xHCI) | |
41 | * Revision 0.95 specification | |
42 | * | |
43 | * Registers should always be accessed with double word or quad word accesses. | |
44 | * | |
45 | * Some xHCI implementations may support 64-bit address pointers. Registers | |
46 | * with 64-bit address pointers should be written to with dword accesses by | |
47 | * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. | |
48 | * xHCI implementations that do not support 64-bit address pointers will ignore | |
49 | * the high dword, and write order is irrelevant. | |
50 | */ | |
51 | ||
52 | /** | |
53 | * struct xhci_cap_regs - xHCI Host Controller Capability Registers. | |
54 | * @hc_capbase: length of the capabilities register and HC version number | |
55 | * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 | |
56 | * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 | |
57 | * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 | |
58 | * @hcc_params: HCCPARAMS - Capability Parameters | |
59 | * @db_off: DBOFF - Doorbell array offset | |
60 | * @run_regs_off: RTSOFF - Runtime register space offset | |
61 | */ | |
62 | struct xhci_cap_regs { | |
63 | u32 hc_capbase; | |
64 | u32 hcs_params1; | |
65 | u32 hcs_params2; | |
66 | u32 hcs_params3; | |
67 | u32 hcc_params; | |
68 | u32 db_off; | |
69 | u32 run_regs_off; | |
70 | /* Reserved up to (CAPLENGTH - 0x1C) */ | |
71 | } __attribute__ ((packed)); | |
72 | ||
73 | /* hc_capbase bitmasks */ | |
74 | /* bits 7:0 - how long is the Capabilities register */ | |
75 | #define HC_LENGTH(p) XHCI_HC_LENGTH(p) | |
76 | /* bits 31:16 */ | |
77 | #define HC_VERSION(p) (((p) >> 16) & 0xffff) | |
78 | ||
79 | /* HCSPARAMS1 - hcs_params1 - bitmasks */ | |
80 | /* bits 0:7, Max Device Slots */ | |
81 | #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) | |
82 | #define HCS_SLOTS_MASK 0xff | |
83 | /* bits 8:18, Max Interrupters */ | |
84 | #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) | |
85 | /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ | |
86 | #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) | |
87 | ||
88 | /* HCSPARAMS2 - hcs_params2 - bitmasks */ | |
89 | /* bits 0:3, frames or uframes that SW needs to queue transactions | |
90 | * ahead of the HW to meet periodic deadlines */ | |
91 | #define HCS_IST(p) (((p) >> 0) & 0xf) | |
92 | /* bits 4:7, max number of Event Ring segments */ | |
93 | #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) | |
94 | /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ | |
95 | /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ | |
96 | ||
97 | /* HCSPARAMS3 - hcs_params3 - bitmasks */ | |
98 | /* bits 0:7, Max U1 to U0 latency for the roothub ports */ | |
99 | #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) | |
100 | /* bits 16:31, Max U2 to U0 latency for the roothub ports */ | |
101 | #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) | |
102 | ||
103 | /* HCCPARAMS - hcc_params - bitmasks */ | |
104 | /* true: HC can use 64-bit address pointers */ | |
105 | #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) | |
106 | /* true: HC can do bandwidth negotiation */ | |
107 | #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) | |
108 | /* true: HC uses 64-byte Device Context structures | |
109 | * FIXME 64-byte context structures aren't supported yet. | |
110 | */ | |
111 | #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) | |
112 | /* true: HC has port power switches */ | |
113 | #define HCC_PPC(p) ((p) & (1 << 3)) | |
114 | /* true: HC has port indicators */ | |
115 | #define HCS_INDICATOR(p) ((p) & (1 << 4)) | |
116 | /* true: HC has Light HC Reset Capability */ | |
117 | #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) | |
118 | /* true: HC supports latency tolerance messaging */ | |
119 | #define HCC_LTC(p) ((p) & (1 << 6)) | |
120 | /* true: no secondary Stream ID Support */ | |
121 | #define HCC_NSS(p) ((p) & (1 << 7)) | |
122 | /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ | |
123 | #define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1)) | |
124 | /* Extended Capabilities pointer from PCI base - section 5.3.6 */ | |
125 | #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) | |
126 | ||
127 | /* db_off bitmask - bits 0:1 reserved */ | |
128 | #define DBOFF_MASK (~0x3) | |
129 | ||
130 | /* run_regs_off bitmask - bits 0:4 reserved */ | |
131 | #define RTSOFF_MASK (~0x1f) | |
132 | ||
133 | ||
134 | /* Number of registers per port */ | |
135 | #define NUM_PORT_REGS 4 | |
136 | ||
137 | /** | |
138 | * struct xhci_op_regs - xHCI Host Controller Operational Registers. | |
139 | * @command: USBCMD - xHC command register | |
140 | * @status: USBSTS - xHC status register | |
141 | * @page_size: This indicates the page size that the host controller | |
142 | * supports. If bit n is set, the HC supports a page size | |
143 | * of 2^(n+12), up to a 128MB page size. | |
144 | * 4K is the minimum page size. | |
145 | * @cmd_ring: CRP - 64-bit Command Ring Pointer | |
146 | * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer | |
147 | * @config_reg: CONFIG - Configure Register | |
148 | * @port_status_base: PORTSCn - base address for Port Status and Control | |
149 | * Each port has a Port Status and Control register, | |
150 | * followed by a Port Power Management Status and Control | |
151 | * register, a Port Link Info register, and a reserved | |
152 | * register. | |
153 | * @port_power_base: PORTPMSCn - base address for | |
154 | * Port Power Management Status and Control | |
155 | * @port_link_base: PORTLIn - base address for Port Link Info (current | |
156 | * Link PM state and control) for USB 2.1 and USB 3.0 | |
157 | * devices. | |
158 | */ | |
159 | struct xhci_op_regs { | |
160 | u32 command; | |
161 | u32 status; | |
162 | u32 page_size; | |
163 | u32 reserved1; | |
164 | u32 reserved2; | |
165 | u32 dev_notification; | |
166 | u32 cmd_ring[2]; | |
167 | /* rsvd: offset 0x20-2F */ | |
168 | u32 reserved3[4]; | |
169 | u32 dcbaa_ptr[2]; | |
170 | u32 config_reg; | |
171 | /* rsvd: offset 0x3C-3FF */ | |
172 | u32 reserved4[241]; | |
173 | /* port 1 registers, which serve as a base address for other ports */ | |
174 | u32 port_status_base; | |
175 | u32 port_power_base; | |
176 | u32 port_link_base; | |
177 | u32 reserved5; | |
178 | /* registers for ports 2-255 */ | |
179 | u32 reserved6[NUM_PORT_REGS*254]; | |
180 | } __attribute__ ((packed)); | |
181 | ||
182 | /* USBCMD - USB command - command bitmasks */ | |
183 | /* start/stop HC execution - do not write unless HC is halted*/ | |
184 | #define CMD_RUN XHCI_CMD_RUN | |
185 | /* Reset HC - resets internal HC state machine and all registers (except | |
186 | * PCI config regs). HC does NOT drive a USB reset on the downstream ports. | |
187 | * The xHCI driver must reinitialize the xHC after setting this bit. | |
188 | */ | |
189 | #define CMD_RESET (1 << 1) | |
190 | /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ | |
191 | #define CMD_EIE XHCI_CMD_EIE | |
192 | /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ | |
193 | #define CMD_HSEIE XHCI_CMD_HSEIE | |
194 | /* bits 4:6 are reserved (and should be preserved on writes). */ | |
195 | /* light reset (port status stays unchanged) - reset completed when this is 0 */ | |
196 | #define CMD_LRESET (1 << 7) | |
197 | /* FIXME: ignoring host controller save/restore state for now. */ | |
198 | #define CMD_CSS (1 << 8) | |
199 | #define CMD_CRS (1 << 9) | |
200 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ | |
201 | #define CMD_EWE XHCI_CMD_EWE | |
202 | /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root | |
203 | * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. | |
204 | * '0' means the xHC can power it off if all ports are in the disconnect, | |
205 | * disabled, or powered-off state. | |
206 | */ | |
207 | #define CMD_PM_INDEX (1 << 11) | |
208 | /* bits 12:31 are reserved (and should be preserved on writes). */ | |
209 | ||
210 | /* USBSTS - USB status - status bitmasks */ | |
211 | /* HC not running - set to 1 when run/stop bit is cleared. */ | |
212 | #define STS_HALT XHCI_STS_HALT | |
213 | /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ | |
214 | #define STS_FATAL (1 << 2) | |
215 | /* event interrupt - clear this prior to clearing any IP flags in IR set*/ | |
216 | #define STS_EINT (1 << 3) | |
217 | /* port change detect */ | |
218 | #define STS_PORT (1 << 4) | |
219 | /* bits 5:7 reserved and zeroed */ | |
220 | /* save state status - '1' means xHC is saving state */ | |
221 | #define STS_SAVE (1 << 8) | |
222 | /* restore state status - '1' means xHC is restoring state */ | |
223 | #define STS_RESTORE (1 << 9) | |
224 | /* true: save or restore error */ | |
225 | #define STS_SRE (1 << 10) | |
226 | /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ | |
227 | #define STS_CNR XHCI_STS_CNR | |
228 | /* true: internal Host Controller Error - SW needs to reset and reinitialize */ | |
229 | #define STS_HCE (1 << 12) | |
230 | /* bits 13:31 reserved and should be preserved */ | |
231 | ||
232 | /* | |
233 | * DNCTRL - Device Notification Control Register - dev_notification bitmasks | |
234 | * Generate a device notification event when the HC sees a transaction with a | |
235 | * notification type that matches a bit set in this bit field. | |
236 | */ | |
237 | #define DEV_NOTE_MASK (0xffff) | |
238 | #define ENABLE_DEV_NOTE(x) (1 << x) | |
239 | /* Most of the device notification types should only be used for debug. | |
240 | * SW does need to pay attention to function wake notifications. | |
241 | */ | |
242 | #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) | |
243 | ||
0ebbab37 SS |
244 | /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ |
245 | /* bit 0 is the command ring cycle state */ | |
246 | /* stop ring operation after completion of the currently executing command */ | |
247 | #define CMD_RING_PAUSE (1 << 1) | |
248 | /* stop ring immediately - abort the currently executing command */ | |
249 | #define CMD_RING_ABORT (1 << 2) | |
250 | /* true: command ring is running */ | |
251 | #define CMD_RING_RUNNING (1 << 3) | |
252 | /* bits 4:5 reserved and should be preserved */ | |
253 | /* Command Ring pointer - bit mask for the lower 32 bits. */ | |
254 | #define CMD_RING_ADDR_MASK (0xffffffc0) | |
255 | ||
74c68741 SS |
256 | /* CONFIG - Configure Register - config_reg bitmasks */ |
257 | /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ | |
258 | #define MAX_DEVS(p) ((p) & 0xff) | |
259 | /* bits 8:31 - reserved and should be preserved */ | |
260 | ||
261 | /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ | |
262 | /* true: device connected */ | |
263 | #define PORT_CONNECT (1 << 0) | |
264 | /* true: port enabled */ | |
265 | #define PORT_PE (1 << 1) | |
266 | /* bit 2 reserved and zeroed */ | |
267 | /* true: port has an over-current condition */ | |
268 | #define PORT_OC (1 << 3) | |
269 | /* true: port reset signaling asserted */ | |
270 | #define PORT_RESET (1 << 4) | |
271 | /* Port Link State - bits 5:8 | |
272 | * A read gives the current link PM state of the port, | |
273 | * a write with Link State Write Strobe set sets the link state. | |
274 | */ | |
275 | /* true: port has power (see HCC_PPC) */ | |
276 | #define PORT_POWER (1 << 9) | |
277 | /* bits 10:13 indicate device speed: | |
278 | * 0 - undefined speed - port hasn't be initialized by a reset yet | |
279 | * 1 - full speed | |
280 | * 2 - low speed | |
281 | * 3 - high speed | |
282 | * 4 - super speed | |
283 | * 5-15 reserved | |
284 | */ | |
285 | #define DEV_SPEED_MASK (0xf<<10) | |
286 | #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) | |
287 | #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == (0x1<<10)) | |
288 | #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == (0x2<<10)) | |
289 | #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == (0x3<<10)) | |
290 | #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == (0x4<<10)) | |
291 | /* Port Indicator Control */ | |
292 | #define PORT_LED_OFF (0 << 14) | |
293 | #define PORT_LED_AMBER (1 << 14) | |
294 | #define PORT_LED_GREEN (2 << 14) | |
295 | #define PORT_LED_MASK (3 << 14) | |
296 | /* Port Link State Write Strobe - set this when changing link state */ | |
297 | #define PORT_LINK_STROBE (1 << 16) | |
298 | /* true: connect status change */ | |
299 | #define PORT_CSC (1 << 17) | |
300 | /* true: port enable change */ | |
301 | #define PORT_PEC (1 << 18) | |
302 | /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port | |
303 | * into an enabled state, and the device into the default state. A "warm" reset | |
304 | * also resets the link, forcing the device through the link training sequence. | |
305 | * SW can also look at the Port Reset register to see when warm reset is done. | |
306 | */ | |
307 | #define PORT_WRC (1 << 19) | |
308 | /* true: over-current change */ | |
309 | #define PORT_OCC (1 << 20) | |
310 | /* true: reset change - 1 to 0 transition of PORT_RESET */ | |
311 | #define PORT_RC (1 << 21) | |
312 | /* port link status change - set on some port link state transitions: | |
313 | * Transition Reason | |
314 | * ------------------------------------------------------------------------------ | |
315 | * - U3 to Resume Wakeup signaling from a device | |
316 | * - Resume to Recovery to U0 USB 3.0 device resume | |
317 | * - Resume to U0 USB 2.0 device resume | |
318 | * - U3 to Recovery to U0 Software resume of USB 3.0 device complete | |
319 | * - U3 to U0 Software resume of USB 2.0 device complete | |
320 | * - U2 to U0 L1 resume of USB 2.1 device complete | |
321 | * - U0 to U0 (???) L1 entry rejection by USB 2.1 device | |
322 | * - U0 to disabled L1 entry error with USB 2.1 device | |
323 | * - Any state to inactive Error on USB 3.0 port | |
324 | */ | |
325 | #define PORT_PLC (1 << 22) | |
326 | /* port configure error change - port failed to configure its link partner */ | |
327 | #define PORT_CEC (1 << 23) | |
328 | /* bit 24 reserved */ | |
329 | /* wake on connect (enable) */ | |
330 | #define PORT_WKCONN_E (1 << 25) | |
331 | /* wake on disconnect (enable) */ | |
332 | #define PORT_WKDISC_E (1 << 26) | |
333 | /* wake on over-current (enable) */ | |
334 | #define PORT_WKOC_E (1 << 27) | |
335 | /* bits 28:29 reserved */ | |
336 | /* true: device is removable - for USB 3.0 roothub emulation */ | |
337 | #define PORT_DEV_REMOVE (1 << 30) | |
338 | /* Initiate a warm port reset - complete when PORT_WRC is '1' */ | |
339 | #define PORT_WR (1 << 31) | |
340 | ||
341 | /* Port Power Management Status and Control - port_power_base bitmasks */ | |
342 | /* Inactivity timer value for transitions into U1, in microseconds. | |
343 | * Timeout can be up to 127us. 0xFF means an infinite timeout. | |
344 | */ | |
345 | #define PORT_U1_TIMEOUT(p) ((p) & 0xff) | |
346 | /* Inactivity timer value for transitions into U2 */ | |
347 | #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) | |
348 | /* Bits 24:31 for port testing */ | |
349 | ||
350 | ||
351 | /** | |
352 | * struct intr_reg - Interrupt Register Set | |
353 | * @irq_pending: IMAN - Interrupt Management Register. Used to enable | |
354 | * interrupts and check for pending interrupts. | |
355 | * @irq_control: IMOD - Interrupt Moderation Register. | |
356 | * Used to throttle interrupts. | |
357 | * @erst_size: Number of segments in the Event Ring Segment Table (ERST). | |
358 | * @erst_base: ERST base address. | |
359 | * @erst_dequeue: Event ring dequeue pointer. | |
360 | * | |
361 | * Each interrupter (defined by a MSI-X vector) has an event ring and an Event | |
362 | * Ring Segment Table (ERST) associated with it. The event ring is comprised of | |
363 | * multiple segments of the same size. The HC places events on the ring and | |
364 | * "updates the Cycle bit in the TRBs to indicate to software the current | |
365 | * position of the Enqueue Pointer." The HCD (Linux) processes those events and | |
366 | * updates the dequeue pointer. | |
367 | */ | |
368 | struct intr_reg { | |
369 | u32 irq_pending; | |
370 | u32 irq_control; | |
371 | u32 erst_size; | |
372 | u32 rsvd; | |
373 | u32 erst_base[2]; | |
374 | u32 erst_dequeue[2]; | |
375 | } __attribute__ ((packed)); | |
376 | ||
66d4eadd | 377 | /* irq_pending bitmasks */ |
74c68741 | 378 | #define ER_IRQ_PENDING(p) ((p) & 0x1) |
66d4eadd SS |
379 | /* bits 2:31 need to be preserved */ |
380 | #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) | |
381 | #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) | |
382 | #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) | |
383 | ||
384 | /* irq_control bitmasks */ | |
385 | /* Minimum interval between interrupts (in 250ns intervals). The interval | |
386 | * between interrupts will be longer if there are no events on the event ring. | |
387 | * Default is 4000 (1 ms). | |
388 | */ | |
389 | #define ER_IRQ_INTERVAL_MASK (0xffff) | |
390 | /* Counter used to count down the time to the next interrupt - HW use only */ | |
391 | #define ER_IRQ_COUNTER_MASK (0xffff << 16) | |
392 | ||
393 | /* erst_size bitmasks */ | |
74c68741 | 394 | /* Preserve bits 16:31 of erst_size */ |
66d4eadd SS |
395 | #define ERST_SIZE_MASK (0xffff << 16) |
396 | ||
397 | /* erst_dequeue bitmasks */ | |
398 | /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) | |
399 | * where the current dequeue pointer lies. This is an optional HW hint. | |
400 | */ | |
401 | #define ERST_DESI_MASK (0x7) | |
402 | /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by | |
403 | * a work queue (or delayed service routine)? | |
404 | */ | |
405 | #define ERST_EHB (1 << 3) | |
0ebbab37 | 406 | #define ERST_PTR_MASK (0xf) |
74c68741 SS |
407 | |
408 | /** | |
409 | * struct xhci_run_regs | |
410 | * @microframe_index: | |
411 | * MFINDEX - current microframe number | |
412 | * | |
413 | * Section 5.5 Host Controller Runtime Registers: | |
414 | * "Software should read and write these registers using only Dword (32 bit) | |
415 | * or larger accesses" | |
416 | */ | |
417 | struct xhci_run_regs { | |
418 | u32 microframe_index; | |
419 | u32 rsvd[7]; | |
420 | struct intr_reg ir_set[128]; | |
421 | } __attribute__ ((packed)); | |
422 | ||
0ebbab37 SS |
423 | /** |
424 | * struct doorbell_array | |
425 | * | |
426 | * Section 5.6 | |
427 | */ | |
428 | struct xhci_doorbell_array { | |
429 | u32 doorbell[256]; | |
430 | } __attribute__ ((packed)); | |
431 | ||
432 | #define DB_TARGET_MASK 0xFFFFFF00 | |
433 | #define DB_STREAM_ID_MASK 0x0000FFFF | |
434 | #define DB_TARGET_HOST 0x0 | |
435 | #define DB_STREAM_ID_HOST 0x0 | |
436 | #define DB_MASK (0xff << 8) | |
437 | ||
438 | ||
439 | struct xhci_transfer_event { | |
440 | /* 64-bit buffer address, or immediate data */ | |
441 | u32 buffer[2]; | |
442 | u32 transfer_len; | |
443 | /* This field is interpreted differently based on the type of TRB */ | |
444 | u32 flags; | |
445 | } __attribute__ ((packed)); | |
446 | ||
447 | /* Completion Code - only applicable for some types of TRBs */ | |
448 | #define COMP_CODE_MASK (0xff << 24) | |
449 | #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) | |
450 | #define COMP_SUCCESS 1 | |
451 | /* Data Buffer Error */ | |
452 | #define COMP_DB_ERR 2 | |
453 | /* Babble Detected Error */ | |
454 | #define COMP_BABBLE 3 | |
455 | /* USB Transaction Error */ | |
456 | #define COMP_TX_ERR 4 | |
457 | /* TRB Error - some TRB field is invalid */ | |
458 | #define COMP_TRB_ERR 5 | |
459 | /* Stall Error - USB device is stalled */ | |
460 | #define COMP_STALL 6 | |
461 | /* Resource Error - HC doesn't have memory for that device configuration */ | |
462 | #define COMP_ENOMEM 7 | |
463 | /* Bandwidth Error - not enough room in schedule for this dev config */ | |
464 | #define COMP_BW_ERR 8 | |
465 | /* No Slots Available Error - HC ran out of device slots */ | |
466 | #define COMP_ENOSLOTS 9 | |
467 | /* Invalid Stream Type Error */ | |
468 | #define COMP_STREAM_ERR 10 | |
469 | /* Slot Not Enabled Error - doorbell rung for disabled device slot */ | |
470 | #define COMP_EBADSLT 11 | |
471 | /* Endpoint Not Enabled Error */ | |
472 | #define COMP_EBADEP 12 | |
473 | /* Short Packet */ | |
474 | #define COMP_SHORT_TX 13 | |
475 | /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ | |
476 | #define COMP_UNDERRUN 14 | |
477 | /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ | |
478 | #define COMP_OVERRUN 15 | |
479 | /* Virtual Function Event Ring Full Error */ | |
480 | #define COMP_VF_FULL 16 | |
481 | /* Parameter Error - Context parameter is invalid */ | |
482 | #define COMP_EINVAL 17 | |
483 | /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ | |
484 | #define COMP_BW_OVER 18 | |
485 | /* Context State Error - illegal context state transition requested */ | |
486 | #define COMP_CTX_STATE 19 | |
487 | /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ | |
488 | #define COMP_PING_ERR 20 | |
489 | /* Event Ring is full */ | |
490 | #define COMP_ER_FULL 21 | |
491 | /* Missed Service Error - HC couldn't service an isoc ep within interval */ | |
492 | #define COMP_MISSED_INT 23 | |
493 | /* Successfully stopped command ring */ | |
494 | #define COMP_CMD_STOP 24 | |
495 | /* Successfully aborted current command and stopped command ring */ | |
496 | #define COMP_CMD_ABORT 25 | |
497 | /* Stopped - transfer was terminated by a stop endpoint command */ | |
498 | #define COMP_STOP 26 | |
499 | /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ | |
500 | #define COMP_STOP_INVAL 27 | |
501 | /* Control Abort Error - Debug Capability - control pipe aborted */ | |
502 | #define COMP_DBG_ABORT 28 | |
503 | /* TRB type 29 and 30 reserved */ | |
504 | /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ | |
505 | #define COMP_BUFF_OVER 31 | |
506 | /* Event Lost Error - xHC has an "internal event overrun condition" */ | |
507 | #define COMP_ISSUES 32 | |
508 | /* Undefined Error - reported when other error codes don't apply */ | |
509 | #define COMP_UNKNOWN 33 | |
510 | /* Invalid Stream ID Error */ | |
511 | #define COMP_STRID_ERR 34 | |
512 | /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ | |
513 | /* FIXME - check for this */ | |
514 | #define COMP_2ND_BW_ERR 35 | |
515 | /* Split Transaction Error */ | |
516 | #define COMP_SPLIT_ERR 36 | |
517 | ||
518 | struct xhci_link_trb { | |
519 | /* 64-bit segment pointer*/ | |
520 | u32 segment_ptr[2]; | |
521 | u32 intr_target; | |
522 | u32 control; | |
523 | } __attribute__ ((packed)); | |
524 | ||
525 | /* control bitfields */ | |
526 | #define LINK_TOGGLE (0x1<<1) | |
527 | ||
528 | ||
529 | union xhci_trb { | |
530 | struct xhci_link_trb link; | |
531 | struct xhci_transfer_event trans_event; | |
532 | }; | |
533 | ||
534 | /* Normal TRB fields */ | |
535 | /* transfer_len bitmasks - bits 0:16 */ | |
536 | #define TRB_LEN(p) ((p) & 0x1ffff) | |
537 | /* TD size - number of bytes remaining in the TD (including this TRB): | |
538 | * bits 17 - 21. Shift the number of bytes by 10. */ | |
539 | #define TD_REMAINDER(p) ((((p) >> 10) & 0x1f) << 17) | |
540 | /* Interrupter Target - which MSI-X vector to target the completion event at */ | |
541 | #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) | |
542 | #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) | |
543 | ||
544 | /* Cycle bit - indicates TRB ownership by HC or HCD */ | |
545 | #define TRB_CYCLE (1<<0) | |
546 | /* | |
547 | * Force next event data TRB to be evaluated before task switch. | |
548 | * Used to pass OS data back after a TD completes. | |
549 | */ | |
550 | #define TRB_ENT (1<<1) | |
551 | /* Interrupt on short packet */ | |
552 | #define TRB_ISP (1<<2) | |
553 | /* Set PCIe no snoop attribute */ | |
554 | #define TRB_NO_SNOOP (1<<3) | |
555 | /* Chain multiple TRBs into a TD */ | |
556 | #define TRB_CHAIN (1<<4) | |
557 | /* Interrupt on completion */ | |
558 | #define TRB_IOC (1<<5) | |
559 | /* The buffer pointer contains immediate data */ | |
560 | #define TRB_IDT (1<<6) | |
561 | ||
562 | ||
563 | /* Control transfer TRB specific fields */ | |
564 | #define TRB_DIR_IN (1<<16) | |
565 | ||
566 | /* TRB bit mask */ | |
567 | #define TRB_TYPE_BITMASK (0xfc00) | |
568 | #define TRB_TYPE(p) ((p) << 10) | |
569 | /* TRB type IDs */ | |
570 | /* bulk, interrupt, isoc scatter/gather, and control data stage */ | |
571 | #define TRB_NORMAL 1 | |
572 | /* setup stage for control transfers */ | |
573 | #define TRB_SETUP 2 | |
574 | /* data stage for control transfers */ | |
575 | #define TRB_DATA 3 | |
576 | /* status stage for control transfers */ | |
577 | #define TRB_STATUS 4 | |
578 | /* isoc transfers */ | |
579 | #define TRB_ISOC 5 | |
580 | /* TRB for linking ring segments */ | |
581 | #define TRB_LINK 6 | |
582 | #define TRB_EVENT_DATA 7 | |
583 | /* Transfer Ring No-op (not for the command ring) */ | |
584 | #define TRB_TR_NOOP 8 | |
585 | /* Command TRBs */ | |
586 | /* Enable Slot Command */ | |
587 | #define TRB_ENABLE_SLOT 9 | |
588 | /* Disable Slot Command */ | |
589 | #define TRB_DISABLE_SLOT 10 | |
590 | /* Address Device Command */ | |
591 | #define TRB_ADDR_DEV 11 | |
592 | /* Configure Endpoint Command */ | |
593 | #define TRB_CONFIG_EP 12 | |
594 | /* Evaluate Context Command */ | |
595 | #define TRB_EVAL_CONTEXT 13 | |
596 | /* Reset Transfer Ring Command */ | |
597 | #define TRB_RESET_RING 14 | |
598 | /* Stop Transfer Ring Command */ | |
599 | #define TRB_STOP_RING 15 | |
600 | /* Set Transfer Ring Dequeue Pointer Command */ | |
601 | #define TRB_SET_DEQ 16 | |
602 | /* Reset Device Command */ | |
603 | #define TRB_RESET_DEV 17 | |
604 | /* Force Event Command (opt) */ | |
605 | #define TRB_FORCE_EVENT 18 | |
606 | /* Negotiate Bandwidth Command (opt) */ | |
607 | #define TRB_NEG_BANDWIDTH 19 | |
608 | /* Set Latency Tolerance Value Command (opt) */ | |
609 | #define TRB_SET_LT 20 | |
610 | /* Get port bandwidth Command */ | |
611 | #define TRB_GET_BW 21 | |
612 | /* Force Header Command - generate a transaction or link management packet */ | |
613 | #define TRB_FORCE_HEADER 22 | |
614 | /* No-op Command - not for transfer rings */ | |
615 | #define TRB_CMD_NOOP 23 | |
616 | /* TRB IDs 24-31 reserved */ | |
617 | /* Event TRBS */ | |
618 | /* Transfer Event */ | |
619 | #define TRB_TRANSFER 32 | |
620 | /* Command Completion Event */ | |
621 | #define TRB_COMPLETION 33 | |
622 | /* Port Status Change Event */ | |
623 | #define TRB_PORT_STATUS 34 | |
624 | /* Bandwidth Request Event (opt) */ | |
625 | #define TRB_BANDWIDTH_EVENT 35 | |
626 | /* Doorbell Event (opt) */ | |
627 | #define TRB_DOORBELL 36 | |
628 | /* Host Controller Event */ | |
629 | #define TRB_HC_EVENT 37 | |
630 | /* Device Notification Event - device sent function wake notification */ | |
631 | #define TRB_DEV_NOTE 38 | |
632 | /* MFINDEX Wrap Event - microframe counter wrapped */ | |
633 | #define TRB_MFINDEX_WRAP 39 | |
634 | /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ | |
635 | ||
636 | /* | |
637 | * TRBS_PER_SEGMENT must be a multiple of 4, | |
638 | * since the command ring is 64-byte aligned. | |
639 | * It must also be greater than 16. | |
640 | */ | |
641 | #define TRBS_PER_SEGMENT 64 | |
642 | #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) | |
643 | ||
644 | struct xhci_segment { | |
645 | union xhci_trb *trbs; | |
646 | /* private to HCD */ | |
647 | struct xhci_segment *next; | |
648 | dma_addr_t dma; | |
649 | } __attribute__ ((packed)); | |
650 | ||
651 | struct xhci_ring { | |
652 | struct xhci_segment *first_seg; | |
653 | union xhci_trb *enqueue; | |
654 | union xhci_trb *dequeue; | |
655 | /* | |
656 | * Write the cycle state into the TRB cycle field to give ownership of | |
657 | * the TRB to the host controller (if we are the producer), or to check | |
658 | * if we own the TRB (if we are the consumer). See section 4.9.1. | |
659 | */ | |
660 | u32 cycle_state; | |
661 | }; | |
662 | ||
663 | struct xhci_erst_entry { | |
664 | /* 64-bit event ring segment address */ | |
665 | u32 seg_addr[2]; | |
666 | u32 seg_size; | |
667 | /* Set to zero */ | |
668 | u32 rsvd; | |
669 | } __attribute__ ((packed)); | |
670 | ||
671 | struct xhci_erst { | |
672 | struct xhci_erst_entry *entries; | |
673 | unsigned int num_entries; | |
674 | /* xhci->event_ring keeps track of segment dma addresses */ | |
675 | dma_addr_t erst_dma_addr; | |
676 | /* Num entries the ERST can contain */ | |
677 | unsigned int erst_size; | |
678 | }; | |
679 | ||
680 | /* | |
681 | * Each segment table entry is 4*32bits long. 1K seems like an ok size: | |
682 | * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, | |
683 | * meaning 64 ring segments. | |
684 | * Initial allocated size of the ERST, in number of entries */ | |
685 | #define ERST_NUM_SEGS 1 | |
686 | /* Initial allocated size of the ERST, in number of entries */ | |
687 | #define ERST_SIZE 64 | |
688 | /* Initial number of event segment rings allocated */ | |
689 | #define ERST_ENTRIES 1 | |
690 | /* XXX: Make these module parameters */ | |
691 | ||
74c68741 SS |
692 | |
693 | /* There is one ehci_hci structure per controller */ | |
694 | struct xhci_hcd { | |
695 | /* glue to PCI and HCD framework */ | |
696 | struct xhci_cap_regs __iomem *cap_regs; | |
697 | struct xhci_op_regs __iomem *op_regs; | |
698 | struct xhci_run_regs __iomem *run_regs; | |
0ebbab37 | 699 | struct xhci_doorbell_array __iomem *dba; |
66d4eadd SS |
700 | /* Our HCD's current interrupter register set */ |
701 | struct intr_reg __iomem *ir_set; | |
74c68741 SS |
702 | |
703 | /* Cached register copies of read-only HC data */ | |
704 | __u32 hcs_params1; | |
705 | __u32 hcs_params2; | |
706 | __u32 hcs_params3; | |
707 | __u32 hcc_params; | |
708 | ||
709 | spinlock_t lock; | |
710 | ||
711 | /* packed release number */ | |
712 | u8 sbrn; | |
713 | u16 hci_version; | |
714 | u8 max_slots; | |
715 | u8 max_interrupters; | |
716 | u8 max_ports; | |
717 | u8 isoc_threshold; | |
718 | int event_ring_max; | |
719 | int addr_64; | |
66d4eadd | 720 | /* 4KB min, 128MB max */ |
74c68741 | 721 | int page_size; |
66d4eadd SS |
722 | /* Valid values are 12 to 20, inclusive */ |
723 | int page_shift; | |
724 | /* only one MSI vector for now, but might need more later */ | |
725 | int msix_count; | |
726 | struct msix_entry *msix_entries; | |
0ebbab37 SS |
727 | /* data structures */ |
728 | struct xhci_ring *cmd_ring; | |
729 | struct xhci_ring *event_ring; | |
730 | struct xhci_erst erst; | |
731 | ||
732 | /* DMA pools */ | |
733 | struct dma_pool *device_pool; | |
734 | struct dma_pool *segment_pool; | |
74c68741 SS |
735 | }; |
736 | ||
737 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ | |
738 | static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) | |
739 | { | |
740 | return (struct xhci_hcd *) (hcd->hcd_priv); | |
741 | } | |
742 | ||
743 | static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) | |
744 | { | |
745 | return container_of((void *) xhci, struct usb_hcd, hcd_priv); | |
746 | } | |
747 | ||
748 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | |
749 | #define XHCI_DEBUG 1 | |
750 | #else | |
751 | #define XHCI_DEBUG 0 | |
752 | #endif | |
753 | ||
754 | #define xhci_dbg(xhci, fmt, args...) \ | |
755 | do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) | |
756 | #define xhci_info(xhci, fmt, args...) \ | |
757 | do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) | |
758 | #define xhci_err(xhci, fmt, args...) \ | |
759 | dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | |
760 | #define xhci_warn(xhci, fmt, args...) \ | |
761 | dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | |
762 | ||
763 | /* TODO: copied from ehci.h - can be refactored? */ | |
764 | /* xHCI spec says all registers are little endian */ | |
765 | static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, | |
766 | __u32 __iomem *regs) | |
767 | { | |
768 | return readl(regs); | |
769 | } | |
770 | static inline void xhci_writel(const struct xhci_hcd *xhci, | |
771 | const unsigned int val, __u32 __iomem *regs) | |
772 | { | |
773 | if (!in_interrupt()) | |
774 | xhci_dbg(xhci, "`MEM_WRITE_DWORD(3'b000, 32'h%0x, 32'h%0x, 4'hf);\n", | |
775 | (unsigned int) regs, val); | |
776 | writel(val, regs); | |
777 | } | |
778 | ||
66d4eadd SS |
779 | /* xHCI debugging */ |
780 | void xhci_print_ir_set(struct xhci_hcd *xhci, struct intr_reg *ir_set, int set_num); | |
781 | void xhci_print_registers(struct xhci_hcd *xhci); | |
0ebbab37 SS |
782 | void xhci_dbg_regs(struct xhci_hcd *xhci); |
783 | void xhci_print_run_regs(struct xhci_hcd *xhci); | |
784 | void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); | |
785 | void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); | |
786 | void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); | |
66d4eadd SS |
787 | |
788 | /* xHCI memory managment */ | |
789 | void xhci_mem_cleanup(struct xhci_hcd *xhci); | |
790 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); | |
791 | ||
792 | #ifdef CONFIG_PCI | |
793 | /* xHCI PCI glue */ | |
794 | int xhci_register_pci(void); | |
795 | void xhci_unregister_pci(void); | |
796 | #endif | |
797 | ||
798 | /* xHCI host controller glue */ | |
799 | int xhci_halt(struct xhci_hcd *xhci); | |
800 | int xhci_reset(struct xhci_hcd *xhci); | |
801 | int xhci_init(struct usb_hcd *hcd); | |
802 | int xhci_run(struct usb_hcd *hcd); | |
803 | void xhci_stop(struct usb_hcd *hcd); | |
804 | void xhci_shutdown(struct usb_hcd *hcd); | |
805 | int xhci_get_frame(struct usb_hcd *hcd); | |
806 | ||
74c68741 | 807 | #endif /* __LINUX_XHCI_HCD_H */ |