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[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c
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5fd54ace 1// SPDX-License-Identifier: GPL-2.0
66d4eadd
SS		 2/*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
66d4eadd
SS		 9 */
10
11#include <linux/pci.h>
7fc2a616 12#include <linux/slab.h>
6eb0de82 13#include <linux/module.h>
c3c5819a 14#include <linux/acpi.h>
768430e4 15#include <linux/reset.h>
2a821fc3 16#include <linux/suspend.h>
66d4eadd
SS		 17
18#include "xhci.h"
4bdfe4c3 19#include "xhci-trace.h"
a66d21d7 20#include "xhci-pci.h"
66d4eadd 21
fa895377
LB		 22#define SSIC_PORT_NUM 2
23#define SSIC_PORT_CFG2 0x880c
24#define SSIC_PORT_CFG2_OFFSET 0x30
abce329c
RM		 25#define PROG_DONE (1 << 30)
26#define SSIC_PORT_UNUSED (1 << 31)
2a632815
SS		 27#define SPARSE_DISABLE_BIT 17
28#define SPARSE_CNTL_ENABLE 0xC12C
abce329c 29
ac9d8fe7
SS		 30/* Device for a quirk */
31#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
32#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
d95815ba 33#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
ea0f69d8 34#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
bba18e33 35#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7 36
c877b3b2 37#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9 38#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2 39
638298dc
TI		 40#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
41#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
4c39135a 42#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
b8cb91e0
MN		 43#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
44#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
45#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
ccc04afb 46#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
0d46faca 47#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
64f5b518 48#define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8
2f8a5b41
AS		 49#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0
50#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
51#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
52#define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af
53#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
54#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed
55
56/* Thunderbolt */
57#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
2815ef7f
MN		 58#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
59#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
c4d1ca05 60#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
2815ef7f
MN		 61#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
62#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
63#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
64#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
65#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
638298dc 66
d1658268 67#define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
bde0716d
JL		 68#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
69#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
70#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
71#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
660a92a5 72
1841cb25 73#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
9da5a109 74#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
ec37198a 75#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
1841cb25 76#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
b71c669a 77#define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
9da5a109 78
66d4eadd
SS		 79static const char hcd_name[] = "xhci_hcd";
80
1885d9a3
AB		 81static struct hc_driver __read_mostly xhci_pci_hc_driver;
82
cd33a321 83static int xhci_pci_setup(struct usb_hcd *hcd);
944e7deb 84static int xhci_pci_run(struct usb_hcd *hcd);
23a3b8d5
MN		 85static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
86 struct usb_tt *tt, gfp_t mem_flags);
cd33a321
RQ		 87
88static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
cd33a321 89 .reset = xhci_pci_setup,
944e7deb 90 .start = xhci_pci_run,
23a3b8d5 91 .update_hub_device = xhci_pci_update_hub_device,
cd33a321
RQ		 92};
93
9abe15d5
JDHG		 94static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
95{
96 struct usb_hcd *hcd = xhci_to_hcd(xhci);
97
98 if (hcd->msix_enabled) {
99 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
9abe15d5 100
f977f4c9
NN		 101 /* for now, the driver only supports one primary interrupter */
102 synchronize_irq(pci_irq_vector(pdev, 0));
9abe15d5
JDHG		 103 }
104}
105
ba47b1aa
JDHG		 106/* Free any IRQs and disable MSI-X */
107static void xhci_cleanup_msix(struct xhci_hcd *xhci)
108{
109 struct usb_hcd *hcd = xhci_to_hcd(xhci);
110 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
111
ba47b1aa
JDHG		 112 /* return if using legacy interrupt */
113 if (hcd->irq > 0)
114 return;
115
f977f4c9 116 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
ba47b1aa
JDHG		 117 pci_free_irq_vectors(pdev);
118 hcd->msix_enabled = 0;
119}
120
9831960d 121/* Try enabling MSI-X with MSI and legacy IRQ as fallback */
74554e9c 122static int xhci_try_enable_msi(struct usb_hcd *hcd)
fabbd95c 123{
9831960d 124 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
74554e9c 125 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
f977f4c9 126 int ret;
fabbd95c
JDHG		 127
128 /*
74554e9c
NN		 129 * Some Fresco Logic host controllers advertise MSI, but fail to
130 * generate interrupts. Don't even try to enable MSI.
131 */
132 if (xhci->quirks & XHCI_BROKEN_MSI)
133 goto legacy_irq;
134
135 /* unregister the legacy interrupt */
136 if (hcd->irq)
137 free_irq(hcd->irq, hcd);
138 hcd->irq = 0;
139
140 /*
141 * calculate number of MSI-X vectors supported.
fabbd95c
JDHG		 142 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
143 * with max number of interrupters based on the xhci HCSPARAMS1.
74554e9c 144 * - num_online_cpus: maximum MSI-X vectors per CPUs core.
fabbd95c
JDHG		 145 * Add additional 1 vector to ensure always available interrupt.
146 */
dfbf4441
NN		 147 xhci->nvecs = min(num_online_cpus() + 1,
148 HCS_MAX_INTRS(xhci->hcs_params1));
fabbd95c 149
9831960d
NN		 150 /* TODO: Check with MSI Soc for sysdev */
151 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs,
152 PCI_IRQ_MSIX | PCI_IRQ_MSI);
dfbf4441 153 if (xhci->nvecs < 0) {
9831960d
NN		 154 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
155 "failed to allocate IRQ vectors");
156 goto legacy_irq;
fabbd95c
JDHG		 157 }
158
f977f4c9
NN		 159 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd",
160 xhci_to_hcd(xhci));
9831960d
NN		 161 if (ret)
162 goto free_irq_vectors;
fabbd95c 163
74554e9c 164 hcd->msi_enabled = 1;
9831960d 165 hcd->msix_enabled = pdev->msix_enabled;
74554e9c 166 return 0;
fabbd95c 167
9831960d
NN		 168free_irq_vectors:
169 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt",
170 pdev->msix_enabled ? "MSI-X" : "MSI");
171 pci_free_irq_vectors(pdev);
a795f708 172
5080ef2d 173legacy_irq:
fabbd95c
JDHG		 174 if (!pdev->irq) {
175 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
176 return -EINVAL;
177 }
178
fabbd95c
JDHG		 179 if (!strlen(hcd->irq_descr))
180 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
181 hcd->driver->description, hcd->self.busnum);
182
36b24ebf
NN		 183 /* fall back to legacy interrupt */
184 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd);
fabbd95c 185 if (ret) {
36b24ebf 186 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq);
fabbd95c
JDHG		 187 return ret;
188 }
189 hcd->irq = pdev->irq;
190 return 0;
191}
192
944e7deb
JDHG		 193static int xhci_pci_run(struct usb_hcd *hcd)
194{
195 int ret;
196
197 if (usb_hcd_is_primary_hcd(hcd)) {
198 ret = xhci_try_enable_msi(hcd);
199 if (ret)
200 return ret;
201 }
202
203 return xhci_run(hcd);
204}
205
ed526ba2
JDHG		 206static void xhci_pci_stop(struct usb_hcd *hcd)
207{
208 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
209
210 xhci_stop(hcd);
211
212 if (usb_hcd_is_primary_hcd(hcd))
213 xhci_cleanup_msix(xhci);
214}
215
66d4eadd
SS		 216/* called after powerup, by probe or system-pm "wakeup" */
217static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
218{
219 /*
220 * TODO: Implement finding debug ports later.
221 * TODO: see if there are any quirks that need to be added to handle
222 * new extended capabilities.
223 */
224
225 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
226 if (!pci_set_mwi(pdev))
227 xhci_dbg(xhci, "MWI active\n");
228
229 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
230 return 0;
231}
232
da3c9c4f
SAS		 233static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
234{
a66d21d7
VK		 235 struct pci_dev *pdev = to_pci_dev(dev);
236 struct xhci_driver_data *driver_data;
237 const struct pci_device_id *id;
238
97918f79 239 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
a66d21d7
VK		 240
241 if (id && id->driver_data) {
242 driver_data = (struct xhci_driver_data *)id->driver_data;
243 xhci->quirks |= driver_data->quirks;
244 }
da3c9c4f 245
ac9d8fe7
SS		 246 /* Look for vendor-specific quirks */
247 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33
SS		 248 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
249 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
250 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
251 pdev->revision == 0x0) {
ac9d8fe7 252 xhci->quirks |= XHCI_RESET_EP_QUIRK;
4bdfe4c3 253 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
15ad5b61 254 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
f5182b41 255 }
455f5892
ON		 256 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
257 pdev->revision == 0x4) {
258 xhci->quirks |= XHCI_SLOW_SUSPEND;
259 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
260 "QUIRK: Fresco Logic xHC revision %u"
261 "must be suspended extra slowly",
262 pdev->revision);
263 }
7f5c4d63
HG		 264 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
265 xhci->quirks |= XHCI_BROKEN_STREAMS;
f5182b41
SS		 266 /* Fresco Logic confirms: all revisions of this chip do not
267 * support MSI, even though some of them claim to in their PCI
268 * capabilities.
269 */
270 xhci->quirks |= XHCI_BROKEN_MSI;
4bdfe4c3
XR		 271 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
272 "QUIRK: Fresco Logic revision %u "
273 "has broken MSI implementation",
f5182b41 274 pdev->revision);
ac9d8fe7 275 }
f5182b41 276
d95815ba
HG		 277 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
278 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
279 xhci->quirks |= XHCI_BROKEN_STREAMS;
280
0238634d
SS		 281 if (pdev->vendor == PCI_VENDOR_ID_NEC)
282 xhci->quirks |= XHCI_NEC_HOST;
ac9d8fe7 283
7e393a83
AX		 284 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
285 xhci->quirks |= XHCI_AMD_0x96_HOST;
286
c41136b0 287 /* AMD PLL quirk */
4fbb8aa7 288 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
c41136b0 289 xhci->quirks |= XHCI_AMD_PLL_FIX;
2597fe99 290
621faf4f 291 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
16263abc
AM		 292 (pdev->device == 0x145c ||
293 pdev->device == 0x15e0 ||
621faf4f
KHF		 294 pdev->device == 0x15e1 ||
295 pdev->device == 0x43bb))
191edc5e
KHF		 296 xhci->quirks |= XHCI_SUSPEND_DELAY;
297
a7d57abc
SS		 298 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
299 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
300 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
301
3c128781 302 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
2a632815 303 xhci->quirks |= XHCI_DISABLE_SPARSE;
3c128781
SS		 304 xhci->quirks |= XHCI_RESET_ON_RESUME;
305 }
2a632815 306
34b67198
MN		 307 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7)
308 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
2597fe99 309
bde0716d
JL		 310 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
311 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
312 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
313 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
314 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
315 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
316
d1658268
ML		 317 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
318 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
2a821fc3 319 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
d1658268 320
e3567d2c
SS		 321 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
322 xhci->quirks |= XHCI_LPM_SUPPORT;
323 xhci->quirks |= XHCI_INTEL_HOST;
227a4fd8 324 xhci->quirks |= XHCI_AVOID_BEI;
e3567d2c 325 }
ad808333
SS		 326 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
327 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18
SS		 328 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
329 xhci->limit_active_eps = 64;
86cc558e 330 xhci->quirks |= XHCI_SW_BW_CHECKING;
e95829f4
SS		 331 /*
332 * PPT desktop boards DH77EB and DH77DF will power back on after
333 * a few seconds of being shutdown. The fix for this is to
334 * switch the ports from xHCI to EHCI on shutdown. We can't use
335 * DMI information to find those particular boards (since each
336 * vendor will change the board name), so we have to key off all
337 * PPT chipsets.
338 */
339 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
ad808333 340 }
0a939993 341 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
4c39135a
MN		 342 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
343 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
c09ec25d 344 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
fd7cd061 345 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
638298dc 346 }
b8cb91e0
MN		 347 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
348 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
349 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
ccc04afb 350 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
0d46faca 351 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
6c97cfc1 352 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
64f5b518
AS		 353 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI ||
354 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI ||
355 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) {
b8cb91e0
MN		 356 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
357 }
7e70cbff 358 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
c02588a3 359 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
7e70cbff 360 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
c02588a3
HK		 361 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
362 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
8fde481e 363 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
64f5b518 364 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI))
fa31b3cb 365 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
346e9973
MN		 366 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
367 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
ffe84e01
MN		 368 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
369 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
64f5b518
AS		 370 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI ||
371 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI))
346e9973
MN		 372 xhci->quirks |= XHCI_MISSING_CAS;
373
34cd2db4 374 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
fed70b61
RN		 375 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
376 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
34cd2db4
MN		 377 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
378
2815ef7f
MN		 379 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
380 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
381 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
c4d1ca05 382 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
2815ef7f
MN		 383 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
384 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
385 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
386 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
07a594f3 387 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
6a7c533d 388 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
5a8e3229 389 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
a611bf47 390 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
2815ef7f
MN		 391 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
392
c877b3b2 393 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9 394 pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2 395 xhci->quirks |= XHCI_RESET_ON_RESUME;
8f873c1f 396 xhci->quirks |= XHCI_BROKEN_STREAMS;
c877b3b2 397 }
da997066 398 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
12de0a35 399 pdev->device == 0x0014) {
12de0a35
MZ		 400 xhci->quirks |= XHCI_ZERO_64B_REGS;
401 }
1aa9578c 402 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
12de0a35 403 pdev->device == 0x0015) {
1aa9578c 404 xhci->quirks |= XHCI_RESET_ON_RESUME;
12de0a35
MZ		 405 xhci->quirks |= XHCI_ZERO_64B_REGS;
406 }
457a4f61
EF		 407 if (pdev->vendor == PCI_VENDOR_ID_VIA)
408 xhci->quirks |= XHCI_RESET_ON_RESUME;
85f4e45b 409
e21eba05
HG		 410 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
411 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
412 pdev->device == 0x3432)
413 xhci->quirks |= XHCI_BROKEN_STREAMS;
414
5bef4b3c 415 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
2170a98d
NSJ		 416 xhci->quirks |= XHCI_LPM_SUPPORT;
417
2391eacb 418 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
4f547472
JG		 419 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
420 /*
421 * try to tame the ASMedia 1042 controller which reports 0.96
422 * but appears to behave more like 1.0
423 */
424 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
2391eacb 425 xhci->quirks |= XHCI_BROKEN_STREAMS;
4f547472 426 }
d2f48f05 427 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
b71c669a 428 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
b71c669a
FC		 429 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
430 }
dbb0897e 431 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
ec37198a 432 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
b71c669a
FC		 433 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
434 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
dbb0897e 435 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
2391eacb 436
9da5a109
JC		 437 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
438 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
439 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
440
69307ccb
RQ		 441 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
442 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
443
11644a76
CG		 444 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
445 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
446 pdev->device == 0x9026)
447 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
448
a4a251f8
SG		 449 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
450 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
451 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
452 xhci->quirks |= XHCI_NO_SOFT_RETRY;
453
f9277281 454 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
d9b0328d 455 xhci->quirks |= XHCI_ZHAOXIN_HOST;
d5e234ff 456 xhci->quirks |= XHCI_LPM_SUPPORT;
d9b0328d 457
2a865a65 458 if (pdev->device == 0x9202) {
f9277281 459 xhci->quirks |= XHCI_RESET_ON_RESUME;
2a865a65
WW		 460 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
461 }
462
463 if (pdev->device == 0x9203)
464 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
f9277281
WW		 465 }
466
a611bf47
ML		 467 /* xHC spec requires PCI devices to support D3hot and D3cold */
468 if (xhci->hci_version >= 0x120)
660a92a5
NBS		 469 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
470
85f4e45b
ON		 471 if (xhci->quirks & XHCI_RESET_ON_RESUME)
472 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
473 "QUIRK: Resetting on resume");
da3c9c4f 474}
c41136b0 475
c3c5819a
MN		 476#ifdef CONFIG_ACPI
477static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
478{
94116f81
AS		 479 static const guid_t intel_dsm_guid =
480 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
481 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
84ed9152
MW		 482 union acpi_object *obj;
483
94116f81 484 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
84ed9152
MW		 485 NULL);
486 ACPI_FREE(obj);
c3c5819a 487}
74622f0a
MN		 488
489static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
490{
491 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
492 struct xhci_hub *rhub = &xhci->usb3_rhub;
493 int ret;
494 int i;
495
496 /* This is not the usb3 roothub we are looking for */
497 if (hcd != rhub->hcd)
498 return;
499
500 if (hdev->maxchild > rhub->num_ports) {
501 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
502 return;
503 }
504
505 for (i = 0; i < hdev->maxchild; i++) {
506 ret = usb_acpi_port_lpm_incapable(hdev, i);
507
508 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
509
510 if (ret >= 0) {
511 rhub->ports[i]->lpm_incapable = ret;
512 continue;
513 }
514 }
515}
516
c3c5819a 517#else
84ed9152 518static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
74622f0a 519static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
c3c5819a
MN		 520#endif /* CONFIG_ACPI */
521
da3c9c4f
SAS		 522/* called during probe() after chip reset completes */
523static int xhci_pci_setup(struct usb_hcd *hcd)
524{
525 struct xhci_hcd *xhci;
526 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
527 int retval;
66d4eadd 528
b50107bb
MN		 529 xhci = hcd_to_xhci(hcd);
530 if (!xhci->sbrn)
531 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
532
ab725cbe
AW		 533 /* imod_interval is the interrupt moderation value in nanoseconds. */
534 xhci->imod_interval = 40000;
535
da3c9c4f 536 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd 537 if (retval)
da3c9c4f 538 return retval;
006d5820 539
da3c9c4f
SAS		 540 if (!usb_hcd_is_primary_hcd(hcd))
541 return 0;
66d4eadd 542
024d411e
MN		 543 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
544 xhci_pme_acpi_rtd3_enable(pdev);
545
66d4eadd
SS		 546 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
547
548 /* Find any debug ports */
989bad11 549 return xhci_pci_reinit(xhci, pdev);
b02d0ed6
SS		 550}
551
23a3b8d5
MN		 552static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
553 struct usb_tt *tt, gfp_t mem_flags)
554{
74622f0a
MN		 555 /* Check if acpi claims some USB3 roothub ports are lpm incapable */
556 if (!hdev->parent)
557 xhci_find_lpm_incapable_ports(hcd, hdev);
558
23a3b8d5
MN		 559 return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
560}
561
f6ff0ac8
SS		 562/*
563 * We need to register our own PCI probe function (instead of the USB core's
564 * function) in order to create a second roothub under xHCI.
565 */
566static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
567{
568 int retval;
569 struct xhci_hcd *xhci;
f6ff0ac8 570 struct usb_hcd *hcd;
a66d21d7 571 struct xhci_driver_data *driver_data;
768430e4 572 struct reset_control *reset;
a66d21d7
VK		 573
574 driver_data = (struct xhci_driver_data *)id->driver_data;
575 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
576 retval = renesas_xhci_check_request_fw(dev, id);
577 if (retval)
578 return retval;
579 }
f6ff0ac8 580
768430e4
NSJ		 581 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
582 if (IS_ERR(reset))
583 return PTR_ERR(reset);
584 reset_control_reset(reset);
585
bcffae77
MN		 586 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
587 pm_runtime_get_noresume(&dev->dev);
588
f6ff0ac8
SS		 589 /* Register the USB 2.0 roothub.
590 * FIXME: USB core must know to register the USB 2.0 roothub first.
591 * This is sort of silly, because we could just set the HCD driver flags
592 * to say USB 2.0, but I'm not sure what the implications would be in
593 * the other parts of the HCD code.
594 */
4e55e22d 595 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
f6ff0ac8
SS		 596
597 if (retval)
bcffae77 598 goto put_runtime_pm;
f6ff0ac8
SS		 599
600 /* USB 2.0 roothub is stored in the PCI device now. */
601 hcd = dev_get_drvdata(&dev->dev);
602 xhci = hcd_to_xhci(hcd);
768430e4 603 xhci->reset = reset;
ff4c65ca
VK		 604 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
605 pci_name(dev), hcd);
f6ff0ac8
SS		 606 if (!xhci->shared_hcd) {
607 retval = -ENOMEM;
608 goto dealloc_usb2_hcd;
609 }
610
fa31b3cb
HG		 611 retval = xhci_ext_cap_init(xhci);
612 if (retval)
613 goto put_usb3_hcd;
614
f6ff0ac8 615 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8 616 IRQF_SHARED);
f6ff0ac8
SS		 617 if (retval)
618 goto put_usb3_hcd;
619 /* Roothub already marked as USB 3.0 speed */
3b3db026 620
8f873c1f
HG		 621 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
622 HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589
ON		 623 xhci->shared_hcd->can_do_streams = 1;
624
bcffae77
MN		 625 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
626 pm_runtime_put_noidle(&dev->dev);
627
a5d6264b
BN		 628 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
629 pm_runtime_forbid(&dev->dev);
630 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
2815ef7f
MN		 631 pm_runtime_allow(&dev->dev);
632
93915a41
RR		 633 dma_set_max_seg_size(&dev->dev, UINT_MAX);
634
f6ff0ac8
SS		 635 return 0;
636
637put_usb3_hcd:
638 usb_put_hcd(xhci->shared_hcd);
639dealloc_usb2_hcd:
640 usb_hcd_pci_remove(dev);
bcffae77
MN		 641put_runtime_pm:
642 pm_runtime_put_noidle(&dev->dev);
f6ff0ac8
SS		 643 return retval;
644}
645
b02d0ed6
SS		 646static void xhci_pci_remove(struct pci_dev *dev)
647{
648 struct xhci_hcd *xhci;
649
650 xhci = hcd_to_xhci(pci_get_drvdata(dev));
a66d21d7 651
98d74f9c 652 xhci->xhc_state |= XHCI_STATE_REMOVING;
2815ef7f
MN		 653
654 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
655 pm_runtime_forbid(&dev->dev);
656
f6ff0ac8
SS		 657 if (xhci->shared_hcd) {
658 usb_remove_hcd(xhci->shared_hcd);
659 usb_put_hcd(xhci->shared_hcd);
f0680904 660 xhci->shared_hcd = NULL;
f6ff0ac8 661 }
638298dc
TI		 662
663 /* Workaround for spurious wakeups at shutdown with HSW */
664 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
665 pci_set_power_state(dev, PCI_D3hot);
f1f6d9a8
MN		 666
667 usb_hcd_pci_remove(dev);
66d4eadd
SS		 668}
669
2b7627b7
TB		 670/*
671 * In some Intel xHCI controllers, in order to get D3 working,
672 * through a vendor specific SSIC CONFIG register at offset 0x883c,
673 * SSIC PORT need to be marked as "unused" before putting xHCI
674 * into D3. After D3 exit, the SSIC port need to be marked as "used".
675 * Without this change, xHCI might not enter D3 state.
2b7627b7 676 */
7e70cbff 677static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
2b7627b7
TB		 678{
679 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2b7627b7
TB		 680 u32 val;
681 void __iomem *reg;
fa895377 682 int i;
2b7627b7 683
7e70cbff
LB		 684 for (i = 0; i < SSIC_PORT_NUM; i++) {
685 reg = (void __iomem *) xhci->cap_regs +
686 SSIC_PORT_CFG2 +
687 i * SSIC_PORT_CFG2_OFFSET;
688
689 /* Notify SSIC that SSIC profile programming is not done. */
690 val = readl(reg) & ~PROG_DONE;
691 writel(val, reg);
692
693 /* Mark SSIC port as unused(suspend) or used(resume) */
694 val = readl(reg);
695 if (suspend)
696 val |= SSIC_PORT_UNUSED;
697 else
698 val &= ~SSIC_PORT_UNUSED;
699 writel(val, reg);
700
701 /* Notify SSIC that SSIC profile programming is done */
702 val = readl(reg) | PROG_DONE;
703 writel(val, reg);
704 readl(reg);
2b7627b7 705 }
7e70cbff
LB		 706}
707
708/*
709 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
710 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
711 */
712static void xhci_pme_quirk(struct usb_hcd *hcd)
713{
714 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
715 void __iomem *reg;
716 u32 val;
2b7627b7
TB		 717
718 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
719 val = readl(reg);
720 writel(val | BIT(28), reg);
721 readl(reg);
722}
723
2a632815
SS		 724static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
725{
726 u32 reg;
727
728 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
729 reg &= ~BIT(SPARSE_DISABLE_BIT);
730 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
731}
732
5535b1d5
AX		 733static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
734{
735 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5 736 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
92149c93 737 int ret;
c3897aa5
SS		 738
739 /*
740 * Systems with the TI redriver that loses port status change events
741 * need to have the registers polled during D3, so avoid D3cold.
742 */
2a821fc3 743 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
9d26d3a8 744 pci_d3cold_disable(pdev);
5535b1d5 745
2a821fc3
ML		 746#ifdef CONFIG_SUSPEND
747 /* d3cold is broken, but only when s2idle is used */
748 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
749 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
750 pci_d3cold_disable(pdev);
751#endif
752
b8cb91e0 753 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff
LB		 754 xhci_pme_quirk(hcd);
755
756 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
757 xhci_ssic_port_unused_quirk(hcd, true);
b8cb91e0 758
2a632815
SS		 759 if (xhci->quirks & XHCI_DISABLE_SPARSE)
760 xhci_sparse_control_quirk(hcd);
761
92149c93 762 ret = xhci_suspend(xhci, do_wakeup);
0c540438
JDHG		 763
764 /* synchronize irq when using MSI-X */
765 xhci_msix_sync_irqs(xhci);
766
92149c93
LB		 767 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
768 xhci_ssic_port_unused_quirk(hcd, false);
769
770 return ret;
5535b1d5
AX		 771}
772
1f7d5520 773static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
5535b1d5
AX		 774{
775 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2 776 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5
AX		 777 int retval = 0;
778
768430e4
NSJ		 779 reset_control_reset(xhci->reset);
780
69e848c2
SS		 781 /* The BIOS on systems with the Intel Panther Point chipset may or may
782 * not support xHCI natively. That means that during system resume, it
783 * may switch the ports back to EHCI so that users can use their
784 * keyboard to select a kernel from GRUB after resume from hibernate.
785 *
786 * The BIOS is supposed to remember whether the OS had xHCI ports
787 * enabled before resume, and switch the ports back to xHCI when the
788 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
789 * writers.
790 *
791 * Unconditionally switch the ports back to xHCI after a system resume.
26b76798
MN		 792 * It should not matter whether the EHCI or xHCI controller is
793 * resumed first. It's enough to do the switchover in xHCI because
794 * USB core won't notice anything as the hub driver doesn't start
795 * running again until after all the devices (including both EHCI and
796 * xHCI host controllers) have been resumed.
69e848c2 797 */
26b76798
MN		 798
799 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
800 usb_enable_intel_xhci_ports(pdev);
69e848c2 801
7e70cbff
LB		 802 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
803 xhci_ssic_port_unused_quirk(hcd, false);
804
b8cb91e0 805 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff 806 xhci_pme_quirk(hcd);
b8cb91e0 807
1f7d5520 808 retval = xhci_resume(xhci, msg);
5535b1d5
AX		 809 return retval;
810}
5535b1d5 811
c3bbacd6
MN		 812static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
813{
814 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
815 struct xhci_port *port;
816 struct usb_device *udev;
c3bbacd6
MN		 817 u32 portsc;
818 int i;
819
820 /*
821 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
822 * cause significant boot delay if usb ports are in suspended U3 state
823 * during boot. Some USB devices survive in U3 state over S4 hibernate
824 *
825 * Disable ports that are in U3 if remote wake is not enabled for either
826 * host controller or connected device
827 */
828
829 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
830 return 0;
831
832 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
833 port = &xhci->hw_ports[i];
834 portsc = readl(port->addr);
835
836 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
837 continue;
838
74151b53 839 if (!port->slot_id || !xhci->devs[port->slot_id]) {
c3bbacd6 840 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
74151b53
NN		 841 port->slot_id, port->rhub->hcd->self.busnum,
842 port->hcd_portnum + 1);
c3bbacd6
MN		 843 continue;
844 }
845
74151b53 846 udev = xhci->devs[port->slot_id]->udev;
c3bbacd6
MN		 847
848 /* if wakeup is enabled then don't disable the port */
849 if (udev->do_remote_wakeup && do_wakeup)
850 continue;
851
852 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
853 port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
854 portsc = xhci_port_state_to_neutral(portsc);
855 writel(portsc | PORT_PE, port->addr);
856 }
857
858 return 0;
859}
860
f2c710f7
HL		 861static void xhci_pci_shutdown(struct usb_hcd *hcd)
862{
863 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
864 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
865
866 xhci_shutdown(hcd);
ed526ba2 867 xhci_cleanup_msix(xhci);
f2c710f7
HL		 868
869 /* Yet another workaround for spurious wakeups at shutdown with HSW */
870 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
871 pci_set_power_state(pdev, PCI_D3hot);
872}
873
66d4eadd
SS		 874/*-------------------------------------------------------------------------*/
875
a66d21d7
VK		 876static const struct xhci_driver_data reneses_data = {
877 .quirks = XHCI_RENESAS_FW_QUIRK,
878 .firmware = "renesas_usb_fw.mem",
879};
880
66d4eadd 881/* PCI driver selection metadata; PCI hotplugging uses this */
ff4c65ca 882static const struct pci_device_id pci_ids[] = {
d6b2b694 883 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014),
a66d21d7
VK		 884 .driver_data = (unsigned long)&reneses_data,
885 },
d6b2b694 886 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015),
a66d21d7
VK		 887 .driver_data = (unsigned long)&reneses_data,
888 },
66d4eadd 889 /* handle any USB 3.0 xHCI controller */
ff4c65ca 890 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
66d4eadd
SS		 891 },
892 { /* end: all zeroes */ }
893};
894MODULE_DEVICE_TABLE(pci, pci_ids);
0665e387
GT		 895
896/*
897 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
898 * load firmware, so don't encumber the xhci-pci driver with it.
899 */
900#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
a66d21d7 901MODULE_FIRMWARE("renesas_usb_fw.mem");
0665e387 902#endif
66d4eadd
SS		 903
904/* pci driver glue; this is a "new style" PCI driver module */
905static struct pci_driver xhci_pci_driver = {
c02f1ef6 906 .name = hcd_name,
66d4eadd
SS		 907 .id_table = pci_ids,
908
f6ff0ac8 909 .probe = xhci_pci_probe,
b02d0ed6 910 .remove = xhci_pci_remove,
66d4eadd
SS		 911 /* suspend and resume implemented later */
912
913 .shutdown = usb_hcd_pci_shutdown,
5535b1d5 914 .driver = {
130eac41 915 .pm = pm_ptr(&usb_hcd_pci_pm_ops),
4c2604a9 916 },
66d4eadd
SS		 917};
918
29e409f0 919static int __init xhci_pci_init(void)
66d4eadd 920{
cd33a321 921 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
130eac41
AB		 922 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend);
923 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume);
924 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late);
925 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown);
ed526ba2 926 xhci_pci_hc_driver.stop = xhci_pci_stop;
66d4eadd
SS		 927 return pci_register_driver(&xhci_pci_driver);
928}
29e409f0 929module_init(xhci_pci_init);
66d4eadd 930
29e409f0 931static void __exit xhci_pci_exit(void)
66d4eadd
SS		 932{
933 pci_unregister_driver(&xhci_pci_driver);
934}
29e409f0
AB		 935module_exit(xhci_pci_exit);
936
937MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
938MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)