[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/acpi.h>

#include "xhci.h"
#include "xhci-trace.h"

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_EJ168		0x7023

#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI		0x22b5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI		0xa12f
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI	0x9d2f

static const char hcd_name[] = "xhci_hcd";

static struct hc_driver __read_mostly xhci_pci_hc_driver;

static int xhci_pci_setup(struct usb_hcd *hcd);

static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
	.extra_priv_size = sizeof(struct xhci_hcd),
	.reset = xhci_pci_setup,
};

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x4) {
			xhci->quirks |= XHCI_SLOW_SUSPEND;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC revision %u"
				"must be suspended extra slowly",
				pdev->revision);
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
			xhci->quirks |= XHCI_BROKEN_STREAMS;
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;

	if (pdev->vendor == PCI_VENDOR_ID_AMD)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) {
		xhci->quirks |= XHCI_PME_STUCK_QUIRK;
	}
	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_EJ168) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	}
	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
			pdev->device == 0x0015)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;

	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
			pdev->device == 0x3432)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
			pdev->device == 0x1042)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (xhci->quirks & XHCI_RESET_ON_RESUME)
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
}

/*
 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 */
static void xhci_pme_quirk(struct xhci_hcd *xhci)
{
	u32 val;
	void __iomem *reg;

	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	val = readl(reg);
	writel(val | BIT(28), reg);
	readl(reg);
}

#ifdef CONFIG_ACPI
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
{
	static const u8 intel_dsm_uuid[] = {
		0xb7, 0x0c, 0x34, 0xac,	0x01, 0xe9, 0xbf, 0x45,
		0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
	};
	acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, NULL);
}
#else
	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	xhci = hcd_to_xhci(hcd);
	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	retval = xhci_pci_reinit(xhci, pdev);
	if (!retval)
		return retval;

	return retval;
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;

	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	pm_runtime_get_noresume(&dev->dev);

	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		goto put_runtime_pm;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
			HCC_MAX_PSA(xhci->hcc_params) >= 4)
		xhci->shared_hcd->can_do_streams = 1;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_acpi_rtd3_enable(dev);

	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	pm_runtime_put_noidle(&dev->dev);

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
put_runtime_pm:
	pm_runtime_put_noidle(&dev->dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}
	usb_hcd_pci_remove(dev);

	/* Workaround for spurious wakeups at shutdown with HSW */
	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
		pci_set_power_state(dev, PCI_D3hot);
}

#ifdef CONFIG_PM
static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
		pdev->no_d3cold = true;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(xhci);

	return xhci_suspend(xhci, do_wakeup);
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(xhci);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

static int __init xhci_pci_init(void)
{
	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
#ifdef CONFIG_PM
	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
#endif
	return pci_register_driver(&xhci_pci_driver);
}
module_init(xhci_pci_init);

static void __exit xhci_pci_exit(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
module_exit(xhci_pci_exit);

MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
c3c5819a	26	#include <linux/acpi.h>
66d4eadd SS	27
66d4eadd SS	28	#include "xhci.h"
4bdfe4c3	29	#include "xhci-trace.h"
66d4eadd	30
ac9d8fe7 SS	31	/* Device for a quirk */
	32	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	33	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
bba18e33	34	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	35
c877b3b2	36	#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9	37	#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2	38
638298dc TI	39	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
638298dc TI	40	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
b8cb91e0 MN	41	#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
	42	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
	43	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
638298dc	44
66d4eadd SS	45	static const char hcd_name[] = "xhci_hcd";
66d4eadd SS	46
1885d9a3 AB	47	static struct hc_driver __read_mostly xhci_pci_hc_driver;
1885d9a3 AB	48
cd33a321 RQ	49	static int xhci_pci_setup(struct usb_hcd *hcd);
	50
	51	static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
	52	.extra_priv_size = sizeof(struct xhci_hcd),
	53	.reset = xhci_pci_setup,
	54	};
	55
66d4eadd SS	56	/* called after powerup, by probe or system-pm "wakeup" */
	57	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	58	{
	59	/*
	60	* TODO: Implement finding debug ports later.
	61	* TODO: see if there are any quirks that need to be added to handle
	62	* new extended capabilities.
	63	*/
	64
	65	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	66	if (!pci_set_mwi(pdev))
	67	xhci_dbg(xhci, "MWI active\n");
	68
	69	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	70	return 0;
	71	}
	72
da3c9c4f SAS	73	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	74	{
	75	struct pci_dev *pdev = to_pci_dev(dev);
	76
ac9d8fe7 SS	77	/* Look for vendor-specific quirks */
ac9d8fe7 SS	78	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	79	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	80	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	81	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	82	pdev->revision == 0x0) {
ac9d8fe7	83	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	84	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	85	"QUIRK: Fresco Logic xHC needs configure"
	86	" endpoint cmd after reset endpoint");
f5182b41	87	}
455f5892 ON	88	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	89	pdev->revision == 0x4) {
	90	xhci->quirks \|= XHCI_SLOW_SUSPEND;
	91	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	92	"QUIRK: Fresco Logic xHC revision %u"
	93	"must be suspended extra slowly",
	94	pdev->revision);
	95	}
7f5c4d63 HG	96	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
7f5c4d63 HG	97	xhci->quirks \|= XHCI_BROKEN_STREAMS;
f5182b41 SS	98	/* Fresco Logic confirms: all revisions of this chip do not
	99	* support MSI, even though some of them claim to in their PCI
	100	* capabilities.
	101	*/
	102	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	103	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	104	"QUIRK: Fresco Logic revision %u "
	105	"has broken MSI implementation",
f5182b41	106	pdev->revision);
1530bbc6	107	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	108	}
f5182b41	109
0238634d SS	110	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	111	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	112
7e393a83 AX	113	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	114	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	115
c41136b0 AX	116	/* AMD PLL quirk */
	117	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	118	xhci->quirks \|= XHCI_AMD_PLL_FIX;
2597fe99 HR	119
	120	if (pdev->vendor == PCI_VENDOR_ID_AMD)
	121	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
	122
e3567d2c SS	123	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	124	xhci->quirks \|= XHCI_LPM_SUPPORT;
	125	xhci->quirks \|= XHCI_INTEL_HOST;
227a4fd8	126	xhci->quirks \|= XHCI_AVOID_BEI;
e3567d2c	127	}
ad808333 SS	128	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	129	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	130	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	131	xhci->limit_active_eps = 64;
86cc558e	132	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	133	/*
	134	* PPT desktop boards DH77EB and DH77DF will power back on after
	135	* a few seconds of being shutdown. The fix for this is to
	136	* switch the ports from xHCI to EHCI on shutdown. We can't use
	137	* DMI information to find those particular boards (since each
	138	* vendor will change the board name), so we have to key off all
	139	* PPT chipsets.
	140	*/
	141	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
ad808333	142	}
0a939993 DT	143	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0a939993 DT	144	pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
c09ec25d	145	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
638298dc	146	}
b8cb91e0 MN	147	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	148	(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI \|\|
	149	pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI \|\|
	150	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) {
	151	xhci->quirks \|= XHCI_PME_STUCK_QUIRK;
	152	}
c877b3b2	153	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9	154	pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2	155	xhci->quirks \|= XHCI_RESET_ON_RESUME;
5cb7df2b	156	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
8f873c1f	157	xhci->quirks \|= XHCI_BROKEN_STREAMS;
c877b3b2	158	}
1aa9578c	159	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb	160	pdev->device == 0x0015)
1aa9578c	161	xhci->quirks \|= XHCI_RESET_ON_RESUME;
457a4f61 EF	162	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	163	xhci->quirks \|= XHCI_RESET_ON_RESUME;
85f4e45b	164
e21eba05 HG	165	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	166	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
	167	pdev->device == 0x3432)
	168	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	169
2391eacb HG	170	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	171	pdev->device == 0x1042)
	172	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	173
85f4e45b ON	174	if (xhci->quirks & XHCI_RESET_ON_RESUME)
	175	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	176	"QUIRK: Resetting on resume");
da3c9c4f	177	}
c41136b0	178
b8cb91e0 MN	179	/*
	180	* Make sure PME works on some Intel xHCI controllers by writing 1 to clear
	181	* the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
	182	*/
	183	static void xhci_pme_quirk(struct xhci_hcd *xhci)
	184	{
	185	u32 val;
	186	void __iomem *reg;
	187
	188	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	189	val = readl(reg);
	190	writel(val \| BIT(28), reg);
	191	readl(reg);
	192	}
	193
c3c5819a MN	194	#ifdef CONFIG_ACPI
	195	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
	196	{
	197	static const u8 intel_dsm_uuid[] = {
	198	0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
	199	0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
	200	};
	201	acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, NULL);
	202	}
	203	#else
	204	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
	205	#endif /* CONFIG_ACPI */
	206
da3c9c4f SAS	207	/* called during probe() after chip reset completes */
	208	static int xhci_pci_setup(struct usb_hcd *hcd)
	209	{
	210	struct xhci_hcd *xhci;
	211	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	212	int retval;
66d4eadd	213
da3c9c4f	214	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	215	if (retval)
da3c9c4f	216	return retval;
006d5820	217
da3c9c4f SAS	218	xhci = hcd_to_xhci(hcd);
	219	if (!usb_hcd_is_primary_hcd(hcd))
	220	return 0;
66d4eadd SS	221
	222	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	223	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	224
	225	/* Find any debug ports */
b02d0ed6 SS	226	retval = xhci_pci_reinit(xhci, pdev);
	227	if (!retval)
	228	return retval;
	229
b02d0ed6 SS	230	return retval;
	231	}
	232
f6ff0ac8 SS	233	/*
	234	* We need to register our own PCI probe function (instead of the USB core's
	235	* function) in order to create a second roothub under xHCI.
	236	*/
	237	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	238	{
	239	int retval;
	240	struct xhci_hcd *xhci;
	241	struct hc_driver *driver;
	242	struct usb_hcd *hcd;
	243
	244	driver = (struct hc_driver *)id->driver_data;
bcffae77 MN	245
	246	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	247	pm_runtime_get_noresume(&dev->dev);
	248
f6ff0ac8 SS	249	/* Register the USB 2.0 roothub.
	250	* FIXME: USB core must know to register the USB 2.0 roothub first.
	251	* This is sort of silly, because we could just set the HCD driver flags
	252	* to say USB 2.0, but I'm not sure what the implications would be in
	253	* the other parts of the HCD code.
	254	*/
	255	retval = usb_hcd_pci_probe(dev, id);
	256
	257	if (retval)
bcffae77	258	goto put_runtime_pm;
f6ff0ac8 SS	259
	260	/* USB 2.0 roothub is stored in the PCI device now. */
	261	hcd = dev_get_drvdata(&dev->dev);
	262	xhci = hcd_to_xhci(hcd);
	263	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	264	pci_name(dev), hcd);
	265	if (!xhci->shared_hcd) {
	266	retval = -ENOMEM;
	267	goto dealloc_usb2_hcd;
	268	}
	269
f6ff0ac8	270	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	271	IRQF_SHARED);
f6ff0ac8 SS	272	if (retval)
	273	goto put_usb3_hcd;
	274	/* Roothub already marked as USB 3.0 speed */
3b3db026	275
8f873c1f HG	276	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
8f873c1f HG	277	HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589 ON	278	xhci->shared_hcd->can_do_streams = 1;
14aec589 ON	279
c3c5819a MN	280	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
	281	xhci_pme_acpi_rtd3_enable(dev);
	282
bcffae77 MN	283	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	284	pm_runtime_put_noidle(&dev->dev);
	285
f6ff0ac8 SS	286	return 0;
	287
	288	put_usb3_hcd:
	289	usb_put_hcd(xhci->shared_hcd);
	290	dealloc_usb2_hcd:
	291	usb_hcd_pci_remove(dev);
bcffae77 MN	292	put_runtime_pm:
bcffae77 MN	293	pm_runtime_put_noidle(&dev->dev);
f6ff0ac8 SS	294	return retval;
	295	}
	296
b02d0ed6 SS	297	static void xhci_pci_remove(struct pci_dev *dev)
	298	{
	299	struct xhci_hcd *xhci;
	300
	301	xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8 SS	302	if (xhci->shared_hcd) {
	303	usb_remove_hcd(xhci->shared_hcd);
	304	usb_put_hcd(xhci->shared_hcd);
	305	}
b02d0ed6	306	usb_hcd_pci_remove(dev);
638298dc TI	307
	308	/* Workaround for spurious wakeups at shutdown with HSW */
	309	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
	310	pci_set_power_state(dev, PCI_D3hot);
66d4eadd SS	311	}
66d4eadd SS	312
5535b1d5 AX	313	#ifdef CONFIG_PM
	314	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	315	{
	316	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5 SS	317	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	318
	319	/*
	320	* Systems with the TI redriver that loses port status change events
	321	* need to have the registers polled during D3, so avoid D3cold.
	322	*/
e1cd9727	323	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
c3897aa5	324	pdev->no_d3cold = true;
5535b1d5	325
b8cb91e0 MN	326	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
	327	xhci_pme_quirk(xhci);
	328
a1377e53	329	return xhci_suspend(xhci, do_wakeup);
5535b1d5 AX	330	}
	331
	332	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	333	{
	334	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	335	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	336	int retval = 0;
5535b1d5 AX	337
69e848c2 SS	338	/* The BIOS on systems with the Intel Panther Point chipset may or may
	339	* not support xHCI natively. That means that during system resume, it
	340	* may switch the ports back to EHCI so that users can use their
	341	* keyboard to select a kernel from GRUB after resume from hibernate.
	342	*
	343	* The BIOS is supposed to remember whether the OS had xHCI ports
	344	* enabled before resume, and switch the ports back to xHCI when the
	345	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	346	* writers.
	347	*
	348	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	349	* It should not matter whether the EHCI or xHCI controller is
	350	* resumed first. It's enough to do the switchover in xHCI because
	351	* USB core won't notice anything as the hub driver doesn't start
	352	* running again until after all the devices (including both EHCI and
	353	* xHCI host controllers) have been resumed.
69e848c2	354	*/
26b76798 MN	355
	356	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	357	usb_enable_intel_xhci_ports(pdev);
69e848c2	358
b8cb91e0 MN	359	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
	360	xhci_pme_quirk(xhci);
	361
5535b1d5 AX	362	retval = xhci_resume(xhci, hibernated);
	363	return retval;
	364	}
	365	#endif /* CONFIG_PM */
	366
66d4eadd SS	367	/-------------------------------------------------------------------------/
	368
	369	/* PCI driver selection metadata; PCI hotplugging uses this */
	370	static const struct pci_device_id pci_ids[] = { {
	371	/* handle any USB 3.0 xHCI controller */
	372	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	373	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	374	},
	375	{ /* end: all zeroes */ }
	376	};
	377	MODULE_DEVICE_TABLE(pci, pci_ids);
	378
	379	/* pci driver glue; this is a "new style" PCI driver module */
	380	static struct pci_driver xhci_pci_driver = {
	381	.name = (char *) hcd_name,
	382	.id_table = pci_ids,
	383
f6ff0ac8	384	.probe = xhci_pci_probe,
b02d0ed6	385	.remove = xhci_pci_remove,
66d4eadd SS	386	/* suspend and resume implemented later */
	387
	388	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	389	#ifdef CONFIG_PM
5535b1d5 AX	390	.driver = {
	391	.pm = &usb_hcd_pci_pm_ops
	392	},
	393	#endif
66d4eadd SS	394	};
66d4eadd SS	395
29e409f0	396	static int __init xhci_pci_init(void)
66d4eadd	397	{
cd33a321	398	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1885d9a3 AB	399	#ifdef CONFIG_PM
	400	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	401	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
	402	#endif
66d4eadd SS	403	return pci_register_driver(&xhci_pci_driver);
66d4eadd SS	404	}
29e409f0	405	module_init(xhci_pci_init);
66d4eadd	406
29e409f0	407	static void __exit xhci_pci_exit(void)
66d4eadd SS	408	{
	409	pci_unregister_driver(&xhci_pci_driver);
	410	}
29e409f0 AB	411	module_exit(xhci_pci_exit);
	412
	413	MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
	414	MODULE_LICENSE("GPL");