[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/acpi.h>

#include "xhci.h"
#include "xhci-trace.h"

#define SSIC_PORT_NUM		2
#define SSIC_PORT_CFG2		0x880c
#define SSIC_PORT_CFG2_OFFSET	0x30
#define PROG_DONE		(1 << 30)
#define SSIC_PORT_UNUSED	(1 << 31)

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_EJ168		0x7023

#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI		0x22b5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI		0xa12f
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI	0x9d2f
#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI		0x0aa8
#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI		0x1aa8

static const char hcd_name[] = "xhci_hcd";

static struct hc_driver __read_mostly xhci_pci_hc_driver;

static int xhci_pci_setup(struct usb_hcd *hcd);

static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
	.reset = xhci_pci_setup,
};

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x4) {
			xhci->quirks |= XHCI_SLOW_SUSPEND;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC revision %u"
				"must be suspended extra slowly",
				pdev->revision);
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
			xhci->quirks |= XHCI_BROKEN_STREAMS;
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;

	if (pdev->vendor == PCI_VENDOR_ID_AMD)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
		xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI)) {
		xhci->quirks |= XHCI_PME_STUCK_QUIRK;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
		xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
	}
	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_EJ168) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	}
	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
			pdev->device == 0x0015)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;

	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
			pdev->device == 0x3432)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
			pdev->device == 0x1042)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (xhci->quirks & XHCI_RESET_ON_RESUME)
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
}

#ifdef CONFIG_ACPI
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
{
	static const u8 intel_dsm_uuid[] = {
		0xb7, 0x0c, 0x34, 0xac,	0x01, 0xe9, 0xbf, 0x45,
		0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
	};
	union acpi_object *obj;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
				NULL);
	ACPI_FREE(obj);
}
#else
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	xhci = hcd_to_xhci(hcd);
	if (!xhci->sbrn)
		pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	retval = xhci_pci_reinit(xhci, pdev);
	if (!retval)
		return retval;

	return retval;
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;

	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	pm_runtime_get_noresume(&dev->dev);

	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		goto put_runtime_pm;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
			HCC_MAX_PSA(xhci->hcc_params) >= 4)
		xhci->shared_hcd->can_do_streams = 1;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_acpi_rtd3_enable(dev);

	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	pm_runtime_put_noidle(&dev->dev);

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
put_runtime_pm:
	pm_runtime_put_noidle(&dev->dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}
	usb_hcd_pci_remove(dev);

	/* Workaround for spurious wakeups at shutdown with HSW */
	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
		pci_set_power_state(dev, PCI_D3hot);
}

#ifdef CONFIG_PM
/*
 * In some Intel xHCI controllers, in order to get D3 working,
 * through a vendor specific SSIC CONFIG register at offset 0x883c,
 * SSIC PORT need to be marked as "unused" before putting xHCI
 * into D3. After D3 exit, the SSIC port need to be marked as "used".
 * Without this change, xHCI might not enter D3 state.
 */
static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	u32 val;
	void __iomem *reg;
	int i;

	for (i = 0; i < SSIC_PORT_NUM; i++) {
		reg = (void __iomem *) xhci->cap_regs +
				SSIC_PORT_CFG2 +
				i * SSIC_PORT_CFG2_OFFSET;

		/* Notify SSIC that SSIC profile programming is not done. */
		val = readl(reg) & ~PROG_DONE;
		writel(val, reg);

		/* Mark SSIC port as unused(suspend) or used(resume) */
		val = readl(reg);
		if (suspend)
			val |= SSIC_PORT_UNUSED;
		else
			val &= ~SSIC_PORT_UNUSED;
		writel(val, reg);

		/* Notify SSIC that SSIC profile programming is done */
		val = readl(reg) | PROG_DONE;
		writel(val, reg);
		readl(reg);
	}
}

/*
 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 */
static void xhci_pme_quirk(struct usb_hcd *hcd)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	void __iomem *reg;
	u32 val;

	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	val = readl(reg);
	writel(val | BIT(28), reg);
	readl(reg);
}

static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			ret;

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
		pdev->no_d3cold = true;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd);

	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
		xhci_ssic_port_unused_quirk(hcd, true);

	ret = xhci_suspend(xhci, do_wakeup);
	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
		xhci_ssic_port_unused_quirk(hcd, false);

	return ret;
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
		xhci_ssic_port_unused_quirk(hcd, false);

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

static int __init xhci_pci_init(void)
{
	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
#ifdef CONFIG_PM
	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
#endif
	return pci_register_driver(&xhci_pci_driver);
}
module_init(xhci_pci_init);

static void __exit xhci_pci_exit(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
module_exit(xhci_pci_exit);

MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
c3c5819a	26	#include <linux/acpi.h>
66d4eadd SS	27
66d4eadd SS	28	#include "xhci.h"
4bdfe4c3	29	#include "xhci-trace.h"
66d4eadd	30
fa895377 LB	31	#define SSIC_PORT_NUM 2
	32	#define SSIC_PORT_CFG2 0x880c
	33	#define SSIC_PORT_CFG2_OFFSET 0x30
abce329c RM	34	#define PROG_DONE (1 << 30)
	35	#define SSIC_PORT_UNUSED (1 << 31)
	36
ac9d8fe7 SS	37	/* Device for a quirk */
	38	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	39	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
bba18e33	40	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	41
c877b3b2	42	#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9	43	#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2	44
638298dc TI	45	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
638298dc TI	46	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
b8cb91e0 MN	47	#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
	48	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
	49	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
ccc04afb	50	#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
0d46faca	51	#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
638298dc	52
66d4eadd SS	53	static const char hcd_name[] = "xhci_hcd";
66d4eadd SS	54
1885d9a3 AB	55	static struct hc_driver __read_mostly xhci_pci_hc_driver;
1885d9a3 AB	56
cd33a321 RQ	57	static int xhci_pci_setup(struct usb_hcd *hcd);
	58
	59	static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
cd33a321 RQ	60	.reset = xhci_pci_setup,
	61	};
	62
66d4eadd SS	63	/* called after powerup, by probe or system-pm "wakeup" */
	64	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	65	{
	66	/*
	67	* TODO: Implement finding debug ports later.
	68	* TODO: see if there are any quirks that need to be added to handle
	69	* new extended capabilities.
	70	*/
	71
	72	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	73	if (!pci_set_mwi(pdev))
	74	xhci_dbg(xhci, "MWI active\n");
	75
	76	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	77	return 0;
	78	}
	79
da3c9c4f SAS	80	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	81	{
	82	struct pci_dev *pdev = to_pci_dev(dev);
	83
ac9d8fe7 SS	84	/* Look for vendor-specific quirks */
ac9d8fe7 SS	85	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	86	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	87	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	88	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	89	pdev->revision == 0x0) {
ac9d8fe7	90	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	91	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	92	"QUIRK: Fresco Logic xHC needs configure"
	93	" endpoint cmd after reset endpoint");
f5182b41	94	}
455f5892 ON	95	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	96	pdev->revision == 0x4) {
	97	xhci->quirks \|= XHCI_SLOW_SUSPEND;
	98	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	99	"QUIRK: Fresco Logic xHC revision %u"
	100	"must be suspended extra slowly",
	101	pdev->revision);
	102	}
7f5c4d63 HG	103	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
7f5c4d63 HG	104	xhci->quirks \|= XHCI_BROKEN_STREAMS;
f5182b41 SS	105	/* Fresco Logic confirms: all revisions of this chip do not
	106	* support MSI, even though some of them claim to in their PCI
	107	* capabilities.
	108	*/
	109	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	110	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	111	"QUIRK: Fresco Logic revision %u "
	112	"has broken MSI implementation",
f5182b41	113	pdev->revision);
1530bbc6	114	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	115	}
f5182b41	116
0238634d SS	117	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	118	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	119
7e393a83 AX	120	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	121	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	122
c41136b0 AX	123	/* AMD PLL quirk */
	124	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	125	xhci->quirks \|= XHCI_AMD_PLL_FIX;
2597fe99 HR	126
	127	if (pdev->vendor == PCI_VENDOR_ID_AMD)
	128	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
	129
e3567d2c SS	130	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	131	xhci->quirks \|= XHCI_LPM_SUPPORT;
	132	xhci->quirks \|= XHCI_INTEL_HOST;
227a4fd8	133	xhci->quirks \|= XHCI_AVOID_BEI;
e3567d2c	134	}
ad808333 SS	135	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	136	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	137	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	138	xhci->limit_active_eps = 64;
86cc558e	139	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	140	/*
	141	* PPT desktop boards DH77EB and DH77DF will power back on after
	142	* a few seconds of being shutdown. The fix for this is to
	143	* switch the ports from xHCI to EHCI on shutdown. We can't use
	144	* DMI information to find those particular boards (since each
	145	* vendor will change the board name), so we have to key off all
	146	* PPT chipsets.
	147	*/
	148	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
ad808333	149	}
0a939993 DT	150	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0a939993 DT	151	pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
c09ec25d	152	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
fd7cd061	153	xhci->quirks \|= XHCI_SPURIOUS_WAKEUP;
638298dc	154	}
b8cb91e0 MN	155	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	156	(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI \|\|
	157	pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI \|\|
ccc04afb	158	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI \|\|
0d46faca RR	159	pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI \|\|
0d46faca RR	160	pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI)) {
b8cb91e0 MN	161	xhci->quirks \|= XHCI_PME_STUCK_QUIRK;
b8cb91e0 MN	162	}
7e70cbff LB	163	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	164	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
	165	xhci->quirks \|= XHCI_SSIC_PORT_UNUSED;
	166	}
c877b3b2	167	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9	168	pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2	169	xhci->quirks \|= XHCI_RESET_ON_RESUME;
5cb7df2b	170	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
8f873c1f	171	xhci->quirks \|= XHCI_BROKEN_STREAMS;
c877b3b2	172	}
1aa9578c	173	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb	174	pdev->device == 0x0015)
1aa9578c	175	xhci->quirks \|= XHCI_RESET_ON_RESUME;
457a4f61 EF	176	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	177	xhci->quirks \|= XHCI_RESET_ON_RESUME;
85f4e45b	178
e21eba05 HG	179	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	180	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
	181	pdev->device == 0x3432)
	182	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	183
2391eacb HG	184	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	185	pdev->device == 0x1042)
	186	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	187
85f4e45b ON	188	if (xhci->quirks & XHCI_RESET_ON_RESUME)
	189	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	190	"QUIRK: Resetting on resume");
da3c9c4f	191	}
c41136b0	192
c3c5819a MN	193	#ifdef CONFIG_ACPI
	194	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
	195	{
	196	static const u8 intel_dsm_uuid[] = {
	197	0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
	198	0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
	199	};
84ed9152 MW	200	union acpi_object *obj;
	201
	202	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
	203	NULL);
	204	ACPI_FREE(obj);
c3c5819a MN	205	}
c3c5819a MN	206	#else
84ed9152	207	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
c3c5819a MN	208	#endif /* CONFIG_ACPI */
c3c5819a MN	209
da3c9c4f SAS	210	/* called during probe() after chip reset completes */
	211	static int xhci_pci_setup(struct usb_hcd *hcd)
	212	{
	213	struct xhci_hcd *xhci;
	214	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	215	int retval;
66d4eadd	216
b50107bb MN	217	xhci = hcd_to_xhci(hcd);
	218	if (!xhci->sbrn)
	219	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	220
da3c9c4f	221	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	222	if (retval)
da3c9c4f	223	return retval;
006d5820	224
da3c9c4f SAS	225	if (!usb_hcd_is_primary_hcd(hcd))
da3c9c4f SAS	226	return 0;
66d4eadd	227
66d4eadd SS	228	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	229
	230	/* Find any debug ports */
b02d0ed6 SS	231	retval = xhci_pci_reinit(xhci, pdev);
	232	if (!retval)
	233	return retval;
	234
b02d0ed6 SS	235	return retval;
	236	}
	237
f6ff0ac8 SS	238	/*
	239	* We need to register our own PCI probe function (instead of the USB core's
	240	* function) in order to create a second roothub under xHCI.
	241	*/
	242	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	243	{
	244	int retval;
	245	struct xhci_hcd *xhci;
	246	struct hc_driver *driver;
	247	struct usb_hcd *hcd;
	248
	249	driver = (struct hc_driver *)id->driver_data;
bcffae77 MN	250
	251	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	252	pm_runtime_get_noresume(&dev->dev);
	253
f6ff0ac8 SS	254	/* Register the USB 2.0 roothub.
	255	* FIXME: USB core must know to register the USB 2.0 roothub first.
	256	* This is sort of silly, because we could just set the HCD driver flags
	257	* to say USB 2.0, but I'm not sure what the implications would be in
	258	* the other parts of the HCD code.
	259	*/
	260	retval = usb_hcd_pci_probe(dev, id);
	261
	262	if (retval)
bcffae77	263	goto put_runtime_pm;
f6ff0ac8 SS	264
	265	/* USB 2.0 roothub is stored in the PCI device now. */
	266	hcd = dev_get_drvdata(&dev->dev);
	267	xhci = hcd_to_xhci(hcd);
	268	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	269	pci_name(dev), hcd);
	270	if (!xhci->shared_hcd) {
	271	retval = -ENOMEM;
	272	goto dealloc_usb2_hcd;
	273	}
	274
f6ff0ac8	275	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	276	IRQF_SHARED);
f6ff0ac8 SS	277	if (retval)
	278	goto put_usb3_hcd;
	279	/* Roothub already marked as USB 3.0 speed */
3b3db026	280
8f873c1f HG	281	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
8f873c1f HG	282	HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589 ON	283	xhci->shared_hcd->can_do_streams = 1;
14aec589 ON	284
c3c5819a MN	285	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
	286	xhci_pme_acpi_rtd3_enable(dev);
	287
bcffae77 MN	288	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	289	pm_runtime_put_noidle(&dev->dev);
	290
f6ff0ac8 SS	291	return 0;
	292
	293	put_usb3_hcd:
	294	usb_put_hcd(xhci->shared_hcd);
	295	dealloc_usb2_hcd:
	296	usb_hcd_pci_remove(dev);
bcffae77 MN	297	put_runtime_pm:
bcffae77 MN	298	pm_runtime_put_noidle(&dev->dev);
f6ff0ac8 SS	299	return retval;
	300	}
	301
b02d0ed6 SS	302	static void xhci_pci_remove(struct pci_dev *dev)
	303	{
	304	struct xhci_hcd *xhci;
	305
	306	xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8 SS	307	if (xhci->shared_hcd) {
	308	usb_remove_hcd(xhci->shared_hcd);
	309	usb_put_hcd(xhci->shared_hcd);
	310	}
b02d0ed6	311	usb_hcd_pci_remove(dev);
638298dc TI	312
	313	/* Workaround for spurious wakeups at shutdown with HSW */
	314	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
	315	pci_set_power_state(dev, PCI_D3hot);
66d4eadd SS	316	}
66d4eadd SS	317
5535b1d5	318	#ifdef CONFIG_PM
2b7627b7 TB	319	/*
	320	* In some Intel xHCI controllers, in order to get D3 working,
	321	* through a vendor specific SSIC CONFIG register at offset 0x883c,
	322	* SSIC PORT need to be marked as "unused" before putting xHCI
	323	* into D3. After D3 exit, the SSIC port need to be marked as "used".
	324	* Without this change, xHCI might not enter D3 state.
2b7627b7	325	*/
7e70cbff	326	static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
2b7627b7 TB	327	{
2b7627b7 TB	328	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2b7627b7 TB	329	u32 val;
2b7627b7 TB	330	void __iomem *reg;
fa895377	331	int i;
2b7627b7	332
7e70cbff LB	333	for (i = 0; i < SSIC_PORT_NUM; i++) {
	334	reg = (void __iomem *) xhci->cap_regs +
	335	SSIC_PORT_CFG2 +
	336	i * SSIC_PORT_CFG2_OFFSET;
	337
	338	/* Notify SSIC that SSIC profile programming is not done. */
	339	val = readl(reg) & ~PROG_DONE;
	340	writel(val, reg);
	341
	342	/* Mark SSIC port as unused(suspend) or used(resume) */
	343	val = readl(reg);
	344	if (suspend)
	345	val \|= SSIC_PORT_UNUSED;
	346	else
	347	val &= ~SSIC_PORT_UNUSED;
	348	writel(val, reg);
	349
	350	/* Notify SSIC that SSIC profile programming is done */
	351	val = readl(reg) \| PROG_DONE;
	352	writel(val, reg);
	353	readl(reg);
2b7627b7	354	}
7e70cbff LB	355	}
	356
	357	/*
	358	* Make sure PME works on some Intel xHCI controllers by writing 1 to clear
	359	* the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
	360	*/
	361	static void xhci_pme_quirk(struct usb_hcd *hcd)
	362	{
	363	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	364	void __iomem *reg;
	365	u32 val;
2b7627b7 TB	366
	367	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	368	val = readl(reg);
	369	writel(val \| BIT(28), reg);
	370	readl(reg);
	371	}
	372
5535b1d5 AX	373	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	374	{
	375	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5	376	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
92149c93	377	int ret;
c3897aa5 SS	378
	379	/*
	380	* Systems with the TI redriver that loses port status change events
	381	* need to have the registers polled during D3, so avoid D3cold.
	382	*/
e1cd9727	383	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
c3897aa5	384	pdev->no_d3cold = true;
5535b1d5	385
b8cb91e0	386	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff LB	387	xhci_pme_quirk(hcd);
	388
	389	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
	390	xhci_ssic_port_unused_quirk(hcd, true);
b8cb91e0	391
92149c93 LB	392	ret = xhci_suspend(xhci, do_wakeup);
	393	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
	394	xhci_ssic_port_unused_quirk(hcd, false);
	395
	396	return ret;
5535b1d5 AX	397	}
	398
	399	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	400	{
	401	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	402	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	403	int retval = 0;
5535b1d5 AX	404
69e848c2 SS	405	/* The BIOS on systems with the Intel Panther Point chipset may or may
	406	* not support xHCI natively. That means that during system resume, it
	407	* may switch the ports back to EHCI so that users can use their
	408	* keyboard to select a kernel from GRUB after resume from hibernate.
	409	*
	410	* The BIOS is supposed to remember whether the OS had xHCI ports
	411	* enabled before resume, and switch the ports back to xHCI when the
	412	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	413	* writers.
	414	*
	415	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	416	* It should not matter whether the EHCI or xHCI controller is
	417	* resumed first. It's enough to do the switchover in xHCI because
	418	* USB core won't notice anything as the hub driver doesn't start
	419	* running again until after all the devices (including both EHCI and
	420	* xHCI host controllers) have been resumed.
69e848c2	421	*/
26b76798 MN	422
	423	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	424	usb_enable_intel_xhci_ports(pdev);
69e848c2	425
7e70cbff LB	426	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
	427	xhci_ssic_port_unused_quirk(hcd, false);
	428
b8cb91e0	429	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff	430	xhci_pme_quirk(hcd);
b8cb91e0	431
5535b1d5 AX	432	retval = xhci_resume(xhci, hibernated);
	433	return retval;
	434	}
	435	#endif /* CONFIG_PM */
	436
66d4eadd SS	437	/-------------------------------------------------------------------------/
	438
	439	/* PCI driver selection metadata; PCI hotplugging uses this */
	440	static const struct pci_device_id pci_ids[] = { {
	441	/* handle any USB 3.0 xHCI controller */
	442	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	443	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	444	},
	445	{ /* end: all zeroes */ }
	446	};
	447	MODULE_DEVICE_TABLE(pci, pci_ids);
	448
	449	/* pci driver glue; this is a "new style" PCI driver module */
	450	static struct pci_driver xhci_pci_driver = {
	451	.name = (char *) hcd_name,
	452	.id_table = pci_ids,
	453
f6ff0ac8	454	.probe = xhci_pci_probe,
b02d0ed6	455	.remove = xhci_pci_remove,
66d4eadd SS	456	/* suspend and resume implemented later */
	457
	458	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	459	#ifdef CONFIG_PM
5535b1d5 AX	460	.driver = {
	461	.pm = &usb_hcd_pci_pm_ops
	462	},
	463	#endif
66d4eadd SS	464	};
66d4eadd SS	465
29e409f0	466	static int __init xhci_pci_init(void)
66d4eadd	467	{
cd33a321	468	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1885d9a3 AB	469	#ifdef CONFIG_PM
	470	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	471	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
	472	#endif
66d4eadd SS	473	return pci_register_driver(&xhci_pci_driver);
66d4eadd SS	474	}
29e409f0	475	module_init(xhci_pci_init);
66d4eadd	476
29e409f0	477	static void __exit xhci_pci_exit(void)
66d4eadd SS	478	{
	479	pci_unregister_driver(&xhci_pci_driver);
	480	}
29e409f0 AB	481	module_exit(xhci_pci_exit);
	482
	483	MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
	484	MODULE_LICENSE("GPL");