[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/acpi.h>

#include "xhci.h"
#include "xhci-trace.h"

#define PORT2_SSIC_CONFIG_REG2	0x883c
#define PROG_DONE		(1 << 30)
#define SSIC_PORT_UNUSED	(1 << 31)

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_EJ168		0x7023

#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI		0x22b5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI		0xa12f
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI	0x9d2f

static const char hcd_name[] = "xhci_hcd";

static struct hc_driver __read_mostly xhci_pci_hc_driver;

static int xhci_pci_setup(struct usb_hcd *hcd);

static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
	.extra_priv_size = sizeof(struct xhci_hcd),
	.reset = xhci_pci_setup,
};

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x4) {
			xhci->quirks |= XHCI_SLOW_SUSPEND;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC revision %u"
				"must be suspended extra slowly",
				pdev->revision);
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
			xhci->quirks |= XHCI_BROKEN_STREAMS;
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;

	if (pdev->vendor == PCI_VENDOR_ID_AMD)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
		xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) {
		xhci->quirks |= XHCI_PME_STUCK_QUIRK;
	}
	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_EJ168) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	}
	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
			pdev->device == 0x0015)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;

	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
			pdev->device == 0x3432)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
			pdev->device == 0x1042)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (xhci->quirks & XHCI_RESET_ON_RESUME)
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
}

#ifdef CONFIG_ACPI
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
{
	static const u8 intel_dsm_uuid[] = {
		0xb7, 0x0c, 0x34, 0xac,	0x01, 0xe9, 0xbf, 0x45,
		0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
	};
	acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, NULL);
}
#else
	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	xhci = hcd_to_xhci(hcd);
	if (!xhci->sbrn)
		pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	retval = xhci_pci_reinit(xhci, pdev);
	if (!retval)
		return retval;

	return retval;
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;

	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	pm_runtime_get_noresume(&dev->dev);

	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		goto put_runtime_pm;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
			HCC_MAX_PSA(xhci->hcc_params) >= 4)
		xhci->shared_hcd->can_do_streams = 1;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_acpi_rtd3_enable(dev);

	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	pm_runtime_put_noidle(&dev->dev);

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
put_runtime_pm:
	pm_runtime_put_noidle(&dev->dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}
	usb_hcd_pci_remove(dev);

	/* Workaround for spurious wakeups at shutdown with HSW */
	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
		pci_set_power_state(dev, PCI_D3hot);
}

#ifdef CONFIG_PM
/*
 * In some Intel xHCI controllers, in order to get D3 working,
 * through a vendor specific SSIC CONFIG register at offset 0x883c,
 * SSIC PORT need to be marked as "unused" before putting xHCI
 * into D3. After D3 exit, the SSIC port need to be marked as "used".
 * Without this change, xHCI might not enter D3 state.
 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 */
static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	u32 val;
	void __iomem *reg;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {

		reg = (void __iomem *) xhci->cap_regs + PORT2_SSIC_CONFIG_REG2;

		/* Notify SSIC that SSIC profile programming is not done */
		val = readl(reg) & ~PROG_DONE;
		writel(val, reg);

		/* Mark SSIC port as unused(suspend) or used(resume) */
		val = readl(reg);
		if (suspend)
			val |= SSIC_PORT_UNUSED;
		else
			val &= ~SSIC_PORT_UNUSED;
		writel(val, reg);

		/* Notify SSIC that SSIC profile programming is done */
		val = readl(reg) | PROG_DONE;
		writel(val, reg);
		readl(reg);
	}

	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	val = readl(reg);
	writel(val | BIT(28), reg);
	readl(reg);
}

static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
		pdev->no_d3cold = true;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd, true);

	return xhci_suspend(xhci, do_wakeup);
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd, false);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

static int __init xhci_pci_init(void)
{
	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
#ifdef CONFIG_PM
	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
#endif
	return pci_register_driver(&xhci_pci_driver);
}
module_init(xhci_pci_init);

static void __exit xhci_pci_exit(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
module_exit(xhci_pci_exit);

MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
c3c5819a	26	#include <linux/acpi.h>
66d4eadd SS	27
66d4eadd SS	28	#include "xhci.h"
4bdfe4c3	29	#include "xhci-trace.h"
66d4eadd	30
abce329c RM	31	#define PORT2_SSIC_CONFIG_REG2 0x883c
	32	#define PROG_DONE (1 << 30)
	33	#define SSIC_PORT_UNUSED (1 << 31)
	34
ac9d8fe7 SS	35	/* Device for a quirk */
	36	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	37	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
bba18e33	38	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	39
c877b3b2	40	#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9	41	#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2	42
638298dc TI	43	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
638298dc TI	44	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
b8cb91e0 MN	45	#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
	46	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
	47	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
638298dc	48
66d4eadd SS	49	static const char hcd_name[] = "xhci_hcd";
66d4eadd SS	50
1885d9a3 AB	51	static struct hc_driver __read_mostly xhci_pci_hc_driver;
1885d9a3 AB	52
cd33a321 RQ	53	static int xhci_pci_setup(struct usb_hcd *hcd);
	54
	55	static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
	56	.extra_priv_size = sizeof(struct xhci_hcd),
	57	.reset = xhci_pci_setup,
	58	};
	59
66d4eadd SS	60	/* called after powerup, by probe or system-pm "wakeup" */
	61	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	62	{
	63	/*
	64	* TODO: Implement finding debug ports later.
	65	* TODO: see if there are any quirks that need to be added to handle
	66	* new extended capabilities.
	67	*/
	68
	69	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	70	if (!pci_set_mwi(pdev))
	71	xhci_dbg(xhci, "MWI active\n");
	72
	73	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	74	return 0;
	75	}
	76
da3c9c4f SAS	77	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	78	{
	79	struct pci_dev *pdev = to_pci_dev(dev);
	80
ac9d8fe7 SS	81	/* Look for vendor-specific quirks */
ac9d8fe7 SS	82	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	83	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	84	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	85	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	86	pdev->revision == 0x0) {
ac9d8fe7	87	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	88	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	89	"QUIRK: Fresco Logic xHC needs configure"
	90	" endpoint cmd after reset endpoint");
f5182b41	91	}
455f5892 ON	92	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	93	pdev->revision == 0x4) {
	94	xhci->quirks \|= XHCI_SLOW_SUSPEND;
	95	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	96	"QUIRK: Fresco Logic xHC revision %u"
	97	"must be suspended extra slowly",
	98	pdev->revision);
	99	}
7f5c4d63 HG	100	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
7f5c4d63 HG	101	xhci->quirks \|= XHCI_BROKEN_STREAMS;
f5182b41 SS	102	/* Fresco Logic confirms: all revisions of this chip do not
	103	* support MSI, even though some of them claim to in their PCI
	104	* capabilities.
	105	*/
	106	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	107	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	108	"QUIRK: Fresco Logic revision %u "
	109	"has broken MSI implementation",
f5182b41	110	pdev->revision);
1530bbc6	111	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	112	}
f5182b41	113
0238634d SS	114	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	115	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	116
7e393a83 AX	117	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	118	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	119
c41136b0 AX	120	/* AMD PLL quirk */
	121	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	122	xhci->quirks \|= XHCI_AMD_PLL_FIX;
2597fe99 HR	123
	124	if (pdev->vendor == PCI_VENDOR_ID_AMD)
	125	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
	126
e3567d2c SS	127	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	128	xhci->quirks \|= XHCI_LPM_SUPPORT;
	129	xhci->quirks \|= XHCI_INTEL_HOST;
227a4fd8	130	xhci->quirks \|= XHCI_AVOID_BEI;
e3567d2c	131	}
ad808333 SS	132	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	133	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	134	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	135	xhci->limit_active_eps = 64;
86cc558e	136	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	137	/*
	138	* PPT desktop boards DH77EB and DH77DF will power back on after
	139	* a few seconds of being shutdown. The fix for this is to
	140	* switch the ports from xHCI to EHCI on shutdown. We can't use
	141	* DMI information to find those particular boards (since each
	142	* vendor will change the board name), so we have to key off all
	143	* PPT chipsets.
	144	*/
	145	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
ad808333	146	}
0a939993 DT	147	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0a939993 DT	148	pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
c09ec25d	149	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
fd7cd061	150	xhci->quirks \|= XHCI_SPURIOUS_WAKEUP;
638298dc	151	}
b8cb91e0 MN	152	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	153	(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI \|\|
	154	pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI \|\|
	155	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) {
	156	xhci->quirks \|= XHCI_PME_STUCK_QUIRK;
	157	}
c877b3b2	158	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9	159	pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2	160	xhci->quirks \|= XHCI_RESET_ON_RESUME;
5cb7df2b	161	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
8f873c1f	162	xhci->quirks \|= XHCI_BROKEN_STREAMS;
c877b3b2	163	}
1aa9578c	164	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb	165	pdev->device == 0x0015)
1aa9578c	166	xhci->quirks \|= XHCI_RESET_ON_RESUME;
457a4f61 EF	167	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	168	xhci->quirks \|= XHCI_RESET_ON_RESUME;
85f4e45b	169
e21eba05 HG	170	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	171	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
	172	pdev->device == 0x3432)
	173	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	174
2391eacb HG	175	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	176	pdev->device == 0x1042)
	177	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	178
85f4e45b ON	179	if (xhci->quirks & XHCI_RESET_ON_RESUME)
	180	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	181	"QUIRK: Resetting on resume");
da3c9c4f	182	}
c41136b0	183
c3c5819a MN	184	#ifdef CONFIG_ACPI
	185	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
	186	{
	187	static const u8 intel_dsm_uuid[] = {
	188	0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
	189	0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
	190	};
	191	acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, NULL);
	192	}
	193	#else
	194	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
	195	#endif /* CONFIG_ACPI */
	196
da3c9c4f SAS	197	/* called during probe() after chip reset completes */
	198	static int xhci_pci_setup(struct usb_hcd *hcd)
	199	{
	200	struct xhci_hcd *xhci;
	201	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	202	int retval;
66d4eadd	203
b50107bb MN	204	xhci = hcd_to_xhci(hcd);
	205	if (!xhci->sbrn)
	206	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	207
da3c9c4f	208	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	209	if (retval)
da3c9c4f	210	return retval;
006d5820	211
da3c9c4f SAS	212	if (!usb_hcd_is_primary_hcd(hcd))
da3c9c4f SAS	213	return 0;
66d4eadd	214
66d4eadd SS	215	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	216
	217	/* Find any debug ports */
b02d0ed6 SS	218	retval = xhci_pci_reinit(xhci, pdev);
	219	if (!retval)
	220	return retval;
	221
b02d0ed6 SS	222	return retval;
	223	}
	224
f6ff0ac8 SS	225	/*
	226	* We need to register our own PCI probe function (instead of the USB core's
	227	* function) in order to create a second roothub under xHCI.
	228	*/
	229	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	230	{
	231	int retval;
	232	struct xhci_hcd *xhci;
	233	struct hc_driver *driver;
	234	struct usb_hcd *hcd;
	235
	236	driver = (struct hc_driver *)id->driver_data;
bcffae77 MN	237
	238	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	239	pm_runtime_get_noresume(&dev->dev);
	240
f6ff0ac8 SS	241	/* Register the USB 2.0 roothub.
	242	* FIXME: USB core must know to register the USB 2.0 roothub first.
	243	* This is sort of silly, because we could just set the HCD driver flags
	244	* to say USB 2.0, but I'm not sure what the implications would be in
	245	* the other parts of the HCD code.
	246	*/
	247	retval = usb_hcd_pci_probe(dev, id);
	248
	249	if (retval)
bcffae77	250	goto put_runtime_pm;
f6ff0ac8 SS	251
	252	/* USB 2.0 roothub is stored in the PCI device now. */
	253	hcd = dev_get_drvdata(&dev->dev);
	254	xhci = hcd_to_xhci(hcd);
	255	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	256	pci_name(dev), hcd);
	257	if (!xhci->shared_hcd) {
	258	retval = -ENOMEM;
	259	goto dealloc_usb2_hcd;
	260	}
	261
f6ff0ac8	262	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	263	IRQF_SHARED);
f6ff0ac8 SS	264	if (retval)
	265	goto put_usb3_hcd;
	266	/* Roothub already marked as USB 3.0 speed */
3b3db026	267
8f873c1f HG	268	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
8f873c1f HG	269	HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589 ON	270	xhci->shared_hcd->can_do_streams = 1;
14aec589 ON	271
c3c5819a MN	272	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
	273	xhci_pme_acpi_rtd3_enable(dev);
	274
bcffae77 MN	275	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	276	pm_runtime_put_noidle(&dev->dev);
	277
f6ff0ac8 SS	278	return 0;
	279
	280	put_usb3_hcd:
	281	usb_put_hcd(xhci->shared_hcd);
	282	dealloc_usb2_hcd:
	283	usb_hcd_pci_remove(dev);
bcffae77 MN	284	put_runtime_pm:
bcffae77 MN	285	pm_runtime_put_noidle(&dev->dev);
f6ff0ac8 SS	286	return retval;
	287	}
	288
b02d0ed6 SS	289	static void xhci_pci_remove(struct pci_dev *dev)
	290	{
	291	struct xhci_hcd *xhci;
	292
	293	xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8 SS	294	if (xhci->shared_hcd) {
	295	usb_remove_hcd(xhci->shared_hcd);
	296	usb_put_hcd(xhci->shared_hcd);
	297	}
b02d0ed6	298	usb_hcd_pci_remove(dev);
638298dc TI	299
	300	/* Workaround for spurious wakeups at shutdown with HSW */
	301	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
	302	pci_set_power_state(dev, PCI_D3hot);
66d4eadd SS	303	}
66d4eadd SS	304
5535b1d5	305	#ifdef CONFIG_PM
2b7627b7 TB	306	/*
	307	* In some Intel xHCI controllers, in order to get D3 working,
	308	* through a vendor specific SSIC CONFIG register at offset 0x883c,
	309	* SSIC PORT need to be marked as "unused" before putting xHCI
	310	* into D3. After D3 exit, the SSIC port need to be marked as "used".
	311	* Without this change, xHCI might not enter D3 state.
	312	* Make sure PME works on some Intel xHCI controllers by writing 1 to clear
	313	* the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
	314	*/
	315	static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)
	316	{
	317	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	318	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	319	u32 val;
	320	void __iomem *reg;
	321
	322	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	323	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
	324
	325	reg = (void __iomem *) xhci->cap_regs + PORT2_SSIC_CONFIG_REG2;
	326
	327	/* Notify SSIC that SSIC profile programming is not done */
	328	val = readl(reg) & ~PROG_DONE;
	329	writel(val, reg);
	330
	331	/* Mark SSIC port as unused(suspend) or used(resume) */
	332	val = readl(reg);
	333	if (suspend)
	334	val \|= SSIC_PORT_UNUSED;
	335	else
	336	val &= ~SSIC_PORT_UNUSED;
	337	writel(val, reg);
	338
	339	/* Notify SSIC that SSIC profile programming is done */
	340	val = readl(reg) \| PROG_DONE;
	341	writel(val, reg);
	342	readl(reg);
	343	}
	344
	345	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	346	val = readl(reg);
	347	writel(val \| BIT(28), reg);
	348	readl(reg);
	349	}
	350
5535b1d5 AX	351	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	352	{
	353	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5 SS	354	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	355
	356	/*
	357	* Systems with the TI redriver that loses port status change events
	358	* need to have the registers polled during D3, so avoid D3cold.
	359	*/
e1cd9727	360	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
c3897aa5	361	pdev->no_d3cold = true;
5535b1d5	362
b8cb91e0	363	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
abce329c	364	xhci_pme_quirk(hcd, true);
b8cb91e0	365
a1377e53	366	return xhci_suspend(xhci, do_wakeup);
5535b1d5 AX	367	}
	368
	369	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	370	{
	371	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	372	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	373	int retval = 0;
5535b1d5 AX	374
69e848c2 SS	375	/* The BIOS on systems with the Intel Panther Point chipset may or may
	376	* not support xHCI natively. That means that during system resume, it
	377	* may switch the ports back to EHCI so that users can use their
	378	* keyboard to select a kernel from GRUB after resume from hibernate.
	379	*
	380	* The BIOS is supposed to remember whether the OS had xHCI ports
	381	* enabled before resume, and switch the ports back to xHCI when the
	382	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	383	* writers.
	384	*
	385	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	386	* It should not matter whether the EHCI or xHCI controller is
	387	* resumed first. It's enough to do the switchover in xHCI because
	388	* USB core won't notice anything as the hub driver doesn't start
	389	* running again until after all the devices (including both EHCI and
	390	* xHCI host controllers) have been resumed.
69e848c2	391	*/
26b76798 MN	392
	393	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	394	usb_enable_intel_xhci_ports(pdev);
69e848c2	395
b8cb91e0	396	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
abce329c	397	xhci_pme_quirk(hcd, false);
b8cb91e0	398
5535b1d5 AX	399	retval = xhci_resume(xhci, hibernated);
	400	return retval;
	401	}
	402	#endif /* CONFIG_PM */
	403
66d4eadd SS	404	/-------------------------------------------------------------------------/
	405
	406	/* PCI driver selection metadata; PCI hotplugging uses this */
	407	static const struct pci_device_id pci_ids[] = { {
	408	/* handle any USB 3.0 xHCI controller */
	409	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	410	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	411	},
	412	{ /* end: all zeroes */ }
	413	};
	414	MODULE_DEVICE_TABLE(pci, pci_ids);
	415
	416	/* pci driver glue; this is a "new style" PCI driver module */
	417	static struct pci_driver xhci_pci_driver = {
	418	.name = (char *) hcd_name,
	419	.id_table = pci_ids,
	420
f6ff0ac8	421	.probe = xhci_pci_probe,
b02d0ed6	422	.remove = xhci_pci_remove,
66d4eadd SS	423	/* suspend and resume implemented later */
	424
	425	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	426	#ifdef CONFIG_PM
5535b1d5 AX	427	.driver = {
	428	.pm = &usb_hcd_pci_pm_ops
	429	},
	430	#endif
66d4eadd SS	431	};
66d4eadd SS	432
29e409f0	433	static int __init xhci_pci_init(void)
66d4eadd	434	{
cd33a321	435	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1885d9a3 AB	436	#ifdef CONFIG_PM
	437	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	438	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
	439	#endif
66d4eadd SS	440	return pci_register_driver(&xhci_pci_driver);
66d4eadd SS	441	}
29e409f0	442	module_init(xhci_pci_init);
66d4eadd	443
29e409f0	444	static void __exit xhci_pci_exit(void)
66d4eadd SS	445	{
	446	pci_unregister_driver(&xhci_pci_driver);
	447	}
29e409f0 AB	448	module_exit(xhci_pci_exit);
	449
	450	MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
	451	MODULE_LICENSE("GPL");