Commit | Line | Data |
---|---|---|
66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver PCI Bus Glue. | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
7fc2a616 | 24 | #include <linux/slab.h> |
6eb0de82 | 25 | #include <linux/module.h> |
66d4eadd SS |
26 | |
27 | #include "xhci.h" | |
4bdfe4c3 | 28 | #include "xhci-trace.h" |
66d4eadd | 29 | |
ac9d8fe7 SS |
30 | /* Device for a quirk */ |
31 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
32 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
bba18e33 | 33 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
ac9d8fe7 | 34 | |
c877b3b2 ML |
35 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
36 | #define PCI_DEVICE_ID_ASROCK_P67 0x7023 | |
37 | ||
638298dc TI |
38 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 |
39 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 | |
40 | ||
66d4eadd SS |
41 | static const char hcd_name[] = "xhci_hcd"; |
42 | ||
43 | /* called after powerup, by probe or system-pm "wakeup" */ | |
44 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
45 | { | |
46 | /* | |
47 | * TODO: Implement finding debug ports later. | |
48 | * TODO: see if there are any quirks that need to be added to handle | |
49 | * new extended capabilities. | |
50 | */ | |
51 | ||
52 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
53 | if (!pci_set_mwi(pdev)) | |
54 | xhci_dbg(xhci, "MWI active\n"); | |
55 | ||
56 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
57 | return 0; | |
58 | } | |
59 | ||
da3c9c4f SAS |
60 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
61 | { | |
62 | struct pci_dev *pdev = to_pci_dev(dev); | |
63 | ||
ac9d8fe7 SS |
64 | /* Look for vendor-specific quirks */ |
65 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
bba18e33 SS |
66 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
67 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { | |
68 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | |
69 | pdev->revision == 0x0) { | |
ac9d8fe7 | 70 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
4bdfe4c3 XR |
71 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
72 | "QUIRK: Fresco Logic xHC needs configure" | |
73 | " endpoint cmd after reset endpoint"); | |
f5182b41 | 74 | } |
455f5892 ON |
75 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
76 | pdev->revision == 0x4) { | |
77 | xhci->quirks |= XHCI_SLOW_SUSPEND; | |
78 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
79 | "QUIRK: Fresco Logic xHC revision %u" | |
80 | "must be suspended extra slowly", | |
81 | pdev->revision); | |
82 | } | |
f5182b41 SS |
83 | /* Fresco Logic confirms: all revisions of this chip do not |
84 | * support MSI, even though some of them claim to in their PCI | |
85 | * capabilities. | |
86 | */ | |
87 | xhci->quirks |= XHCI_BROKEN_MSI; | |
4bdfe4c3 XR |
88 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
89 | "QUIRK: Fresco Logic revision %u " | |
90 | "has broken MSI implementation", | |
f5182b41 | 91 | pdev->revision); |
1530bbc6 | 92 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 93 | } |
f5182b41 | 94 | |
0238634d SS |
95 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
96 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 97 | |
7e393a83 AX |
98 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
99 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
100 | ||
c41136b0 AX |
101 | /* AMD PLL quirk */ |
102 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | |
103 | xhci->quirks |= XHCI_AMD_PLL_FIX; | |
e3567d2c SS |
104 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
105 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
106 | xhci->quirks |= XHCI_INTEL_HOST; | |
107 | } | |
ad808333 SS |
108 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
109 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
2cf95c18 SS |
110 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
111 | xhci->limit_active_eps = 64; | |
86cc558e | 112 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
e95829f4 SS |
113 | /* |
114 | * PPT desktop boards DH77EB and DH77DF will power back on after | |
115 | * a few seconds of being shutdown. The fix for this is to | |
116 | * switch the ports from xHCI to EHCI on shutdown. We can't use | |
117 | * DMI information to find those particular boards (since each | |
118 | * vendor will change the board name), so we have to key off all | |
119 | * PPT chipsets. | |
120 | */ | |
121 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
80fab3b2 | 122 | xhci->quirks |= XHCI_AVOID_BEI; |
ad808333 | 123 | } |
638298dc TI |
124 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
125 | (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI || | |
126 | pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) { | |
127 | /* Workaround for occasional spurious wakeups from S5 (or | |
128 | * any other sleep) on Haswell machines with LPT and LPT-LP | |
129 | * with the new Intel BIOS | |
130 | */ | |
6962d914 TI |
131 | /* Limit the quirk to only known vendors, as this triggers |
132 | * yet another BIOS bug on some other machines | |
133 | * https://bugzilla.kernel.org/show_bug.cgi?id=66171 | |
134 | */ | |
135 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) | |
136 | xhci->quirks |= XHCI_SPURIOUS_WAKEUP; | |
c09ec25d DT |
137 | |
138 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
638298dc | 139 | } |
c877b3b2 ML |
140 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
141 | pdev->device == PCI_DEVICE_ID_ASROCK_P67) { | |
142 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
4bdfe4c3 XR |
143 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
144 | "QUIRK: Resetting on resume"); | |
5cb7df2b | 145 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
c877b3b2 | 146 | } |
1aa9578c | 147 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
6db249eb | 148 | pdev->device == 0x0015) |
1aa9578c | 149 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
457a4f61 EF |
150 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
151 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
da3c9c4f | 152 | } |
c41136b0 | 153 | |
da3c9c4f SAS |
154 | /* called during probe() after chip reset completes */ |
155 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
156 | { | |
157 | struct xhci_hcd *xhci; | |
158 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
159 | int retval; | |
66d4eadd | 160 | |
da3c9c4f | 161 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 162 | if (retval) |
da3c9c4f | 163 | return retval; |
006d5820 | 164 | |
da3c9c4f SAS |
165 | xhci = hcd_to_xhci(hcd); |
166 | if (!usb_hcd_is_primary_hcd(hcd)) | |
167 | return 0; | |
66d4eadd SS |
168 | |
169 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
170 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); | |
171 | ||
172 | /* Find any debug ports */ | |
b02d0ed6 SS |
173 | retval = xhci_pci_reinit(xhci, pdev); |
174 | if (!retval) | |
175 | return retval; | |
176 | ||
b02d0ed6 SS |
177 | kfree(xhci); |
178 | return retval; | |
179 | } | |
180 | ||
f6ff0ac8 SS |
181 | /* |
182 | * We need to register our own PCI probe function (instead of the USB core's | |
183 | * function) in order to create a second roothub under xHCI. | |
184 | */ | |
185 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
186 | { | |
187 | int retval; | |
188 | struct xhci_hcd *xhci; | |
189 | struct hc_driver *driver; | |
190 | struct usb_hcd *hcd; | |
191 | ||
192 | driver = (struct hc_driver *)id->driver_data; | |
bcffae77 MN |
193 | |
194 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ | |
195 | pm_runtime_get_noresume(&dev->dev); | |
196 | ||
f6ff0ac8 SS |
197 | /* Register the USB 2.0 roothub. |
198 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
199 | * This is sort of silly, because we could just set the HCD driver flags | |
200 | * to say USB 2.0, but I'm not sure what the implications would be in | |
201 | * the other parts of the HCD code. | |
202 | */ | |
203 | retval = usb_hcd_pci_probe(dev, id); | |
204 | ||
205 | if (retval) | |
bcffae77 | 206 | goto put_runtime_pm; |
f6ff0ac8 SS |
207 | |
208 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
209 | hcd = dev_get_drvdata(&dev->dev); | |
210 | xhci = hcd_to_xhci(hcd); | |
211 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
212 | pci_name(dev), hcd); | |
213 | if (!xhci->shared_hcd) { | |
214 | retval = -ENOMEM; | |
215 | goto dealloc_usb2_hcd; | |
216 | } | |
217 | ||
218 | /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) | |
219 | * is called by usb_add_hcd(). | |
220 | */ | |
221 | *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; | |
222 | ||
223 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, | |
b5dd18d8 | 224 | IRQF_SHARED); |
f6ff0ac8 SS |
225 | if (retval) |
226 | goto put_usb3_hcd; | |
227 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 | 228 | |
14aec589 ON |
229 | if (HCC_MAX_PSA(xhci->hcc_params) >= 4) |
230 | xhci->shared_hcd->can_do_streams = 1; | |
231 | ||
bcffae77 MN |
232 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
233 | pm_runtime_put_noidle(&dev->dev); | |
234 | ||
f6ff0ac8 SS |
235 | return 0; |
236 | ||
237 | put_usb3_hcd: | |
238 | usb_put_hcd(xhci->shared_hcd); | |
239 | dealloc_usb2_hcd: | |
240 | usb_hcd_pci_remove(dev); | |
bcffae77 MN |
241 | put_runtime_pm: |
242 | pm_runtime_put_noidle(&dev->dev); | |
f6ff0ac8 SS |
243 | return retval; |
244 | } | |
245 | ||
b02d0ed6 SS |
246 | static void xhci_pci_remove(struct pci_dev *dev) |
247 | { | |
248 | struct xhci_hcd *xhci; | |
249 | ||
250 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
f6ff0ac8 SS |
251 | if (xhci->shared_hcd) { |
252 | usb_remove_hcd(xhci->shared_hcd); | |
253 | usb_put_hcd(xhci->shared_hcd); | |
254 | } | |
b02d0ed6 | 255 | usb_hcd_pci_remove(dev); |
638298dc TI |
256 | |
257 | /* Workaround for spurious wakeups at shutdown with HSW */ | |
258 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
259 | pci_set_power_state(dev, PCI_D3hot); | |
260 | ||
b02d0ed6 | 261 | kfree(xhci); |
66d4eadd SS |
262 | } |
263 | ||
5535b1d5 AX |
264 | #ifdef CONFIG_PM |
265 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | |
266 | { | |
267 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c3897aa5 SS |
268 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
269 | ||
270 | /* | |
271 | * Systems with the TI redriver that loses port status change events | |
272 | * need to have the registers polled during D3, so avoid D3cold. | |
273 | */ | |
274 | if (xhci_compliance_mode_recovery_timer_quirk_check()) | |
275 | pdev->no_d3cold = true; | |
5535b1d5 | 276 | |
77b84767 | 277 | return xhci_suspend(xhci); |
5535b1d5 AX |
278 | } |
279 | ||
280 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
281 | { | |
282 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 283 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
284 | int retval = 0; |
285 | ||
69e848c2 SS |
286 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
287 | * not support xHCI natively. That means that during system resume, it | |
288 | * may switch the ports back to EHCI so that users can use their | |
289 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
290 | * | |
291 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
292 | * enabled before resume, and switch the ports back to xHCI when the | |
293 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
294 | * writers. | |
295 | * | |
296 | * Unconditionally switch the ports back to xHCI after a system resume. | |
26b76798 MN |
297 | * It should not matter whether the EHCI or xHCI controller is |
298 | * resumed first. It's enough to do the switchover in xHCI because | |
299 | * USB core won't notice anything as the hub driver doesn't start | |
300 | * running again until after all the devices (including both EHCI and | |
301 | * xHCI host controllers) have been resumed. | |
69e848c2 | 302 | */ |
26b76798 MN |
303 | |
304 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
305 | usb_enable_intel_xhci_ports(pdev); | |
69e848c2 | 306 | |
5535b1d5 AX |
307 | retval = xhci_resume(xhci, hibernated); |
308 | return retval; | |
309 | } | |
310 | #endif /* CONFIG_PM */ | |
311 | ||
66d4eadd SS |
312 | static const struct hc_driver xhci_pci_hc_driver = { |
313 | .description = hcd_name, | |
314 | .product_desc = "xHCI Host Controller", | |
b02d0ed6 | 315 | .hcd_priv_size = sizeof(struct xhci_hcd *), |
66d4eadd SS |
316 | |
317 | /* | |
318 | * generic hardware linkage | |
319 | */ | |
7f84eef0 | 320 | .irq = xhci_irq, |
f6ff0ac8 | 321 | .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, |
66d4eadd SS |
322 | |
323 | /* | |
324 | * basic lifecycle operations | |
325 | */ | |
326 | .reset = xhci_pci_setup, | |
327 | .start = xhci_run, | |
5535b1d5 AX |
328 | #ifdef CONFIG_PM |
329 | .pci_suspend = xhci_pci_suspend, | |
330 | .pci_resume = xhci_pci_resume, | |
331 | #endif | |
66d4eadd SS |
332 | .stop = xhci_stop, |
333 | .shutdown = xhci_shutdown, | |
334 | ||
3ffbba95 SS |
335 | /* |
336 | * managing i/o requests and associated device resources | |
337 | */ | |
d0e96f5a SS |
338 | .urb_enqueue = xhci_urb_enqueue, |
339 | .urb_dequeue = xhci_urb_dequeue, | |
3ffbba95 SS |
340 | .alloc_dev = xhci_alloc_dev, |
341 | .free_dev = xhci_free_dev, | |
eab1cafc SS |
342 | .alloc_streams = xhci_alloc_streams, |
343 | .free_streams = xhci_free_streams, | |
f94e0186 SS |
344 | .add_endpoint = xhci_add_endpoint, |
345 | .drop_endpoint = xhci_drop_endpoint, | |
a1587d97 | 346 | .endpoint_reset = xhci_endpoint_reset, |
f94e0186 SS |
347 | .check_bandwidth = xhci_check_bandwidth, |
348 | .reset_bandwidth = xhci_reset_bandwidth, | |
3ffbba95 | 349 | .address_device = xhci_address_device, |
48fc7dbd | 350 | .enable_device = xhci_enable_device, |
b356b7c7 | 351 | .update_hub_device = xhci_update_hub_device, |
f0615c45 | 352 | .reset_device = xhci_discover_or_reset_device, |
3ffbba95 | 353 | |
66d4eadd SS |
354 | /* |
355 | * scheduling support | |
356 | */ | |
357 | .get_frame_number = xhci_get_frame, | |
358 | ||
0f2a7930 SS |
359 | /* Root hub support */ |
360 | .hub_control = xhci_hub_control, | |
361 | .hub_status_data = xhci_hub_status_data, | |
9777e3ce AX |
362 | .bus_suspend = xhci_bus_suspend, |
363 | .bus_resume = xhci_bus_resume, | |
9574323c AX |
364 | /* |
365 | * call back when device connected and addressed | |
366 | */ | |
367 | .update_device = xhci_update_device, | |
65580b43 | 368 | .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, |
3b3db026 SS |
369 | .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, |
370 | .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, | |
3f5eb141 | 371 | .find_raw_port_number = xhci_find_raw_port_number, |
66d4eadd SS |
372 | }; |
373 | ||
374 | /*-------------------------------------------------------------------------*/ | |
375 | ||
376 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
377 | static const struct pci_device_id pci_ids[] = { { | |
378 | /* handle any USB 3.0 xHCI controller */ | |
379 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
380 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
381 | }, | |
382 | { /* end: all zeroes */ } | |
383 | }; | |
384 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
385 | ||
386 | /* pci driver glue; this is a "new style" PCI driver module */ | |
387 | static struct pci_driver xhci_pci_driver = { | |
388 | .name = (char *) hcd_name, | |
389 | .id_table = pci_ids, | |
390 | ||
f6ff0ac8 | 391 | .probe = xhci_pci_probe, |
b02d0ed6 | 392 | .remove = xhci_pci_remove, |
66d4eadd SS |
393 | /* suspend and resume implemented later */ |
394 | ||
395 | .shutdown = usb_hcd_pci_shutdown, | |
f875fdbf | 396 | #ifdef CONFIG_PM |
5535b1d5 AX |
397 | .driver = { |
398 | .pm = &usb_hcd_pci_pm_ops | |
399 | }, | |
400 | #endif | |
66d4eadd SS |
401 | }; |
402 | ||
0cc47d54 | 403 | int __init xhci_register_pci(void) |
66d4eadd SS |
404 | { |
405 | return pci_register_driver(&xhci_pci_driver); | |
406 | } | |
407 | ||
a46c46a1 | 408 | void xhci_unregister_pci(void) |
66d4eadd SS |
409 | { |
410 | pci_unregister_driver(&xhci_pci_driver); | |
411 | } |