[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/acpi.h>

#include "xhci.h"
#include "xhci-trace.h"

#define SSIC_PORT_NUM		2
#define SSIC_PORT_CFG2		0x880c
#define SSIC_PORT_CFG2_OFFSET	0x30
#define PROG_DONE		(1 << 30)
#define SSIC_PORT_UNUSED	(1 << 31)

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_EJ168		0x7023

#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI		0x22b5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI		0xa12f
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI	0x9d2f
#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI		0x0aa8

static const char hcd_name[] = "xhci_hcd";

static struct hc_driver __read_mostly xhci_pci_hc_driver;

static int xhci_pci_setup(struct usb_hcd *hcd);

static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
	.reset = xhci_pci_setup,
};

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x4) {
			xhci->quirks |= XHCI_SLOW_SUSPEND;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC revision %u"
				"must be suspended extra slowly",
				pdev->revision);
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
			xhci->quirks |= XHCI_BROKEN_STREAMS;
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;

	if (pdev->vendor == PCI_VENDOR_ID_AMD)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
		xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI)) {
		xhci->quirks |= XHCI_PME_STUCK_QUIRK;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
		xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
	}
	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_EJ168) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	}
	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
			pdev->device == 0x0015)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;

	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
			pdev->device == 0x3432)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
			pdev->device == 0x1042)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (xhci->quirks & XHCI_RESET_ON_RESUME)
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
}

#ifdef CONFIG_ACPI
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
{
	static const u8 intel_dsm_uuid[] = {
		0xb7, 0x0c, 0x34, 0xac,	0x01, 0xe9, 0xbf, 0x45,
		0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
	};
	union acpi_object *obj;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
				NULL);
	ACPI_FREE(obj);
}
#else
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	xhci = hcd_to_xhci(hcd);
	if (!xhci->sbrn)
		pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	retval = xhci_pci_reinit(xhci, pdev);
	if (!retval)
		return retval;

	return retval;
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;

	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	pm_runtime_get_noresume(&dev->dev);

	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		goto put_runtime_pm;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
			HCC_MAX_PSA(xhci->hcc_params) >= 4)
		xhci->shared_hcd->can_do_streams = 1;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_acpi_rtd3_enable(dev);

	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	pm_runtime_put_noidle(&dev->dev);

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
put_runtime_pm:
	pm_runtime_put_noidle(&dev->dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}
	usb_hcd_pci_remove(dev);

	/* Workaround for spurious wakeups at shutdown with HSW */
	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
		pci_set_power_state(dev, PCI_D3hot);
}

#ifdef CONFIG_PM
/*
 * In some Intel xHCI controllers, in order to get D3 working,
 * through a vendor specific SSIC CONFIG register at offset 0x883c,
 * SSIC PORT need to be marked as "unused" before putting xHCI
 * into D3. After D3 exit, the SSIC port need to be marked as "used".
 * Without this change, xHCI might not enter D3 state.
 */
static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	u32 val;
	void __iomem *reg;
	int i;

	for (i = 0; i < SSIC_PORT_NUM; i++) {
		reg = (void __iomem *) xhci->cap_regs +
				SSIC_PORT_CFG2 +
				i * SSIC_PORT_CFG2_OFFSET;

		/* Notify SSIC that SSIC profile programming is not done. */
		val = readl(reg) & ~PROG_DONE;
		writel(val, reg);

		/* Mark SSIC port as unused(suspend) or used(resume) */
		val = readl(reg);
		if (suspend)
			val |= SSIC_PORT_UNUSED;
		else
			val &= ~SSIC_PORT_UNUSED;
		writel(val, reg);

		/* Notify SSIC that SSIC profile programming is done */
		val = readl(reg) | PROG_DONE;
		writel(val, reg);
		readl(reg);
	}
}

/*
 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 */
static void xhci_pme_quirk(struct usb_hcd *hcd)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	void __iomem *reg;
	u32 val;

	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	val = readl(reg);
	writel(val | BIT(28), reg);
	readl(reg);
}

static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			ret;

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
		pdev->no_d3cold = true;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd);

	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
		xhci_ssic_port_unused_quirk(hcd, true);

	ret = xhci_suspend(xhci, do_wakeup);
	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
		xhci_ssic_port_unused_quirk(hcd, false);

	return ret;
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
		xhci_ssic_port_unused_quirk(hcd, false);

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

static int __init xhci_pci_init(void)
{
	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
#ifdef CONFIG_PM
	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
#endif
	return pci_register_driver(&xhci_pci_driver);
}
module_init(xhci_pci_init);

static void __exit xhci_pci_exit(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
module_exit(xhci_pci_exit);

MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
c3c5819a	26	#include <linux/acpi.h>
66d4eadd SS	27
66d4eadd SS	28	#include "xhci.h"
4bdfe4c3	29	#include "xhci-trace.h"
66d4eadd	30
fa895377 LB	31	#define SSIC_PORT_NUM 2
	32	#define SSIC_PORT_CFG2 0x880c
	33	#define SSIC_PORT_CFG2_OFFSET 0x30
abce329c RM	34	#define PROG_DONE (1 << 30)
	35	#define SSIC_PORT_UNUSED (1 << 31)
	36
ac9d8fe7 SS	37	/* Device for a quirk */
	38	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	39	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
bba18e33	40	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	41
c877b3b2	42	#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9	43	#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2	44
638298dc TI	45	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
638298dc TI	46	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
b8cb91e0 MN	47	#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
	48	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
	49	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
ccc04afb	50	#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
638298dc	51
66d4eadd SS	52	static const char hcd_name[] = "xhci_hcd";
66d4eadd SS	53
1885d9a3 AB	54	static struct hc_driver __read_mostly xhci_pci_hc_driver;
1885d9a3 AB	55
cd33a321 RQ	56	static int xhci_pci_setup(struct usb_hcd *hcd);
	57
	58	static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
cd33a321 RQ	59	.reset = xhci_pci_setup,
	60	};
	61
66d4eadd SS	62	/* called after powerup, by probe or system-pm "wakeup" */
	63	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	64	{
	65	/*
	66	* TODO: Implement finding debug ports later.
	67	* TODO: see if there are any quirks that need to be added to handle
	68	* new extended capabilities.
	69	*/
	70
	71	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	72	if (!pci_set_mwi(pdev))
	73	xhci_dbg(xhci, "MWI active\n");
	74
	75	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	76	return 0;
	77	}
	78
da3c9c4f SAS	79	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	80	{
	81	struct pci_dev *pdev = to_pci_dev(dev);
	82
ac9d8fe7 SS	83	/* Look for vendor-specific quirks */
ac9d8fe7 SS	84	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	85	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	86	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	87	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	88	pdev->revision == 0x0) {
ac9d8fe7	89	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	90	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	91	"QUIRK: Fresco Logic xHC needs configure"
	92	" endpoint cmd after reset endpoint");
f5182b41	93	}
455f5892 ON	94	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	95	pdev->revision == 0x4) {
	96	xhci->quirks \|= XHCI_SLOW_SUSPEND;
	97	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	98	"QUIRK: Fresco Logic xHC revision %u"
	99	"must be suspended extra slowly",
	100	pdev->revision);
	101	}
7f5c4d63 HG	102	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
7f5c4d63 HG	103	xhci->quirks \|= XHCI_BROKEN_STREAMS;
f5182b41 SS	104	/* Fresco Logic confirms: all revisions of this chip do not
	105	* support MSI, even though some of them claim to in their PCI
	106	* capabilities.
	107	*/
	108	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	109	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	110	"QUIRK: Fresco Logic revision %u "
	111	"has broken MSI implementation",
f5182b41	112	pdev->revision);
1530bbc6	113	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	114	}
f5182b41	115
0238634d SS	116	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	117	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	118
7e393a83 AX	119	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	120	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	121
c41136b0 AX	122	/* AMD PLL quirk */
	123	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	124	xhci->quirks \|= XHCI_AMD_PLL_FIX;
2597fe99 HR	125
	126	if (pdev->vendor == PCI_VENDOR_ID_AMD)
	127	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
	128
e3567d2c SS	129	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	130	xhci->quirks \|= XHCI_LPM_SUPPORT;
	131	xhci->quirks \|= XHCI_INTEL_HOST;
227a4fd8	132	xhci->quirks \|= XHCI_AVOID_BEI;
e3567d2c	133	}
ad808333 SS	134	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	135	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	136	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	137	xhci->limit_active_eps = 64;
86cc558e	138	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	139	/*
	140	* PPT desktop boards DH77EB and DH77DF will power back on after
	141	* a few seconds of being shutdown. The fix for this is to
	142	* switch the ports from xHCI to EHCI on shutdown. We can't use
	143	* DMI information to find those particular boards (since each
	144	* vendor will change the board name), so we have to key off all
	145	* PPT chipsets.
	146	*/
	147	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
ad808333	148	}
0a939993 DT	149	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
0a939993 DT	150	pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
c09ec25d	151	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
fd7cd061	152	xhci->quirks \|= XHCI_SPURIOUS_WAKEUP;
638298dc	153	}
b8cb91e0 MN	154	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	155	(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI \|\|
	156	pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI \|\|
ccc04afb LB	157	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI \|\|
ccc04afb LB	158	pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI)) {
b8cb91e0 MN	159	xhci->quirks \|= XHCI_PME_STUCK_QUIRK;
b8cb91e0 MN	160	}
7e70cbff LB	161	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	162	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
	163	xhci->quirks \|= XHCI_SSIC_PORT_UNUSED;
	164	}
c877b3b2	165	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9	166	pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2	167	xhci->quirks \|= XHCI_RESET_ON_RESUME;
5cb7df2b	168	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
8f873c1f	169	xhci->quirks \|= XHCI_BROKEN_STREAMS;
c877b3b2	170	}
1aa9578c	171	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb	172	pdev->device == 0x0015)
1aa9578c	173	xhci->quirks \|= XHCI_RESET_ON_RESUME;
457a4f61 EF	174	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	175	xhci->quirks \|= XHCI_RESET_ON_RESUME;
85f4e45b	176
e21eba05 HG	177	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	178	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
	179	pdev->device == 0x3432)
	180	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	181
2391eacb HG	182	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	183	pdev->device == 0x1042)
	184	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	185
85f4e45b ON	186	if (xhci->quirks & XHCI_RESET_ON_RESUME)
	187	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	188	"QUIRK: Resetting on resume");
da3c9c4f	189	}
c41136b0	190
c3c5819a MN	191	#ifdef CONFIG_ACPI
	192	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
	193	{
	194	static const u8 intel_dsm_uuid[] = {
	195	0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
	196	0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
	197	};
84ed9152 MW	198	union acpi_object *obj;
	199
	200	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
	201	NULL);
	202	ACPI_FREE(obj);
c3c5819a MN	203	}
c3c5819a MN	204	#else
84ed9152	205	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
c3c5819a MN	206	#endif /* CONFIG_ACPI */
c3c5819a MN	207
da3c9c4f SAS	208	/* called during probe() after chip reset completes */
	209	static int xhci_pci_setup(struct usb_hcd *hcd)
	210	{
	211	struct xhci_hcd *xhci;
	212	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	213	int retval;
66d4eadd	214
b50107bb MN	215	xhci = hcd_to_xhci(hcd);
	216	if (!xhci->sbrn)
	217	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	218
da3c9c4f	219	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	220	if (retval)
da3c9c4f	221	return retval;
006d5820	222
da3c9c4f SAS	223	if (!usb_hcd_is_primary_hcd(hcd))
da3c9c4f SAS	224	return 0;
66d4eadd	225
66d4eadd SS	226	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	227
	228	/* Find any debug ports */
b02d0ed6 SS	229	retval = xhci_pci_reinit(xhci, pdev);
	230	if (!retval)
	231	return retval;
	232
b02d0ed6 SS	233	return retval;
	234	}
	235
f6ff0ac8 SS	236	/*
	237	* We need to register our own PCI probe function (instead of the USB core's
	238	* function) in order to create a second roothub under xHCI.
	239	*/
	240	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	241	{
	242	int retval;
	243	struct xhci_hcd *xhci;
	244	struct hc_driver *driver;
	245	struct usb_hcd *hcd;
	246
	247	driver = (struct hc_driver *)id->driver_data;
bcffae77 MN	248
	249	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	250	pm_runtime_get_noresume(&dev->dev);
	251
f6ff0ac8 SS	252	/* Register the USB 2.0 roothub.
	253	* FIXME: USB core must know to register the USB 2.0 roothub first.
	254	* This is sort of silly, because we could just set the HCD driver flags
	255	* to say USB 2.0, but I'm not sure what the implications would be in
	256	* the other parts of the HCD code.
	257	*/
	258	retval = usb_hcd_pci_probe(dev, id);
	259
	260	if (retval)
bcffae77	261	goto put_runtime_pm;
f6ff0ac8 SS	262
	263	/* USB 2.0 roothub is stored in the PCI device now. */
	264	hcd = dev_get_drvdata(&dev->dev);
	265	xhci = hcd_to_xhci(hcd);
	266	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	267	pci_name(dev), hcd);
	268	if (!xhci->shared_hcd) {
	269	retval = -ENOMEM;
	270	goto dealloc_usb2_hcd;
	271	}
	272
f6ff0ac8	273	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	274	IRQF_SHARED);
f6ff0ac8 SS	275	if (retval)
	276	goto put_usb3_hcd;
	277	/* Roothub already marked as USB 3.0 speed */
3b3db026	278
8f873c1f HG	279	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
8f873c1f HG	280	HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589 ON	281	xhci->shared_hcd->can_do_streams = 1;
14aec589 ON	282
c3c5819a MN	283	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
	284	xhci_pme_acpi_rtd3_enable(dev);
	285
bcffae77 MN	286	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	287	pm_runtime_put_noidle(&dev->dev);
	288
f6ff0ac8 SS	289	return 0;
	290
	291	put_usb3_hcd:
	292	usb_put_hcd(xhci->shared_hcd);
	293	dealloc_usb2_hcd:
	294	usb_hcd_pci_remove(dev);
bcffae77 MN	295	put_runtime_pm:
bcffae77 MN	296	pm_runtime_put_noidle(&dev->dev);
f6ff0ac8 SS	297	return retval;
	298	}
	299
b02d0ed6 SS	300	static void xhci_pci_remove(struct pci_dev *dev)
	301	{
	302	struct xhci_hcd *xhci;
	303
	304	xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8 SS	305	if (xhci->shared_hcd) {
	306	usb_remove_hcd(xhci->shared_hcd);
	307	usb_put_hcd(xhci->shared_hcd);
	308	}
b02d0ed6	309	usb_hcd_pci_remove(dev);
638298dc TI	310
	311	/* Workaround for spurious wakeups at shutdown with HSW */
	312	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
	313	pci_set_power_state(dev, PCI_D3hot);
66d4eadd SS	314	}
66d4eadd SS	315
5535b1d5	316	#ifdef CONFIG_PM
2b7627b7 TB	317	/*
	318	* In some Intel xHCI controllers, in order to get D3 working,
	319	* through a vendor specific SSIC CONFIG register at offset 0x883c,
	320	* SSIC PORT need to be marked as "unused" before putting xHCI
	321	* into D3. After D3 exit, the SSIC port need to be marked as "used".
	322	* Without this change, xHCI might not enter D3 state.
2b7627b7	323	*/
7e70cbff	324	static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
2b7627b7 TB	325	{
2b7627b7 TB	326	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2b7627b7 TB	327	u32 val;
2b7627b7 TB	328	void __iomem *reg;
fa895377	329	int i;
2b7627b7	330
7e70cbff LB	331	for (i = 0; i < SSIC_PORT_NUM; i++) {
	332	reg = (void __iomem *) xhci->cap_regs +
	333	SSIC_PORT_CFG2 +
	334	i * SSIC_PORT_CFG2_OFFSET;
	335
	336	/* Notify SSIC that SSIC profile programming is not done. */
	337	val = readl(reg) & ~PROG_DONE;
	338	writel(val, reg);
	339
	340	/* Mark SSIC port as unused(suspend) or used(resume) */
	341	val = readl(reg);
	342	if (suspend)
	343	val \|= SSIC_PORT_UNUSED;
	344	else
	345	val &= ~SSIC_PORT_UNUSED;
	346	writel(val, reg);
	347
	348	/* Notify SSIC that SSIC profile programming is done */
	349	val = readl(reg) \| PROG_DONE;
	350	writel(val, reg);
	351	readl(reg);
2b7627b7	352	}
7e70cbff LB	353	}
	354
	355	/*
	356	* Make sure PME works on some Intel xHCI controllers by writing 1 to clear
	357	* the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
	358	*/
	359	static void xhci_pme_quirk(struct usb_hcd *hcd)
	360	{
	361	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	362	void __iomem *reg;
	363	u32 val;
2b7627b7 TB	364
	365	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	366	val = readl(reg);
	367	writel(val \| BIT(28), reg);
	368	readl(reg);
	369	}
	370
5535b1d5 AX	371	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	372	{
	373	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5	374	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
92149c93	375	int ret;
c3897aa5 SS	376
	377	/*
	378	* Systems with the TI redriver that loses port status change events
	379	* need to have the registers polled during D3, so avoid D3cold.
	380	*/
e1cd9727	381	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
c3897aa5	382	pdev->no_d3cold = true;
5535b1d5	383
b8cb91e0	384	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff LB	385	xhci_pme_quirk(hcd);
	386
	387	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
	388	xhci_ssic_port_unused_quirk(hcd, true);
b8cb91e0	389
92149c93 LB	390	ret = xhci_suspend(xhci, do_wakeup);
	391	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
	392	xhci_ssic_port_unused_quirk(hcd, false);
	393
	394	return ret;
5535b1d5 AX	395	}
	396
	397	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	398	{
	399	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	400	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	401	int retval = 0;
5535b1d5 AX	402
69e848c2 SS	403	/* The BIOS on systems with the Intel Panther Point chipset may or may
	404	* not support xHCI natively. That means that during system resume, it
	405	* may switch the ports back to EHCI so that users can use their
	406	* keyboard to select a kernel from GRUB after resume from hibernate.
	407	*
	408	* The BIOS is supposed to remember whether the OS had xHCI ports
	409	* enabled before resume, and switch the ports back to xHCI when the
	410	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	411	* writers.
	412	*
	413	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	414	* It should not matter whether the EHCI or xHCI controller is
	415	* resumed first. It's enough to do the switchover in xHCI because
	416	* USB core won't notice anything as the hub driver doesn't start
	417	* running again until after all the devices (including both EHCI and
	418	* xHCI host controllers) have been resumed.
69e848c2	419	*/
26b76798 MN	420
	421	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	422	usb_enable_intel_xhci_ports(pdev);
69e848c2	423
7e70cbff LB	424	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
	425	xhci_ssic_port_unused_quirk(hcd, false);
	426
b8cb91e0	427	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff	428	xhci_pme_quirk(hcd);
b8cb91e0	429
5535b1d5 AX	430	retval = xhci_resume(xhci, hibernated);
	431	return retval;
	432	}
	433	#endif /* CONFIG_PM */
	434
66d4eadd SS	435	/-------------------------------------------------------------------------/
	436
	437	/* PCI driver selection metadata; PCI hotplugging uses this */
	438	static const struct pci_device_id pci_ids[] = { {
	439	/* handle any USB 3.0 xHCI controller */
	440	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	441	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	442	},
	443	{ /* end: all zeroes */ }
	444	};
	445	MODULE_DEVICE_TABLE(pci, pci_ids);
	446
	447	/* pci driver glue; this is a "new style" PCI driver module */
	448	static struct pci_driver xhci_pci_driver = {
	449	.name = (char *) hcd_name,
	450	.id_table = pci_ids,
	451
f6ff0ac8	452	.probe = xhci_pci_probe,
b02d0ed6	453	.remove = xhci_pci_remove,
66d4eadd SS	454	/* suspend and resume implemented later */
	455
	456	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	457	#ifdef CONFIG_PM
5535b1d5 AX	458	.driver = {
	459	.pm = &usb_hcd_pci_pm_ops
	460	},
	461	#endif
66d4eadd SS	462	};
66d4eadd SS	463
29e409f0	464	static int __init xhci_pci_init(void)
66d4eadd	465	{
cd33a321	466	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1885d9a3 AB	467	#ifdef CONFIG_PM
	468	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	469	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
	470	#endif
66d4eadd SS	471	return pci_register_driver(&xhci_pci_driver);
66d4eadd SS	472	}
29e409f0	473	module_init(xhci_pci_init);
66d4eadd	474
29e409f0	475	static void __exit xhci_pci_exit(void)
66d4eadd SS	476	{
	477	pci_unregister_driver(&xhci_pci_driver);
	478	}
29e409f0 AB	479	module_exit(xhci_pci_exit);
	480
	481	MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
	482	MODULE_LICENSE("GPL");