[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>

#include "xhci.h"

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_ASROCK_P67	0x7023

static const char hcd_name[] = "xhci_hcd";

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
		if (pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
					" endpoint cmd after reset endpoint\n");
		}
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation\n",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;
	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
	}
	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
	}
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
}

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	xhci = hcd_to_xhci(hcd);
	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	retval = xhci_pci_reinit(xhci, pdev);
	if (!retval)
		return retval;

	kfree(xhci);
	return retval;
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;
	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		return retval;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
	 * is called by usb_add_hcd().
	 */
	*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	/* We know the LPM timeout algorithms for this host, let the USB core
	 * enable and disable LPM for devices under the USB 3.0 roothub.
	 */
	if (xhci->quirks & XHCI_LPM_SUPPORT)
		hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}
	usb_hcd_pci_remove(dev);
	kfree(xhci);
}

#ifdef CONFIG_PM
static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	int	retval = 0;

	if (hcd->state != HC_STATE_SUSPENDED ||
			xhci->shared_hcd->state != HC_STATE_SUSPENDED)
		return -EINVAL;

	retval = xhci_suspend(xhci);

	return retval;
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * We can't tell whether the EHCI or xHCI controller will be resumed
	 * first, so we have to do the port switchover in both drivers.  Writing
	 * a '1' to the port switchover registers should have no effect if the
	 * port was already switched over.
	 */
	if (usb_is_intel_switchable_xhci(pdev))
		usb_enable_xhci_ports(pdev);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

static const struct hc_driver xhci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"xHCI Host Controller",
	.hcd_priv_size =	sizeof(struct xhci_hcd *),

	/*
	 * generic hardware linkage
	 */
	.irq =			xhci_irq,
	.flags =		HCD_MEMORY | HCD_USB3 | HCD_SHARED,

	/*
	 * basic lifecycle operations
	 */
	.reset =		xhci_pci_setup,
	.start =		xhci_run,
#ifdef CONFIG_PM
	.pci_suspend =          xhci_pci_suspend,
	.pci_resume =           xhci_pci_resume,
#endif
	.stop =			xhci_stop,
	.shutdown =		xhci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		xhci_urb_enqueue,
	.urb_dequeue =		xhci_urb_dequeue,
	.alloc_dev =		xhci_alloc_dev,
	.free_dev =		xhci_free_dev,
	.alloc_streams =	xhci_alloc_streams,
	.free_streams =		xhci_free_streams,
	.add_endpoint =		xhci_add_endpoint,
	.drop_endpoint =	xhci_drop_endpoint,
	.endpoint_reset =	xhci_endpoint_reset,
	.check_bandwidth =	xhci_check_bandwidth,
	.reset_bandwidth =	xhci_reset_bandwidth,
	.address_device =	xhci_address_device,
	.update_hub_device =	xhci_update_hub_device,
	.reset_device =		xhci_discover_or_reset_device,

	/*
	 * scheduling support
	 */
	.get_frame_number =	xhci_get_frame,

	/* Root hub support */
	.hub_control =		xhci_hub_control,
	.hub_status_data =	xhci_hub_status_data,
	.bus_suspend =		xhci_bus_suspend,
	.bus_resume =		xhci_bus_resume,
	/*
	 * call back when device connected and addressed
	 */
	.update_device =        xhci_update_device,
	.set_usb2_hw_lpm =	xhci_set_usb2_hardware_lpm,
	.enable_usb3_lpm_timeout =	xhci_enable_usb3_lpm_timeout,
	.disable_usb3_lpm_timeout =	xhci_disable_usb3_lpm_timeout,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM_SLEEP
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

int __init xhci_register_pci(void)
{
	return pci_register_driver(&xhci_pci_driver);
}

void xhci_unregister_pci(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
66d4eadd SS	26
	27	#include "xhci.h"
	28
ac9d8fe7 SS	29	/* Device for a quirk */
	30	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	31	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
	32
c877b3b2 ML	33	#define PCI_VENDOR_ID_ETRON 0x1b6f
	34	#define PCI_DEVICE_ID_ASROCK_P67 0x7023
	35
66d4eadd SS	36	static const char hcd_name[] = "xhci_hcd";
	37
	38	/* called after powerup, by probe or system-pm "wakeup" */
	39	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	40	{
	41	/*
	42	* TODO: Implement finding debug ports later.
	43	* TODO: see if there are any quirks that need to be added to handle
	44	* new extended capabilities.
	45	*/
	46
	47	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	48	if (!pci_set_mwi(pdev))
	49	xhci_dbg(xhci, "MWI active\n");
	50
	51	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	52	return 0;
	53	}
	54
da3c9c4f SAS	55	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	56	{
	57	struct pci_dev *pdev = to_pci_dev(dev);
	58
ac9d8fe7 SS	59	/* Look for vendor-specific quirks */
ac9d8fe7 SS	60	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
f5182b41 SS	61	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
f5182b41 SS	62	if (pdev->revision == 0x0) {
ac9d8fe7 SS	63	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
	64	xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
	65	" endpoint cmd after reset endpoint\n");
f5182b41 SS	66	}
	67	/* Fresco Logic confirms: all revisions of this chip do not
	68	* support MSI, even though some of them claim to in their PCI
	69	* capabilities.
	70	*/
	71	xhci->quirks \|= XHCI_BROKEN_MSI;
	72	xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
	73	"has broken MSI implementation\n",
	74	pdev->revision);
1530bbc6	75	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	76	}
f5182b41	77
0238634d SS	78	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	79	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	80
7e393a83 AX	81	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	82	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	83
c41136b0 AX	84	/* AMD PLL quirk */
	85	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	86	xhci->quirks \|= XHCI_AMD_PLL_FIX;
e3567d2c SS	87	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	88	xhci->quirks \|= XHCI_LPM_SUPPORT;
	89	xhci->quirks \|= XHCI_INTEL_HOST;
	90	}
ad808333 SS	91	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	92	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
	93	xhci->quirks \|= XHCI_SPURIOUS_SUCCESS;
2cf95c18 SS	94	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	95	xhci->limit_active_eps = 64;
86cc558e	96	xhci->quirks \|= XHCI_SW_BW_CHECKING;
ad808333	97	}
c877b3b2 ML	98	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
	99	pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
	100	xhci->quirks \|= XHCI_RESET_ON_RESUME;
	101	xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
	102	}
457a4f61 EF	103	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	104	xhci->quirks \|= XHCI_RESET_ON_RESUME;
da3c9c4f	105	}
c41136b0	106
da3c9c4f SAS	107	/* called during probe() after chip reset completes */
	108	static int xhci_pci_setup(struct usb_hcd *hcd)
	109	{
	110	struct xhci_hcd *xhci;
	111	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	112	int retval;
66d4eadd	113
da3c9c4f	114	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	115	if (retval)
da3c9c4f	116	return retval;
006d5820	117
da3c9c4f SAS	118	xhci = hcd_to_xhci(hcd);
	119	if (!usb_hcd_is_primary_hcd(hcd))
	120	return 0;
66d4eadd SS	121
	122	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	123	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	124
	125	/* Find any debug ports */
b02d0ed6 SS	126	retval = xhci_pci_reinit(xhci, pdev);
	127	if (!retval)
	128	return retval;
	129
b02d0ed6 SS	130	kfree(xhci);
	131	return retval;
	132	}
	133
f6ff0ac8 SS	134	/*
	135	* We need to register our own PCI probe function (instead of the USB core's
	136	* function) in order to create a second roothub under xHCI.
	137	*/
	138	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	139	{
	140	int retval;
	141	struct xhci_hcd *xhci;
	142	struct hc_driver *driver;
	143	struct usb_hcd *hcd;
	144
	145	driver = (struct hc_driver *)id->driver_data;
	146	/* Register the USB 2.0 roothub.
	147	* FIXME: USB core must know to register the USB 2.0 roothub first.
	148	* This is sort of silly, because we could just set the HCD driver flags
	149	* to say USB 2.0, but I'm not sure what the implications would be in
	150	* the other parts of the HCD code.
	151	*/
	152	retval = usb_hcd_pci_probe(dev, id);
	153
	154	if (retval)
	155	return retval;
	156
	157	/* USB 2.0 roothub is stored in the PCI device now. */
	158	hcd = dev_get_drvdata(&dev->dev);
	159	xhci = hcd_to_xhci(hcd);
	160	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	161	pci_name(dev), hcd);
	162	if (!xhci->shared_hcd) {
	163	retval = -ENOMEM;
	164	goto dealloc_usb2_hcd;
	165	}
	166
	167	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
	168	* is called by usb_add_hcd().
	169	*/
	170	((struct xhci_hcd *) xhci->shared_hcd->hcd_priv) = xhci;
	171
	172	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	173	IRQF_SHARED);
f6ff0ac8 SS	174	if (retval)
	175	goto put_usb3_hcd;
	176	/* Roothub already marked as USB 3.0 speed */
3b3db026 SS	177
	178	/* We know the LPM timeout algorithms for this host, let the USB core
	179	* enable and disable LPM for devices under the USB 3.0 roothub.
	180	*/
	181	if (xhci->quirks & XHCI_LPM_SUPPORT)
	182	hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;
	183
f6ff0ac8 SS	184	return 0;
	185
	186	put_usb3_hcd:
	187	usb_put_hcd(xhci->shared_hcd);
	188	dealloc_usb2_hcd:
	189	usb_hcd_pci_remove(dev);
	190	return retval;
	191	}
	192
b02d0ed6 SS	193	static void xhci_pci_remove(struct pci_dev *dev)
	194	{
	195	struct xhci_hcd *xhci;
	196
	197	xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8 SS	198	if (xhci->shared_hcd) {
	199	usb_remove_hcd(xhci->shared_hcd);
	200	usb_put_hcd(xhci->shared_hcd);
	201	}
b02d0ed6 SS	202	usb_hcd_pci_remove(dev);
b02d0ed6 SS	203	kfree(xhci);
66d4eadd SS	204	}
66d4eadd SS	205
5535b1d5 AX	206	#ifdef CONFIG_PM
	207	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	208	{
	209	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	210	int retval = 0;
	211
b3209379 SS	212	if (hcd->state != HC_STATE_SUSPENDED \|\|
b3209379 SS	213	xhci->shared_hcd->state != HC_STATE_SUSPENDED)
5535b1d5 AX	214	return -EINVAL;
	215
	216	retval = xhci_suspend(xhci);
	217
	218	return retval;
	219	}
	220
	221	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	222	{
	223	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	224	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	225	int retval = 0;
5535b1d5 AX	226
69e848c2 SS	227	/* The BIOS on systems with the Intel Panther Point chipset may or may
	228	* not support xHCI natively. That means that during system resume, it
	229	* may switch the ports back to EHCI so that users can use their
	230	* keyboard to select a kernel from GRUB after resume from hibernate.
	231	*
	232	* The BIOS is supposed to remember whether the OS had xHCI ports
	233	* enabled before resume, and switch the ports back to xHCI when the
	234	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	235	* writers.
	236	*
	237	* Unconditionally switch the ports back to xHCI after a system resume.
	238	* We can't tell whether the EHCI or xHCI controller will be resumed
	239	* first, so we have to do the port switchover in both drivers. Writing
	240	* a '1' to the port switchover registers should have no effect if the
	241	* port was already switched over.
	242	*/
	243	if (usb_is_intel_switchable_xhci(pdev))
	244	usb_enable_xhci_ports(pdev);
	245
5535b1d5 AX	246	retval = xhci_resume(xhci, hibernated);
	247	return retval;
	248	}
	249	#endif /* CONFIG_PM */
	250
66d4eadd SS	251	static const struct hc_driver xhci_pci_hc_driver = {
	252	.description = hcd_name,
	253	.product_desc = "xHCI Host Controller",
b02d0ed6	254	.hcd_priv_size = sizeof(struct xhci_hcd *),
66d4eadd SS	255
	256	/*
	257	* generic hardware linkage
	258	*/
7f84eef0	259	.irq = xhci_irq,
f6ff0ac8	260	.flags = HCD_MEMORY \| HCD_USB3 \| HCD_SHARED,
66d4eadd SS	261
	262	/*
	263	* basic lifecycle operations
	264	*/
	265	.reset = xhci_pci_setup,
	266	.start = xhci_run,
5535b1d5 AX	267	#ifdef CONFIG_PM
	268	.pci_suspend = xhci_pci_suspend,
	269	.pci_resume = xhci_pci_resume,
	270	#endif
66d4eadd SS	271	.stop = xhci_stop,
	272	.shutdown = xhci_shutdown,
	273
3ffbba95 SS	274	/*
	275	* managing i/o requests and associated device resources
	276	*/
d0e96f5a SS	277	.urb_enqueue = xhci_urb_enqueue,
d0e96f5a SS	278	.urb_dequeue = xhci_urb_dequeue,
3ffbba95 SS	279	.alloc_dev = xhci_alloc_dev,
3ffbba95 SS	280	.free_dev = xhci_free_dev,
eab1cafc SS	281	.alloc_streams = xhci_alloc_streams,
eab1cafc SS	282	.free_streams = xhci_free_streams,
f94e0186 SS	283	.add_endpoint = xhci_add_endpoint,
f94e0186 SS	284	.drop_endpoint = xhci_drop_endpoint,
a1587d97	285	.endpoint_reset = xhci_endpoint_reset,
f94e0186 SS	286	.check_bandwidth = xhci_check_bandwidth,
f94e0186 SS	287	.reset_bandwidth = xhci_reset_bandwidth,
3ffbba95	288	.address_device = xhci_address_device,
b356b7c7	289	.update_hub_device = xhci_update_hub_device,
f0615c45	290	.reset_device = xhci_discover_or_reset_device,
3ffbba95	291
66d4eadd SS	292	/*
	293	* scheduling support
	294	*/
	295	.get_frame_number = xhci_get_frame,
	296
0f2a7930 SS	297	/* Root hub support */
	298	.hub_control = xhci_hub_control,
	299	.hub_status_data = xhci_hub_status_data,
9777e3ce AX	300	.bus_suspend = xhci_bus_suspend,
9777e3ce AX	301	.bus_resume = xhci_bus_resume,
9574323c AX	302	/*
	303	* call back when device connected and addressed
	304	*/
	305	.update_device = xhci_update_device,
65580b43	306	.set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
3b3db026 SS	307	.enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
3b3db026 SS	308	.disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
66d4eadd SS	309	};
	310
	311	/-------------------------------------------------------------------------/
	312
	313	/* PCI driver selection metadata; PCI hotplugging uses this */
	314	static const struct pci_device_id pci_ids[] = { {
	315	/* handle any USB 3.0 xHCI controller */
	316	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	317	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	318	},
	319	{ /* end: all zeroes */ }
	320	};
	321	MODULE_DEVICE_TABLE(pci, pci_ids);
	322
	323	/* pci driver glue; this is a "new style" PCI driver module */
	324	static struct pci_driver xhci_pci_driver = {
	325	.name = (char *) hcd_name,
	326	.id_table = pci_ids,
	327
f6ff0ac8	328	.probe = xhci_pci_probe,
b02d0ed6	329	.remove = xhci_pci_remove,
66d4eadd SS	330	/* suspend and resume implemented later */
	331
	332	.shutdown = usb_hcd_pci_shutdown,
5535b1d5 AX	333	#ifdef CONFIG_PM_SLEEP
	334	.driver = {
	335	.pm = &usb_hcd_pci_pm_ops
	336	},
	337	#endif
66d4eadd SS	338	};
66d4eadd SS	339
0cc47d54	340	int __init xhci_register_pci(void)
66d4eadd SS	341	{
	342	return pci_register_driver(&xhci_pci_driver);
	343	}
	344
a46c46a1	345	void xhci_unregister_pci(void)
66d4eadd SS	346	{
	347	pci_unregister_driver(&xhci_pci_driver);
	348	}