[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>

#include "xhci.h"
#include "xhci-trace.h"

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_EJ168		0x7023

#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31

static const char hcd_name[] = "xhci_hcd";

static struct hc_driver __read_mostly xhci_pci_hc_driver;

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x4) {
			xhci->quirks |= XHCI_SLOW_SUSPEND;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC revision %u"
				"must be suspended extra slowly",
				pdev->revision);
		}
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;

	if (pdev->vendor == PCI_VENDOR_ID_AMD)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	    (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI ||
	     pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) {
		/* Workaround for occasional spurious wakeups from S5 (or
		 * any other sleep) on Haswell machines with LPT and LPT-LP
		 * with the new Intel BIOS
		 */
		/* Limit the quirk to only known vendors, as this triggers
		 * yet another BIOS bug on some other machines
		 * https://bugzilla.kernel.org/show_bug.cgi?id=66171
		 */
		if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)
			xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
	}
	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_EJ168) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	}
	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
			pdev->device == 0x0015)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;

	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
			pdev->device == 0x3432)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (xhci->quirks & XHCI_RESET_ON_RESUME)
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
}

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	xhci = hcd_to_xhci(hcd);
	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	retval = xhci_pci_reinit(xhci, pdev);
	if (!retval)
		return retval;

	kfree(xhci);
	return retval;
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;

	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	pm_runtime_get_noresume(&dev->dev);

	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		goto put_runtime_pm;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
	 * is called by usb_add_hcd().
	 */
	*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
			HCC_MAX_PSA(xhci->hcc_params) >= 4)
		xhci->shared_hcd->can_do_streams = 1;

	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	pm_runtime_put_noidle(&dev->dev);

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
put_runtime_pm:
	pm_runtime_put_noidle(&dev->dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}
	usb_hcd_pci_remove(dev);

	/* Workaround for spurious wakeups at shutdown with HSW */
	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
		pci_set_power_state(dev, PCI_D3hot);

	kfree(xhci);
}

#ifdef CONFIG_PM
static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci_compliance_mode_recovery_timer_quirk_check())
		pdev->no_d3cold = true;

	return xhci_suspend(xhci);
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

int __init xhci_register_pci(void)
{
	xhci_init_driver(&xhci_pci_hc_driver, xhci_pci_setup);
#ifdef CONFIG_PM
	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
#endif
	return pci_register_driver(&xhci_pci_driver);
}

void xhci_unregister_pci(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
66d4eadd SS	26
66d4eadd SS	27	#include "xhci.h"
4bdfe4c3	28	#include "xhci-trace.h"
66d4eadd	29
ac9d8fe7 SS	30	/* Device for a quirk */
	31	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	32	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
bba18e33	33	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	34
c877b3b2	35	#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9	36	#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2	37
638298dc TI	38	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
	39	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
	40
66d4eadd SS	41	static const char hcd_name[] = "xhci_hcd";
66d4eadd SS	42
1885d9a3 AB	43	static struct hc_driver __read_mostly xhci_pci_hc_driver;
1885d9a3 AB	44
66d4eadd SS	45	/* called after powerup, by probe or system-pm "wakeup" */
	46	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	47	{
	48	/*
	49	* TODO: Implement finding debug ports later.
	50	* TODO: see if there are any quirks that need to be added to handle
	51	* new extended capabilities.
	52	*/
	53
	54	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	55	if (!pci_set_mwi(pdev))
	56	xhci_dbg(xhci, "MWI active\n");
	57
	58	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	59	return 0;
	60	}
	61
da3c9c4f SAS	62	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	63	{
	64	struct pci_dev *pdev = to_pci_dev(dev);
	65
ac9d8fe7 SS	66	/* Look for vendor-specific quirks */
ac9d8fe7 SS	67	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	68	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	69	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	70	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	71	pdev->revision == 0x0) {
ac9d8fe7	72	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	73	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	74	"QUIRK: Fresco Logic xHC needs configure"
	75	" endpoint cmd after reset endpoint");
f5182b41	76	}
455f5892 ON	77	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	78	pdev->revision == 0x4) {
	79	xhci->quirks \|= XHCI_SLOW_SUSPEND;
	80	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	81	"QUIRK: Fresco Logic xHC revision %u"
	82	"must be suspended extra slowly",
	83	pdev->revision);
	84	}
f5182b41 SS	85	/* Fresco Logic confirms: all revisions of this chip do not
	86	* support MSI, even though some of them claim to in their PCI
	87	* capabilities.
	88	*/
	89	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	90	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	91	"QUIRK: Fresco Logic revision %u "
	92	"has broken MSI implementation",
f5182b41	93	pdev->revision);
1530bbc6	94	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	95	}
f5182b41	96
0238634d SS	97	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	98	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	99
7e393a83 AX	100	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	101	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	102
c41136b0 AX	103	/* AMD PLL quirk */
	104	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	105	xhci->quirks \|= XHCI_AMD_PLL_FIX;
2597fe99 HR	106
	107	if (pdev->vendor == PCI_VENDOR_ID_AMD)
	108	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
	109
e3567d2c SS	110	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	111	xhci->quirks \|= XHCI_LPM_SUPPORT;
	112	xhci->quirks \|= XHCI_INTEL_HOST;
	113	}
ad808333 SS	114	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	115	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	116	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	117	xhci->limit_active_eps = 64;
86cc558e	118	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	119	/*
	120	* PPT desktop boards DH77EB and DH77DF will power back on after
	121	* a few seconds of being shutdown. The fix for this is to
	122	* switch the ports from xHCI to EHCI on shutdown. We can't use
	123	* DMI information to find those particular boards (since each
	124	* vendor will change the board name), so we have to key off all
	125	* PPT chipsets.
	126	*/
	127	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
80fab3b2	128	xhci->quirks \|= XHCI_AVOID_BEI;
ad808333	129	}
638298dc TI	130	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	131	(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI \|\|
	132	pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) {
	133	/* Workaround for occasional spurious wakeups from S5 (or
	134	* any other sleep) on Haswell machines with LPT and LPT-LP
	135	* with the new Intel BIOS
	136	*/
6962d914 TI	137	/* Limit the quirk to only known vendors, as this triggers
	138	* yet another BIOS bug on some other machines
	139	* https://bugzilla.kernel.org/show_bug.cgi?id=66171
	140	*/
	141	if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)
	142	xhci->quirks \|= XHCI_SPURIOUS_WAKEUP;
0a939993 DT	143	}
	144	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	145	pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
c09ec25d	146	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
638298dc	147	}
c877b3b2	148	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9	149	pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2	150	xhci->quirks \|= XHCI_RESET_ON_RESUME;
5cb7df2b	151	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
8f873c1f	152	xhci->quirks \|= XHCI_BROKEN_STREAMS;
c877b3b2	153	}
1aa9578c	154	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb	155	pdev->device == 0x0015)
1aa9578c	156	xhci->quirks \|= XHCI_RESET_ON_RESUME;
457a4f61 EF	157	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	158	xhci->quirks \|= XHCI_RESET_ON_RESUME;
85f4e45b	159
e21eba05 HG	160	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	161	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
	162	pdev->device == 0x3432)
	163	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	164
85f4e45b ON	165	if (xhci->quirks & XHCI_RESET_ON_RESUME)
	166	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	167	"QUIRK: Resetting on resume");
da3c9c4f	168	}
c41136b0	169
da3c9c4f SAS	170	/* called during probe() after chip reset completes */
	171	static int xhci_pci_setup(struct usb_hcd *hcd)
	172	{
	173	struct xhci_hcd *xhci;
	174	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	175	int retval;
66d4eadd	176
da3c9c4f	177	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	178	if (retval)
da3c9c4f	179	return retval;
006d5820	180
da3c9c4f SAS	181	xhci = hcd_to_xhci(hcd);
	182	if (!usb_hcd_is_primary_hcd(hcd))
	183	return 0;
66d4eadd SS	184
	185	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	186	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	187
	188	/* Find any debug ports */
b02d0ed6 SS	189	retval = xhci_pci_reinit(xhci, pdev);
	190	if (!retval)
	191	return retval;
	192
b02d0ed6 SS	193	kfree(xhci);
	194	return retval;
	195	}
	196
f6ff0ac8 SS	197	/*
	198	* We need to register our own PCI probe function (instead of the USB core's
	199	* function) in order to create a second roothub under xHCI.
	200	*/
	201	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	202	{
	203	int retval;
	204	struct xhci_hcd *xhci;
	205	struct hc_driver *driver;
	206	struct usb_hcd *hcd;
	207
	208	driver = (struct hc_driver *)id->driver_data;
bcffae77 MN	209
	210	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	211	pm_runtime_get_noresume(&dev->dev);
	212
f6ff0ac8 SS	213	/* Register the USB 2.0 roothub.
	214	* FIXME: USB core must know to register the USB 2.0 roothub first.
	215	* This is sort of silly, because we could just set the HCD driver flags
	216	* to say USB 2.0, but I'm not sure what the implications would be in
	217	* the other parts of the HCD code.
	218	*/
	219	retval = usb_hcd_pci_probe(dev, id);
	220
	221	if (retval)
bcffae77	222	goto put_runtime_pm;
f6ff0ac8 SS	223
	224	/* USB 2.0 roothub is stored in the PCI device now. */
	225	hcd = dev_get_drvdata(&dev->dev);
	226	xhci = hcd_to_xhci(hcd);
	227	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	228	pci_name(dev), hcd);
	229	if (!xhci->shared_hcd) {
	230	retval = -ENOMEM;
	231	goto dealloc_usb2_hcd;
	232	}
	233
	234	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
	235	* is called by usb_add_hcd().
	236	*/
	237	((struct xhci_hcd *) xhci->shared_hcd->hcd_priv) = xhci;
	238
	239	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	240	IRQF_SHARED);
f6ff0ac8 SS	241	if (retval)
	242	goto put_usb3_hcd;
	243	/* Roothub already marked as USB 3.0 speed */
3b3db026	244
8f873c1f HG	245	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
8f873c1f HG	246	HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589 ON	247	xhci->shared_hcd->can_do_streams = 1;
14aec589 ON	248
bcffae77 MN	249	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	250	pm_runtime_put_noidle(&dev->dev);
	251
f6ff0ac8 SS	252	return 0;
	253
	254	put_usb3_hcd:
	255	usb_put_hcd(xhci->shared_hcd);
	256	dealloc_usb2_hcd:
	257	usb_hcd_pci_remove(dev);
bcffae77 MN	258	put_runtime_pm:
bcffae77 MN	259	pm_runtime_put_noidle(&dev->dev);
f6ff0ac8 SS	260	return retval;
	261	}
	262
b02d0ed6 SS	263	static void xhci_pci_remove(struct pci_dev *dev)
	264	{
	265	struct xhci_hcd *xhci;
	266
	267	xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8 SS	268	if (xhci->shared_hcd) {
	269	usb_remove_hcd(xhci->shared_hcd);
	270	usb_put_hcd(xhci->shared_hcd);
	271	}
b02d0ed6	272	usb_hcd_pci_remove(dev);
638298dc TI	273
	274	/* Workaround for spurious wakeups at shutdown with HSW */
	275	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
	276	pci_set_power_state(dev, PCI_D3hot);
	277
b02d0ed6	278	kfree(xhci);
66d4eadd SS	279	}
66d4eadd SS	280
5535b1d5 AX	281	#ifdef CONFIG_PM
	282	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	283	{
	284	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5 SS	285	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	286
	287	/*
	288	* Systems with the TI redriver that loses port status change events
	289	* need to have the registers polled during D3, so avoid D3cold.
	290	*/
	291	if (xhci_compliance_mode_recovery_timer_quirk_check())
	292	pdev->no_d3cold = true;
5535b1d5	293
77b84767	294	return xhci_suspend(xhci);
5535b1d5 AX	295	}
	296
	297	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	298	{
	299	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	300	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	301	int retval = 0;
5535b1d5 AX	302
69e848c2 SS	303	/* The BIOS on systems with the Intel Panther Point chipset may or may
	304	* not support xHCI natively. That means that during system resume, it
	305	* may switch the ports back to EHCI so that users can use their
	306	* keyboard to select a kernel from GRUB after resume from hibernate.
	307	*
	308	* The BIOS is supposed to remember whether the OS had xHCI ports
	309	* enabled before resume, and switch the ports back to xHCI when the
	310	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	311	* writers.
	312	*
	313	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	314	* It should not matter whether the EHCI or xHCI controller is
	315	* resumed first. It's enough to do the switchover in xHCI because
	316	* USB core won't notice anything as the hub driver doesn't start
	317	* running again until after all the devices (including both EHCI and
	318	* xHCI host controllers) have been resumed.
69e848c2	319	*/
26b76798 MN	320
	321	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	322	usb_enable_intel_xhci_ports(pdev);
69e848c2	323
5535b1d5 AX	324	retval = xhci_resume(xhci, hibernated);
	325	return retval;
	326	}
	327	#endif /* CONFIG_PM */
	328
66d4eadd SS	329	/-------------------------------------------------------------------------/
	330
	331	/* PCI driver selection metadata; PCI hotplugging uses this */
	332	static const struct pci_device_id pci_ids[] = { {
	333	/* handle any USB 3.0 xHCI controller */
	334	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	335	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	336	},
	337	{ /* end: all zeroes */ }
	338	};
	339	MODULE_DEVICE_TABLE(pci, pci_ids);
	340
	341	/* pci driver glue; this is a "new style" PCI driver module */
	342	static struct pci_driver xhci_pci_driver = {
	343	.name = (char *) hcd_name,
	344	.id_table = pci_ids,
	345
f6ff0ac8	346	.probe = xhci_pci_probe,
b02d0ed6	347	.remove = xhci_pci_remove,
66d4eadd SS	348	/* suspend and resume implemented later */
	349
	350	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	351	#ifdef CONFIG_PM
5535b1d5 AX	352	.driver = {
	353	.pm = &usb_hcd_pci_pm_ops
	354	},
	355	#endif
66d4eadd SS	356	};
66d4eadd SS	357
0cc47d54	358	int __init xhci_register_pci(void)
66d4eadd	359	{
1885d9a3 AB	360	xhci_init_driver(&xhci_pci_hc_driver, xhci_pci_setup);
	361	#ifdef CONFIG_PM
	362	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	363	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
	364	#endif
66d4eadd SS	365	return pci_register_driver(&xhci_pci_driver);
	366	}
	367
a46c46a1	368	void xhci_unregister_pci(void)
66d4eadd SS	369	{
	370	pci_unregister_driver(&xhci_pci_driver);
	371	}