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Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / drivers / usb / gadget / udc / amd5536udc.c
CommitLineData
55d402d8
TD		 1/*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
55d402d8
TD		 11 */
12
13/*
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
17 *
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
20 * by BIOS init).
21 *
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24 * can be used with gadget ether.
25 */
26
27/* debug control */
28/* #define UDC_VERBOSE */
29
30/* Driver strings */
31#define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
c15e03e1 32#define UDC_DRIVER_VERSION_STRING "01.00.0206"
55d402d8
TD		 33
34/* system */
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
55d402d8
TD		 38#include <linux/delay.h>
39#include <linux/ioport.h>
40#include <linux/sched.h>
41#include <linux/slab.h>
55d402d8 42#include <linux/errno.h>
55d402d8
TD		 43#include <linux/timer.h>
44#include <linux/list.h>
45#include <linux/interrupt.h>
46#include <linux/ioctl.h>
47#include <linux/fs.h>
48#include <linux/dmapool.h>
49#include <linux/moduleparam.h>
50#include <linux/device.h>
51#include <linux/io.h>
52#include <linux/irq.h>
b38b03b3 53#include <linux/prefetch.h>
55d402d8
TD		 54
55#include <asm/byteorder.h>
55d402d8
TD		 56#include <asm/unaligned.h>
57
58/* gadget stack */
59#include <linux/usb/ch9.h>
9454a57a 60#include <linux/usb/gadget.h>
55d402d8
TD		 61
62/* udc specific */
63#include "amd5536udc.h"
64
65
66static void udc_tasklet_disconnect(unsigned long);
67static void empty_req_queue(struct udc_ep *);
68static int udc_probe(struct udc *dev);
69static void udc_basic_init(struct udc *dev);
70static void udc_setup_endpoints(struct udc *dev);
71static void udc_soft_reset(struct udc *dev);
72static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
73static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
74static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
75static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
76 unsigned long buf_len, gfp_t gfp_flags);
77static int udc_remote_wakeup(struct udc *dev);
78static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
79static void udc_pci_remove(struct pci_dev *pdev);
80
81/* description */
82static const char mod_desc[] = UDC_MOD_DESCRIPTION;
83static const char name[] = "amd5536udc";
84
85/* structure to hold endpoint function pointers */
86static const struct usb_ep_ops udc_ep_ops;
87
88/* received setup data */
89static union udc_setup_data setup_data;
90
91/* pointer to device object */
92static struct udc *udc;
93
94/* irq spin lock for soft reset */
95static DEFINE_SPINLOCK(udc_irq_spinlock);
96/* stall spin lock */
97static DEFINE_SPINLOCK(udc_stall_spinlock);
98
99/*
100* slave mode: pending bytes in rx fifo after nyet,
101* used if EPIN irq came but no req was available
102*/
103static unsigned int udc_rxfifo_pending;
104
105/* count soft resets after suspend to avoid loop */
106static int soft_reset_occured;
107static int soft_reset_after_usbreset_occured;
108
109/* timer */
110static struct timer_list udc_timer;
111static int stop_timer;
112
113/* set_rde -- Is used to control enabling of RX DMA. Problem is
114 * that UDC has only one bit (RDE) to enable/disable RX DMA for
115 * all OUT endpoints. So we have to handle race conditions like
116 * when OUT data reaches the fifo but no request was queued yet.
117 * This cannot be solved by letting the RX DMA disabled until a
118 * request gets queued because there may be other OUT packets
119 * in the FIFO (important for not blocking control traffic).
120 * The value of set_rde controls the correspondig timer.
121 *
122 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
123 * set_rde 0 == do not touch RDE, do no start the RDE timer
124 * set_rde 1 == timer function will look whether FIFO has data
125 * set_rde 2 == set by timer function to enable RX DMA on next call
126 */
127static int set_rde = -1;
128
129static DECLARE_COMPLETION(on_exit);
130static struct timer_list udc_pollstall_timer;
131static int stop_pollstall_timer;
132static DECLARE_COMPLETION(on_pollstall_exit);
133
134/* tasklet for usb disconnect */
135static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
136 (unsigned long) &udc);
137
138
139/* endpoint names used for print */
140static const char ep0_string[] = "ep0in";
6f02ac5a
RB		 141static const struct {
142 const char *name;
143 const struct usb_ep_caps caps;
144} ep_info[] = {
145#define EP_INFO(_name, _caps) \
146 { \
147 .name = _name, \
148 .caps = _caps, \
149 }
150
151 EP_INFO(ep0_string,
152 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_IN)),
153 EP_INFO("ep1in-int",
154 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
155 EP_INFO("ep2in-bulk",
156 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
157 EP_INFO("ep3in-bulk",
158 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
159 EP_INFO("ep4in-bulk",
160 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
161 EP_INFO("ep5in-bulk",
162 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
163 EP_INFO("ep6in-bulk",
164 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
165 EP_INFO("ep7in-bulk",
166 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
167 EP_INFO("ep8in-bulk",
168 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
169 EP_INFO("ep9in-bulk",
170 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
171 EP_INFO("ep10in-bulk",
172 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
173 EP_INFO("ep11in-bulk",
174 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
175 EP_INFO("ep12in-bulk",
176 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
177 EP_INFO("ep13in-bulk",
178 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
179 EP_INFO("ep14in-bulk",
180 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
181 EP_INFO("ep15in-bulk",
182 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
183 EP_INFO("ep0out",
184 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_OUT)),
185 EP_INFO("ep1out-bulk",
186 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
187 EP_INFO("ep2out-bulk",
188 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
189 EP_INFO("ep3out-bulk",
190 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
191 EP_INFO("ep4out-bulk",
192 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
193 EP_INFO("ep5out-bulk",
194 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
195 EP_INFO("ep6out-bulk",
196 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
197 EP_INFO("ep7out-bulk",
198 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
199 EP_INFO("ep8out-bulk",
200 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
201 EP_INFO("ep9out-bulk",
202 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
203 EP_INFO("ep10out-bulk",
204 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
205 EP_INFO("ep11out-bulk",
206 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
207 EP_INFO("ep12out-bulk",
208 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
209 EP_INFO("ep13out-bulk",
210 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
211 EP_INFO("ep14out-bulk",
212 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
213 EP_INFO("ep15out-bulk",
214 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
215
216#undef EP_INFO
55d402d8
TD		 217};
218
219/* DMA usage flag */
90ab5ee9 220static bool use_dma = 1;
55d402d8 221/* packet per buffer dma */
90ab5ee9 222static bool use_dma_ppb = 1;
55d402d8 223/* with per descr. update */
90ab5ee9 224static bool use_dma_ppb_du;
55d402d8
TD		 225/* buffer fill mode */
226static int use_dma_bufferfill_mode;
227/* full speed only mode */
90ab5ee9 228static bool use_fullspeed;
55d402d8
TD		 229/* tx buffer size for high speed */
230static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
231
232/* module parameters */
233module_param(use_dma, bool, S_IRUGO);
234MODULE_PARM_DESC(use_dma, "true for DMA");
235module_param(use_dma_ppb, bool, S_IRUGO);
236MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
237module_param(use_dma_ppb_du, bool, S_IRUGO);
238MODULE_PARM_DESC(use_dma_ppb_du,
239 "true for DMA in packet per buffer mode with descriptor update");
240module_param(use_fullspeed, bool, S_IRUGO);
241MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
242
243/*---------------------------------------------------------------------------*/
244/* Prints UDC device registers and endpoint irq registers */
245static void print_regs(struct udc *dev)
246{
247 DBG(dev, "------- Device registers -------\n");
248 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
249 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
250 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
251 DBG(dev, "\n");
252 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
253 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
254 DBG(dev, "\n");
255 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
256 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
257 DBG(dev, "\n");
258 DBG(dev, "USE DMA = %d\n", use_dma);
259 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
260 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
261 "WITHOUT desc. update)\n");
262 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
0cf7a633 263 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
55d402d8
TD		 264 DBG(dev, "DMA mode = PPBDU (packet per buffer "
265 "WITH desc. update)\n");
266 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
267 }
268 if (use_dma && use_dma_bufferfill_mode) {
269 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
270 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
271 }
170b778f 272 if (!use_dma)
55d402d8 273 dev_info(&dev->pdev->dev, "FIFO mode\n");
55d402d8
TD		 274 DBG(dev, "-------------------------------------------------------\n");
275}
276
277/* Masks unused interrupts */
278static int udc_mask_unused_interrupts(struct udc *dev)
279{
280 u32 tmp;
281
282 /* mask all dev interrupts */
283 tmp = AMD_BIT(UDC_DEVINT_SVC) |
284 AMD_BIT(UDC_DEVINT_ENUM) |
285 AMD_BIT(UDC_DEVINT_US) |
286 AMD_BIT(UDC_DEVINT_UR) |
287 AMD_BIT(UDC_DEVINT_ES) |
288 AMD_BIT(UDC_DEVINT_SI) |
289 AMD_BIT(UDC_DEVINT_SOF)|
290 AMD_BIT(UDC_DEVINT_SC);
291 writel(tmp, &dev->regs->irqmsk);
292
293 /* mask all ep interrupts */
294 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
295
296 return 0;
297}
298
299/* Enables endpoint 0 interrupts */
300static int udc_enable_ep0_interrupts(struct udc *dev)
301{
302 u32 tmp;
303
304 DBG(dev, "udc_enable_ep0_interrupts()\n");
305
306 /* read irq mask */
307 tmp = readl(&dev->regs->ep_irqmsk);
308 /* enable ep0 irq's */
309 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
310 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
311 writel(tmp, &dev->regs->ep_irqmsk);
312
313 return 0;
314}
315
316/* Enables device interrupts for SET_INTF and SET_CONFIG */
317static int udc_enable_dev_setup_interrupts(struct udc *dev)
318{
319 u32 tmp;
320
321 DBG(dev, "enable device interrupts for setup data\n");
322
323 /* read irq mask */
324 tmp = readl(&dev->regs->irqmsk);
325
326 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
327 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
328 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
329 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
330 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
331 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
332 writel(tmp, &dev->regs->irqmsk);
333
334 return 0;
335}
336
25985edc 337/* Calculates fifo start of endpoint based on preceding endpoints */
55d402d8
TD		 338static int udc_set_txfifo_addr(struct udc_ep *ep)
339{
340 struct udc *dev;
341 u32 tmp;
342 int i;
343
344 if (!ep || !(ep->in))
345 return -EINVAL;
346
347 dev = ep->dev;
348 ep->txfifo = dev->txfifo;
349
350 /* traverse ep's */
351 for (i = 0; i < ep->num; i++) {
352 if (dev->ep[i].regs) {
353 /* read fifo size */
354 tmp = readl(&dev->ep[i].regs->bufin_framenum);
355 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
356 ep->txfifo += tmp;
357 }
358 }
359 return 0;
360}
361
362/* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
363static u32 cnak_pending;
364
365static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
366{
367 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
368 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
369 cnak_pending |= 1 << (num);
370 ep->naking = 1;
371 } else
372 cnak_pending = cnak_pending & (~(1 << (num)));
373}
374
375
376/* Enables endpoint, is called by gadget driver */
377static int
378udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
379{
380 struct udc_ep *ep;
381 struct udc *dev;
382 u32 tmp;
383 unsigned long iflags;
384 u8 udc_csr_epix;
fd05e720 385 unsigned maxpacket;
55d402d8
TD		 386
387 if (!usbep
388 || usbep->name == ep0_string
389 || !desc
390 || desc->bDescriptorType != USB_DT_ENDPOINT)
391 return -EINVAL;
392
393 ep = container_of(usbep, struct udc_ep, ep);
394 dev = ep->dev;
395
396 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
397
398 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
399 return -ESHUTDOWN;
400
401 spin_lock_irqsave(&dev->lock, iflags);
ef20a72b 402 ep->ep.desc = desc;
55d402d8
TD		 403
404 ep->halted = 0;
405
406 /* set traffic type */
407 tmp = readl(&dev->ep[ep->num].regs->ctl);
408 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
409 writel(tmp, &dev->ep[ep->num].regs->ctl);
410
411 /* set max packet size */
29cc8897 412 maxpacket = usb_endpoint_maxp(desc);
55d402d8 413 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
fd05e720
AV		 414 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
415 ep->ep.maxpacket = maxpacket;
55d402d8
TD		 416 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
417
418 /* IN ep */
419 if (ep->in) {
420
421 /* ep ix in UDC CSR register space */
422 udc_csr_epix = ep->num;
423
424 /* set buffer size (tx fifo entries) */
425 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
426 /* double buffering: fifo size = 2 x max packet size */
427 tmp = AMD_ADDBITS(
428 tmp,
fd05e720
AV		 429 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
430 / UDC_DWORD_BYTES,
55d402d8
TD		 431 UDC_EPIN_BUFF_SIZE);
432 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
433
434 /* calc. tx fifo base addr */
435 udc_set_txfifo_addr(ep);
436
437 /* flush fifo */
438 tmp = readl(&ep->regs->ctl);
439 tmp |= AMD_BIT(UDC_EPCTL_F);
440 writel(tmp, &ep->regs->ctl);
441
442 /* OUT ep */
443 } else {
444 /* ep ix in UDC CSR register space */
445 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
446
447 /* set max packet size UDC CSR */
448 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
fd05e720 449 tmp = AMD_ADDBITS(tmp, maxpacket,
55d402d8
TD		 450 UDC_CSR_NE_MAX_PKT);
451 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
452
453 if (use_dma && !ep->in) {
454 /* alloc and init BNA dummy request */
455 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
456 ep->bna_occurred = 0;
457 }
458
459 if (ep->num != UDC_EP0OUT_IX)
460 dev->data_ep_enabled = 1;
461 }
462
463 /* set ep values */
464 tmp = readl(&dev->csr->ne[udc_csr_epix]);
465 /* max packet */
fd05e720 466 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
55d402d8
TD		 467 /* ep number */
468 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
469 /* ep direction */
470 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
471 /* ep type */
472 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
473 /* ep config */
474 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
475 /* ep interface */
476 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
477 /* ep alt */
478 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
479 /* write reg */
480 writel(tmp, &dev->csr->ne[udc_csr_epix]);
481
482 /* enable ep irq */
483 tmp = readl(&dev->regs->ep_irqmsk);
484 tmp &= AMD_UNMASK_BIT(ep->num);
485 writel(tmp, &dev->regs->ep_irqmsk);
486
487 /*
488 * clear NAK by writing CNAK
489 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
490 */
491 if (!use_dma || ep->in) {
492 tmp = readl(&ep->regs->ctl);
493 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
494 writel(tmp, &ep->regs->ctl);
495 ep->naking = 0;
496 UDC_QUEUE_CNAK(ep, ep->num);
497 }
498 tmp = desc->bEndpointAddress;
499 DBG(dev, "%s enabled\n", usbep->name);
500
501 spin_unlock_irqrestore(&dev->lock, iflags);
502 return 0;
503}
504
505/* Resets endpoint */
506static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
507{
508 u32 tmp;
509
510 VDBG(ep->dev, "ep-%d reset\n", ep->num);
f9c56cdd 511 ep->ep.desc = NULL;
55d402d8
TD		 512 ep->ep.ops = &udc_ep_ops;
513 INIT_LIST_HEAD(&ep->queue);
514
e117e742 515 usb_ep_set_maxpacket_limit(&ep->ep,(u16) ~0);
55d402d8
TD		 516 /* set NAK */
517 tmp = readl(&ep->regs->ctl);
518 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
519 writel(tmp, &ep->regs->ctl);
520 ep->naking = 1;
521
522 /* disable interrupt */
523 tmp = readl(&regs->ep_irqmsk);
524 tmp |= AMD_BIT(ep->num);
525 writel(tmp, &regs->ep_irqmsk);
526
527 if (ep->in) {
528 /* unset P and IN bit of potential former DMA */
529 tmp = readl(&ep->regs->ctl);
530 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
531 writel(tmp, &ep->regs->ctl);
532
533 tmp = readl(&ep->regs->sts);
534 tmp |= AMD_BIT(UDC_EPSTS_IN);
535 writel(tmp, &ep->regs->sts);
536
537 /* flush the fifo */
538 tmp = readl(&ep->regs->ctl);
539 tmp |= AMD_BIT(UDC_EPCTL_F);
540 writel(tmp, &ep->regs->ctl);
541
542 }
543 /* reset desc pointer */
544 writel(0, &ep->regs->desptr);
545}
546
547/* Disables endpoint, is called by gadget driver */
548static int udc_ep_disable(struct usb_ep *usbep)
549{
550 struct udc_ep *ep = NULL;
551 unsigned long iflags;
552
553 if (!usbep)
554 return -EINVAL;
555
556 ep = container_of(usbep, struct udc_ep, ep);
ef20a72b 557 if (usbep->name == ep0_string || !ep->ep.desc)
55d402d8
TD		 558 return -EINVAL;
559
560 DBG(ep->dev, "Disable ep-%d\n", ep->num);
561
562 spin_lock_irqsave(&ep->dev->lock, iflags);
563 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
564 empty_req_queue(ep);
565 ep_init(ep->dev->regs, ep);
566 spin_unlock_irqrestore(&ep->dev->lock, iflags);
567
568 return 0;
569}
570
571/* Allocates request packet, called by gadget driver */
572static struct usb_request *
573udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
574{
575 struct udc_request *req;
576 struct udc_data_dma *dma_desc;
577 struct udc_ep *ep;
578
579 if (!usbep)
580 return NULL;
581
582 ep = container_of(usbep, struct udc_ep, ep);
583
584 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
585 req = kzalloc(sizeof(struct udc_request), gfp);
586 if (!req)
587 return NULL;
588
589 req->req.dma = DMA_DONT_USE;
590 INIT_LIST_HEAD(&req->queue);
591
592 if (ep->dma) {
593 /* ep0 in requests are allocated from data pool here */
594 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
595 &req->td_phys);
596 if (!dma_desc) {
597 kfree(req);
598 return NULL;
599 }
600
601 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
602 "td_phys = %lx\n",
603 req, dma_desc,
604 (unsigned long)req->td_phys);
605 /* prevent from using desc. - set HOST BUSY */
606 dma_desc->status = AMD_ADDBITS(dma_desc->status,
607 UDC_DMA_STP_STS_BS_HOST_BUSY,
608 UDC_DMA_STP_STS_BS);
551509d2 609 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
55d402d8
TD		 610 req->td_data = dma_desc;
611 req->td_data_last = NULL;
612 req->chain_len = 1;
613 }
614
615 return &req->req;
616}
617
618/* Frees request packet, called by gadget driver */
619static void
620udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
621{
622 struct udc_ep *ep;
623 struct udc_request *req;
624
625 if (!usbep || !usbreq)
626 return;
627
628 ep = container_of(usbep, struct udc_ep, ep);
629 req = container_of(usbreq, struct udc_request, req);
630 VDBG(ep->dev, "free_req req=%p\n", req);
631 BUG_ON(!list_empty(&req->queue));
632 if (req->td_data) {
633 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
634
635 /* free dma chain if created */
170b778f 636 if (req->chain_len > 1)
55d402d8 637 udc_free_dma_chain(ep->dev, req);
55d402d8
TD		 638
639 pci_pool_free(ep->dev->data_requests, req->td_data,
640 req->td_phys);
641 }
642 kfree(req);
643}
644
645/* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
646static void udc_init_bna_dummy(struct udc_request *req)
647{
648 if (req) {
649 /* set last bit */
650 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
651 /* set next pointer to itself */
652 req->td_data->next = req->td_phys;
653 /* set HOST BUSY */
654 req->td_data->status
655 = AMD_ADDBITS(req->td_data->status,
656 UDC_DMA_STP_STS_BS_DMA_DONE,
657 UDC_DMA_STP_STS_BS);
658#ifdef UDC_VERBOSE
659 pr_debug("bna desc = %p, sts = %08x\n",
660 req->td_data, req->td_data->status);
661#endif
662 }
663}
664
665/* Allocate BNA dummy descriptor */
666static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
667{
668 struct udc_request *req = NULL;
669 struct usb_request *_req = NULL;
670
671 /* alloc the dummy request */
672 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
673 if (_req) {
674 req = container_of(_req, struct udc_request, req);
675 ep->bna_dummy_req = req;
676 udc_init_bna_dummy(req);
677 }
678 return req;
679}
680
681/* Write data to TX fifo for IN packets */
682static void
683udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
684{
685 u8 *req_buf;
686 u32 *buf;
687 int i, j;
688 unsigned bytes = 0;
689 unsigned remaining = 0;
690
691 if (!req || !ep)
692 return;
693
694 req_buf = req->buf + req->actual;
695 prefetch(req_buf);
696 remaining = req->length - req->actual;
697
698 buf = (u32 *) req_buf;
699
700 bytes = ep->ep.maxpacket;
701 if (bytes > remaining)
702 bytes = remaining;
703
704 /* dwords first */
170b778f 705 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
55d402d8 706 writel(*(buf + i), ep->txfifo);
55d402d8
TD		 707
708 /* remaining bytes must be written by byte access */
709 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
710 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
711 ep->txfifo);
712 }
713
714 /* dummy write confirm */
715 writel(0, &ep->regs->confirm);
716}
717
718/* Read dwords from RX fifo for OUT transfers */
719static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
720{
721 int i;
722
723 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
724
170b778f 725 for (i = 0; i < dwords; i++)
55d402d8 726 *(buf + i) = readl(dev->rxfifo);
55d402d8
TD		 727 return 0;
728}
729
730/* Read bytes from RX fifo for OUT transfers */
731static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
732{
733 int i, j;
734 u32 tmp;
735
736 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
737
738 /* dwords first */
170b778f 739 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
55d402d8 740 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
55d402d8
TD		 741
742 /* remaining bytes must be read by byte access */
743 if (bytes % UDC_DWORD_BYTES) {
744 tmp = readl(dev->rxfifo);
745 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
746 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
747 tmp = tmp >> UDC_BITS_PER_BYTE;
748 }
749 }
750
751 return 0;
752}
753
754/* Read data from RX fifo for OUT transfers */
755static int
756udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
757{
758 u8 *buf;
759 unsigned buf_space;
760 unsigned bytes = 0;
761 unsigned finished = 0;
762
763 /* received number bytes */
764 bytes = readl(&ep->regs->sts);
765 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
766
767 buf_space = req->req.length - req->req.actual;
768 buf = req->req.buf + req->req.actual;
769 if (bytes > buf_space) {
770 if ((buf_space % ep->ep.maxpacket) != 0) {
771 DBG(ep->dev,
772 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
773 ep->ep.name, bytes, buf_space);
774 req->req.status = -EOVERFLOW;
775 }
776 bytes = buf_space;
777 }
778 req->req.actual += bytes;
779
780 /* last packet ? */
781 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
782 || ((req->req.actual == req->req.length) && !req->req.zero))
783 finished = 1;
784
785 /* read rx fifo bytes */
786 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
787 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
788
789 return finished;
790}
791
792/* create/re-init a DMA descriptor or a DMA descriptor chain */
793static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
794{
795 int retval = 0;
796 u32 tmp;
797
798 VDBG(ep->dev, "prep_dma\n");
799 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
800 ep->num, req->td_data);
801
802 /* set buffer pointer */
803 req->td_data->bufptr = req->req.dma;
804
805 /* set last bit */
806 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
807
808 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
809 if (use_dma_ppb) {
810
811 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
812 if (retval != 0) {
813 if (retval == -ENOMEM)
814 DBG(ep->dev, "Out of DMA memory\n");
815 return retval;
816 }
817 if (ep->in) {
818 if (req->req.length == ep->ep.maxpacket) {
819 /* write tx bytes */
820 req->td_data->status =
821 AMD_ADDBITS(req->td_data->status,
822 ep->ep.maxpacket,
823 UDC_DMA_IN_STS_TXBYTES);
824
825 }
826 }
827
828 }
829
830 if (ep->in) {
831 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
832 "maxpacket=%d ep%d\n",
833 use_dma_ppb, req->req.length,
834 ep->ep.maxpacket, ep->num);
835 /*
836 * if bytes < max packet then tx bytes must
837 * be written in packet per buffer mode
838 */
839 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
840 || ep->num == UDC_EP0OUT_IX
841 || ep->num == UDC_EP0IN_IX) {
842 /* write tx bytes */
843 req->td_data->status =
844 AMD_ADDBITS(req->td_data->status,
845 req->req.length,
846 UDC_DMA_IN_STS_TXBYTES);
847 /* reset frame num */
848 req->td_data->status =
849 AMD_ADDBITS(req->td_data->status,
850 0,
851 UDC_DMA_IN_STS_FRAMENUM);
852 }
853 /* set HOST BUSY */
854 req->td_data->status =
855 AMD_ADDBITS(req->td_data->status,
856 UDC_DMA_STP_STS_BS_HOST_BUSY,
857 UDC_DMA_STP_STS_BS);
858 } else {
859 VDBG(ep->dev, "OUT set host ready\n");
860 /* set HOST READY */
861 req->td_data->status =
862 AMD_ADDBITS(req->td_data->status,
863 UDC_DMA_STP_STS_BS_HOST_READY,
864 UDC_DMA_STP_STS_BS);
865
866
867 /* clear NAK by writing CNAK */
868 if (ep->naking) {
869 tmp = readl(&ep->regs->ctl);
870 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
871 writel(tmp, &ep->regs->ctl);
872 ep->naking = 0;
873 UDC_QUEUE_CNAK(ep, ep->num);
874 }
875
876 }
877
878 return retval;
879}
880
881/* Completes request packet ... caller MUST hold lock */
882static void
883complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
884__releases(ep->dev->lock)
885__acquires(ep->dev->lock)
886{
887 struct udc *dev;
888 unsigned halted;
889
890 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
891
892 dev = ep->dev;
893 /* unmap DMA */
220e8600
FB		 894 if (ep->dma)
895 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
55d402d8
TD		 896
897 halted = ep->halted;
898 ep->halted = 1;
899
900 /* set new status if pending */
901 if (req->req.status == -EINPROGRESS)
902 req->req.status = sts;
903
904 /* remove from ep queue */
905 list_del_init(&req->queue);
906
907 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
908 &req->req, req->req.length, ep->ep.name, sts);
909
910 spin_unlock(&dev->lock);
304f7e5e 911 usb_gadget_giveback_request(&ep->ep, &req->req);
55d402d8
TD		 912 spin_lock(&dev->lock);
913 ep->halted = halted;
914}
915
916/* frees pci pool descriptors of a DMA chain */
917static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
918{
919
920 int ret_val = 0;
921 struct udc_data_dma *td;
922 struct udc_data_dma *td_last = NULL;
923 unsigned int i;
924
925 DBG(dev, "free chain req = %p\n", req);
926
927 /* do not free first desc., will be done by free for request */
928 td_last = req->td_data;
929 td = phys_to_virt(td_last->next);
930
931 for (i = 1; i < req->chain_len; i++) {
932
933 pci_pool_free(dev->data_requests, td,
934 (dma_addr_t) td_last->next);
935 td_last = td;
936 td = phys_to_virt(td_last->next);
937 }
938
939 return ret_val;
940}
941
942/* Iterates to the end of a DMA chain and returns last descriptor */
943static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
944{
945 struct udc_data_dma *td;
946
947 td = req->td_data;
170b778f 948 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
55d402d8 949 td = phys_to_virt(td->next);
55d402d8
TD		 950
951 return td;
952
953}
954
955/* Iterates to the end of a DMA chain and counts bytes received */
956static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
957{
958 struct udc_data_dma *td;
959 u32 count;
960
961 td = req->td_data;
962 /* received number bytes */
963 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
964
965 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
966 td = phys_to_virt(td->next);
967 /* received number bytes */
968 if (td) {
969 count += AMD_GETBITS(td->status,
970 UDC_DMA_OUT_STS_RXBYTES);
971 }
972 }
973
974 return count;
975
976}
977
978/* Creates or re-inits a DMA chain */
979static int udc_create_dma_chain(
980 struct udc_ep *ep,
981 struct udc_request *req,
982 unsigned long buf_len, gfp_t gfp_flags
983)
984{
985 unsigned long bytes = req->req.length;
986 unsigned int i;
987 dma_addr_t dma_addr;
988 struct udc_data_dma *td = NULL;
989 struct udc_data_dma *last = NULL;
990 unsigned long txbytes;
991 unsigned create_new_chain = 0;
992 unsigned len;
993
994 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
995 bytes, buf_len);
996 dma_addr = DMA_DONT_USE;
997
998 /* unset L bit in first desc for OUT */
170b778f 999 if (!ep->in)
55d402d8 1000 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
55d402d8
TD		 1001
1002 /* alloc only new desc's if not already available */
1003 len = req->req.length / ep->ep.maxpacket;
170b778f 1004 if (req->req.length % ep->ep.maxpacket)
55d402d8 1005 len++;
55d402d8
TD		 1006
1007 if (len > req->chain_len) {
1008 /* shorter chain already allocated before */
170b778f 1009 if (req->chain_len > 1)
55d402d8 1010 udc_free_dma_chain(ep->dev, req);
55d402d8
TD		 1011 req->chain_len = len;
1012 create_new_chain = 1;
1013 }
1014
1015 td = req->td_data;
1016 /* gen. required number of descriptors and buffers */
1017 for (i = buf_len; i < bytes; i += buf_len) {
1018 /* create or determine next desc. */
1019 if (create_new_chain) {
1020
1021 td = pci_pool_alloc(ep->dev->data_requests,
1022 gfp_flags, &dma_addr);
1023 if (!td)
1024 return -ENOMEM;
1025
1026 td->status = 0;
1027 } else if (i == buf_len) {
1028 /* first td */
1029 td = (struct udc_data_dma *) phys_to_virt(
1030 req->td_data->next);
1031 td->status = 0;
1032 } else {
1033 td = (struct udc_data_dma *) phys_to_virt(last->next);
1034 td->status = 0;
1035 }
1036
1037
1038 if (td)
1039 td->bufptr = req->req.dma + i; /* assign buffer */
1040 else
1041 break;
1042
1043 /* short packet ? */
1044 if ((bytes - i) >= buf_len) {
1045 txbytes = buf_len;
1046 } else {
1047 /* short packet */
1048 txbytes = bytes - i;
1049 }
1050
1051 /* link td and assign tx bytes */
1052 if (i == buf_len) {
170b778f 1053 if (create_new_chain)
55d402d8 1054 req->td_data->next = dma_addr;
170b778f
CR		 1055 /*
1056 else
1057 req->td_data->next = virt_to_phys(td);
1058 */
55d402d8
TD		 1059 /* write tx bytes */
1060 if (ep->in) {
1061 /* first desc */
1062 req->td_data->status =
1063 AMD_ADDBITS(req->td_data->status,
1064 ep->ep.maxpacket,
1065 UDC_DMA_IN_STS_TXBYTES);
1066 /* second desc */
1067 td->status = AMD_ADDBITS(td->status,
1068 txbytes,
1069 UDC_DMA_IN_STS_TXBYTES);
1070 }
1071 } else {
170b778f 1072 if (create_new_chain)
55d402d8 1073 last->next = dma_addr;
170b778f
CR		 1074 /*
1075 else
1076 last->next = virt_to_phys(td);
1077 */
55d402d8
TD		 1078 if (ep->in) {
1079 /* write tx bytes */
1080 td->status = AMD_ADDBITS(td->status,
1081 txbytes,
1082 UDC_DMA_IN_STS_TXBYTES);
1083 }
1084 }
1085 last = td;
1086 }
1087 /* set last bit */
1088 if (td) {
1089 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1090 /* last desc. points to itself */
1091 req->td_data_last = td;
1092 }
1093
1094 return 0;
1095}
1096
1097/* Enabling RX DMA */
1098static void udc_set_rde(struct udc *dev)
1099{
1100 u32 tmp;
1101
1102 VDBG(dev, "udc_set_rde()\n");
1103 /* stop RDE timer */
1104 if (timer_pending(&udc_timer)) {
1105 set_rde = 0;
1106 mod_timer(&udc_timer, jiffies - 1);
1107 }
1108 /* set RDE */
1109 tmp = readl(&dev->regs->ctl);
1110 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1111 writel(tmp, &dev->regs->ctl);
1112}
1113
1114/* Queues a request packet, called by gadget driver */
1115static int
1116udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1117{
1118 int retval = 0;
1119 u8 open_rxfifo = 0;
1120 unsigned long iflags;
1121 struct udc_ep *ep;
1122 struct udc_request *req;
1123 struct udc *dev;
1124 u32 tmp;
1125
1126 /* check the inputs */
1127 req = container_of(usbreq, struct udc_request, req);
1128
1129 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1130 || !list_empty(&req->queue))
1131 return -EINVAL;
1132
1133 ep = container_of(usbep, struct udc_ep, ep);
ef20a72b 1134 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
55d402d8
TD		 1135 return -EINVAL;
1136
1137 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1138 dev = ep->dev;
1139
1140 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1141 return -ESHUTDOWN;
1142
1143 /* map dma (usually done before) */
220e8600 1144 if (ep->dma) {
55d402d8 1145 VDBG(dev, "DMA map req %p\n", req);
220e8600
FB		 1146 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1147 if (retval)
1148 return retval;
55d402d8
TD		 1149 }
1150
1151 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1152 usbep->name, usbreq, usbreq->length,
1153 req->td_data, usbreq->buf);
1154
1155 spin_lock_irqsave(&dev->lock, iflags);
1156 usbreq->actual = 0;
1157 usbreq->status = -EINPROGRESS;
1158 req->dma_done = 0;
1159
1160 /* on empty queue just do first transfer */
1161 if (list_empty(&ep->queue)) {
1162 /* zlp */
1163 if (usbreq->length == 0) {
1164 /* IN zlp's are handled by hardware */
1165 complete_req(ep, req, 0);
1166 VDBG(dev, "%s: zlp\n", ep->ep.name);
1167 /*
1168 * if set_config or set_intf is waiting for ack by zlp
1169 * then set CSR_DONE
1170 */
1171 if (dev->set_cfg_not_acked) {
1172 tmp = readl(&dev->regs->ctl);
1173 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1174 writel(tmp, &dev->regs->ctl);
1175 dev->set_cfg_not_acked = 0;
1176 }
1177 /* setup command is ACK'ed now by zlp */
1178 if (dev->waiting_zlp_ack_ep0in) {
1179 /* clear NAK by writing CNAK in EP0_IN */
1180 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1181 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1182 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1183 dev->ep[UDC_EP0IN_IX].naking = 0;
1184 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1185 UDC_EP0IN_IX);
1186 dev->waiting_zlp_ack_ep0in = 0;
1187 }
1188 goto finished;
1189 }
1190 if (ep->dma) {
ffcba5a5 1191 retval = prep_dma(ep, req, GFP_ATOMIC);
55d402d8
TD		 1192 if (retval != 0)
1193 goto finished;
1194 /* write desc pointer to enable DMA */
1195 if (ep->in) {
1196 /* set HOST READY */
1197 req->td_data->status =
1198 AMD_ADDBITS(req->td_data->status,
1199 UDC_DMA_IN_STS_BS_HOST_READY,
1200 UDC_DMA_IN_STS_BS);
1201 }
1202
1203 /* disabled rx dma while descriptor update */
1204 if (!ep->in) {
1205 /* stop RDE timer */
1206 if (timer_pending(&udc_timer)) {
1207 set_rde = 0;
1208 mod_timer(&udc_timer, jiffies - 1);
1209 }
1210 /* clear RDE */
1211 tmp = readl(&dev->regs->ctl);
1212 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1213 writel(tmp, &dev->regs->ctl);
1214 open_rxfifo = 1;
1215
1216 /*
1217 * if BNA occurred then let BNA dummy desc.
1218 * point to current desc.
1219 */
1220 if (ep->bna_occurred) {
1221 VDBG(dev, "copy to BNA dummy desc.\n");
1222 memcpy(ep->bna_dummy_req->td_data,
1223 req->td_data,
1224 sizeof(struct udc_data_dma));
1225 }
1226 }
1227 /* write desc pointer */
1228 writel(req->td_phys, &ep->regs->desptr);
1229
1230 /* clear NAK by writing CNAK */
1231 if (ep->naking) {
1232 tmp = readl(&ep->regs->ctl);
1233 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1234 writel(tmp, &ep->regs->ctl);
1235 ep->naking = 0;
1236 UDC_QUEUE_CNAK(ep, ep->num);
1237 }
1238
1239 if (ep->in) {
1240 /* enable ep irq */
1241 tmp = readl(&dev->regs->ep_irqmsk);
1242 tmp &= AMD_UNMASK_BIT(ep->num);
1243 writel(tmp, &dev->regs->ep_irqmsk);
1244 }
c5deb832
TD		 1245 } else if (ep->in) {
1246 /* enable ep irq */
1247 tmp = readl(&dev->regs->ep_irqmsk);
1248 tmp &= AMD_UNMASK_BIT(ep->num);
1249 writel(tmp, &dev->regs->ep_irqmsk);
1250 }
55d402d8
TD		 1251
1252 } else if (ep->dma) {
1253
1254 /*
1255 * prep_dma not used for OUT ep's, this is not possible
1256 * for PPB modes, because of chain creation reasons
1257 */
1258 if (ep->in) {
ffcba5a5 1259 retval = prep_dma(ep, req, GFP_ATOMIC);
55d402d8
TD		 1260 if (retval != 0)
1261 goto finished;
1262 }
1263 }
1264 VDBG(dev, "list_add\n");
1265 /* add request to ep queue */
1266 if (req) {
1267
1268 list_add_tail(&req->queue, &ep->queue);
1269
1270 /* open rxfifo if out data queued */
1271 if (open_rxfifo) {
1272 /* enable DMA */
1273 req->dma_going = 1;
1274 udc_set_rde(dev);
1275 if (ep->num != UDC_EP0OUT_IX)
1276 dev->data_ep_queued = 1;
1277 }
1278 /* stop OUT naking */
1279 if (!ep->in) {
1280 if (!use_dma && udc_rxfifo_pending) {
fec8de3a 1281 DBG(dev, "udc_queue(): pending bytes in "
55d402d8
TD		 1282 "rxfifo after nyet\n");
1283 /*
1284 * read pending bytes afer nyet:
1285 * referring to isr
1286 */
1287 if (udc_rxfifo_read(ep, req)) {
1288 /* finish */
1289 complete_req(ep, req, 0);
1290 }
1291 udc_rxfifo_pending = 0;
1292
1293 }
1294 }
1295 }
1296
1297finished:
1298 spin_unlock_irqrestore(&dev->lock, iflags);
1299 return retval;
1300}
1301
1302/* Empty request queue of an endpoint; caller holds spinlock */
1303static void empty_req_queue(struct udc_ep *ep)
1304{
1305 struct udc_request *req;
1306
1307 ep->halted = 1;
1308 while (!list_empty(&ep->queue)) {
1309 req = list_entry(ep->queue.next,
1310 struct udc_request,
1311 queue);
1312 complete_req(ep, req, -ESHUTDOWN);
1313 }
1314}
1315
1316/* Dequeues a request packet, called by gadget driver */
1317static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1318{
1319 struct udc_ep *ep;
1320 struct udc_request *req;
1321 unsigned halted;
1322 unsigned long iflags;
1323
1324 ep = container_of(usbep, struct udc_ep, ep);
ef20a72b 1325 if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
55d402d8
TD		 1326 && ep->num != UDC_EP0OUT_IX)))
1327 return -EINVAL;
1328
1329 req = container_of(usbreq, struct udc_request, req);
1330
1331 spin_lock_irqsave(&ep->dev->lock, iflags);
1332 halted = ep->halted;
1333 ep->halted = 1;
1334 /* request in processing or next one */
1335 if (ep->queue.next == &req->queue) {
1336 if (ep->dma && req->dma_going) {
1337 if (ep->in)
1338 ep->cancel_transfer = 1;
1339 else {
1340 u32 tmp;
1341 u32 dma_sts;
1342 /* stop potential receive DMA */
1343 tmp = readl(&udc->regs->ctl);
1344 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1345 &udc->regs->ctl);
1346 /*
1347 * Cancel transfer later in ISR
1348 * if descriptor was touched.
1349 */
1350 dma_sts = AMD_GETBITS(req->td_data->status,
1351 UDC_DMA_OUT_STS_BS);
1352 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1353 ep->cancel_transfer = 1;
1354 else {
1355 udc_init_bna_dummy(ep->req);
1356 writel(ep->bna_dummy_req->td_phys,
1357 &ep->regs->desptr);
1358 }
1359 writel(tmp, &udc->regs->ctl);
1360 }
1361 }
1362 }
1363 complete_req(ep, req, -ECONNRESET);
1364 ep->halted = halted;
1365
1366 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1367 return 0;
1368}
1369
1370/* Halt or clear halt of endpoint */
1371static int
1372udc_set_halt(struct usb_ep *usbep, int halt)
1373{
1374 struct udc_ep *ep;
1375 u32 tmp;
1376 unsigned long iflags;
1377 int retval = 0;
1378
1379 if (!usbep)
1380 return -EINVAL;
1381
1382 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1383
1384 ep = container_of(usbep, struct udc_ep, ep);
ef20a72b 1385 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
55d402d8
TD		 1386 return -EINVAL;
1387 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1388 return -ESHUTDOWN;
1389
1390 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1391 /* halt or clear halt */
1392 if (halt) {
1393 if (ep->num == 0)
1394 ep->dev->stall_ep0in = 1;
1395 else {
1396 /*
1397 * set STALL
1398 * rxfifo empty not taken into acount
1399 */
1400 tmp = readl(&ep->regs->ctl);
1401 tmp |= AMD_BIT(UDC_EPCTL_S);
1402 writel(tmp, &ep->regs->ctl);
1403 ep->halted = 1;
1404
1405 /* setup poll timer */
1406 if (!timer_pending(&udc_pollstall_timer)) {
1407 udc_pollstall_timer.expires = jiffies +
1408 HZ * UDC_POLLSTALL_TIMER_USECONDS
1409 / (1000 * 1000);
1410 if (!stop_pollstall_timer) {
1411 DBG(ep->dev, "start polltimer\n");
1412 add_timer(&udc_pollstall_timer);
1413 }
1414 }
1415 }
1416 } else {
1417 /* ep is halted by set_halt() before */
1418 if (ep->halted) {
1419 tmp = readl(&ep->regs->ctl);
1420 /* clear stall bit */
1421 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1422 /* clear NAK by writing CNAK */
1423 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1424 writel(tmp, &ep->regs->ctl);
1425 ep->halted = 0;
1426 UDC_QUEUE_CNAK(ep, ep->num);
1427 }
1428 }
1429 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1430 return retval;
1431}
1432
1433/* gadget interface */
1434static const struct usb_ep_ops udc_ep_ops = {
1435 .enable = udc_ep_enable,
1436 .disable = udc_ep_disable,
1437
1438 .alloc_request = udc_alloc_request,
1439 .free_request = udc_free_request,
1440
1441 .queue = udc_queue,
1442 .dequeue = udc_dequeue,
1443
1444 .set_halt = udc_set_halt,
1445 /* fifo ops not implemented */
1446};
1447
1448/*-------------------------------------------------------------------------*/
1449
1450/* Get frame counter (not implemented) */
1451static int udc_get_frame(struct usb_gadget *gadget)
1452{
1453 return -EOPNOTSUPP;
1454}
1455
1456/* Remote wakeup gadget interface */
1457static int udc_wakeup(struct usb_gadget *gadget)
1458{
1459 struct udc *dev;
1460
1461 if (!gadget)
1462 return -EINVAL;
1463 dev = container_of(gadget, struct udc, gadget);
1464 udc_remote_wakeup(dev);
1465
1466 return 0;
1467}
1468
45005f69
FB		 1469static int amd5536_udc_start(struct usb_gadget *g,
1470 struct usb_gadget_driver *driver);
22835b80
FB		 1471static int amd5536_udc_stop(struct usb_gadget *g);
1472
55d402d8
TD		 1473static const struct usb_gadget_ops udc_ops = {
1474 .wakeup = udc_wakeup,
1475 .get_frame = udc_get_frame,
45005f69
FB		 1476 .udc_start = amd5536_udc_start,
1477 .udc_stop = amd5536_udc_stop,
55d402d8
TD		 1478};
1479
1480/* Setups endpoint parameters, adds endpoints to linked list */
1481static void make_ep_lists(struct udc *dev)
1482{
1483 /* make gadget ep lists */
1484 INIT_LIST_HEAD(&dev->gadget.ep_list);
1485 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1486 &dev->gadget.ep_list);
1487 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1488 &dev->gadget.ep_list);
1489 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1490 &dev->gadget.ep_list);
1491
1492 /* fifo config */
1493 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1494 if (dev->gadget.speed == USB_SPEED_FULL)
1495 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1496 else if (dev->gadget.speed == USB_SPEED_HIGH)
1497 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1498 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1499}
1500
1501/* init registers at driver load time */
1502static int startup_registers(struct udc *dev)
1503{
1504 u32 tmp;
1505
1506 /* init controller by soft reset */
1507 udc_soft_reset(dev);
1508
1509 /* mask not needed interrupts */
1510 udc_mask_unused_interrupts(dev);
1511
1512 /* put into initial config */
1513 udc_basic_init(dev);
1514 /* link up all endpoints */
1515 udc_setup_endpoints(dev);
1516
1517 /* program speed */
1518 tmp = readl(&dev->regs->cfg);
170b778f 1519 if (use_fullspeed)
55d402d8 1520 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
170b778f 1521 else
55d402d8 1522 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
55d402d8
TD		 1523 writel(tmp, &dev->regs->cfg);
1524
1525 return 0;
1526}
1527
1528/* Inits UDC context */
1529static void udc_basic_init(struct udc *dev)
1530{
1531 u32 tmp;
1532
1533 DBG(dev, "udc_basic_init()\n");
1534
1535 dev->gadget.speed = USB_SPEED_UNKNOWN;
1536
1537 /* stop RDE timer */
1538 if (timer_pending(&udc_timer)) {
1539 set_rde = 0;
1540 mod_timer(&udc_timer, jiffies - 1);
1541 }
1542 /* stop poll stall timer */
170b778f 1543 if (timer_pending(&udc_pollstall_timer))
55d402d8 1544 mod_timer(&udc_pollstall_timer, jiffies - 1);
55d402d8
TD		 1545 /* disable DMA */
1546 tmp = readl(&dev->regs->ctl);
1547 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1548 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1549 writel(tmp, &dev->regs->ctl);
1550
1551 /* enable dynamic CSR programming */
1552 tmp = readl(&dev->regs->cfg);
1553 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1554 /* set self powered */
1555 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1556 /* set remote wakeupable */
1557 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1558 writel(tmp, &dev->regs->cfg);
1559
1560 make_ep_lists(dev);
1561
1562 dev->data_ep_enabled = 0;
1563 dev->data_ep_queued = 0;
1564}
1565
1566/* Sets initial endpoint parameters */
1567static void udc_setup_endpoints(struct udc *dev)
1568{
1569 struct udc_ep *ep;
1570 u32 tmp;
1571 u32 reg;
1572
1573 DBG(dev, "udc_setup_endpoints()\n");
1574
1575 /* read enum speed */
1576 tmp = readl(&dev->regs->sts);
1577 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
170b778f 1578 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
55d402d8 1579 dev->gadget.speed = USB_SPEED_HIGH;
170b778f 1580 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
55d402d8 1581 dev->gadget.speed = USB_SPEED_FULL;
55d402d8
TD		 1582
1583 /* set basic ep parameters */
1584 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1585 ep = &dev->ep[tmp];
1586 ep->dev = dev;
6f02ac5a
RB		 1587 ep->ep.name = ep_info[tmp].name;
1588 ep->ep.caps = ep_info[tmp].caps;
55d402d8
TD		 1589 ep->num = tmp;
1590 /* txfifo size is calculated at enable time */
1591 ep->txfifo = dev->txfifo;
1592
1593 /* fifo size */
1594 if (tmp < UDC_EPIN_NUM) {
1595 ep->fifo_depth = UDC_TXFIFO_SIZE;
1596 ep->in = 1;
1597 } else {
1598 ep->fifo_depth = UDC_RXFIFO_SIZE;
1599 ep->in = 0;
1600
1601 }
1602 ep->regs = &dev->ep_regs[tmp];
1603 /*
1604 * ep will be reset only if ep was not enabled before to avoid
1605 * disabling ep interrupts when ENUM interrupt occurs but ep is
1606 * not enabled by gadget driver
1607 */
ef20a72b 1608 if (!ep->ep.desc)
55d402d8 1609 ep_init(dev->regs, ep);
55d402d8
TD		 1610
1611 if (use_dma) {
1612 /*
1613 * ep->dma is not really used, just to indicate that
1614 * DMA is active: remove this
1615 * dma regs = dev control regs
1616 */
1617 ep->dma = &dev->regs->ctl;
1618
1619 /* nak OUT endpoints until enable - not for ep0 */
1620 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1621 && tmp > UDC_EPIN_NUM) {
1622 /* set NAK */
1623 reg = readl(&dev->ep[tmp].regs->ctl);
1624 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1625 writel(reg, &dev->ep[tmp].regs->ctl);
1626 dev->ep[tmp].naking = 1;
1627
1628 }
1629 }
1630 }
1631 /* EP0 max packet */
1632 if (dev->gadget.speed == USB_SPEED_FULL) {
e117e742
RB		 1633 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1634 UDC_FS_EP0IN_MAX_PKT_SIZE);
1635 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1636 UDC_FS_EP0OUT_MAX_PKT_SIZE);
55d402d8 1637 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
e117e742
RB		 1638 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1639 UDC_EP0IN_MAX_PKT_SIZE);
1640 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1641 UDC_EP0OUT_MAX_PKT_SIZE);
55d402d8
TD		 1642 }
1643
1644 /*
1645 * with suspend bug workaround, ep0 params for gadget driver
1646 * are set at gadget driver bind() call
1647 */
1648 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1649 dev->ep[UDC_EP0IN_IX].halted = 0;
1650 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1651
1652 /* init cfg/alt/int */
1653 dev->cur_config = 0;
1654 dev->cur_intf = 0;
1655 dev->cur_alt = 0;
1656}
1657
1658/* Bringup after Connect event, initial bringup to be ready for ep0 events */
1659static void usb_connect(struct udc *dev)
1660{
1661
1662 dev_info(&dev->pdev->dev, "USB Connect\n");
1663
1664 dev->connected = 1;
1665
1666 /* put into initial config */
1667 udc_basic_init(dev);
1668
1669 /* enable device setup interrupts */
1670 udc_enable_dev_setup_interrupts(dev);
1671}
1672
1673/*
1674 * Calls gadget with disconnect event and resets the UDC and makes
1675 * initial bringup to be ready for ep0 events
1676 */
1677static void usb_disconnect(struct udc *dev)
1678{
1679
1680 dev_info(&dev->pdev->dev, "USB Disconnect\n");
1681
1682 dev->connected = 0;
1683
1684 /* mask interrupts */
1685 udc_mask_unused_interrupts(dev);
1686
1687 /* REVISIT there doesn't seem to be a point to having this
1688 * talk to a tasklet ... do it directly, we already hold
1689 * the spinlock needed to process the disconnect.
1690 */
1691
1692 tasklet_schedule(&disconnect_tasklet);
1693}
1694
1695/* Tasklet for disconnect to be outside of interrupt context */
1696static void udc_tasklet_disconnect(unsigned long par)
1697{
1698 struct udc *dev = (struct udc *)(*((struct udc **) par));
1699 u32 tmp;
1700
1701 DBG(dev, "Tasklet disconnect\n");
1702 spin_lock_irq(&dev->lock);
1703
1704 if (dev->driver) {
1705 spin_unlock(&dev->lock);
1706 dev->driver->disconnect(&dev->gadget);
1707 spin_lock(&dev->lock);
1708
1709 /* empty queues */
170b778f 1710 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
55d402d8 1711 empty_req_queue(&dev->ep[tmp]);
55d402d8
TD		 1712
1713 }
1714
1715 /* disable ep0 */
1716 ep_init(dev->regs,
1717 &dev->ep[UDC_EP0IN_IX]);
1718
1719
1720 if (!soft_reset_occured) {
1721 /* init controller by soft reset */
1722 udc_soft_reset(dev);
1723 soft_reset_occured++;
1724 }
1725
1726 /* re-enable dev interrupts */
1727 udc_enable_dev_setup_interrupts(dev);
1728 /* back to full speed ? */
1729 if (use_fullspeed) {
1730 tmp = readl(&dev->regs->cfg);
1731 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1732 writel(tmp, &dev->regs->cfg);
1733 }
1734
1735 spin_unlock_irq(&dev->lock);
1736}
1737
1738/* Reset the UDC core */
1739static void udc_soft_reset(struct udc *dev)
1740{
1741 unsigned long flags;
1742
1743 DBG(dev, "Soft reset\n");
1744 /*
1745 * reset possible waiting interrupts, because int.
1746 * status is lost after soft reset,
1747 * ep int. status reset
1748 */
1749 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1750 /* device int. status reset */
1751 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1752
1753 spin_lock_irqsave(&udc_irq_spinlock, flags);
1754 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1755 readl(&dev->regs->cfg);
1756 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1757
1758}
1759
1760/* RDE timer callback to set RDE bit */
1761static void udc_timer_function(unsigned long v)
1762{
1763 u32 tmp;
1764
1765 spin_lock_irq(&udc_irq_spinlock);
1766
1767 if (set_rde > 0) {
1768 /*
1769 * open the fifo if fifo was filled on last timer call
1770 * conditionally
1771 */
1772 if (set_rde > 1) {
1773 /* set RDE to receive setup data */
1774 tmp = readl(&udc->regs->ctl);
1775 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1776 writel(tmp, &udc->regs->ctl);
1777 set_rde = -1;
1778 } else if (readl(&udc->regs->sts)
1779 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1780 /*
1781 * if fifo empty setup polling, do not just
1782 * open the fifo
1783 */
1784 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
170b778f 1785 if (!stop_timer)
55d402d8 1786 add_timer(&udc_timer);
55d402d8
TD		 1787 } else {
1788 /*
1789 * fifo contains data now, setup timer for opening
1790 * the fifo when timer expires to be able to receive
1791 * setup packets, when data packets gets queued by
1792 * gadget layer then timer will forced to expire with
1793 * set_rde=0 (RDE is set in udc_queue())
1794 */
1795 set_rde++;
1796 /* debug: lhadmot_timer_start = 221070 */
1797 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
170b778f 1798 if (!stop_timer)
55d402d8 1799 add_timer(&udc_timer);
55d402d8
TD		 1800 }
1801
1802 } else
1803 set_rde = -1; /* RDE was set by udc_queue() */
1804 spin_unlock_irq(&udc_irq_spinlock);
1805 if (stop_timer)
1806 complete(&on_exit);
1807
1808}
1809
1810/* Handle halt state, used in stall poll timer */
1811static void udc_handle_halt_state(struct udc_ep *ep)
1812{
1813 u32 tmp;
1814 /* set stall as long not halted */
1815 if (ep->halted == 1) {
1816 tmp = readl(&ep->regs->ctl);
1817 /* STALL cleared ? */
1818 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1819 /*
1820 * FIXME: MSC spec requires that stall remains
1821 * even on receivng of CLEAR_FEATURE HALT. So
1822 * we would set STALL again here to be compliant.
1823 * But with current mass storage drivers this does
1824 * not work (would produce endless host retries).
1825 * So we clear halt on CLEAR_FEATURE.
1826 *
1827 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1828 tmp |= AMD_BIT(UDC_EPCTL_S);
1829 writel(tmp, &ep->regs->ctl);*/
1830
1831 /* clear NAK by writing CNAK */
1832 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1833 writel(tmp, &ep->regs->ctl);
1834 ep->halted = 0;
1835 UDC_QUEUE_CNAK(ep, ep->num);
1836 }
1837 }
1838}
1839
1840/* Stall timer callback to poll S bit and set it again after */
1841static void udc_pollstall_timer_function(unsigned long v)
1842{
1843 struct udc_ep *ep;
1844 int halted = 0;
1845
1846 spin_lock_irq(&udc_stall_spinlock);
1847 /*
1848 * only one IN and OUT endpoints are handled
1849 * IN poll stall
1850 */
1851 ep = &udc->ep[UDC_EPIN_IX];
1852 udc_handle_halt_state(ep);
1853 if (ep->halted)
1854 halted = 1;
1855 /* OUT poll stall */
1856 ep = &udc->ep[UDC_EPOUT_IX];
1857 udc_handle_halt_state(ep);
1858 if (ep->halted)
1859 halted = 1;
1860
1861 /* setup timer again when still halted */
1862 if (!stop_pollstall_timer && halted) {
1863 udc_pollstall_timer.expires = jiffies +
1864 HZ * UDC_POLLSTALL_TIMER_USECONDS
1865 / (1000 * 1000);
1866 add_timer(&udc_pollstall_timer);
1867 }
1868 spin_unlock_irq(&udc_stall_spinlock);
1869
1870 if (stop_pollstall_timer)
1871 complete(&on_pollstall_exit);
1872}
1873
1874/* Inits endpoint 0 so that SETUP packets are processed */
1875static void activate_control_endpoints(struct udc *dev)
1876{
1877 u32 tmp;
1878
1879 DBG(dev, "activate_control_endpoints\n");
1880
1881 /* flush fifo */
1882 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1883 tmp |= AMD_BIT(UDC_EPCTL_F);
1884 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1885
1886 /* set ep0 directions */
1887 dev->ep[UDC_EP0IN_IX].in = 1;
1888 dev->ep[UDC_EP0OUT_IX].in = 0;
1889
1890 /* set buffer size (tx fifo entries) of EP0_IN */
1891 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1892 if (dev->gadget.speed == USB_SPEED_FULL)
1893 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1894 UDC_EPIN_BUFF_SIZE);
1895 else if (dev->gadget.speed == USB_SPEED_HIGH)
1896 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1897 UDC_EPIN_BUFF_SIZE);
1898 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1899
1900 /* set max packet size of EP0_IN */
1901 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1902 if (dev->gadget.speed == USB_SPEED_FULL)
1903 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1904 UDC_EP_MAX_PKT_SIZE);
1905 else if (dev->gadget.speed == USB_SPEED_HIGH)
1906 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1907 UDC_EP_MAX_PKT_SIZE);
1908 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1909
1910 /* set max packet size of EP0_OUT */
1911 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1912 if (dev->gadget.speed == USB_SPEED_FULL)
1913 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1914 UDC_EP_MAX_PKT_SIZE);
1915 else if (dev->gadget.speed == USB_SPEED_HIGH)
1916 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1917 UDC_EP_MAX_PKT_SIZE);
1918 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1919
1920 /* set max packet size of EP0 in UDC CSR */
1921 tmp = readl(&dev->csr->ne[0]);
1922 if (dev->gadget.speed == USB_SPEED_FULL)
1923 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1924 UDC_CSR_NE_MAX_PKT);
1925 else if (dev->gadget.speed == USB_SPEED_HIGH)
1926 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1927 UDC_CSR_NE_MAX_PKT);
1928 writel(tmp, &dev->csr->ne[0]);
1929
1930 if (use_dma) {
1931 dev->ep[UDC_EP0OUT_IX].td->status |=
1932 AMD_BIT(UDC_DMA_OUT_STS_L);
1933 /* write dma desc address */
1934 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1935 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1936 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1937 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1938 /* stop RDE timer */
1939 if (timer_pending(&udc_timer)) {
1940 set_rde = 0;
1941 mod_timer(&udc_timer, jiffies - 1);
1942 }
1943 /* stop pollstall timer */
170b778f 1944 if (timer_pending(&udc_pollstall_timer))
55d402d8 1945 mod_timer(&udc_pollstall_timer, jiffies - 1);
55d402d8
TD		 1946 /* enable DMA */
1947 tmp = readl(&dev->regs->ctl);
1948 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1949 | AMD_BIT(UDC_DEVCTL_RDE)
1950 | AMD_BIT(UDC_DEVCTL_TDE);
170b778f 1951 if (use_dma_bufferfill_mode)
55d402d8 1952 tmp |= AMD_BIT(UDC_DEVCTL_BF);
170b778f 1953 else if (use_dma_ppb_du)
55d402d8 1954 tmp |= AMD_BIT(UDC_DEVCTL_DU);
55d402d8
TD		 1955 writel(tmp, &dev->regs->ctl);
1956 }
1957
1958 /* clear NAK by writing CNAK for EP0IN */
1959 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1960 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1961 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1962 dev->ep[UDC_EP0IN_IX].naking = 0;
1963 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1964
1965 /* clear NAK by writing CNAK for EP0OUT */
1966 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1967 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1968 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1969 dev->ep[UDC_EP0OUT_IX].naking = 0;
1970 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1971}
1972
1973/* Make endpoint 0 ready for control traffic */
1974static int setup_ep0(struct udc *dev)
1975{
1976 activate_control_endpoints(dev);
1977 /* enable ep0 interrupts */
1978 udc_enable_ep0_interrupts(dev);
1979 /* enable device setup interrupts */
1980 udc_enable_dev_setup_interrupts(dev);
1981
1982 return 0;
1983}
1984
1985/* Called by gadget driver to register itself */
45005f69
FB		 1986static int amd5536_udc_start(struct usb_gadget *g,
1987 struct usb_gadget_driver *driver)
55d402d8 1988{
45005f69 1989 struct udc *dev = to_amd5536_udc(g);
55d402d8
TD		 1990 u32 tmp;
1991
55d402d8
TD		 1992 driver->driver.bus = NULL;
1993 dev->driver = driver;
55d402d8 1994
55d402d8
TD		 1995 /* Some gadget drivers use both ep0 directions.
1996 * NOTE: to gadget driver, ep0 is just one endpoint...
1997 */
1998 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1999 dev->ep[UDC_EP0IN_IX].ep.driver_data;
2000
55d402d8
TD		 2001 /* get ready for ep0 traffic */
2002 setup_ep0(dev);
2003
2004 /* clear SD */
2005 tmp = readl(&dev->regs->ctl);
2006 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
2007 writel(tmp, &dev->regs->ctl);
2008
2009 usb_connect(dev);
2010
2011 return 0;
2012}
55d402d8
TD		 2013
2014/* shutdown requests and disconnect from gadget */
2015static void
2016shutdown(struct udc *dev, struct usb_gadget_driver *driver)
2017__releases(dev->lock)
2018__acquires(dev->lock)
2019{
2020 int tmp;
2021
c5deb832
TD		 2022 /* empty queues and init hardware */
2023 udc_basic_init(dev);
45005f69 2024
c5deb832
TD		 2025 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
2026 empty_req_queue(&dev->ep[tmp]);
2027
55d402d8
TD		 2028 udc_setup_endpoints(dev);
2029}
2030
2031/* Called by gadget driver to unregister itself */
22835b80 2032static int amd5536_udc_stop(struct usb_gadget *g)
55d402d8 2033{
45005f69
FB		 2034 struct udc *dev = to_amd5536_udc(g);
2035 unsigned long flags;
55d402d8
TD		 2036 u32 tmp;
2037
55d402d8
TD		 2038 spin_lock_irqsave(&dev->lock, flags);
2039 udc_mask_unused_interrupts(dev);
21090f06 2040 shutdown(dev, NULL);
55d402d8
TD		 2041 spin_unlock_irqrestore(&dev->lock, flags);
2042
55d402d8
TD		 2043 dev->driver = NULL;
2044
2045 /* set SD */
2046 tmp = readl(&dev->regs->ctl);
2047 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2048 writel(tmp, &dev->regs->ctl);
2049
55d402d8
TD		 2050 return 0;
2051}
55d402d8
TD		 2052
2053/* Clear pending NAK bits */
2054static void udc_process_cnak_queue(struct udc *dev)
2055{
2056 u32 tmp;
2057 u32 reg;
2058
2059 /* check epin's */
2060 DBG(dev, "CNAK pending queue processing\n");
2061 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2062 if (cnak_pending & (1 << tmp)) {
2063 DBG(dev, "CNAK pending for ep%d\n", tmp);
2064 /* clear NAK by writing CNAK */
2065 reg = readl(&dev->ep[tmp].regs->ctl);
2066 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2067 writel(reg, &dev->ep[tmp].regs->ctl);
2068 dev->ep[tmp].naking = 0;
2069 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2070 }
2071 }
2072 /* ... and ep0out */
2073 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2074 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2075 /* clear NAK by writing CNAK */
2076 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2077 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2078 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2079 dev->ep[UDC_EP0OUT_IX].naking = 0;
2080 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2081 dev->ep[UDC_EP0OUT_IX].num);
2082 }
2083}
2084
2085/* Enabling RX DMA after setup packet */
2086static void udc_ep0_set_rde(struct udc *dev)
2087{
2088 if (use_dma) {
2089 /*
2090 * only enable RXDMA when no data endpoint enabled
2091 * or data is queued
2092 */
2093 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2094 udc_set_rde(dev);
2095 } else {
2096 /*
2097 * setup timer for enabling RDE (to not enable
2098 * RXFIFO DMA for data endpoints to early)
2099 */
2100 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2101 udc_timer.expires =
2102 jiffies + HZ/UDC_RDE_TIMER_DIV;
2103 set_rde = 1;
170b778f 2104 if (!stop_timer)
55d402d8 2105 add_timer(&udc_timer);
55d402d8
TD		 2106 }
2107 }
2108 }
2109}
2110
2111
2112/* Interrupt handler for data OUT traffic */
2113static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2114{
2115 irqreturn_t ret_val = IRQ_NONE;
2116 u32 tmp;
2117 struct udc_ep *ep;
2118 struct udc_request *req;
2119 unsigned int count;
2120 struct udc_data_dma *td = NULL;
2121 unsigned dma_done;
2122
2123 VDBG(dev, "ep%d irq\n", ep_ix);
2124 ep = &dev->ep[ep_ix];
2125
2126 tmp = readl(&ep->regs->sts);
2127 if (use_dma) {
2128 /* BNA event ? */
2129 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
5647a149 2130 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
55d402d8
TD		 2131 ep->num, readl(&ep->regs->desptr));
2132 /* clear BNA */
2133 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2134 if (!ep->cancel_transfer)
2135 ep->bna_occurred = 1;
2136 else
2137 ep->cancel_transfer = 0;
2138 ret_val = IRQ_HANDLED;
2139 goto finished;
2140 }
2141 }
2142 /* HE event ? */
2143 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
25985edc 2144 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
55d402d8
TD		 2145
2146 /* clear HE */
2147 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2148 ret_val = IRQ_HANDLED;
2149 goto finished;
2150 }
2151
2152 if (!list_empty(&ep->queue)) {
2153
2154 /* next request */
2155 req = list_entry(ep->queue.next,
2156 struct udc_request, queue);
2157 } else {
2158 req = NULL;
2159 udc_rxfifo_pending = 1;
2160 }
2161 VDBG(dev, "req = %p\n", req);
2162 /* fifo mode */
2163 if (!use_dma) {
2164
2165 /* read fifo */
2166 if (req && udc_rxfifo_read(ep, req)) {
2167 ret_val = IRQ_HANDLED;
2168
2169 /* finish */
2170 complete_req(ep, req, 0);
2171 /* next request */
2172 if (!list_empty(&ep->queue) && !ep->halted) {
2173 req = list_entry(ep->queue.next,
2174 struct udc_request, queue);
2175 } else
2176 req = NULL;
2177 }
2178
2179 /* DMA */
2180 } else if (!ep->cancel_transfer && req != NULL) {
2181 ret_val = IRQ_HANDLED;
2182
2183 /* check for DMA done */
2184 if (!use_dma_ppb) {
2185 dma_done = AMD_GETBITS(req->td_data->status,
2186 UDC_DMA_OUT_STS_BS);
2187 /* packet per buffer mode - rx bytes */
2188 } else {
2189 /*
2190 * if BNA occurred then recover desc. from
2191 * BNA dummy desc.
2192 */
2193 if (ep->bna_occurred) {
2194 VDBG(dev, "Recover desc. from BNA dummy\n");
2195 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2196 sizeof(struct udc_data_dma));
2197 ep->bna_occurred = 0;
2198 udc_init_bna_dummy(ep->req);
2199 }
2200 td = udc_get_last_dma_desc(req);
2201 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2202 }
2203 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2204 /* buffer fill mode - rx bytes */
2205 if (!use_dma_ppb) {
2206 /* received number bytes */
2207 count = AMD_GETBITS(req->td_data->status,
2208 UDC_DMA_OUT_STS_RXBYTES);
2209 VDBG(dev, "rx bytes=%u\n", count);
2210 /* packet per buffer mode - rx bytes */
2211 } else {
2212 VDBG(dev, "req->td_data=%p\n", req->td_data);
2213 VDBG(dev, "last desc = %p\n", td);
2214 /* received number bytes */
2215 if (use_dma_ppb_du) {
2216 /* every desc. counts bytes */
2217 count = udc_get_ppbdu_rxbytes(req);
2218 } else {
2219 /* last desc. counts bytes */
2220 count = AMD_GETBITS(td->status,
2221 UDC_DMA_OUT_STS_RXBYTES);
2222 if (!count && req->req.length
2223 == UDC_DMA_MAXPACKET) {
2224 /*
2225 * on 64k packets the RXBYTES
2226 * field is zero
2227 */
2228 count = UDC_DMA_MAXPACKET;
2229 }
2230 }
2231 VDBG(dev, "last desc rx bytes=%u\n", count);
2232 }
2233
2234 tmp = req->req.length - req->req.actual;
2235 if (count > tmp) {
2236 if ((tmp % ep->ep.maxpacket) != 0) {
2237 DBG(dev, "%s: rx %db, space=%db\n",
2238 ep->ep.name, count, tmp);
2239 req->req.status = -EOVERFLOW;
2240 }
2241 count = tmp;
2242 }
2243 req->req.actual += count;
2244 req->dma_going = 0;
2245 /* complete request */
2246 complete_req(ep, req, 0);
2247
2248 /* next request */
2249 if (!list_empty(&ep->queue) && !ep->halted) {
2250 req = list_entry(ep->queue.next,
2251 struct udc_request,
2252 queue);
2253 /*
2254 * DMA may be already started by udc_queue()
2255 * called by gadget drivers completion
2256 * routine. This happens when queue
2257 * holds one request only.
2258 */
2259 if (req->dma_going == 0) {
2260 /* next dma */
2261 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2262 goto finished;
2263 /* write desc pointer */
2264 writel(req->td_phys,
2265 &ep->regs->desptr);
2266 req->dma_going = 1;
2267 /* enable DMA */
2268 udc_set_rde(dev);
2269 }
2270 } else {
2271 /*
2272 * implant BNA dummy descriptor to allow
2273 * RXFIFO opening by RDE
2274 */
2275 if (ep->bna_dummy_req) {
2276 /* write desc pointer */
2277 writel(ep->bna_dummy_req->td_phys,
2278 &ep->regs->desptr);
2279 ep->bna_occurred = 0;
2280 }
2281
2282 /*
2283 * schedule timer for setting RDE if queue
2284 * remains empty to allow ep0 packets pass
2285 * through
2286 */
2287 if (set_rde != 0
2288 && !timer_pending(&udc_timer)) {
2289 udc_timer.expires =
2290 jiffies
2291 + HZ*UDC_RDE_TIMER_SECONDS;
2292 set_rde = 1;
170b778f 2293 if (!stop_timer)
55d402d8 2294 add_timer(&udc_timer);
55d402d8
TD		 2295 }
2296 if (ep->num != UDC_EP0OUT_IX)
2297 dev->data_ep_queued = 0;
2298 }
2299
2300 } else {
2301 /*
2302 * RX DMA must be reenabled for each desc in PPBDU mode
2303 * and must be enabled for PPBNDU mode in case of BNA
2304 */
2305 udc_set_rde(dev);
2306 }
2307
2308 } else if (ep->cancel_transfer) {
2309 ret_val = IRQ_HANDLED;
2310 ep->cancel_transfer = 0;
2311 }
2312
2313 /* check pending CNAKS */
2314 if (cnak_pending) {
2315 /* CNAk processing when rxfifo empty only */
170b778f 2316 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
55d402d8 2317 udc_process_cnak_queue(dev);
55d402d8
TD		 2318 }
2319
2320 /* clear OUT bits in ep status */
2321 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2322finished:
2323 return ret_val;
2324}
2325
2326/* Interrupt handler for data IN traffic */
2327static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2328{
2329 irqreturn_t ret_val = IRQ_NONE;
2330 u32 tmp;
2331 u32 epsts;
2332 struct udc_ep *ep;
2333 struct udc_request *req;
2334 struct udc_data_dma *td;
2335 unsigned dma_done;
2336 unsigned len;
2337
2338 ep = &dev->ep[ep_ix];
2339
2340 epsts = readl(&ep->regs->sts);
2341 if (use_dma) {
2342 /* BNA ? */
2343 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2344 dev_err(&dev->pdev->dev,
5647a149 2345 "BNA ep%din occurred - DESPTR = %08lx\n",
55d402d8
TD		 2346 ep->num,
2347 (unsigned long) readl(&ep->regs->desptr));
2348
2349 /* clear BNA */
2350 writel(epsts, &ep->regs->sts);
2351 ret_val = IRQ_HANDLED;
2352 goto finished;
2353 }
2354 }
2355 /* HE event ? */
2356 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2357 dev_err(&dev->pdev->dev,
5647a149 2358 "HE ep%dn occurred - DESPTR = %08lx\n",
55d402d8
TD		 2359 ep->num, (unsigned long) readl(&ep->regs->desptr));
2360
2361 /* clear HE */
2362 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2363 ret_val = IRQ_HANDLED;
2364 goto finished;
2365 }
2366
2367 /* DMA completion */
2368 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2369 VDBG(dev, "TDC set- completion\n");
2370 ret_val = IRQ_HANDLED;
2371 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2372 req = list_entry(ep->queue.next,
2373 struct udc_request, queue);
058e698b 2374 /*
25985edc 2375 * length bytes transferred
058e698b
JL		 2376 * check dma done of last desc. in PPBDU mode
2377 */
2378 if (use_dma_ppb_du) {
2379 td = udc_get_last_dma_desc(req);
2380 if (td) {
2381 dma_done =
2382 AMD_GETBITS(td->status,
2383 UDC_DMA_IN_STS_BS);
2384 /* don't care DMA done */
55d402d8
TD		 2385 req->req.actual = req->req.length;
2386 }
058e698b
JL		 2387 } else {
2388 /* assume all bytes transferred */
2389 req->req.actual = req->req.length;
2390 }
55d402d8 2391
058e698b
JL		 2392 if (req->req.actual == req->req.length) {
2393 /* complete req */
2394 complete_req(ep, req, 0);
2395 req->dma_going = 0;
2396 /* further request available ? */
2397 if (list_empty(&ep->queue)) {
2398 /* disable interrupt */
2399 tmp = readl(&dev->regs->ep_irqmsk);
2400 tmp |= AMD_BIT(ep->num);
2401 writel(tmp, &dev->regs->ep_irqmsk);
55d402d8
TD		 2402 }
2403 }
2404 }
2405 ep->cancel_transfer = 0;
2406
2407 }
2408 /*
2409 * status reg has IN bit set and TDC not set (if TDC was handled,
2410 * IN must not be handled (UDC defect) ?
2411 */
2412 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2413 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2414 ret_val = IRQ_HANDLED;
2415 if (!list_empty(&ep->queue)) {
2416 /* next request */
2417 req = list_entry(ep->queue.next,
2418 struct udc_request, queue);
2419 /* FIFO mode */
2420 if (!use_dma) {
2421 /* write fifo */
2422 udc_txfifo_write(ep, &req->req);
2423 len = req->req.length - req->req.actual;
1435db48
CR		 2424 if (len > ep->ep.maxpacket)
2425 len = ep->ep.maxpacket;
2426 req->req.actual += len;
55d402d8
TD		 2427 if (req->req.actual == req->req.length
2428 || (len != ep->ep.maxpacket)) {
2429 /* complete req */
2430 complete_req(ep, req, 0);
2431 }
2432 /* DMA */
2433 } else if (req && !req->dma_going) {
2434 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2435 req, req->td_data);
2436 if (req->td_data) {
2437
2438 req->dma_going = 1;
2439
2440 /*
2441 * unset L bit of first desc.
2442 * for chain
2443 */
2444 if (use_dma_ppb && req->req.length >
2445 ep->ep.maxpacket) {
2446 req->td_data->status &=
2447 AMD_CLEAR_BIT(
2448 UDC_DMA_IN_STS_L);
2449 }
2450
2451 /* write desc pointer */
2452 writel(req->td_phys, &ep->regs->desptr);
2453
2454 /* set HOST READY */
2455 req->td_data->status =
2456 AMD_ADDBITS(
2457 req->td_data->status,
2458 UDC_DMA_IN_STS_BS_HOST_READY,
2459 UDC_DMA_IN_STS_BS);
2460
2461 /* set poll demand bit */
2462 tmp = readl(&ep->regs->ctl);
2463 tmp |= AMD_BIT(UDC_EPCTL_P);
2464 writel(tmp, &ep->regs->ctl);
2465 }
2466 }
2467
c5deb832
TD		 2468 } else if (!use_dma && ep->in) {
2469 /* disable interrupt */
2470 tmp = readl(
2471 &dev->regs->ep_irqmsk);
2472 tmp |= AMD_BIT(ep->num);
2473 writel(tmp,
2474 &dev->regs->ep_irqmsk);
55d402d8
TD		 2475 }
2476 }
2477 /* clear status bits */
2478 writel(epsts, &ep->regs->sts);
2479
2480finished:
2481 return ret_val;
2482
2483}
2484
2485/* Interrupt handler for Control OUT traffic */
2486static irqreturn_t udc_control_out_isr(struct udc *dev)
2487__releases(dev->lock)
2488__acquires(dev->lock)
2489{
2490 irqreturn_t ret_val = IRQ_NONE;
2491 u32 tmp;
2492 int setup_supported;
2493 u32 count;
2494 int set = 0;
2495 struct udc_ep *ep;
2496 struct udc_ep *ep_tmp;
2497
2498 ep = &dev->ep[UDC_EP0OUT_IX];
2499
2500 /* clear irq */
2501 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2502
2503 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2504 /* check BNA and clear if set */
2505 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2506 VDBG(dev, "ep0: BNA set\n");
2507 writel(AMD_BIT(UDC_EPSTS_BNA),
2508 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2509 ep->bna_occurred = 1;
2510 ret_val = IRQ_HANDLED;
2511 goto finished;
2512 }
2513
2514 /* type of data: SETUP or DATA 0 bytes */
2515 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2516 VDBG(dev, "data_typ = %x\n", tmp);
2517
2518 /* setup data */
2519 if (tmp == UDC_EPSTS_OUT_SETUP) {
2520 ret_val = IRQ_HANDLED;
2521
2522 ep->dev->stall_ep0in = 0;
2523 dev->waiting_zlp_ack_ep0in = 0;
2524
2525 /* set NAK for EP0_IN */
2526 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2527 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2528 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2529 dev->ep[UDC_EP0IN_IX].naking = 1;
2530 /* get setup data */
2531 if (use_dma) {
2532
2533 /* clear OUT bits in ep status */
2534 writel(UDC_EPSTS_OUT_CLEAR,
2535 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2536
2537 setup_data.data[0] =
2538 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2539 setup_data.data[1] =
2540 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2541 /* set HOST READY */
2542 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2543 UDC_DMA_STP_STS_BS_HOST_READY;
2544 } else {
2545 /* read fifo */
2546 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2547 }
2548
2549 /* determine direction of control data */
2550 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2551 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2552 /* enable RDE */
2553 udc_ep0_set_rde(dev);
2554 set = 0;
2555 } else {
2556 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2557 /*
2558 * implant BNA dummy descriptor to allow RXFIFO opening
2559 * by RDE
2560 */
2561 if (ep->bna_dummy_req) {
2562 /* write desc pointer */
2563 writel(ep->bna_dummy_req->td_phys,
2564 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2565 ep->bna_occurred = 0;
2566 }
2567
2568 set = 1;
2569 dev->ep[UDC_EP0OUT_IX].naking = 1;
2570 /*
2571 * setup timer for enabling RDE (to not enable
2572 * RXFIFO DMA for data to early)
2573 */
2574 set_rde = 1;
2575 if (!timer_pending(&udc_timer)) {
2576 udc_timer.expires = jiffies +
2577 HZ/UDC_RDE_TIMER_DIV;
170b778f 2578 if (!stop_timer)
55d402d8 2579 add_timer(&udc_timer);
55d402d8
TD		 2580 }
2581 }
2582
2583 /*
2584 * mass storage reset must be processed here because
2585 * next packet may be a CLEAR_FEATURE HALT which would not
2586 * clear the stall bit when no STALL handshake was received
2587 * before (autostall can cause this)
2588 */
2589 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2590 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2591 DBG(dev, "MSC Reset\n");
2592 /*
2593 * clear stall bits
2594 * only one IN and OUT endpoints are handled
2595 */
2596 ep_tmp = &udc->ep[UDC_EPIN_IX];
2597 udc_set_halt(&ep_tmp->ep, 0);
2598 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2599 udc_set_halt(&ep_tmp->ep, 0);
2600 }
2601
2602 /* call gadget with setup data received */
2603 spin_unlock(&dev->lock);
2604 setup_supported = dev->driver->setup(&dev->gadget,
2605 &setup_data.request);
2606 spin_lock(&dev->lock);
2607
2608 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2609 /* ep0 in returns data (not zlp) on IN phase */
2610 if (setup_supported >= 0 && setup_supported <
2611 UDC_EP0IN_MAXPACKET) {
2612 /* clear NAK by writing CNAK in EP0_IN */
2613 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2614 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2615 dev->ep[UDC_EP0IN_IX].naking = 0;
2616 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2617
2618 /* if unsupported request then stall */
2619 } else if (setup_supported < 0) {
2620 tmp |= AMD_BIT(UDC_EPCTL_S);
2621 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2622 } else
2623 dev->waiting_zlp_ack_ep0in = 1;
2624
2625
2626 /* clear NAK by writing CNAK in EP0_OUT */
2627 if (!set) {
2628 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2629 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2630 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2631 dev->ep[UDC_EP0OUT_IX].naking = 0;
2632 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2633 }
2634
2635 if (!use_dma) {
2636 /* clear OUT bits in ep status */
2637 writel(UDC_EPSTS_OUT_CLEAR,
2638 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2639 }
2640
2641 /* data packet 0 bytes */
2642 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2643 /* clear OUT bits in ep status */
2644 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2645
2646 /* get setup data: only 0 packet */
2647 if (use_dma) {
2648 /* no req if 0 packet, just reactivate */
2649 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2650 VDBG(dev, "ZLP\n");
2651
2652 /* set HOST READY */
2653 dev->ep[UDC_EP0OUT_IX].td->status =
2654 AMD_ADDBITS(
2655 dev->ep[UDC_EP0OUT_IX].td->status,
2656 UDC_DMA_OUT_STS_BS_HOST_READY,
2657 UDC_DMA_OUT_STS_BS);
2658 /* enable RDE */
2659 udc_ep0_set_rde(dev);
2660 ret_val = IRQ_HANDLED;
2661
2662 } else {
2663 /* control write */
2664 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2665 /* re-program desc. pointer for possible ZLPs */
2666 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2667 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2668 /* enable RDE */
2669 udc_ep0_set_rde(dev);
2670 }
2671 } else {
2672
2673 /* received number bytes */
2674 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2675 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2676 /* out data for fifo mode not working */
2677 count = 0;
2678
2679 /* 0 packet or real data ? */
2680 if (count != 0) {
2681 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2682 } else {
2683 /* dummy read confirm */
2684 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2685 ret_val = IRQ_HANDLED;
2686 }
2687 }
2688 }
2689
2690 /* check pending CNAKS */
2691 if (cnak_pending) {
2692 /* CNAk processing when rxfifo empty only */
170b778f 2693 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
55d402d8 2694 udc_process_cnak_queue(dev);
55d402d8
TD		 2695 }
2696
2697finished:
2698 return ret_val;
2699}
2700
2701/* Interrupt handler for Control IN traffic */
2702static irqreturn_t udc_control_in_isr(struct udc *dev)
2703{
2704 irqreturn_t ret_val = IRQ_NONE;
2705 u32 tmp;
2706 struct udc_ep *ep;
2707 struct udc_request *req;
2708 unsigned len;
2709
2710 ep = &dev->ep[UDC_EP0IN_IX];
2711
2712 /* clear irq */
2713 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2714
2715 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2716 /* DMA completion */
2717 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
5647a149 2718 VDBG(dev, "isr: TDC clear\n");
55d402d8
TD		 2719 ret_val = IRQ_HANDLED;
2720
2721 /* clear TDC bit */
2722 writel(AMD_BIT(UDC_EPSTS_TDC),
2723 &dev->ep[UDC_EP0IN_IX].regs->sts);
2724
2725 /* status reg has IN bit set ? */
2726 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2727 ret_val = IRQ_HANDLED;
2728
2729 if (ep->dma) {
2730 /* clear IN bit */
2731 writel(AMD_BIT(UDC_EPSTS_IN),
2732 &dev->ep[UDC_EP0IN_IX].regs->sts);
2733 }
2734 if (dev->stall_ep0in) {
2735 DBG(dev, "stall ep0in\n");
2736 /* halt ep0in */
2737 tmp = readl(&ep->regs->ctl);
2738 tmp |= AMD_BIT(UDC_EPCTL_S);
2739 writel(tmp, &ep->regs->ctl);
2740 } else {
2741 if (!list_empty(&ep->queue)) {
2742 /* next request */
2743 req = list_entry(ep->queue.next,
2744 struct udc_request, queue);
2745
2746 if (ep->dma) {
2747 /* write desc pointer */
2748 writel(req->td_phys, &ep->regs->desptr);
2749 /* set HOST READY */
2750 req->td_data->status =
2751 AMD_ADDBITS(
2752 req->td_data->status,
2753 UDC_DMA_STP_STS_BS_HOST_READY,
2754 UDC_DMA_STP_STS_BS);
2755
2756 /* set poll demand bit */
2757 tmp =
2758 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2759 tmp |= AMD_BIT(UDC_EPCTL_P);
2760 writel(tmp,
2761 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2762
2763 /* all bytes will be transferred */
2764 req->req.actual = req->req.length;
2765
2766 /* complete req */
2767 complete_req(ep, req, 0);
2768
2769 } else {
2770 /* write fifo */
2771 udc_txfifo_write(ep, &req->req);
2772
25985edc 2773 /* lengh bytes transferred */
55d402d8
TD		 2774 len = req->req.length - req->req.actual;
2775 if (len > ep->ep.maxpacket)
2776 len = ep->ep.maxpacket;
2777
2778 req->req.actual += len;
2779 if (req->req.actual == req->req.length
2780 || (len != ep->ep.maxpacket)) {
2781 /* complete req */
2782 complete_req(ep, req, 0);
2783 }
2784 }
2785
2786 }
2787 }
2788 ep->halted = 0;
2789 dev->stall_ep0in = 0;
2790 if (!ep->dma) {
2791 /* clear IN bit */
2792 writel(AMD_BIT(UDC_EPSTS_IN),
2793 &dev->ep[UDC_EP0IN_IX].regs->sts);
2794 }
2795 }
2796
2797 return ret_val;
2798}
2799
2800
2801/* Interrupt handler for global device events */
2802static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2803__releases(dev->lock)
2804__acquires(dev->lock)
2805{
2806 irqreturn_t ret_val = IRQ_NONE;
2807 u32 tmp;
2808 u32 cfg;
2809 struct udc_ep *ep;
2810 u16 i;
2811 u8 udc_csr_epix;
2812
2813 /* SET_CONFIG irq ? */
2814 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2815 ret_val = IRQ_HANDLED;
2816
2817 /* read config value */
2818 tmp = readl(&dev->regs->sts);
2819 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2820 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2821 dev->cur_config = cfg;
2822 dev->set_cfg_not_acked = 1;
2823
2824 /* make usb request for gadget driver */
2825 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2826 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
fd05e720 2827 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
55d402d8
TD		 2828
2829 /* programm the NE registers */
2830 for (i = 0; i < UDC_EP_NUM; i++) {
2831 ep = &dev->ep[i];
2832 if (ep->in) {
2833
2834 /* ep ix in UDC CSR register space */
2835 udc_csr_epix = ep->num;
2836
2837
2838 /* OUT ep */
2839 } else {
2840 /* ep ix in UDC CSR register space */
2841 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2842 }
2843
2844 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2845 /* ep cfg */
2846 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2847 UDC_CSR_NE_CFG);
2848 /* write reg */
2849 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2850
2851 /* clear stall bits */
2852 ep->halted = 0;
2853 tmp = readl(&ep->regs->ctl);
2854 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2855 writel(tmp, &ep->regs->ctl);
2856 }
2857 /* call gadget zero with setup data received */
2858 spin_unlock(&dev->lock);
2859 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2860 spin_lock(&dev->lock);
2861
2862 } /* SET_INTERFACE ? */
2863 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2864 ret_val = IRQ_HANDLED;
2865
2866 dev->set_cfg_not_acked = 1;
2867 /* read interface and alt setting values */
2868 tmp = readl(&dev->regs->sts);
2869 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2870 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2871
2872 /* make usb request for gadget driver */
2873 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2874 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2875 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
fd05e720
AV		 2876 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2877 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
55d402d8
TD		 2878
2879 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2880 dev->cur_alt, dev->cur_intf);
2881
2882 /* programm the NE registers */
2883 for (i = 0; i < UDC_EP_NUM; i++) {
2884 ep = &dev->ep[i];
2885 if (ep->in) {
2886
2887 /* ep ix in UDC CSR register space */
2888 udc_csr_epix = ep->num;
2889
2890
2891 /* OUT ep */
2892 } else {
2893 /* ep ix in UDC CSR register space */
2894 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2895 }
2896
2897 /* UDC CSR reg */
2898 /* set ep values */
2899 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2900 /* ep interface */
2901 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2902 UDC_CSR_NE_INTF);
2903 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2904 /* ep alt */
2905 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2906 UDC_CSR_NE_ALT);
2907 /* write reg */
2908 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2909
2910 /* clear stall bits */
2911 ep->halted = 0;
2912 tmp = readl(&ep->regs->ctl);
2913 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2914 writel(tmp, &ep->regs->ctl);
2915 }
2916
2917 /* call gadget zero with setup data received */
2918 spin_unlock(&dev->lock);
2919 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2920 spin_lock(&dev->lock);
2921
2922 } /* USB reset */
2923 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2924 DBG(dev, "USB Reset interrupt\n");
2925 ret_val = IRQ_HANDLED;
2926
2927 /* allow soft reset when suspend occurs */
2928 soft_reset_occured = 0;
2929
2930 dev->waiting_zlp_ack_ep0in = 0;
2931 dev->set_cfg_not_acked = 0;
2932
2933 /* mask not needed interrupts */
2934 udc_mask_unused_interrupts(dev);
2935
2936 /* call gadget to resume and reset configs etc. */
2937 spin_unlock(&dev->lock);
2938 if (dev->sys_suspended && dev->driver->resume) {
2939 dev->driver->resume(&dev->gadget);
2940 dev->sys_suspended = 0;
2941 }
107d13c7 2942 usb_gadget_udc_reset(&dev->gadget, dev->driver);
55d402d8
TD		 2943 spin_lock(&dev->lock);
2944
2945 /* disable ep0 to empty req queue */
2946 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2947 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2948
2949 /* soft reset when rxfifo not empty */
2950 tmp = readl(&dev->regs->sts);
2951 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2952 && !soft_reset_after_usbreset_occured) {
2953 udc_soft_reset(dev);
2954 soft_reset_after_usbreset_occured++;
2955 }
2956
2957 /*
2958 * DMA reset to kill potential old DMA hw hang,
2959 * POLL bit is already reset by ep_init() through
2960 * disconnect()
2961 */
2962 DBG(dev, "DMA machine reset\n");
2963 tmp = readl(&dev->regs->cfg);
2964 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2965 writel(tmp, &dev->regs->cfg);
2966
2967 /* put into initial config */
2968 udc_basic_init(dev);
2969
2970 /* enable device setup interrupts */
2971 udc_enable_dev_setup_interrupts(dev);
2972
2973 /* enable suspend interrupt */
2974 tmp = readl(&dev->regs->irqmsk);
2975 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2976 writel(tmp, &dev->regs->irqmsk);
2977
2978 } /* USB suspend */
2979 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2980 DBG(dev, "USB Suspend interrupt\n");
2981 ret_val = IRQ_HANDLED;
2982 if (dev->driver->suspend) {
2983 spin_unlock(&dev->lock);
2984 dev->sys_suspended = 1;
2985 dev->driver->suspend(&dev->gadget);
2986 spin_lock(&dev->lock);
2987 }
2988 } /* new speed ? */
2989 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2990 DBG(dev, "ENUM interrupt\n");
2991 ret_val = IRQ_HANDLED;
2992 soft_reset_after_usbreset_occured = 0;
2993
2994 /* disable ep0 to empty req queue */
2995 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2996 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2997
2998 /* link up all endpoints */
2999 udc_setup_endpoints(dev);
e538dfda
MN		 3000 dev_info(&dev->pdev->dev, "Connect: %s\n",
3001 usb_speed_string(dev->gadget.speed));
55d402d8
TD		 3002
3003 /* init ep 0 */
3004 activate_control_endpoints(dev);
3005
3006 /* enable ep0 interrupts */
3007 udc_enable_ep0_interrupts(dev);
3008 }
3009 /* session valid change interrupt */
3010 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
3011 DBG(dev, "USB SVC interrupt\n");
3012 ret_val = IRQ_HANDLED;
3013
3014 /* check that session is not valid to detect disconnect */
3015 tmp = readl(&dev->regs->sts);
3016 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
3017 /* disable suspend interrupt */
3018 tmp = readl(&dev->regs->irqmsk);
3019 tmp |= AMD_BIT(UDC_DEVINT_US);
3020 writel(tmp, &dev->regs->irqmsk);
3021 DBG(dev, "USB Disconnect (session valid low)\n");
3022 /* cleanup on disconnect */
3023 usb_disconnect(udc);
3024 }
3025
3026 }
3027
3028 return ret_val;
3029}
3030
3031/* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3032static irqreturn_t udc_irq(int irq, void *pdev)
3033{
3034 struct udc *dev = pdev;
3035 u32 reg;
3036 u16 i;
3037 u32 ep_irq;
3038 irqreturn_t ret_val = IRQ_NONE;
3039
3040 spin_lock(&dev->lock);
3041
3042 /* check for ep irq */
3043 reg = readl(&dev->regs->ep_irqsts);
3044 if (reg) {
3045 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3046 ret_val |= udc_control_out_isr(dev);
3047 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3048 ret_val |= udc_control_in_isr(dev);
3049
3050 /*
3051 * data endpoint
3052 * iterate ep's
3053 */
3054 for (i = 1; i < UDC_EP_NUM; i++) {
3055 ep_irq = 1 << i;
3056 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3057 continue;
3058
3059 /* clear irq status */
3060 writel(ep_irq, &dev->regs->ep_irqsts);
3061
3062 /* irq for out ep ? */
3063 if (i > UDC_EPIN_NUM)
3064 ret_val |= udc_data_out_isr(dev, i);
3065 else
3066 ret_val |= udc_data_in_isr(dev, i);
3067 }
3068
3069 }
3070
3071
3072 /* check for dev irq */
3073 reg = readl(&dev->regs->irqsts);
3074 if (reg) {
3075 /* clear irq */
3076 writel(reg, &dev->regs->irqsts);
3077 ret_val |= udc_dev_isr(dev, reg);
3078 }
3079
3080
3081 spin_unlock(&dev->lock);
3082 return ret_val;
3083}
3084
3085/* Tears down device */
3086static void gadget_release(struct device *pdev)
3087{
3088 struct amd5536udc *dev = dev_get_drvdata(pdev);
3089 kfree(dev);
3090}
3091
3092/* Cleanup on device remove */
3093static void udc_remove(struct udc *dev)
3094{
3095 /* remove timer */
3096 stop_timer++;
3097 if (timer_pending(&udc_timer))
3098 wait_for_completion(&on_exit);
3099 if (udc_timer.data)
3100 del_timer_sync(&udc_timer);
3101 /* remove pollstall timer */
3102 stop_pollstall_timer++;
3103 if (timer_pending(&udc_pollstall_timer))
3104 wait_for_completion(&on_pollstall_exit);
3105 if (udc_pollstall_timer.data)
3106 del_timer_sync(&udc_pollstall_timer);
3107 udc = NULL;
3108}
3109
3110/* Reset all pci context */
3111static void udc_pci_remove(struct pci_dev *pdev)
3112{
3113 struct udc *dev;
3114
3115 dev = pci_get_drvdata(pdev);
3116
0f91349b 3117 usb_del_gadget_udc(&udc->gadget);
55d402d8
TD		 3118 /* gadget driver must not be registered */
3119 BUG_ON(dev->driver != NULL);
3120
3121 /* dma pool cleanup */
3122 if (dev->data_requests)
3123 pci_pool_destroy(dev->data_requests);
3124
3125 if (dev->stp_requests) {
3126 /* cleanup DMA desc's for ep0in */
3127 pci_pool_free(dev->stp_requests,
3128 dev->ep[UDC_EP0OUT_IX].td_stp,
3129 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3130 pci_pool_free(dev->stp_requests,
3131 dev->ep[UDC_EP0OUT_IX].td,
3132 dev->ep[UDC_EP0OUT_IX].td_phys);
3133
3134 pci_pool_destroy(dev->stp_requests);
3135 }
3136
3137 /* reset controller */
3138 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3139 if (dev->irq_registered)
3140 free_irq(pdev->irq, dev);
3141 if (dev->regs)
3142 iounmap(dev->regs);
3143 if (dev->mem_region)
3144 release_mem_region(pci_resource_start(pdev, 0),
3145 pci_resource_len(pdev, 0));
3146 if (dev->active)
3147 pci_disable_device(pdev);
3148
55d402d8
TD		 3149 udc_remove(dev);
3150}
3151
3152/* create dma pools on init */
3153static int init_dma_pools(struct udc *dev)
3154{
3155 struct udc_stp_dma *td_stp;
3156 struct udc_data_dma *td_data;
3157 int retval;
3158
3159 /* consistent DMA mode setting ? */
3160 if (use_dma_ppb) {
3161 use_dma_bufferfill_mode = 0;
3162 } else {
3163 use_dma_ppb_du = 0;
3164 use_dma_bufferfill_mode = 1;
3165 }
3166
3167 /* DMA setup */
3168 dev->data_requests = dma_pool_create("data_requests", NULL,
3169 sizeof(struct udc_data_dma), 0, 0);
3170 if (!dev->data_requests) {
3171 DBG(dev, "can't get request data pool\n");
3172 retval = -ENOMEM;
3173 goto finished;
3174 }
3175
3176 /* EP0 in dma regs = dev control regs */
3177 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3178
3179 /* dma desc for setup data */
3180 dev->stp_requests = dma_pool_create("setup requests", NULL,
3181 sizeof(struct udc_stp_dma), 0, 0);
3182 if (!dev->stp_requests) {
3183 DBG(dev, "can't get stp request pool\n");
3184 retval = -ENOMEM;
3185 goto finished;
3186 }
3187 /* setup */
3188 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3189 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3190 if (td_stp == NULL) {
3191 retval = -ENOMEM;
3192 goto finished;
3193 }
3194 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3195
3196 /* data: 0 packets !? */
3197 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3198 &dev->ep[UDC_EP0OUT_IX].td_phys);
3199 if (td_data == NULL) {
3200 retval = -ENOMEM;
3201 goto finished;
3202 }
3203 dev->ep[UDC_EP0OUT_IX].td = td_data;
3204 return 0;
3205
3206finished:
3207 return retval;
3208}
3209
3210/* Called by pci bus driver to init pci context */
3211static int udc_pci_probe(
3212 struct pci_dev *pdev,
3213 const struct pci_device_id *id
3214)
3215{
3216 struct udc *dev;
3217 unsigned long resource;
3218 unsigned long len;
3219 int retval = 0;
3220
3221 /* one udc only */
3222 if (udc) {
3223 dev_dbg(&pdev->dev, "already probed\n");
3224 return -EBUSY;
3225 }
3226
3227 /* init */
3228 dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3229 if (!dev) {
3230 retval = -ENOMEM;
3231 goto finished;
3232 }
55d402d8
TD		 3233
3234 /* pci setup */
3235 if (pci_enable_device(pdev) < 0) {
73d79aab 3236 kfree(dev);
af3d305c 3237 dev = NULL;
55d402d8
TD		 3238 retval = -ENODEV;
3239 goto finished;
3240 }
3241 dev->active = 1;
3242
3243 /* PCI resource allocation */
3244 resource = pci_resource_start(pdev, 0);
3245 len = pci_resource_len(pdev, 0);
3246
3247 if (!request_mem_region(resource, len, name)) {
3248 dev_dbg(&pdev->dev, "pci device used already\n");
73d79aab 3249 kfree(dev);
af3d305c 3250 dev = NULL;
55d402d8
TD		 3251 retval = -EBUSY;
3252 goto finished;
3253 }
3254 dev->mem_region = 1;
3255
3256 dev->virt_addr = ioremap_nocache(resource, len);
3257 if (dev->virt_addr == NULL) {
3258 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
73d79aab 3259 kfree(dev);
af3d305c 3260 dev = NULL;
55d402d8
TD		 3261 retval = -EFAULT;
3262 goto finished;
3263 }
3264
3265 if (!pdev->irq) {
25e14c1f 3266 dev_err(&pdev->dev, "irq not set\n");
73d79aab 3267 kfree(dev);
af3d305c 3268 dev = NULL;
55d402d8
TD		 3269 retval = -ENODEV;
3270 goto finished;
3271 }
3272
c5deb832
TD		 3273 spin_lock_init(&dev->lock);
3274 /* udc csr registers base */
3275 dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3276 /* dev registers base */
3277 dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3278 /* ep registers base */
3279 dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3280 /* fifo's base */
3281 dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3282 dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3283
55d402d8 3284 if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
25e14c1f 3285 dev_dbg(&pdev->dev, "request_irq(%d) fail\n", pdev->irq);
73d79aab 3286 kfree(dev);
af3d305c 3287 dev = NULL;
55d402d8
TD		 3288 retval = -EBUSY;
3289 goto finished;
3290 }
3291 dev->irq_registered = 1;
3292
3293 pci_set_drvdata(pdev, dev);
3294
1d3ee41e
AK		 3295 /* chip revision for Hs AMD5536 */
3296 dev->chiprev = pdev->revision;
55d402d8
TD		 3297
3298 pci_set_master(pdev);
51745281 3299 pci_try_set_mwi(pdev);
55d402d8 3300
55d402d8
TD		 3301 /* init dma pools */
3302 if (use_dma) {
3303 retval = init_dma_pools(dev);
3304 if (retval != 0)
3305 goto finished;
3306 }
3307
3308 dev->phys_addr = resource;
3309 dev->irq = pdev->irq;
3310 dev->pdev = pdev;
55d402d8
TD		 3311
3312 /* general probing */
3313 if (udc_probe(dev) == 0)
3314 return 0;
3315
3316finished:
3317 if (dev)
3318 udc_pci_remove(pdev);
3319 return retval;
3320}
3321
3322/* general probe */
3323static int udc_probe(struct udc *dev)
3324{
3325 char tmp[128];
3326 u32 reg;
3327 int retval;
3328
3329 /* mark timer as not initialized */
3330 udc_timer.data = 0;
3331 udc_pollstall_timer.data = 0;
3332
3333 /* device struct setup */
55d402d8
TD		 3334 dev->gadget.ops = &udc_ops;
3335
0031a06e 3336 dev_set_name(&dev->gadget.dev, "gadget");
55d402d8 3337 dev->gadget.name = name;
d327ab5b 3338 dev->gadget.max_speed = USB_SPEED_HIGH;
55d402d8 3339
55d402d8
TD		 3340 /* init registers, interrupts, ... */
3341 startup_registers(dev);
3342
3343 dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3344
3345 snprintf(tmp, sizeof tmp, "%d", dev->irq);
3346 dev_info(&dev->pdev->dev,
3347 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3348 tmp, dev->phys_addr, dev->chiprev,
3349 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3350 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3351 if (dev->chiprev == UDC_HSA0_REV) {
3352 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3353 retval = -ENODEV;
3354 goto finished;
3355 }
3356 dev_info(&dev->pdev->dev,
3357 "driver version: %s(for Geode5536 B1)\n", tmp);
3358 udc = dev;
3359
e1f07ced
FB		 3360 retval = usb_add_gadget_udc_release(&udc->pdev->dev, &dev->gadget,
3361 gadget_release);
0f91349b
SAS		 3362 if (retval)
3363 goto finished;
3364
55d402d8
TD		 3365 /* timer init */
3366 init_timer(&udc_timer);
3367 udc_timer.function = udc_timer_function;
3368 udc_timer.data = 1;
3369 /* timer pollstall init */
3370 init_timer(&udc_pollstall_timer);
3371 udc_pollstall_timer.function = udc_pollstall_timer_function;
3372 udc_pollstall_timer.data = 1;
3373
3374 /* set SD */
3375 reg = readl(&dev->regs->ctl);
3376 reg |= AMD_BIT(UDC_DEVCTL_SD);
3377 writel(reg, &dev->regs->ctl);
3378
3379 /* print dev register info */
3380 print_regs(dev);
3381
3382 return 0;
3383
3384finished:
3385 return retval;
3386}
3387
3388/* Initiates a remote wakeup */
3389static int udc_remote_wakeup(struct udc *dev)
3390{
3391 unsigned long flags;
3392 u32 tmp;
3393
3394 DBG(dev, "UDC initiates remote wakeup\n");
3395
3396 spin_lock_irqsave(&dev->lock, flags);
3397
3398 tmp = readl(&dev->regs->ctl);
3399 tmp |= AMD_BIT(UDC_DEVCTL_RES);
3400 writel(tmp, &dev->regs->ctl);
3401 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3402 writel(tmp, &dev->regs->ctl);
3403
3404 spin_unlock_irqrestore(&dev->lock, flags);
3405 return 0;
3406}
3407
3408/* PCI device parameters */
9510ecee 3409static const struct pci_device_id pci_id[] = {
55d402d8
TD		 3410 {
3411 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3412 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3413 .class_mask = 0xffffffff,
3414 },
3415 {},
3416};
3417MODULE_DEVICE_TABLE(pci, pci_id);
3418
3419/* PCI functions */
3420static struct pci_driver udc_pci_driver = {
3421 .name = (char *) name,
3422 .id_table = pci_id,
3423 .probe = udc_pci_probe,
3424 .remove = udc_pci_remove,
3425};
3426
3cdb7721 3427module_pci_driver(udc_pci_driver);
55d402d8
TD		 3428
3429MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3430MODULE_AUTHOR("Thomas Dahlmann");
3431MODULE_LICENSE("GPL");
3432
Linux 6.x block layer and io_uring tree(s)