[linux-2.6-block.git] / drivers / usb / dwc3 / dwc3-omap.c

/**
 * dwc3-omap.c - OMAP Specific Glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2  of
 * the License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dwc3-omap.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/extcon.h>
#include <linux/regulator/consumer.h>

#include <linux/usb/otg.h>

/*
 * All these registers belong to OMAP's Wrapper around the
 * DesignWare USB3 Core.
 */

#define USBOTGSS_REVISION			0x0000
#define USBOTGSS_SYSCONFIG			0x0010
#define USBOTGSS_IRQ_EOI			0x0020
#define USBOTGSS_EOI_OFFSET			0x0008
#define USBOTGSS_IRQSTATUS_RAW_0		0x0024
#define USBOTGSS_IRQSTATUS_0			0x0028
#define USBOTGSS_IRQENABLE_SET_0		0x002c
#define USBOTGSS_IRQENABLE_CLR_0		0x0030
#define USBOTGSS_IRQ0_OFFSET			0x0004
#define USBOTGSS_IRQSTATUS_RAW_1		0x0030
#define USBOTGSS_IRQSTATUS_1			0x0034
#define USBOTGSS_IRQENABLE_SET_1		0x0038
#define USBOTGSS_IRQENABLE_CLR_1		0x003c
#define USBOTGSS_IRQSTATUS_RAW_2		0x0040
#define USBOTGSS_IRQSTATUS_2			0x0044
#define USBOTGSS_IRQENABLE_SET_2		0x0048
#define USBOTGSS_IRQENABLE_CLR_2		0x004c
#define USBOTGSS_IRQSTATUS_RAW_3		0x0050
#define USBOTGSS_IRQSTATUS_3			0x0054
#define USBOTGSS_IRQENABLE_SET_3		0x0058
#define USBOTGSS_IRQENABLE_CLR_3		0x005c
#define USBOTGSS_IRQSTATUS_EOI_MISC		0x0030
#define USBOTGSS_IRQSTATUS_RAW_MISC		0x0034
#define USBOTGSS_IRQSTATUS_MISC			0x0038
#define USBOTGSS_IRQENABLE_SET_MISC		0x003c
#define USBOTGSS_IRQENABLE_CLR_MISC		0x0040
#define USBOTGSS_IRQMISC_OFFSET			0x03fc
#define USBOTGSS_UTMI_OTG_CTRL			0x0080
#define USBOTGSS_UTMI_OTG_STATUS		0x0084
#define USBOTGSS_UTMI_OTG_OFFSET		0x0480
#define USBOTGSS_TXFIFO_DEPTH			0x0508
#define USBOTGSS_RXFIFO_DEPTH			0x050c
#define USBOTGSS_MMRAM_OFFSET			0x0100
#define USBOTGSS_FLADJ				0x0104
#define USBOTGSS_DEBUG_CFG			0x0108
#define USBOTGSS_DEBUG_DATA			0x010c
#define USBOTGSS_DEV_EBC_EN			0x0110
#define USBOTGSS_DEBUG_OFFSET			0x0600

/* SYSCONFIG REGISTER */
#define USBOTGSS_SYSCONFIG_DMADISABLE		(1 << 16)

/* IRQ_EOI REGISTER */
#define USBOTGSS_IRQ_EOI_LINE_NUMBER		(1 << 0)

/* IRQS0 BITS */
#define USBOTGSS_IRQO_COREIRQ_ST		(1 << 0)

/* IRQMISC BITS */
#define USBOTGSS_IRQMISC_DMADISABLECLR		(1 << 17)
#define USBOTGSS_IRQMISC_OEVT			(1 << 16)
#define USBOTGSS_IRQMISC_DRVVBUS_RISE		(1 << 13)
#define USBOTGSS_IRQMISC_CHRGVBUS_RISE		(1 << 12)
#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE	(1 << 11)
#define USBOTGSS_IRQMISC_IDPULLUP_RISE		(1 << 8)
#define USBOTGSS_IRQMISC_DRVVBUS_FALL		(1 << 5)
#define USBOTGSS_IRQMISC_CHRGVBUS_FALL		(1 << 4)
#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL		(1 << 3)
#define USBOTGSS_IRQMISC_IDPULLUP_FALL		(1 << 0)

/* UTMI_OTG_CTRL REGISTER */
#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS		(1 << 5)
#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS		(1 << 4)
#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS	(1 << 3)
#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP		(1 << 0)

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	(1 << 31)
#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	(1 << 9)
#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		(1 << 4)
#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	(1 << 3)
#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	(1 << 2)
#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	(1 << 1)

struct dwc3_omap {
	struct device		*dev;

	int			irq;
	void __iomem		*base;

	u32			utmi_otg_status;
	u32			utmi_otg_offset;
	u32			irqmisc_offset;
	u32			irq_eoi_offset;
	u32			debug_offset;
	u32			irq0_offset;

	u32			dma_status:1;

	struct extcon_specific_cable_nb extcon_vbus_dev;
	struct extcon_specific_cable_nb extcon_id_dev;
	struct notifier_block	vbus_nb;
	struct notifier_block	id_nb;

	struct regulator	*vbus_reg;
};

enum omap_dwc3_vbus_id_status {
	OMAP_DWC3_ID_FLOAT,
	OMAP_DWC3_ID_GROUND,
	OMAP_DWC3_VBUS_OFF,
	OMAP_DWC3_VBUS_VALID,
};

static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
{
	return readl(base + offset);
}

static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
{
	writel(value, base + offset);
}

static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
							omap->utmi_otg_offset);
}

static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
					omap->utmi_otg_offset, value);

}

static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
						omap->irq0_offset);
}

static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
						omap->irq0_offset, value);

}

static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
						omap->irqmisc_offset);
}

static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
					omap->irqmisc_offset, value);

}

static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
						omap->irqmisc_offset, value);

}

static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
						omap->irq0_offset, value);
}

static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
	enum omap_dwc3_vbus_id_status status)
{
	int	ret;
	u32	val;

	switch (status) {
	case OMAP_DWC3_ID_GROUND:
		dev_dbg(omap->dev, "ID GND\n");

		if (omap->vbus_reg) {
			ret = regulator_enable(omap->vbus_reg);
			if (ret) {
				dev_dbg(omap->dev, "regulator enable failed\n");
				return;
			}
		}

		val = dwc3_omap_read_utmi_status(omap);
		val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
				| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
				| USBOTGSS_UTMI_OTG_STATUS_SESSEND);
		val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
				| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
		dwc3_omap_write_utmi_status(omap, val);
		break;

	case OMAP_DWC3_VBUS_VALID:
		dev_dbg(omap->dev, "VBUS Connect\n");

		val = dwc3_omap_read_utmi_status(omap);
		val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
		val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
				| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
				| USBOTGSS_UTMI_OTG_STATUS_SESSVALID
				| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
		dwc3_omap_write_utmi_status(omap, val);
		break;

	case OMAP_DWC3_ID_FLOAT:
		if (omap->vbus_reg)
			regulator_disable(omap->vbus_reg);

	case OMAP_DWC3_VBUS_OFF:
		dev_dbg(omap->dev, "VBUS Disconnect\n");

		val = dwc3_omap_read_utmi_status(omap);
		val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
				| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
				| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
		val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
				| USBOTGSS_UTMI_OTG_STATUS_IDDIG;
		dwc3_omap_write_utmi_status(omap, val);
		break;

	default:
		dev_dbg(omap->dev, "invalid state\n");
	}
}

static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;
	u32			reg;

	reg = dwc3_omap_read_irqmisc_status(omap);

	if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
		dev_dbg(omap->dev, "DMA Disable was Cleared\n");
		omap->dma_status = false;
	}

	if (reg & USBOTGSS_IRQMISC_OEVT)
		dev_dbg(omap->dev, "OTG Event\n");

	if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
		dev_dbg(omap->dev, "DRVVBUS Rise\n");

	if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
		dev_dbg(omap->dev, "CHRGVBUS Rise\n");

	if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
		dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");

	if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
		dev_dbg(omap->dev, "IDPULLUP Rise\n");

	if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
		dev_dbg(omap->dev, "DRVVBUS Fall\n");

	if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
		dev_dbg(omap->dev, "CHRGVBUS Fall\n");

	if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
		dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");

	if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
		dev_dbg(omap->dev, "IDPULLUP Fall\n");

	dwc3_omap_write_irqmisc_status(omap, reg);

	reg = dwc3_omap_read_irq0_status(omap);

	dwc3_omap_write_irq0_status(omap, reg);

	return IRQ_HANDLED;
}

static int dwc3_omap_remove_core(struct device *dev, void *c)
{
	struct platform_device *pdev = to_platform_device(dev);

	platform_device_unregister(pdev);

	return 0;
}

static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
{
	u32			reg;

	/* enable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_write_irq0_set(omap, reg);

	reg = (USBOTGSS_IRQMISC_OEVT |
			USBOTGSS_IRQMISC_DRVVBUS_RISE |
			USBOTGSS_IRQMISC_CHRGVBUS_RISE |
			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
			USBOTGSS_IRQMISC_IDPULLUP_RISE |
			USBOTGSS_IRQMISC_DRVVBUS_FALL |
			USBOTGSS_IRQMISC_CHRGVBUS_FALL |
			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
			USBOTGSS_IRQMISC_IDPULLUP_FALL);

	dwc3_omap_write_irqmisc_set(omap, reg);
}

static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
{
	/* disable all IRQs */
	dwc3_omap_write_irqmisc_set(omap, 0x00);
	dwc3_omap_write_irq0_set(omap, 0x00);
}

static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);

static int dwc3_omap_id_notifier(struct notifier_block *nb,
	unsigned long event, void *ptr)
{
	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);

	if (event)
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);

	return NOTIFY_DONE;
}

static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
	unsigned long event, void *ptr)
{
	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);

	if (event)
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);

	return NOTIFY_DONE;
}

static int dwc3_omap_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;

	struct dwc3_omap	*omap;
	struct resource		*res;
	struct device		*dev = &pdev->dev;
	struct extcon_dev	*edev;
	struct regulator	*vbus_reg = NULL;

	int			ret;
	int			irq;

	int			utmi_mode = 0;

	u32			reg;

	void __iomem		*base;

	if (!node) {
		dev_err(dev, "device node not found\n");
		return -EINVAL;
	}

	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
	if (!omap) {
		dev_err(dev, "not enough memory\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, omap);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	if (of_property_read_bool(node, "vbus-supply")) {
		vbus_reg = devm_regulator_get(dev, "vbus");
		if (IS_ERR(vbus_reg)) {
			dev_err(dev, "vbus init failed\n");
			return PTR_ERR(vbus_reg);
		}
	}

	omap->dev	= dev;
	omap->irq	= irq;
	omap->base	= base;
	omap->vbus_reg	= vbus_reg;
	dev->dma_mask	= &dwc3_omap_dma_mask;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "get_sync failed with err %d\n", ret);
		goto err0;
	}

	/*
	 * Differentiate between OMAP5 and AM437x.
	 *
	 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
	 * though there are changes in wrapper register offsets.
	 *
	 * Using dt compatible to differentiate AM437x.
	 */

	if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
		omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
		omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
		omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
		omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
		omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
	}

	reg = dwc3_omap_read_utmi_status(omap);

	of_property_read_u32(node, "utmi-mode", &utmi_mode);

	switch (utmi_mode) {
	case DWC3_OMAP_UTMI_MODE_SW:
		reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
		break;
	case DWC3_OMAP_UTMI_MODE_HW:
		reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
		break;
	default:
		dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
	}

	dwc3_omap_write_utmi_status(omap, reg);

	/* check the DMA Status */
	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);

	ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
			"dwc3-omap", omap);
	if (ret) {
		dev_err(dev, "failed to request IRQ #%d --> %d\n",
				omap->irq, ret);
		goto err1;
	}

	dwc3_omap_enable_irqs(omap);

	if (of_property_read_bool(node, "extcon")) {
		edev = extcon_get_edev_by_phandle(dev, 0);
		if (IS_ERR(edev)) {
			dev_vdbg(dev, "couldn't get extcon device\n");
			ret = -EPROBE_DEFER;
			goto err2;
		}

		omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
		ret = extcon_register_interest(&omap->extcon_vbus_dev,
			edev->name, "USB", &omap->vbus_nb);
		if (ret < 0)
			dev_vdbg(dev, "failed to register notifier for USB\n");
		omap->id_nb.notifier_call = dwc3_omap_id_notifier;
		ret = extcon_register_interest(&omap->extcon_id_dev, edev->name,
					 "USB-HOST", &omap->id_nb);
		if (ret < 0)
			dev_vdbg(dev,
				"failed to register notifier for USB-HOST\n");

		if (extcon_get_cable_state(edev, "USB") == true)
			dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
		if (extcon_get_cable_state(edev, "USB-HOST") == true)
			dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	}

	ret = of_platform_populate(node, NULL, NULL, dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to create dwc3 core\n");
		goto err3;
	}

	return 0;

err3:
	if (omap->extcon_vbus_dev.edev)
		extcon_unregister_interest(&omap->extcon_vbus_dev);
	if (omap->extcon_id_dev.edev)
		extcon_unregister_interest(&omap->extcon_id_dev);

err2:
	dwc3_omap_disable_irqs(omap);

err1:
	pm_runtime_put_sync(dev);

err0:
	pm_runtime_disable(dev);

	return ret;
}

static int dwc3_omap_remove(struct platform_device *pdev)
{
	struct dwc3_omap	*omap = platform_get_drvdata(pdev);

	if (omap->extcon_vbus_dev.edev)
		extcon_unregister_interest(&omap->extcon_vbus_dev);
	if (omap->extcon_id_dev.edev)
		extcon_unregister_interest(&omap->extcon_id_dev);
	dwc3_omap_disable_irqs(omap);
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);

	return 0;
}

static const struct of_device_id of_dwc3_match[] = {
	{
		.compatible =	"ti,dwc3"
	},
	{
		.compatible =	"ti,am437x-dwc3"
	},
	{ },
};
MODULE_DEVICE_TABLE(of, of_dwc3_match);

#ifdef CONFIG_PM_SLEEP
static int dwc3_omap_prepare(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_disable_irqs(omap);

	return 0;
}

static void dwc3_omap_complete(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_enable_irqs(omap);
}

static int dwc3_omap_suspend(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);

	return 0;
}

static int dwc3_omap_resume(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);

	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;
}

static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
	.prepare	= dwc3_omap_prepare,
	.complete	= dwc3_omap_complete,

	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
};

#define DEV_PM_OPS	(&dwc3_omap_dev_pm_ops)
#else
#define DEV_PM_OPS	NULL
#endif /* CONFIG_PM_SLEEP */

static struct platform_driver dwc3_omap_driver = {
	.probe		= dwc3_omap_probe,
	.remove		= dwc3_omap_remove,
	.driver		= {
		.name	= "omap-dwc3",
		.of_match_table	= of_dwc3_match,
		.pm	= DEV_PM_OPS,
	},
};

module_platform_driver(dwc3_omap_driver);

MODULE_ALIAS("platform:omap-dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
Commit	Line	Data
72246da4 FB	1	/**
	2	* dwc3-omap.c - OMAP Specific Glue layer
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
5945f789 FB	9	* This program is free software: you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 of
	11	* the License as published by the Free Software Foundation.
72246da4	12	*
5945f789 FB	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
72246da4 FB	17	*/
72246da4 FB	18
a72e658b	19	#include <linux/module.h>
72246da4 FB	20	#include <linux/kernel.h>
	21	#include <linux/slab.h>
	22	#include <linux/interrupt.h>
72246da4	23	#include <linux/platform_device.h>
9962444f	24	#include <linux/platform_data/dwc3-omap.h>
af310e96	25	#include <linux/pm_runtime.h>
72246da4 FB	26	#include <linux/dma-mapping.h>
	27	#include <linux/ioport.h>
	28	#include <linux/io.h>
45b3cd4a	29	#include <linux/of.h>
b4bfe6aa	30	#include <linux/of_platform.h>
8061ad72	31	#include <linux/extcon.h>
8061ad72	32	#include <linux/regulator/consumer.h>
72246da4	33
a418cc4e	34	#include <linux/usb/otg.h>
a418cc4e	35
72246da4 FB	36	/*
	37	* All these registers belong to OMAP's Wrapper around the
	38	* DesignWare USB3 Core.
	39	*/
	40
	41	#define USBOTGSS_REVISION 0x0000
	42	#define USBOTGSS_SYSCONFIG 0x0010
	43	#define USBOTGSS_IRQ_EOI 0x0020
ff7307b5	44	#define USBOTGSS_EOI_OFFSET 0x0008
72246da4 FB	45	#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
	46	#define USBOTGSS_IRQSTATUS_0 0x0028
	47	#define USBOTGSS_IRQENABLE_SET_0 0x002c
	48	#define USBOTGSS_IRQENABLE_CLR_0 0x0030
ff7307b5	49	#define USBOTGSS_IRQ0_OFFSET 0x0004
b1fd6cb5 GC	50	#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
	51	#define USBOTGSS_IRQSTATUS_1 0x0034
	52	#define USBOTGSS_IRQENABLE_SET_1 0x0038
	53	#define USBOTGSS_IRQENABLE_CLR_1 0x003c
	54	#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
	55	#define USBOTGSS_IRQSTATUS_2 0x0044
	56	#define USBOTGSS_IRQENABLE_SET_2 0x0048
	57	#define USBOTGSS_IRQENABLE_CLR_2 0x004c
	58	#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
	59	#define USBOTGSS_IRQSTATUS_3 0x0054
	60	#define USBOTGSS_IRQENABLE_SET_3 0x0058
	61	#define USBOTGSS_IRQENABLE_CLR_3 0x005c
ff7307b5 GC	62	#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
	63	#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
	64	#define USBOTGSS_IRQSTATUS_MISC 0x0038
	65	#define USBOTGSS_IRQENABLE_SET_MISC 0x003c
	66	#define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
	67	#define USBOTGSS_IRQMISC_OFFSET 0x03fc
72246da4 FB	68	#define USBOTGSS_UTMI_OTG_CTRL 0x0080
72246da4 FB	69	#define USBOTGSS_UTMI_OTG_STATUS 0x0084
ff7307b5 GC	70	#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
	71	#define USBOTGSS_TXFIFO_DEPTH 0x0508
	72	#define USBOTGSS_RXFIFO_DEPTH 0x050c
72246da4 FB	73	#define USBOTGSS_MMRAM_OFFSET 0x0100
	74	#define USBOTGSS_FLADJ 0x0104
	75	#define USBOTGSS_DEBUG_CFG 0x0108
	76	#define USBOTGSS_DEBUG_DATA 0x010c
ff7307b5 GC	77	#define USBOTGSS_DEV_EBC_EN 0x0110
ff7307b5 GC	78	#define USBOTGSS_DEBUG_OFFSET 0x0600
72246da4 FB	79
	80	/* SYSCONFIG REGISTER */
	81	#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
4b5faa7a	82
72246da4 FB	83	/* IRQ_EOI REGISTER */
	84	#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
	85
	86	/* IRQS0 BITS */
	87	#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
	88
b1fd6cb5 GC	89	/* IRQMISC BITS */
	90	#define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
	91	#define USBOTGSS_IRQMISC_OEVT (1 << 16)
	92	#define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
	93	#define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
	94	#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
	95	#define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
	96	#define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
	97	#define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
	98	#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
	99	#define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
72246da4 FB	100
	101	/* UTMI_OTG_CTRL REGISTER */
	102	#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
	103	#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
	104	#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
	105	#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
	106
	107	/* UTMI_OTG_STATUS REGISTER */
	108	#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
	109	#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
	110	#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
	111	#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
	112	#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
	113	#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
	114	#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
	115
	116	struct dwc3_omap {
72246da4 FB	117	struct device *dev;
	118
	119	int irq;
	120	void __iomem *base;
	121
f3e117f4	122	u32 utmi_otg_status;
1e2a064c GC	123	u32 utmi_otg_offset;
	124	u32 irqmisc_offset;
	125	u32 irq_eoi_offset;
	126	u32 debug_offset;
	127	u32 irq0_offset;
f3e117f4	128
72246da4	129	u32 dma_status:1;
8061ad72 KVA	130
	131	struct extcon_specific_cable_nb extcon_vbus_dev;
	132	struct extcon_specific_cable_nb extcon_id_dev;
	133	struct notifier_block vbus_nb;
	134	struct notifier_block id_nb;
	135
	136	struct regulator *vbus_reg;
72246da4 FB	137	};
72246da4 FB	138
8061ad72 KVA	139	enum omap_dwc3_vbus_id_status {
	140	OMAP_DWC3_ID_FLOAT,
	141	OMAP_DWC3_ID_GROUND,
	142	OMAP_DWC3_VBUS_OFF,
	143	OMAP_DWC3_VBUS_VALID,
	144	};
7e41bba9	145
ab5e59db IS	146	static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
	147	{
	148	return readl(base + offset);
	149	}
	150
	151	static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
	152	{
	153	writel(value, base + offset);
	154	}
	155
b1fd6cb5 GC	156	static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
	157	{
	158	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
	159	omap->utmi_otg_offset);
	160	}
	161
	162	static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
	163	{
	164	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
	165	omap->utmi_otg_offset, value);
	166
	167	}
	168
	169	static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
	170	{
	171	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
	172	omap->irq0_offset);
	173	}
	174
	175	static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
	176	{
	177	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
	178	omap->irq0_offset, value);
	179
	180	}
	181
	182	static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
	183	{
	184	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
	185	omap->irqmisc_offset);
	186	}
	187
	188	static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
	189	{
	190	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
	191	omap->irqmisc_offset, value);
	192
	193	}
	194
	195	static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
	196	{
	197	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
	198	omap->irqmisc_offset, value);
	199
	200	}
	201
	202	static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
	203	{
	204	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
	205	omap->irq0_offset, value);
	206	}
	207
8061ad72 KVA	208	static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
8061ad72 KVA	209	enum omap_dwc3_vbus_id_status status)
7e41bba9	210	{
8061ad72 KVA	211	int ret;
8061ad72 KVA	212	u32 val;
2ba7943a	213
7e41bba9 KVA	214	switch (status) {
	215	case OMAP_DWC3_ID_GROUND:
	216	dev_dbg(omap->dev, "ID GND\n");
	217
8061ad72 KVA	218	if (omap->vbus_reg) {
	219	ret = regulator_enable(omap->vbus_reg);
	220	if (ret) {
	221	dev_dbg(omap->dev, "regulator enable failed\n");
	222	return;
	223	}
	224	}
	225
b1fd6cb5	226	val = dwc3_omap_read_utmi_status(omap);
7e41bba9 KVA	227	val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
	228	\| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
	229	\| USBOTGSS_UTMI_OTG_STATUS_SESSEND);
	230	val \|= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
	231	\| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
b1fd6cb5	232	dwc3_omap_write_utmi_status(omap, val);
7e41bba9 KVA	233	break;
	234
	235	case OMAP_DWC3_VBUS_VALID:
	236	dev_dbg(omap->dev, "VBUS Connect\n");
	237
b1fd6cb5	238	val = dwc3_omap_read_utmi_status(omap);
7e41bba9 KVA	239	val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
	240	val \|= USBOTGSS_UTMI_OTG_STATUS_IDDIG
	241	\| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
	242	\| USBOTGSS_UTMI_OTG_STATUS_SESSVALID
	243	\| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
b1fd6cb5	244	dwc3_omap_write_utmi_status(omap, val);
7e41bba9 KVA	245	break;
	246
	247	case OMAP_DWC3_ID_FLOAT:
8061ad72 KVA	248	if (omap->vbus_reg)
	249	regulator_disable(omap->vbus_reg);
	250
7e41bba9 KVA	251	case OMAP_DWC3_VBUS_OFF:
	252	dev_dbg(omap->dev, "VBUS Disconnect\n");
	253
b1fd6cb5	254	val = dwc3_omap_read_utmi_status(omap);
7e41bba9 KVA	255	val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
	256	\| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
	257	\| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
	258	val \|= USBOTGSS_UTMI_OTG_STATUS_SESSEND
	259	\| USBOTGSS_UTMI_OTG_STATUS_IDDIG;
b1fd6cb5	260	dwc3_omap_write_utmi_status(omap, val);
7e41bba9 KVA	261	break;
	262
	263	default:
8061ad72	264	dev_dbg(omap->dev, "invalid state\n");
7e41bba9	265	}
7e41bba9	266	}
7e41bba9	267
72246da4 FB	268	static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
	269	{
	270	struct dwc3_omap *omap = _omap;
	271	u32 reg;
72246da4	272
b1fd6cb5	273	reg = dwc3_omap_read_irqmisc_status(omap);
72246da4	274
b1fd6cb5	275	if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
ccba3bca	276	dev_dbg(omap->dev, "DMA Disable was Cleared\n");
72246da4 FB	277	omap->dma_status = false;
	278	}
	279
b1fd6cb5	280	if (reg & USBOTGSS_IRQMISC_OEVT)
ccba3bca	281	dev_dbg(omap->dev, "OTG Event\n");
72246da4	282
b1fd6cb5	283	if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
ccba3bca	284	dev_dbg(omap->dev, "DRVVBUS Rise\n");
72246da4	285
b1fd6cb5	286	if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
ccba3bca	287	dev_dbg(omap->dev, "CHRGVBUS Rise\n");
72246da4	288
b1fd6cb5	289	if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
ccba3bca	290	dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
72246da4	291
b1fd6cb5	292	if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
ccba3bca	293	dev_dbg(omap->dev, "IDPULLUP Rise\n");
72246da4	294
b1fd6cb5	295	if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
ccba3bca	296	dev_dbg(omap->dev, "DRVVBUS Fall\n");
72246da4	297
b1fd6cb5	298	if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
ccba3bca	299	dev_dbg(omap->dev, "CHRGVBUS Fall\n");
72246da4	300
b1fd6cb5	301	if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
ccba3bca	302	dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
72246da4	303
b1fd6cb5	304	if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
ccba3bca	305	dev_dbg(omap->dev, "IDPULLUP Fall\n");
72246da4	306
b1fd6cb5 GC	307	dwc3_omap_write_irqmisc_status(omap, reg);
	308
	309	reg = dwc3_omap_read_irq0_status(omap);
42077b0a	310
b1fd6cb5	311	dwc3_omap_write_irq0_status(omap, reg);
72246da4	312
72246da4 FB	313	return IRQ_HANDLED;
	314	}
	315
94c6a436 KVA	316	static int dwc3_omap_remove_core(struct device dev, void c)
	317	{
	318	struct platform_device *pdev = to_platform_device(dev);
	319
	320	platform_device_unregister(pdev);
	321
	322	return 0;
	323	}
	324
9a4b5dab FB	325	static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
	326	{
	327	u32 reg;
	328
	329	/* enable all IRQs */
	330	reg = USBOTGSS_IRQO_COREIRQ_ST;
b1fd6cb5 GC	331	dwc3_omap_write_irq0_set(omap, reg);
	332
	333	reg = (USBOTGSS_IRQMISC_OEVT \|
	334	USBOTGSS_IRQMISC_DRVVBUS_RISE \|
	335	USBOTGSS_IRQMISC_CHRGVBUS_RISE \|
	336	USBOTGSS_IRQMISC_DISCHRGVBUS_RISE \|
	337	USBOTGSS_IRQMISC_IDPULLUP_RISE \|
	338	USBOTGSS_IRQMISC_DRVVBUS_FALL \|
	339	USBOTGSS_IRQMISC_CHRGVBUS_FALL \|
	340	USBOTGSS_IRQMISC_DISCHRGVBUS_FALL \|
	341	USBOTGSS_IRQMISC_IDPULLUP_FALL);
	342
	343	dwc3_omap_write_irqmisc_set(omap, reg);
9a4b5dab FB	344	}
	345
	346	static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
	347	{
	348	/* disable all IRQs */
b1fd6cb5 GC	349	dwc3_omap_write_irqmisc_set(omap, 0x00);
b1fd6cb5 GC	350	dwc3_omap_write_irq0_set(omap, 0x00);
9a4b5dab FB	351	}
9a4b5dab FB	352
ddff14f1 KVA	353	static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
ddff14f1 KVA	354
8061ad72 KVA	355	static int dwc3_omap_id_notifier(struct notifier_block *nb,
	356	unsigned long event, void *ptr)
	357	{
	358	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
	359
	360	if (event)
	361	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	362	else
	363	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
	364
	365	return NOTIFY_DONE;
	366	}
	367
	368	static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
	369	unsigned long event, void *ptr)
	370	{
	371	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
	372
	373	if (event)
	374	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	375	else
	376	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
	377
	378	return NOTIFY_DONE;
	379	}
	380
41ac7b3a	381	static int dwc3_omap_probe(struct platform_device *pdev)
72246da4	382	{
45b3cd4a FB	383	struct device_node *node = pdev->dev.of_node;
45b3cd4a FB	384
72246da4 FB	385	struct dwc3_omap *omap;
72246da4 FB	386	struct resource *res;
802ca850	387	struct device *dev = &pdev->dev;
8061ad72 KVA	388	struct extcon_dev *edev;
8061ad72 KVA	389	struct regulator *vbus_reg = NULL;
72246da4	390
b09e99ee	391	int ret;
72246da4 FB	392	int irq;
72246da4 FB	393
e36a0c87 KVA	394	int utmi_mode = 0;
e36a0c87 KVA	395
72246da4 FB	396	u32 reg;
	397
	398	void __iomem *base;
72246da4	399
4495afcf KVA	400	if (!node) {
	401	dev_err(dev, "device node not found\n");
	402	return -EINVAL;
	403	}
	404
802ca850	405	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
72246da4	406	if (!omap) {
802ca850 CP	407	dev_err(dev, "not enough memory\n");
802ca850 CP	408	return -ENOMEM;
72246da4 FB	409	}
	410
	411	platform_set_drvdata(pdev, omap);
	412
e36a0c87	413	irq = platform_get_irq(pdev, 0);
72246da4	414	if (irq < 0) {
802ca850 CP	415	dev_err(dev, "missing IRQ resource\n");
802ca850 CP	416	return -EINVAL;
72246da4 FB	417	}
72246da4 FB	418
e36a0c87	419	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8bbcd17d FB	420	base = devm_ioremap_resource(dev, res);
	421	if (IS_ERR(base))
	422	return PTR_ERR(base);
72246da4	423
8061ad72 KVA	424	if (of_property_read_bool(node, "vbus-supply")) {
	425	vbus_reg = devm_regulator_get(dev, "vbus");
	426	if (IS_ERR(vbus_reg)) {
	427	dev_err(dev, "vbus init failed\n");
	428	return PTR_ERR(vbus_reg);
	429	}
	430	}
	431
802ca850	432	omap->dev = dev;
72246da4 FB	433	omap->irq = irq;
72246da4 FB	434	omap->base = base;
8061ad72	435	omap->vbus_reg = vbus_reg;
ddff14f1	436	dev->dma_mask = &dwc3_omap_dma_mask;
72246da4	437
af310e96 KVA	438	pm_runtime_enable(dev);
	439	ret = pm_runtime_get_sync(dev);
	440	if (ret < 0) {
	441	dev_err(dev, "get_sync failed with err %d\n", ret);
594daba1	442	goto err0;
af310e96 KVA	443	}
af310e96 KVA	444
ca632a0d GC	445	/*
	446	* Differentiate between OMAP5 and AM437x.
	447	*
	448	* For OMAP5(ES2.0) and AM437x wrapper revision is same, even
	449	* though there are changes in wrapper register offsets.
	450	*
	451	* Using dt compatible to differentiate AM437x.
ff7307b5 GC	452	*/
	453
	454	if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
	455	omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
	456	omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
	457	omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
	458	omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
	459	omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
	460	}
	461
b1fd6cb5	462	reg = dwc3_omap_read_utmi_status(omap);
9962444f	463
4495afcf	464	of_property_read_u32(node, "utmi-mode", &utmi_mode);
e36a0c87 KVA	465
	466	switch (utmi_mode) {
	467	case DWC3_OMAP_UTMI_MODE_SW:
	468	reg \|= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	469	break;
	470	case DWC3_OMAP_UTMI_MODE_HW:
	471	reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	472	break;
	473	default:
	474	dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
9962444f FB	475	}
9962444f FB	476
b1fd6cb5	477	dwc3_omap_write_utmi_status(omap, reg);
9962444f	478
72246da4	479	/* check the DMA Status */
ab5e59db	480	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
72246da4 FB	481	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
72246da4 FB	482
802ca850	483	ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
dd17a6b2	484	"dwc3-omap", omap);
72246da4	485	if (ret) {
802ca850	486	dev_err(dev, "failed to request IRQ #%d --> %d\n",
72246da4	487	omap->irq, ret);
594daba1	488	goto err1;
72246da4 FB	489	}
72246da4 FB	490
9a4b5dab	491	dwc3_omap_enable_irqs(omap);
72246da4	492
8061ad72	493	if (of_property_read_bool(node, "extcon")) {
1ad94ffe	494	edev = extcon_get_edev_by_phandle(dev, 0);
8061ad72 KVA	495	if (IS_ERR(edev)) {
8061ad72 KVA	496	dev_vdbg(dev, "couldn't get extcon device\n");
e0a6104e	497	ret = -EPROBE_DEFER;
8061ad72 KVA	498	goto err2;
	499	}
	500
	501	omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
	502	ret = extcon_register_interest(&omap->extcon_vbus_dev,
	503	edev->name, "USB", &omap->vbus_nb);
	504	if (ret < 0)
	505	dev_vdbg(dev, "failed to register notifier for USB\n");
	506	omap->id_nb.notifier_call = dwc3_omap_id_notifier;
	507	ret = extcon_register_interest(&omap->extcon_id_dev, edev->name,
	508	"USB-HOST", &omap->id_nb);
	509	if (ret < 0)
	510	dev_vdbg(dev,
	511	"failed to register notifier for USB-HOST\n");
	512
	513	if (extcon_get_cable_state(edev, "USB") == true)
	514	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	515	if (extcon_get_cable_state(edev, "USB-HOST") == true)
	516	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	517	}
	518
4495afcf KVA	519	ret = of_platform_populate(node, NULL, NULL, dev);
	520	if (ret) {
	521	dev_err(&pdev->dev, "failed to create dwc3 core\n");
8061ad72	522	goto err3;
72246da4 FB	523	}
	524
	525	return 0;
594daba1	526
8061ad72 KVA	527	err3:
	528	if (omap->extcon_vbus_dev.edev)
	529	extcon_unregister_interest(&omap->extcon_vbus_dev);
	530	if (omap->extcon_id_dev.edev)
	531	extcon_unregister_interest(&omap->extcon_id_dev);
	532
594daba1 KVA	533	err2:
	534	dwc3_omap_disable_irqs(omap);
	535
	536	err1:
	537	pm_runtime_put_sync(dev);
	538
	539	err0:
	540	pm_runtime_disable(dev);
	541
	542	return ret;
72246da4 FB	543	}
72246da4 FB	544
fb4e98ab	545	static int dwc3_omap_remove(struct platform_device *pdev)
72246da4	546	{
9a4b5dab FB	547	struct dwc3_omap *omap = platform_get_drvdata(pdev);
9a4b5dab FB	548
8061ad72 KVA	549	if (omap->extcon_vbus_dev.edev)
	550	extcon_unregister_interest(&omap->extcon_vbus_dev);
	551	if (omap->extcon_id_dev.edev)
	552	extcon_unregister_interest(&omap->extcon_id_dev);
9a4b5dab	553	dwc3_omap_disable_irqs(omap);
af310e96 KVA	554	pm_runtime_put_sync(&pdev->dev);
af310e96 KVA	555	pm_runtime_disable(&pdev->dev);
94c6a436 KVA	556	device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
94c6a436 KVA	557
72246da4 FB	558	return 0;
	559	}
	560
2c2dc89c	561	static const struct of_device_id of_dwc3_match[] = {
72246da4	562	{
e36a0c87	563	.compatible = "ti,dwc3"
72246da4	564	},
ff7307b5 GC	565	{
	566	.compatible = "ti,am437x-dwc3"
	567	},
72246da4 FB	568	{ },
72246da4 FB	569	};
2c2dc89c	570	MODULE_DEVICE_TABLE(of, of_dwc3_match);
72246da4	571
19fda7cd	572	#ifdef CONFIG_PM_SLEEP
f3e117f4 FB	573	static int dwc3_omap_prepare(struct device *dev)
	574	{
	575	struct dwc3_omap *omap = dev_get_drvdata(dev);
	576
	577	dwc3_omap_disable_irqs(omap);
	578
	579	return 0;
	580	}
	581
	582	static void dwc3_omap_complete(struct device *dev)
	583	{
	584	struct dwc3_omap *omap = dev_get_drvdata(dev);
	585
	586	dwc3_omap_enable_irqs(omap);
	587	}
	588
	589	static int dwc3_omap_suspend(struct device *dev)
	590	{
	591	struct dwc3_omap *omap = dev_get_drvdata(dev);
	592
b1fd6cb5	593	omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);
f3e117f4 FB	594
	595	return 0;
	596	}
	597
	598	static int dwc3_omap_resume(struct device *dev)
	599	{
	600	struct dwc3_omap *omap = dev_get_drvdata(dev);
	601
b1fd6cb5	602	dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);
f3e117f4 FB	603
	604	pm_runtime_disable(dev);
	605	pm_runtime_set_active(dev);
	606	pm_runtime_enable(dev);
	607
	608	return 0;
	609	}
	610
	611	static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
	612	.prepare = dwc3_omap_prepare,
	613	.complete = dwc3_omap_complete,
	614
	615	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
	616	};
	617
	618	#define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
	619	#else
	620	#define DEV_PM_OPS NULL
19fda7cd	621	#endif /* CONFIG_PM_SLEEP */
f3e117f4	622
72246da4 FB	623	static struct platform_driver dwc3_omap_driver = {
72246da4 FB	624	.probe = dwc3_omap_probe,
7690417d	625	.remove = dwc3_omap_remove,
72246da4 FB	626	.driver = {
72246da4 FB	627	.name = "omap-dwc3",
2c2dc89c	628	.of_match_table = of_dwc3_match,
f3e117f4	629	.pm = DEV_PM_OPS,
72246da4 FB	630	},
	631	};
	632
cc27c96c AL	633	module_platform_driver(dwc3_omap_driver);
cc27c96c AL	634
7ae4fc4d	635	MODULE_ALIAS("platform:omap-dwc3");
72246da4	636	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789	637	MODULE_LICENSE("GPL v2");
72246da4	638	MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");