[linux-2.6-block.git] / drivers / usb / dwc3 / dwc3-omap.c

/**
 * dwc3-omap.c - OMAP Specific Glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dwc3-omap.h>
#include <linux/dma-mapping.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of.h>

#include <linux/usb/otg.h>
#include <linux/usb/nop-usb-xceiv.h>

#include "core.h"

/*
 * All these registers belong to OMAP's Wrapper around the
 * DesignWare USB3 Core.
 */

#define USBOTGSS_REVISION			0x0000
#define USBOTGSS_SYSCONFIG			0x0010
#define USBOTGSS_IRQ_EOI			0x0020
#define USBOTGSS_IRQSTATUS_RAW_0		0x0024
#define USBOTGSS_IRQSTATUS_0			0x0028
#define USBOTGSS_IRQENABLE_SET_0		0x002c
#define USBOTGSS_IRQENABLE_CLR_0		0x0030
#define USBOTGSS_IRQSTATUS_RAW_1		0x0034
#define USBOTGSS_IRQSTATUS_1			0x0038
#define USBOTGSS_IRQENABLE_SET_1		0x003c
#define USBOTGSS_IRQENABLE_CLR_1		0x0040
#define USBOTGSS_UTMI_OTG_CTRL			0x0080
#define USBOTGSS_UTMI_OTG_STATUS		0x0084
#define USBOTGSS_MMRAM_OFFSET			0x0100
#define USBOTGSS_FLADJ				0x0104
#define USBOTGSS_DEBUG_CFG			0x0108
#define USBOTGSS_DEBUG_DATA			0x010c

/* SYSCONFIG REGISTER */
#define USBOTGSS_SYSCONFIG_DMADISABLE		(1 << 16)
#define USBOTGSS_SYSCONFIG_STANDBYMODE(x)	((x) << 4)

#define USBOTGSS_STANDBYMODE_FORCE_STANDBY	0
#define USBOTGSS_STANDBYMODE_NO_STANDBY		1
#define USBOTGSS_STANDBYMODE_SMART_STANDBY	2
#define USBOTGSS_STANDBYMODE_SMART_WAKEUP	3

#define USBOTGSS_STANDBYMODE_MASK		(0x03 << 4)

#define USBOTGSS_SYSCONFIG_IDLEMODE(x)		((x) << 2)

#define USBOTGSS_IDLEMODE_FORCE_IDLE		0
#define USBOTGSS_IDLEMODE_NO_IDLE		1
#define USBOTGSS_IDLEMODE_SMART_IDLE		2
#define USBOTGSS_IDLEMODE_SMART_WAKEUP		3

#define USBOTGSS_IDLEMODE_MASK			(0x03 << 2)

/* IRQ_EOI REGISTER */
#define USBOTGSS_IRQ_EOI_LINE_NUMBER		(1 << 0)

/* IRQS0 BITS */
#define USBOTGSS_IRQO_COREIRQ_ST		(1 << 0)

/* IRQ1 BITS */
#define USBOTGSS_IRQ1_DMADISABLECLR		(1 << 17)
#define USBOTGSS_IRQ1_OEVT			(1 << 16)
#define USBOTGSS_IRQ1_DRVVBUS_RISE		(1 << 13)
#define USBOTGSS_IRQ1_CHRGVBUS_RISE		(1 << 12)
#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE		(1 << 11)
#define USBOTGSS_IRQ1_IDPULLUP_RISE		(1 << 8)
#define USBOTGSS_IRQ1_DRVVBUS_FALL		(1 << 5)
#define USBOTGSS_IRQ1_CHRGVBUS_FALL		(1 << 4)
#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL		(1 << 3)
#define USBOTGSS_IRQ1_IDPULLUP_FALL		(1 << 0)

/* UTMI_OTG_CTRL REGISTER */
#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS		(1 << 5)
#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS		(1 << 4)
#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS	(1 << 3)
#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP		(1 << 0)

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	(1 << 31)
#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	(1 << 9)
#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		(1 << 4)
#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	(1 << 3)
#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	(1 << 2)
#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	(1 << 1)

struct dwc3_omap {
	/* device lock */
	spinlock_t		lock;

	struct platform_device	*dwc3;
	struct platform_device	*usb2_phy;
	struct platform_device	*usb3_phy;
	struct device		*dev;

	int			irq;
	void __iomem		*base;

	void			*context;
	u32			resource_size;

	u32			dma_status:1;
};

static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
{
	return readl(base + offset);
}

static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
{
	writel(value, base + offset);
}

static int dwc3_omap_register_phys(struct dwc3_omap *omap)
{
	struct nop_usb_xceiv_platform_data pdata;
	struct platform_device	*pdev;
	int			ret;

	memset(&pdata, 0x00, sizeof(pdata));

	pdev = platform_device_alloc("nop_usb_xceiv", 0);
	if (!pdev)
		return -ENOMEM;

	omap->usb2_phy = pdev;
	pdata.type = USB_PHY_TYPE_USB2;

	ret = platform_device_add_data(omap->usb2_phy, &pdata, sizeof(pdata));
	if (ret)
		goto err1;

	pdev = platform_device_alloc("nop_usb_xceiv", 1);
	if (!pdev) {
		ret = -ENOMEM;
		goto err1;
	}

	omap->usb3_phy = pdev;
	pdata.type = USB_PHY_TYPE_USB3;

	ret = platform_device_add_data(omap->usb3_phy, &pdata, sizeof(pdata));
	if (ret)
		goto err2;

	ret = platform_device_add(omap->usb2_phy);
	if (ret)
		goto err2;

	ret = platform_device_add(omap->usb3_phy);
	if (ret)
		goto err3;

	return 0;

err3:
	platform_device_del(omap->usb2_phy);

err2:
	platform_device_put(omap->usb3_phy);

err1:
	platform_device_put(omap->usb2_phy);

	return ret;
}

static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;
	u32			reg;

	spin_lock(&omap->lock);

	reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);

	if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
		dev_dbg(omap->dev, "DMA Disable was Cleared\n");
		omap->dma_status = false;
	}

	if (reg & USBOTGSS_IRQ1_OEVT)
		dev_dbg(omap->dev, "OTG Event\n");

	if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
		dev_dbg(omap->dev, "DRVVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
		dev_dbg(omap->dev, "CHRGVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
		dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
		dev_dbg(omap->dev, "IDPULLUP Rise\n");

	if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
		dev_dbg(omap->dev, "DRVVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
		dev_dbg(omap->dev, "CHRGVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
		dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
		dev_dbg(omap->dev, "IDPULLUP Fall\n");

	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);

	reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);

	spin_unlock(&omap->lock);

	return IRQ_HANDLED;
}

static int dwc3_omap_remove_core(struct device *dev, void *c)
{
	struct platform_device *pdev = to_platform_device(dev);

	platform_device_unregister(pdev);

	return 0;
}

static int dwc3_omap_probe(struct platform_device *pdev)
{
	struct dwc3_omap_data	*pdata = pdev->dev.platform_data;
	struct device_node	*node = pdev->dev.of_node;

	struct platform_device	*dwc3;
	struct dwc3_omap	*omap;
	struct resource		*res;
	struct device		*dev = &pdev->dev;

	int			size;
	int			ret = -ENOMEM;
	int			irq;

	const u32		*utmi_mode;
	u32			reg;

	void __iomem		*base;
	void			*context;

	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
	if (!omap) {
		dev_err(dev, "not enough memory\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, omap);

	irq = platform_get_irq(pdev, 1);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(dev, "missing memory base resource\n");
		return -EINVAL;
	}

	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
	if (!base) {
		dev_err(dev, "ioremap failed\n");
		return -ENOMEM;
	}

	ret = dwc3_omap_register_phys(omap);
	if (ret) {
		dev_err(dev, "couldn't register PHYs\n");
		return ret;
	}

	dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
	if (!dwc3) {
		dev_err(dev, "couldn't allocate dwc3 device\n");
		return -ENOMEM;
	}

	context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL);
	if (!context) {
		dev_err(dev, "couldn't allocate dwc3 context memory\n");
		goto err2;
	}

	spin_lock_init(&omap->lock);
	dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);

	dwc3->dev.parent = dev;
	dwc3->dev.dma_mask = dev->dma_mask;
	dwc3->dev.dma_parms = dev->dma_parms;
	omap->resource_size = resource_size(res);
	omap->context	= context;
	omap->dev	= dev;
	omap->irq	= irq;
	omap->base	= base;
	omap->dwc3	= dwc3;

	reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);

	utmi_mode = of_get_property(node, "utmi-mode", &size);
	if (utmi_mode && size == sizeof(*utmi_mode)) {
		reg |= *utmi_mode;
	} else {
		if (!pdata) {
			dev_dbg(dev, "missing platform data\n");
		} else {
			switch (pdata->utmi_mode) {
			case DWC3_OMAP_UTMI_MODE_SW:
				reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
				break;
			case DWC3_OMAP_UTMI_MODE_HW:
				reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
				break;
			default:
				dev_dbg(dev, "UNKNOWN utmi mode %d\n",
						pdata->utmi_mode);
			}
		}
	}

	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);

	/* check the DMA Status */
	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);

	/* Set No-Idle and No-Standby */
	reg &= ~(USBOTGSS_STANDBYMODE_MASK
			| USBOTGSS_IDLEMODE_MASK);

	reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
		| USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));

	dwc3_omap_writel(omap->base, USBOTGSS_SYSCONFIG, reg);

	ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
			"dwc3-omap", omap);
	if (ret) {
		dev_err(dev, "failed to request IRQ #%d --> %d\n",
				omap->irq, ret);
		goto err2;
	}

	/* enable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);

	reg = (USBOTGSS_IRQ1_OEVT |
			USBOTGSS_IRQ1_DRVVBUS_RISE |
			USBOTGSS_IRQ1_CHRGVBUS_RISE |
			USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
			USBOTGSS_IRQ1_IDPULLUP_RISE |
			USBOTGSS_IRQ1_DRVVBUS_FALL |
			USBOTGSS_IRQ1_CHRGVBUS_FALL |
			USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
			USBOTGSS_IRQ1_IDPULLUP_FALL);

	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);

	ret = platform_device_add_resources(dwc3, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(dev, "couldn't add resources to dwc3 device\n");
		goto err2;
	}

	ret = platform_device_add(dwc3);
	if (ret) {
		dev_err(dev, "failed to register dwc3 device\n");
		goto err2;
	}

	return 0;

err2:
	platform_device_put(dwc3);
	return ret;
}

static int dwc3_omap_remove(struct platform_device *pdev)
{
	struct dwc3_omap	*omap = platform_get_drvdata(pdev);

	platform_device_unregister(omap->usb2_phy);
	platform_device_unregister(omap->usb3_phy);
	device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);

	return 0;
}

static const struct of_device_id of_dwc3_matach[] = {
	{
		"ti,dwc3",
	},
	{ },
};
MODULE_DEVICE_TABLE(of, of_dwc3_matach);

static struct platform_driver dwc3_omap_driver = {
	.probe		= dwc3_omap_probe,
	.remove		= dwc3_omap_remove,
	.driver		= {
		.name	= "omap-dwc3",
		.of_match_table	= of_dwc3_matach,
	},
};

module_platform_driver(dwc3_omap_driver);

MODULE_ALIAS("platform:omap-dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
Commit	Line	Data
72246da4 FB	1	/**
	2	* dwc3-omap.c - OMAP Specific Glue layer
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/interrupt.h>
	43	#include <linux/spinlock.h>
	44	#include <linux/platform_device.h>
9962444f	45	#include <linux/platform_data/dwc3-omap.h>
72246da4 FB	46	#include <linux/dma-mapping.h>
	47	#include <linux/ioport.h>
	48	#include <linux/io.h>
45b3cd4a	49	#include <linux/of.h>
72246da4	50
a418cc4e FB	51	#include <linux/usb/otg.h>
	52	#include <linux/usb/nop-usb-xceiv.h>
	53
5ddcee27	54	#include "core.h"
72246da4 FB	55
	56	/*
	57	* All these registers belong to OMAP's Wrapper around the
	58	* DesignWare USB3 Core.
	59	*/
	60
	61	#define USBOTGSS_REVISION 0x0000
	62	#define USBOTGSS_SYSCONFIG 0x0010
	63	#define USBOTGSS_IRQ_EOI 0x0020
	64	#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
	65	#define USBOTGSS_IRQSTATUS_0 0x0028
	66	#define USBOTGSS_IRQENABLE_SET_0 0x002c
	67	#define USBOTGSS_IRQENABLE_CLR_0 0x0030
	68	#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
	69	#define USBOTGSS_IRQSTATUS_1 0x0038
	70	#define USBOTGSS_IRQENABLE_SET_1 0x003c
	71	#define USBOTGSS_IRQENABLE_CLR_1 0x0040
	72	#define USBOTGSS_UTMI_OTG_CTRL 0x0080
	73	#define USBOTGSS_UTMI_OTG_STATUS 0x0084
	74	#define USBOTGSS_MMRAM_OFFSET 0x0100
	75	#define USBOTGSS_FLADJ 0x0104
	76	#define USBOTGSS_DEBUG_CFG 0x0108
	77	#define USBOTGSS_DEBUG_DATA 0x010c
	78
	79	/* SYSCONFIG REGISTER */
	80	#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
	81	#define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
4b5faa7a FB	82
	83	#define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0
	84	#define USBOTGSS_STANDBYMODE_NO_STANDBY 1
	85	#define USBOTGSS_STANDBYMODE_SMART_STANDBY 2
	86	#define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3
	87
	88	#define USBOTGSS_STANDBYMODE_MASK (0x03 << 4)
	89
72246da4 FB	90	#define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
72246da4 FB	91
4b5faa7a FB	92	#define USBOTGSS_IDLEMODE_FORCE_IDLE 0
	93	#define USBOTGSS_IDLEMODE_NO_IDLE 1
	94	#define USBOTGSS_IDLEMODE_SMART_IDLE 2
	95	#define USBOTGSS_IDLEMODE_SMART_WAKEUP 3
	96
	97	#define USBOTGSS_IDLEMODE_MASK (0x03 << 2)
	98
72246da4 FB	99	/* IRQ_EOI REGISTER */
	100	#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
	101
	102	/* IRQS0 BITS */
	103	#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
	104
	105	/* IRQ1 BITS */
	106	#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
	107	#define USBOTGSS_IRQ1_OEVT (1 << 16)
	108	#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
	109	#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
	110	#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
	111	#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
	112	#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
	113	#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
	114	#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
	115	#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
	116
	117	/* UTMI_OTG_CTRL REGISTER */
	118	#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
	119	#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
	120	#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
	121	#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
	122
	123	/* UTMI_OTG_STATUS REGISTER */
	124	#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
	125	#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
	126	#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
	127	#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
	128	#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
	129	#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
	130	#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
	131
	132	struct dwc3_omap {
	133	/* device lock */
	134	spinlock_t lock;
	135
	136	struct platform_device *dwc3;
a418cc4e FB	137	struct platform_device *usb2_phy;
a418cc4e FB	138	struct platform_device *usb3_phy;
72246da4 FB	139	struct device *dev;
	140
	141	int irq;
	142	void __iomem *base;
	143
	144	void *context;
	145	u32 resource_size;
	146
	147	u32 dma_status:1;
	148	};
	149
ab5e59db IS	150	static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
	151	{
	152	return readl(base + offset);
	153	}
	154
	155	static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
	156	{
	157	writel(value, base + offset);
	158	}
	159
41ac7b3a	160	static int dwc3_omap_register_phys(struct dwc3_omap *omap)
a418cc4e FB	161	{
	162	struct nop_usb_xceiv_platform_data pdata;
	163	struct platform_device *pdev;
	164	int ret;
	165
	166	memset(&pdata, 0x00, sizeof(pdata));
	167
	168	pdev = platform_device_alloc("nop_usb_xceiv", 0);
	169	if (!pdev)
	170	return -ENOMEM;
	171
	172	omap->usb2_phy = pdev;
	173	pdata.type = USB_PHY_TYPE_USB2;
	174
	175	ret = platform_device_add_data(omap->usb2_phy, &pdata, sizeof(pdata));
	176	if (ret)
	177	goto err1;
	178
	179	pdev = platform_device_alloc("nop_usb_xceiv", 1);
	180	if (!pdev) {
	181	ret = -ENOMEM;
	182	goto err1;
	183	}
	184
	185	omap->usb3_phy = pdev;
	186	pdata.type = USB_PHY_TYPE_USB3;
	187
	188	ret = platform_device_add_data(omap->usb3_phy, &pdata, sizeof(pdata));
	189	if (ret)
	190	goto err2;
	191
	192	ret = platform_device_add(omap->usb2_phy);
	193	if (ret)
	194	goto err2;
	195
	196	ret = platform_device_add(omap->usb3_phy);
	197	if (ret)
	198	goto err3;
	199
	200	return 0;
	201
	202	err3:
	203	platform_device_del(omap->usb2_phy);
	204
	205	err2:
	206	platform_device_put(omap->usb3_phy);
	207
	208	err1:
	209	platform_device_put(omap->usb2_phy);
	210
	211	return ret;
	212	}
ab5e59db	213
72246da4 FB	214	static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
	215	{
	216	struct dwc3_omap *omap = _omap;
	217	u32 reg;
72246da4 FB	218
	219	spin_lock(&omap->lock);
	220
ab5e59db	221	reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
72246da4 FB	222
72246da4 FB	223	if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
ccba3bca	224	dev_dbg(omap->dev, "DMA Disable was Cleared\n");
72246da4 FB	225	omap->dma_status = false;
	226	}
	227
	228	if (reg & USBOTGSS_IRQ1_OEVT)
ccba3bca	229	dev_dbg(omap->dev, "OTG Event\n");
72246da4	230
42077b0a	231	if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
ccba3bca	232	dev_dbg(omap->dev, "DRVVBUS Rise\n");
72246da4	233
42077b0a	234	if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
ccba3bca	235	dev_dbg(omap->dev, "CHRGVBUS Rise\n");
72246da4	236
42077b0a	237	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
ccba3bca	238	dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
72246da4	239
42077b0a	240	if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
ccba3bca	241	dev_dbg(omap->dev, "IDPULLUP Rise\n");
72246da4	242
42077b0a	243	if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
ccba3bca	244	dev_dbg(omap->dev, "DRVVBUS Fall\n");
72246da4	245
42077b0a	246	if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
ccba3bca	247	dev_dbg(omap->dev, "CHRGVBUS Fall\n");
72246da4	248
42077b0a	249	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
ccba3bca	250	dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
72246da4	251
42077b0a	252	if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
ccba3bca	253	dev_dbg(omap->dev, "IDPULLUP Fall\n");
72246da4	254
ab5e59db	255	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
42077b0a	256
ab5e59db IS	257	reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
ab5e59db IS	258	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
72246da4 FB	259
	260	spin_unlock(&omap->lock);
	261
	262	return IRQ_HANDLED;
	263	}
	264
94c6a436 KVA	265	static int dwc3_omap_remove_core(struct device dev, void c)
	266	{
	267	struct platform_device *pdev = to_platform_device(dev);
	268
	269	platform_device_unregister(pdev);
	270
	271	return 0;
	272	}
	273
41ac7b3a	274	static int dwc3_omap_probe(struct platform_device *pdev)
72246da4	275	{
9962444f	276	struct dwc3_omap_data *pdata = pdev->dev.platform_data;
45b3cd4a FB	277	struct device_node *node = pdev->dev.of_node;
45b3cd4a FB	278
72246da4 FB	279	struct platform_device *dwc3;
	280	struct dwc3_omap *omap;
	281	struct resource *res;
802ca850	282	struct device *dev = &pdev->dev;
72246da4	283
45b3cd4a	284	int size;
72246da4 FB	285	int ret = -ENOMEM;
	286	int irq;
	287
45b3cd4a	288	const u32 *utmi_mode;
72246da4 FB	289	u32 reg;
	290
	291	void __iomem *base;
	292	void *context;
	293
802ca850	294	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
72246da4	295	if (!omap) {
802ca850 CP	296	dev_err(dev, "not enough memory\n");
802ca850 CP	297	return -ENOMEM;
72246da4 FB	298	}
	299
	300	platform_set_drvdata(pdev, omap);
	301
	302	irq = platform_get_irq(pdev, 1);
	303	if (irq < 0) {
802ca850 CP	304	dev_err(dev, "missing IRQ resource\n");
802ca850 CP	305	return -EINVAL;
72246da4 FB	306	}
	307
	308	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	309	if (!res) {
802ca850 CP	310	dev_err(dev, "missing memory base resource\n");
802ca850 CP	311	return -EINVAL;
72246da4 FB	312	}
72246da4 FB	313
802ca850	314	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
72246da4	315	if (!base) {
802ca850 CP	316	dev_err(dev, "ioremap failed\n");
802ca850 CP	317	return -ENOMEM;
72246da4 FB	318	}
72246da4 FB	319
a418cc4e FB	320	ret = dwc3_omap_register_phys(omap);
	321	if (ret) {
	322	dev_err(dev, "couldn't register PHYs\n");
	323	return ret;
	324	}
	325
124dafde	326	dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
72246da4	327	if (!dwc3) {
802ca850	328	dev_err(dev, "couldn't allocate dwc3 device\n");
124dafde	329	return -ENOMEM;
72246da4 FB	330	}
72246da4 FB	331
802ca850	332	context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL);
72246da4	333	if (!context) {
802ca850 CP	334	dev_err(dev, "couldn't allocate dwc3 context memory\n");
802ca850 CP	335	goto err2;
72246da4 FB	336	}
	337
	338	spin_lock_init(&omap->lock);
802ca850	339	dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
72246da4	340
802ca850 CP	341	dwc3->dev.parent = dev;
	342	dwc3->dev.dma_mask = dev->dma_mask;
	343	dwc3->dev.dma_parms = dev->dma_parms;
72246da4 FB	344	omap->resource_size = resource_size(res);
72246da4 FB	345	omap->context = context;
802ca850	346	omap->dev = dev;
72246da4 FB	347	omap->irq = irq;
	348	omap->base = base;
	349	omap->dwc3 = dwc3;
	350
ab5e59db	351	reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
9962444f	352
45b3cd4a FB	353	utmi_mode = of_get_property(node, "utmi-mode", &size);
	354	if (utmi_mode && size == sizeof(*utmi_mode)) {
	355	reg \|= *utmi_mode;
9962444f	356	} else {
45b3cd4a	357	if (!pdata) {
802ca850	358	dev_dbg(dev, "missing platform data\n");
45b3cd4a FB	359	} else {
	360	switch (pdata->utmi_mode) {
	361	case DWC3_OMAP_UTMI_MODE_SW:
	362	reg \|= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	363	break;
	364	case DWC3_OMAP_UTMI_MODE_HW:
	365	reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	366	break;
	367	default:
802ca850	368	dev_dbg(dev, "UNKNOWN utmi mode %d\n",
45b3cd4a FB	369	pdata->utmi_mode);
45b3cd4a FB	370	}
9962444f FB	371	}
	372	}
	373
ab5e59db	374	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
9962444f	375
72246da4	376	/* check the DMA Status */
ab5e59db	377	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
72246da4 FB	378	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
72246da4 FB	379
4b5faa7a FB	380	/* Set No-Idle and No-Standby */
	381	reg &= ~(USBOTGSS_STANDBYMODE_MASK
	382	\| USBOTGSS_IDLEMODE_MASK);
	383
	384	reg \|= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
	385	\| USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));
	386
ab5e59db	387	dwc3_omap_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
4b5faa7a	388
802ca850	389	ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
dd17a6b2	390	"dwc3-omap", omap);
72246da4	391	if (ret) {
802ca850	392	dev_err(dev, "failed to request IRQ #%d --> %d\n",
72246da4	393	omap->irq, ret);
802ca850	394	goto err2;
72246da4 FB	395	}
	396
	397	/* enable all IRQs */
df01c61e	398	reg = USBOTGSS_IRQO_COREIRQ_ST;
ab5e59db	399	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
72246da4	400
324e5481	401	reg = (USBOTGSS_IRQ1_OEVT \|
72246da4 FB	402	USBOTGSS_IRQ1_DRVVBUS_RISE \|
	403	USBOTGSS_IRQ1_CHRGVBUS_RISE \|
	404	USBOTGSS_IRQ1_DISCHRGVBUS_RISE \|
	405	USBOTGSS_IRQ1_IDPULLUP_RISE \|
	406	USBOTGSS_IRQ1_DRVVBUS_FALL \|
	407	USBOTGSS_IRQ1_CHRGVBUS_FALL \|
	408	USBOTGSS_IRQ1_DISCHRGVBUS_FALL \|
	409	USBOTGSS_IRQ1_IDPULLUP_FALL);
	410
ab5e59db	411	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
72246da4 FB	412
	413	ret = platform_device_add_resources(dwc3, pdev->resource,
	414	pdev->num_resources);
	415	if (ret) {
802ca850 CP	416	dev_err(dev, "couldn't add resources to dwc3 device\n");
802ca850 CP	417	goto err2;
72246da4 FB	418	}
	419
	420	ret = platform_device_add(dwc3);
	421	if (ret) {
802ca850 CP	422	dev_err(dev, "failed to register dwc3 device\n");
802ca850 CP	423	goto err2;
72246da4 FB	424	}
	425
	426	return 0;
	427
72246da4	428	err2:
802ca850	429	platform_device_put(dwc3);
72246da4 FB	430	return ret;
	431	}
	432
fb4e98ab	433	static int dwc3_omap_remove(struct platform_device *pdev)
72246da4 FB	434	{
	435	struct dwc3_omap *omap = platform_get_drvdata(pdev);
	436
a418cc4e FB	437	platform_device_unregister(omap->usb2_phy);
a418cc4e FB	438	platform_device_unregister(omap->usb3_phy);
94c6a436 KVA	439	device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
94c6a436 KVA	440
72246da4 FB	441	return 0;
	442	}
	443
	444	static const struct of_device_id of_dwc3_matach[] = {
	445	{
	446	"ti,dwc3",
	447	},
	448	{ },
	449	};
	450	MODULE_DEVICE_TABLE(of, of_dwc3_matach);
	451
	452	static struct platform_driver dwc3_omap_driver = {
	453	.probe = dwc3_omap_probe,
7690417d	454	.remove = dwc3_omap_remove,
72246da4 FB	455	.driver = {
72246da4 FB	456	.name = "omap-dwc3",
72246da4 FB	457	.of_match_table = of_dwc3_matach,
	458	},
	459	};
	460
cc27c96c AL	461	module_platform_driver(dwc3_omap_driver);
cc27c96c AL	462
7ae4fc4d	463	MODULE_ALIAS("platform:omap-dwc3");
72246da4 FB	464	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	465	MODULE_LICENSE("Dual BSD/GPL");
	466	MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");