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72246da4 FB |
1 | /** |
2 | * core.h - DesignWare USB3 DRD Core Header | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
20 | #define __DRIVERS_USB_DWC3_CORE_H | |
21 | ||
22 | #include <linux/device.h> | |
23 | #include <linux/spinlock.h> | |
d07e8819 | 24 | #include <linux/ioport.h> |
72246da4 FB |
25 | #include <linux/list.h> |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/mm.h> | |
28 | #include <linux/debugfs.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
a45c82b8 | 32 | #include <linux/usb/otg.h> |
72246da4 FB |
33 | |
34 | /* Global constants */ | |
3ef35faf | 35 | #define DWC3_EP0_BOUNCE_SIZE 512 |
72246da4 | 36 | #define DWC3_ENDPOINTS_NUM 32 |
51249dca | 37 | #define DWC3_XHCI_RESOURCES_NUM 2 |
72246da4 | 38 | |
0ffcaf37 | 39 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
5da93478 FB |
40 | #define DWC3_EVENT_SIZE 4 /* bytes */ |
41 | #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ | |
42 | #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) | |
72246da4 FB |
43 | #define DWC3_EVENT_TYPE_MASK 0xfe |
44 | ||
45 | #define DWC3_EVENT_TYPE_DEV 0 | |
46 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
47 | #define DWC3_EVENT_TYPE_I2C 4 | |
48 | ||
49 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
50 | #define DWC3_DEVICE_EVENT_RESET 1 | |
51 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
52 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
53 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
2c61a8ef | 54 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
72246da4 FB |
55 | #define DWC3_DEVICE_EVENT_EOPF 6 |
56 | #define DWC3_DEVICE_EVENT_SOF 7 | |
57 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
58 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
59 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
60 | ||
61 | #define DWC3_GEVNTCOUNT_MASK 0xfffc | |
62 | #define DWC3_GSNPSID_MASK 0xffff0000 | |
63 | #define DWC3_GSNPSREV_MASK 0xffff | |
64 | ||
51249dca IS |
65 | /* DWC3 registers memory space boundries */ |
66 | #define DWC3_XHCI_REGS_START 0x0 | |
67 | #define DWC3_XHCI_REGS_END 0x7fff | |
68 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
69 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
70 | #define DWC3_DEVICE_REGS_START 0xc700 | |
71 | #define DWC3_DEVICE_REGS_END 0xcbff | |
72 | #define DWC3_OTG_REGS_START 0xcc00 | |
73 | #define DWC3_OTG_REGS_END 0xccff | |
74 | ||
72246da4 FB |
75 | /* Global Registers */ |
76 | #define DWC3_GSBUSCFG0 0xc100 | |
77 | #define DWC3_GSBUSCFG1 0xc104 | |
78 | #define DWC3_GTXTHRCFG 0xc108 | |
79 | #define DWC3_GRXTHRCFG 0xc10c | |
80 | #define DWC3_GCTL 0xc110 | |
81 | #define DWC3_GEVTEN 0xc114 | |
82 | #define DWC3_GSTS 0xc118 | |
83 | #define DWC3_GSNPSID 0xc120 | |
84 | #define DWC3_GGPIO 0xc124 | |
85 | #define DWC3_GUID 0xc128 | |
86 | #define DWC3_GUCTL 0xc12c | |
87 | #define DWC3_GBUSERRADDR0 0xc130 | |
88 | #define DWC3_GBUSERRADDR1 0xc134 | |
89 | #define DWC3_GPRTBIMAP0 0xc138 | |
90 | #define DWC3_GPRTBIMAP1 0xc13c | |
91 | #define DWC3_GHWPARAMS0 0xc140 | |
92 | #define DWC3_GHWPARAMS1 0xc144 | |
93 | #define DWC3_GHWPARAMS2 0xc148 | |
94 | #define DWC3_GHWPARAMS3 0xc14c | |
95 | #define DWC3_GHWPARAMS4 0xc150 | |
96 | #define DWC3_GHWPARAMS5 0xc154 | |
97 | #define DWC3_GHWPARAMS6 0xc158 | |
98 | #define DWC3_GHWPARAMS7 0xc15c | |
99 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
100 | #define DWC3_GDBGLTSSM 0xc164 | |
101 | #define DWC3_GPRTBIMAP_HS0 0xc180 | |
102 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
103 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
104 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
105 | ||
106 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) | |
107 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) | |
108 | ||
109 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) | |
110 | ||
111 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) | |
112 | ||
113 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) | |
114 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) | |
115 | ||
116 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) | |
117 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) | |
118 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) | |
119 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) | |
120 | ||
121 | #define DWC3_GHWPARAMS8 0xc600 | |
122 | ||
123 | /* Device Registers */ | |
124 | #define DWC3_DCFG 0xc700 | |
125 | #define DWC3_DCTL 0xc704 | |
126 | #define DWC3_DEVTEN 0xc708 | |
127 | #define DWC3_DSTS 0xc70c | |
128 | #define DWC3_DGCMDPAR 0xc710 | |
129 | #define DWC3_DGCMD 0xc714 | |
130 | #define DWC3_DALEPENA 0xc720 | |
131 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) | |
132 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) | |
133 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) | |
134 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) | |
135 | ||
136 | /* OTG Registers */ | |
137 | #define DWC3_OCFG 0xcc00 | |
138 | #define DWC3_OCTL 0xcc04 | |
d4436c3a GC |
139 | #define DWC3_OEVT 0xcc08 |
140 | #define DWC3_OEVTEN 0xcc0C | |
141 | #define DWC3_OSTS 0xcc10 | |
72246da4 FB |
142 | |
143 | /* Bit fields */ | |
144 | ||
145 | /* Global Configuration Register */ | |
1d046793 | 146 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
f4aadbe4 | 147 | #define DWC3_GCTL_U2RSTECN (1 << 16) |
1d046793 | 148 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
72246da4 FB |
149 | #define DWC3_GCTL_CLK_BUS (0) |
150 | #define DWC3_GCTL_CLK_PIPE (1) | |
151 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
152 | #define DWC3_GCTL_CLK_MASK (3) | |
153 | ||
0b9fe32d | 154 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
1d046793 | 155 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
72246da4 FB |
156 | #define DWC3_GCTL_PRTCAP_HOST 1 |
157 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
158 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
159 | ||
2c61a8ef | 160 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) |
183ca111 | 161 | #define DWC3_GCTL_SOFITPSYNC (1 << 10) |
2c61a8ef PZ |
162 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
163 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | |
164 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) | |
165 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) | |
166 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) | |
72246da4 FB |
167 | |
168 | /* Global USB2 PHY Configuration Register */ | |
2c61a8ef PZ |
169 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) |
170 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) | |
72246da4 FB |
171 | |
172 | /* Global USB3 PIPE Control Register */ | |
2c61a8ef PZ |
173 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) |
174 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) | |
72246da4 | 175 | |
457e84b6 | 176 | /* Global TX Fifo Size Register */ |
2c61a8ef PZ |
177 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) |
178 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) | |
457e84b6 | 179 | |
68d6a01b FB |
180 | /* Global Event Size Registers */ |
181 | #define DWC3_GEVNTSIZ_INTMASK (1 << 31) | |
182 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) | |
183 | ||
aabb7075 | 184 | /* Global HWPARAMS1 Register */ |
1d046793 | 185 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
aabb7075 FB |
186 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
187 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
2c61a8ef PZ |
188 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
189 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) | |
190 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) | |
191 | ||
192 | /* Global HWPARAMS4 Register */ | |
193 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | |
194 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | |
aabb7075 | 195 | |
72246da4 FB |
196 | /* Device Configuration Register */ |
197 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
198 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
199 | ||
200 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
201 | #define DWC3_DCFG_SUPERSPEED (4 << 0) | |
202 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
203 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) | |
204 | #define DWC3_DCFG_LOWSPEED (2 << 0) | |
205 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) | |
206 | ||
2c61a8ef PZ |
207 | #define DWC3_DCFG_LPM_CAP (1 << 22) |
208 | ||
72246da4 FB |
209 | /* Device Control Register */ |
210 | #define DWC3_DCTL_RUN_STOP (1 << 31) | |
211 | #define DWC3_DCTL_CSFTRST (1 << 30) | |
212 | #define DWC3_DCTL_LSFTRST (1 << 29) | |
213 | ||
214 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
7e39b817 | 215 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
72246da4 FB |
216 | |
217 | #define DWC3_DCTL_APPL1RES (1 << 23) | |
218 | ||
2c61a8ef PZ |
219 | /* These apply for core versions 1.87a and earlier */ |
220 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) | |
221 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
222 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
223 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
224 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
225 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
226 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
227 | ||
228 | /* These apply for core versions 1.94a and later */ | |
229 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) | |
230 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) | |
231 | #define DWC3_DCTL_CRS (1 << 17) | |
232 | #define DWC3_DCTL_CSS (1 << 16) | |
8db7ed15 | 233 | |
72246da4 FB |
234 | #define DWC3_DCTL_INITU2ENA (1 << 12) |
235 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | |
236 | #define DWC3_DCTL_INITU1ENA (1 << 10) | |
237 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | |
238 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | |
239 | ||
240 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
241 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
242 | ||
243 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
244 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
245 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
246 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
247 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
248 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
249 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
250 | ||
251 | /* Device Event Enable Register */ | |
252 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) | |
253 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) | |
254 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) | |
255 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) | |
256 | #define DWC3_DEVTEN_SOFEN (1 << 7) | |
257 | #define DWC3_DEVTEN_EOPFEN (1 << 6) | |
2c61a8ef | 258 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) |
72246da4 FB |
259 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) |
260 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) | |
261 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) | |
262 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) | |
263 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) | |
264 | ||
265 | /* Device Status Register */ | |
2c61a8ef PZ |
266 | #define DWC3_DSTS_DCNRD (1 << 29) |
267 | ||
268 | /* This applies for core versions 1.87a and earlier */ | |
72246da4 | 269 | #define DWC3_DSTS_PWRUPREQ (1 << 24) |
2c61a8ef PZ |
270 | |
271 | /* These apply for core versions 1.94a and later */ | |
272 | #define DWC3_DSTS_RSS (1 << 25) | |
273 | #define DWC3_DSTS_SSS (1 << 24) | |
274 | ||
72246da4 FB |
275 | #define DWC3_DSTS_COREIDLE (1 << 23) |
276 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) | |
277 | ||
278 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
279 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
280 | ||
281 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) | |
282 | ||
d05b8182 | 283 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
72246da4 FB |
284 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
285 | ||
286 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
287 | ||
288 | #define DWC3_DSTS_SUPERSPEED (4 << 0) | |
289 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
290 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) | |
291 | #define DWC3_DSTS_LOWSPEED (2 << 0) | |
292 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) | |
293 | ||
294 | /* Device Generic Command Register */ | |
295 | #define DWC3_DGCMD_SET_LMP 0x01 | |
296 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
297 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
2c61a8ef PZ |
298 | |
299 | /* These apply for core versions 1.94a and later */ | |
300 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 | |
301 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 | |
302 | ||
72246da4 FB |
303 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
304 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
305 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
306 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
307 | ||
b09bb642 FB |
308 | #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) |
309 | #define DWC3_DGCMD_CMDACT (1 << 10) | |
2c61a8ef PZ |
310 | #define DWC3_DGCMD_CMDIOC (1 << 8) |
311 | ||
312 | /* Device Generic Command Parameter Register */ | |
313 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) | |
314 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) | |
315 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) | |
316 | #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) | |
317 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) | |
318 | #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) | |
b09bb642 | 319 | |
72246da4 FB |
320 | /* Device Endpoint Command Register */ |
321 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
1d046793 | 322 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
835fadb4 | 323 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
b09bb642 | 324 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) |
72246da4 FB |
325 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) |
326 | #define DWC3_DEPCMD_CMDACT (1 << 10) | |
327 | #define DWC3_DEPCMD_CMDIOC (1 << 8) | |
328 | ||
329 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
330 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
331 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
332 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
333 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
334 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
2c61a8ef | 335 | /* This applies for core versions 1.90a and earlier */ |
72246da4 | 336 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
2c61a8ef PZ |
337 | /* This applies for core versions 1.94a and later */ |
338 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) | |
72246da4 FB |
339 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
340 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
341 | ||
342 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ | |
343 | #define DWC3_DALEPENA_EP(n) (1 << n) | |
344 | ||
345 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
346 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
347 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
348 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
349 | ||
350 | /* Structures */ | |
351 | ||
f6bafc6a | 352 | struct dwc3_trb; |
72246da4 FB |
353 | |
354 | /** | |
355 | * struct dwc3_event_buffer - Software event buffer representation | |
72246da4 FB |
356 | * @buf: _THE_ buffer |
357 | * @length: size of this buffer | |
abed4118 | 358 | * @lpos: event offset |
60d04bbe | 359 | * @count: cache of last read event count register |
abed4118 | 360 | * @flags: flags related to this event buffer |
72246da4 FB |
361 | * @dma: dma_addr_t |
362 | * @dwc: pointer to DWC controller | |
363 | */ | |
364 | struct dwc3_event_buffer { | |
365 | void *buf; | |
366 | unsigned length; | |
367 | unsigned int lpos; | |
60d04bbe | 368 | unsigned int count; |
abed4118 FB |
369 | unsigned int flags; |
370 | ||
371 | #define DWC3_EVENT_PENDING BIT(0) | |
72246da4 FB |
372 | |
373 | dma_addr_t dma; | |
374 | ||
375 | struct dwc3 *dwc; | |
376 | }; | |
377 | ||
378 | #define DWC3_EP_FLAG_STALLED (1 << 0) | |
379 | #define DWC3_EP_FLAG_WEDGED (1 << 1) | |
380 | ||
381 | #define DWC3_EP_DIRECTION_TX true | |
382 | #define DWC3_EP_DIRECTION_RX false | |
383 | ||
384 | #define DWC3_TRB_NUM 32 | |
385 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) | |
386 | ||
387 | /** | |
388 | * struct dwc3_ep - device side endpoint representation | |
389 | * @endpoint: usb endpoint | |
390 | * @request_list: list of requests for this endpoint | |
391 | * @req_queued: list of requests on this ep which have TRBs setup | |
392 | * @trb_pool: array of transaction buffers | |
393 | * @trb_pool_dma: dma address of @trb_pool | |
394 | * @free_slot: next slot which is going to be used | |
395 | * @busy_slot: first slot which is owned by HW | |
396 | * @desc: usb_endpoint_descriptor pointer | |
397 | * @dwc: pointer to DWC controller | |
4cfcf876 | 398 | * @saved_state: ep state saved during hibernation |
72246da4 FB |
399 | * @flags: endpoint flags (wedged, stalled, ...) |
400 | * @current_trb: index of current used trb | |
401 | * @number: endpoint number (1 - 15) | |
402 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
b4996a86 | 403 | * @resource_index: Resource transfer index |
c75f52fb | 404 | * @interval: the interval on which the ISOC transfer is started |
72246da4 FB |
405 | * @name: a human readable name e.g. ep1out-bulk |
406 | * @direction: true for TX, false for RX | |
879631aa | 407 | * @stream_capable: true when streams are enabled |
72246da4 FB |
408 | */ |
409 | struct dwc3_ep { | |
410 | struct usb_ep endpoint; | |
411 | struct list_head request_list; | |
412 | struct list_head req_queued; | |
413 | ||
f6bafc6a | 414 | struct dwc3_trb *trb_pool; |
72246da4 FB |
415 | dma_addr_t trb_pool_dma; |
416 | u32 free_slot; | |
417 | u32 busy_slot; | |
c90bfaec | 418 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
72246da4 FB |
419 | struct dwc3 *dwc; |
420 | ||
4cfcf876 | 421 | u32 saved_state; |
72246da4 FB |
422 | unsigned flags; |
423 | #define DWC3_EP_ENABLED (1 << 0) | |
424 | #define DWC3_EP_STALL (1 << 1) | |
425 | #define DWC3_EP_WEDGE (1 << 2) | |
426 | #define DWC3_EP_BUSY (1 << 4) | |
427 | #define DWC3_EP_PENDING_REQUEST (1 << 5) | |
d6d6ec7b | 428 | #define DWC3_EP_MISSED_ISOC (1 << 6) |
72246da4 | 429 | |
984f66a6 FB |
430 | /* This last one is specific to EP0 */ |
431 | #define DWC3_EP0_DIR_IN (1 << 31) | |
432 | ||
72246da4 FB |
433 | unsigned current_trb; |
434 | ||
435 | u8 number; | |
436 | u8 type; | |
b4996a86 | 437 | u8 resource_index; |
72246da4 FB |
438 | u32 interval; |
439 | ||
440 | char name[20]; | |
441 | ||
442 | unsigned direction:1; | |
879631aa | 443 | unsigned stream_capable:1; |
72246da4 FB |
444 | }; |
445 | ||
446 | enum dwc3_phy { | |
447 | DWC3_PHY_UNKNOWN = 0, | |
448 | DWC3_PHY_USB3, | |
449 | DWC3_PHY_USB2, | |
450 | }; | |
451 | ||
b53c772d FB |
452 | enum dwc3_ep0_next { |
453 | DWC3_EP0_UNKNOWN = 0, | |
454 | DWC3_EP0_COMPLETE, | |
b53c772d FB |
455 | DWC3_EP0_NRDY_DATA, |
456 | DWC3_EP0_NRDY_STATUS, | |
457 | }; | |
458 | ||
72246da4 FB |
459 | enum dwc3_ep0_state { |
460 | EP0_UNCONNECTED = 0, | |
c7fcdeb2 FB |
461 | EP0_SETUP_PHASE, |
462 | EP0_DATA_PHASE, | |
463 | EP0_STATUS_PHASE, | |
72246da4 FB |
464 | }; |
465 | ||
466 | enum dwc3_link_state { | |
467 | /* In SuperSpeed */ | |
468 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
469 | DWC3_LINK_STATE_U1 = 0x01, | |
470 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
471 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
472 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
473 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
474 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
475 | DWC3_LINK_STATE_POLL = 0x07, | |
476 | DWC3_LINK_STATE_RECOV = 0x08, | |
477 | DWC3_LINK_STATE_HRESET = 0x09, | |
478 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
479 | DWC3_LINK_STATE_LPBK = 0x0b, | |
2c61a8ef PZ |
480 | DWC3_LINK_STATE_RESET = 0x0e, |
481 | DWC3_LINK_STATE_RESUME = 0x0f, | |
72246da4 FB |
482 | DWC3_LINK_STATE_MASK = 0x0f, |
483 | }; | |
484 | ||
f6bafc6a FB |
485 | /* TRB Length, PCM and Status */ |
486 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
487 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
488 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
389f2828 | 489 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
f6bafc6a FB |
490 | |
491 | #define DWC3_TRBSTS_OK 0 | |
492 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
493 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
2c61a8ef | 494 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
f6bafc6a FB |
495 | |
496 | /* TRB Control */ | |
497 | #define DWC3_TRB_CTRL_HWO (1 << 0) | |
498 | #define DWC3_TRB_CTRL_LST (1 << 1) | |
499 | #define DWC3_TRB_CTRL_CHN (1 << 2) | |
500 | #define DWC3_TRB_CTRL_CSP (1 << 3) | |
501 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) | |
502 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) | |
503 | #define DWC3_TRB_CTRL_IOC (1 << 11) | |
504 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) | |
505 | ||
506 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) | |
507 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
508 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
509 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
510 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
511 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
512 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
513 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
72246da4 FB |
514 | |
515 | /** | |
f6bafc6a | 516 | * struct dwc3_trb - transfer request block (hw format) |
72246da4 FB |
517 | * @bpl: DW0-3 |
518 | * @bph: DW4-7 | |
519 | * @size: DW8-B | |
520 | * @trl: DWC-F | |
521 | */ | |
f6bafc6a FB |
522 | struct dwc3_trb { |
523 | u32 bpl; | |
524 | u32 bph; | |
525 | u32 size; | |
526 | u32 ctrl; | |
72246da4 FB |
527 | } __packed; |
528 | ||
a3299499 FB |
529 | /** |
530 | * dwc3_hwparams - copy of HWPARAMS registers | |
531 | * @hwparams0 - GHWPARAMS0 | |
532 | * @hwparams1 - GHWPARAMS1 | |
533 | * @hwparams2 - GHWPARAMS2 | |
534 | * @hwparams3 - GHWPARAMS3 | |
535 | * @hwparams4 - GHWPARAMS4 | |
536 | * @hwparams5 - GHWPARAMS5 | |
537 | * @hwparams6 - GHWPARAMS6 | |
538 | * @hwparams7 - GHWPARAMS7 | |
539 | * @hwparams8 - GHWPARAMS8 | |
540 | */ | |
541 | struct dwc3_hwparams { | |
542 | u32 hwparams0; | |
543 | u32 hwparams1; | |
544 | u32 hwparams2; | |
545 | u32 hwparams3; | |
546 | u32 hwparams4; | |
547 | u32 hwparams5; | |
548 | u32 hwparams6; | |
549 | u32 hwparams7; | |
550 | u32 hwparams8; | |
551 | }; | |
552 | ||
0949e99b FB |
553 | /* HWPARAMS0 */ |
554 | #define DWC3_MODE(n) ((n) & 0x7) | |
555 | ||
457e84b6 FB |
556 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
557 | ||
0949e99b | 558 | /* HWPARAMS1 */ |
457e84b6 FB |
559 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
560 | ||
789451f6 FB |
561 | /* HWPARAMS3 */ |
562 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) | |
563 | #define DWC3_NUM_EPS_MASK (0x3f << 12) | |
564 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ | |
565 | (DWC3_NUM_EPS_MASK)) >> 12) | |
566 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ | |
567 | (DWC3_NUM_IN_EPS_MASK)) >> 18) | |
568 | ||
457e84b6 FB |
569 | /* HWPARAMS7 */ |
570 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
9f622b2a | 571 | |
e0ce0b0a SAS |
572 | struct dwc3_request { |
573 | struct usb_request request; | |
574 | struct list_head list; | |
575 | struct dwc3_ep *dep; | |
e5ba5ec8 | 576 | u32 start_slot; |
e0ce0b0a SAS |
577 | |
578 | u8 epnum; | |
f6bafc6a | 579 | struct dwc3_trb *trb; |
e0ce0b0a SAS |
580 | dma_addr_t trb_dma; |
581 | ||
582 | unsigned direction:1; | |
583 | unsigned mapped:1; | |
584 | unsigned queued:1; | |
585 | }; | |
586 | ||
2c61a8ef PZ |
587 | /* |
588 | * struct dwc3_scratchpad_array - hibernation scratchpad array | |
589 | * (format defined by hw) | |
590 | */ | |
591 | struct dwc3_scratchpad_array { | |
592 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; | |
593 | }; | |
594 | ||
72246da4 FB |
595 | /** |
596 | * struct dwc3 - representation of our controller | |
91db07dc FB |
597 | * @ctrl_req: usb control request which is used for ep0 |
598 | * @ep0_trb: trb which is used for the ctrl_req | |
5812b1c2 | 599 | * @ep0_bounce: bounce buffer for ep0 |
91db07dc FB |
600 | * @setup_buf: used while precessing STD USB requests |
601 | * @ctrl_req_addr: dma address of ctrl_req | |
602 | * @ep0_trb: dma address of ep0_trb | |
603 | * @ep0_usb_req: dummy req used while handling STD USB requests | |
5812b1c2 | 604 | * @ep0_bounce_addr: dma address of ep0_bounce |
0ffcaf37 | 605 | * @scratch_addr: dma address of scratchbuf |
72246da4 FB |
606 | * @lock: for synchronizing |
607 | * @dev: pointer to our struct device | |
d07e8819 | 608 | * @xhci: pointer to our xHCI child |
72246da4 FB |
609 | * @event_buffer_list: a list of event buffers |
610 | * @gadget: device side representation of the peripheral controller | |
611 | * @gadget_driver: pointer to the gadget driver | |
612 | * @regs: base address for our registers | |
613 | * @regs_size: address space size | |
0ffcaf37 | 614 | * @nr_scratch: number of scratch buffers |
9f622b2a | 615 | * @num_event_buffers: calculated number of event buffers |
fae2b904 | 616 | * @u1u2: only used on revisions <1.83a for workaround |
6c167fc9 | 617 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
72246da4 | 618 | * @revision: revision register contents |
a45c82b8 | 619 | * @dr_mode: requested mode of operation |
51e1e7bc FB |
620 | * @usb2_phy: pointer to USB2 PHY |
621 | * @usb3_phy: pointer to USB3 PHY | |
7415f17c FB |
622 | * @dcfg: saved contents of DCFG register |
623 | * @gctl: saved contents of GCTL register | |
c12a0d86 | 624 | * @isoch_delay: wValue from Set Isochronous Delay request; |
865e09e7 FB |
625 | * @u2sel: parameter from Set SEL request. |
626 | * @u2pel: parameter from Set SEL request. | |
627 | * @u1sel: parameter from Set SEL request. | |
628 | * @u1pel: parameter from Set SEL request. | |
789451f6 FB |
629 | * @num_out_eps: number of out endpoints |
630 | * @num_in_eps: number of in endpoints | |
b53c772d | 631 | * @ep0_next_event: hold the next expected event |
72246da4 FB |
632 | * @ep0state: state of endpoint zero |
633 | * @link_state: link state | |
634 | * @speed: device speed (super, high, full, low) | |
635 | * @mem: points to start of memory which is used for this struct. | |
a3299499 | 636 | * @hwparams: copy of hwparams registers |
72246da4 | 637 | * @root: debugfs root folder pointer |
f2b685d5 FB |
638 | * @regset: debugfs pointer to regdump file |
639 | * @test_mode: true when we're entering a USB test mode | |
640 | * @test_mode_nr: test feature selector | |
641 | * @delayed_status: true when gadget driver asks for delayed status | |
642 | * @ep0_bounced: true when we used bounce buffer | |
643 | * @ep0_expect_in: true when we expect a DATA IN transfer | |
81bc5599 | 644 | * @has_hibernation: true when dwc3 was configured with Hibernation |
f2b685d5 FB |
645 | * @is_selfpowered: true when we are selfpowered |
646 | * @needs_fifo_resize: not all users might want fifo resizing, flag it | |
647 | * @pullups_connected: true when Run/Stop bit is set | |
648 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. | |
649 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround | |
650 | * @start_config_issued: true when StartConfig command has been issued | |
651 | * @three_stage_setup: set if we perform a three phase setup | |
72246da4 FB |
652 | */ |
653 | struct dwc3 { | |
654 | struct usb_ctrlrequest *ctrl_req; | |
f6bafc6a | 655 | struct dwc3_trb *ep0_trb; |
5812b1c2 | 656 | void *ep0_bounce; |
0ffcaf37 | 657 | void *scratchbuf; |
72246da4 FB |
658 | u8 *setup_buf; |
659 | dma_addr_t ctrl_req_addr; | |
660 | dma_addr_t ep0_trb_addr; | |
5812b1c2 | 661 | dma_addr_t ep0_bounce_addr; |
0ffcaf37 | 662 | dma_addr_t scratch_addr; |
e0ce0b0a | 663 | struct dwc3_request ep0_usb_req; |
789451f6 | 664 | |
72246da4 FB |
665 | /* device lock */ |
666 | spinlock_t lock; | |
789451f6 | 667 | |
72246da4 FB |
668 | struct device *dev; |
669 | ||
d07e8819 | 670 | struct platform_device *xhci; |
51249dca | 671 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
d07e8819 | 672 | |
457d3f21 | 673 | struct dwc3_event_buffer **ev_buffs; |
72246da4 FB |
674 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
675 | ||
676 | struct usb_gadget gadget; | |
677 | struct usb_gadget_driver *gadget_driver; | |
678 | ||
51e1e7bc FB |
679 | struct usb_phy *usb2_phy; |
680 | struct usb_phy *usb3_phy; | |
681 | ||
72246da4 FB |
682 | void __iomem *regs; |
683 | size_t regs_size; | |
684 | ||
a45c82b8 RK |
685 | enum usb_dr_mode dr_mode; |
686 | ||
7415f17c FB |
687 | /* used for suspend/resume */ |
688 | u32 dcfg; | |
689 | u32 gctl; | |
690 | ||
0ffcaf37 | 691 | u32 nr_scratch; |
9f622b2a | 692 | u32 num_event_buffers; |
fae2b904 | 693 | u32 u1u2; |
6c167fc9 | 694 | u32 maximum_speed; |
72246da4 FB |
695 | u32 revision; |
696 | ||
697 | #define DWC3_REVISION_173A 0x5533173a | |
698 | #define DWC3_REVISION_175A 0x5533175a | |
699 | #define DWC3_REVISION_180A 0x5533180a | |
700 | #define DWC3_REVISION_183A 0x5533183a | |
701 | #define DWC3_REVISION_185A 0x5533185a | |
2c61a8ef | 702 | #define DWC3_REVISION_187A 0x5533187a |
72246da4 FB |
703 | #define DWC3_REVISION_188A 0x5533188a |
704 | #define DWC3_REVISION_190A 0x5533190a | |
2c61a8ef | 705 | #define DWC3_REVISION_194A 0x5533194a |
1522d703 FB |
706 | #define DWC3_REVISION_200A 0x5533200a |
707 | #define DWC3_REVISION_202A 0x5533202a | |
708 | #define DWC3_REVISION_210A 0x5533210a | |
709 | #define DWC3_REVISION_220A 0x5533220a | |
7ac6a593 FB |
710 | #define DWC3_REVISION_230A 0x5533230a |
711 | #define DWC3_REVISION_240A 0x5533240a | |
712 | #define DWC3_REVISION_250A 0x5533250a | |
72246da4 | 713 | |
b53c772d | 714 | enum dwc3_ep0_next ep0_next_event; |
72246da4 FB |
715 | enum dwc3_ep0_state ep0state; |
716 | enum dwc3_link_state link_state; | |
72246da4 | 717 | |
c12a0d86 | 718 | u16 isoch_delay; |
865e09e7 FB |
719 | u16 u2sel; |
720 | u16 u2pel; | |
721 | u8 u1sel; | |
722 | u8 u1pel; | |
723 | ||
72246da4 | 724 | u8 speed; |
865e09e7 | 725 | |
789451f6 FB |
726 | u8 num_out_eps; |
727 | u8 num_in_eps; | |
728 | ||
72246da4 FB |
729 | void *mem; |
730 | ||
a3299499 | 731 | struct dwc3_hwparams hwparams; |
72246da4 | 732 | struct dentry *root; |
d7668024 | 733 | struct debugfs_regset32 *regset; |
3b637367 GC |
734 | |
735 | u8 test_mode; | |
736 | u8 test_mode_nr; | |
f2b685d5 FB |
737 | |
738 | unsigned delayed_status:1; | |
739 | unsigned ep0_bounced:1; | |
740 | unsigned ep0_expect_in:1; | |
81bc5599 | 741 | unsigned has_hibernation:1; |
f2b685d5 FB |
742 | unsigned is_selfpowered:1; |
743 | unsigned needs_fifo_resize:1; | |
744 | unsigned pullups_connected:1; | |
745 | unsigned resize_fifos:1; | |
746 | unsigned setup_packet_pending:1; | |
747 | unsigned start_config_issued:1; | |
748 | unsigned three_stage_setup:1; | |
72246da4 FB |
749 | }; |
750 | ||
751 | /* -------------------------------------------------------------------------- */ | |
752 | ||
72246da4 FB |
753 | /* -------------------------------------------------------------------------- */ |
754 | ||
755 | struct dwc3_event_type { | |
756 | u32 is_devspec:1; | |
1974d494 HR |
757 | u32 type:7; |
758 | u32 reserved8_31:24; | |
72246da4 FB |
759 | } __packed; |
760 | ||
761 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
762 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
763 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
764 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
765 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
766 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
767 | ||
768 | /** | |
769 | * struct dwc3_event_depvt - Device Endpoint Events | |
770 | * @one_bit: indicates this is an endpoint event (not used) | |
771 | * @endpoint_number: number of the endpoint | |
772 | * @endpoint_event: The event we have: | |
773 | * 0x00 - Reserved | |
774 | * 0x01 - XferComplete | |
775 | * 0x02 - XferInProgress | |
776 | * 0x03 - XferNotReady | |
777 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
778 | * 0x05 - Reserved | |
779 | * 0x06 - StreamEvt | |
780 | * 0x07 - EPCmdCmplt | |
781 | * @reserved11_10: Reserved, don't use. | |
782 | * @status: Indicates the status of the event. Refer to databook for | |
783 | * more information. | |
784 | * @parameters: Parameters of the current event. Refer to databook for | |
785 | * more information. | |
786 | */ | |
787 | struct dwc3_event_depevt { | |
788 | u32 one_bit:1; | |
789 | u32 endpoint_number:5; | |
790 | u32 endpoint_event:4; | |
791 | u32 reserved11_10:2; | |
792 | u32 status:4; | |
40aa41fb FB |
793 | |
794 | /* Within XferNotReady */ | |
795 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) | |
796 | ||
797 | /* Within XferComplete */ | |
1d046793 PZ |
798 | #define DEPEVT_STATUS_BUSERR (1 << 0) |
799 | #define DEPEVT_STATUS_SHORT (1 << 1) | |
800 | #define DEPEVT_STATUS_IOC (1 << 2) | |
72246da4 | 801 | #define DEPEVT_STATUS_LST (1 << 3) |
dc137f01 | 802 | |
879631aa FB |
803 | /* Stream event only */ |
804 | #define DEPEVT_STREAMEVT_FOUND 1 | |
805 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
806 | ||
dc137f01 | 807 | /* Control-only Status */ |
dc137f01 FB |
808 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
809 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
810 | ||
72246da4 FB |
811 | u32 parameters:16; |
812 | } __packed; | |
813 | ||
814 | /** | |
815 | * struct dwc3_event_devt - Device Events | |
816 | * @one_bit: indicates this is a non-endpoint event (not used) | |
817 | * @device_event: indicates it's a device event. Should read as 0x00 | |
818 | * @type: indicates the type of device event. | |
819 | * 0 - DisconnEvt | |
820 | * 1 - USBRst | |
821 | * 2 - ConnectDone | |
822 | * 3 - ULStChng | |
823 | * 4 - WkUpEvt | |
824 | * 5 - Reserved | |
825 | * 6 - EOPF | |
826 | * 7 - SOF | |
827 | * 8 - Reserved | |
828 | * 9 - ErrticErr | |
829 | * 10 - CmdCmplt | |
830 | * 11 - EvntOverflow | |
831 | * 12 - VndrDevTstRcved | |
832 | * @reserved15_12: Reserved, not used | |
833 | * @event_info: Information about this event | |
06f9b6e5 | 834 | * @reserved31_25: Reserved, not used |
72246da4 FB |
835 | */ |
836 | struct dwc3_event_devt { | |
837 | u32 one_bit:1; | |
838 | u32 device_event:7; | |
839 | u32 type:4; | |
840 | u32 reserved15_12:4; | |
06f9b6e5 HR |
841 | u32 event_info:9; |
842 | u32 reserved31_25:7; | |
72246da4 FB |
843 | } __packed; |
844 | ||
845 | /** | |
846 | * struct dwc3_event_gevt - Other Core Events | |
847 | * @one_bit: indicates this is a non-endpoint event (not used) | |
848 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
849 | * @phy_port_number: self-explanatory | |
850 | * @reserved31_12: Reserved, not used. | |
851 | */ | |
852 | struct dwc3_event_gevt { | |
853 | u32 one_bit:1; | |
854 | u32 device_event:7; | |
855 | u32 phy_port_number:4; | |
856 | u32 reserved31_12:20; | |
857 | } __packed; | |
858 | ||
859 | /** | |
860 | * union dwc3_event - representation of Event Buffer contents | |
861 | * @raw: raw 32-bit event | |
862 | * @type: the type of the event | |
863 | * @depevt: Device Endpoint Event | |
864 | * @devt: Device Event | |
865 | * @gevt: Global Event | |
866 | */ | |
867 | union dwc3_event { | |
868 | u32 raw; | |
869 | struct dwc3_event_type type; | |
870 | struct dwc3_event_depevt depevt; | |
871 | struct dwc3_event_devt devt; | |
872 | struct dwc3_event_gevt gevt; | |
873 | }; | |
874 | ||
875 | /* | |
876 | * DWC3 Features to be used as Driver Data | |
877 | */ | |
878 | ||
879 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
880 | #define DWC3_HAS_XHCI BIT(1) | |
881 | #define DWC3_HAS_OTG BIT(3) | |
882 | ||
d07e8819 | 883 | /* prototypes */ |
3140e8cb | 884 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
457e84b6 | 885 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); |
3140e8cb | 886 | |
388e5c51 | 887 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
d07e8819 FB |
888 | int dwc3_host_init(struct dwc3 *dwc); |
889 | void dwc3_host_exit(struct dwc3 *dwc); | |
388e5c51 VG |
890 | #else |
891 | static inline int dwc3_host_init(struct dwc3 *dwc) | |
892 | { return 0; } | |
893 | static inline void dwc3_host_exit(struct dwc3 *dwc) | |
894 | { } | |
895 | #endif | |
896 | ||
897 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) | |
f80b45e7 FB |
898 | int dwc3_gadget_init(struct dwc3 *dwc); |
899 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
388e5c51 VG |
900 | #else |
901 | static inline int dwc3_gadget_init(struct dwc3 *dwc) | |
902 | { return 0; } | |
903 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) | |
904 | { } | |
905 | #endif | |
f80b45e7 | 906 | |
7415f17c FB |
907 | /* power management interface */ |
908 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) | |
909 | int dwc3_gadget_prepare(struct dwc3 *dwc); | |
910 | void dwc3_gadget_complete(struct dwc3 *dwc); | |
911 | int dwc3_gadget_suspend(struct dwc3 *dwc); | |
912 | int dwc3_gadget_resume(struct dwc3 *dwc); | |
913 | #else | |
914 | static inline int dwc3_gadget_prepare(struct dwc3 *dwc) | |
915 | { | |
916 | return 0; | |
917 | } | |
918 | ||
919 | static inline void dwc3_gadget_complete(struct dwc3 *dwc) | |
920 | { | |
921 | } | |
922 | ||
923 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) | |
924 | { | |
925 | return 0; | |
926 | } | |
927 | ||
928 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) | |
929 | { | |
930 | return 0; | |
931 | } | |
932 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ | |
933 | ||
72246da4 | 934 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |