usb: dwc3: add P3 in U2 SS inactive quirk
[linux-2.6-block.git] / drivers / usb / dwc3 / core.h
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1/**
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
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9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
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13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
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17 */
18
19#ifndef __DRIVERS_USB_DWC3_CORE_H
20#define __DRIVERS_USB_DWC3_CORE_H
21
22#include <linux/device.h>
23#include <linux/spinlock.h>
d07e8819 24#include <linux/ioport.h>
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25#include <linux/list.h>
26#include <linux/dma-mapping.h>
27#include <linux/mm.h>
28#include <linux/debugfs.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
a45c82b8 32#include <linux/usb/otg.h>
72246da4 33
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34#include <linux/phy/phy.h>
35
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36#define DWC3_MSG_MAX 500
37
72246da4 38/* Global constants */
3ef35faf 39#define DWC3_EP0_BOUNCE_SIZE 512
72246da4 40#define DWC3_ENDPOINTS_NUM 32
51249dca 41#define DWC3_XHCI_RESOURCES_NUM 2
72246da4 42
0ffcaf37 43#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
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44#define DWC3_EVENT_SIZE 4 /* bytes */
45#define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
46#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
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47#define DWC3_EVENT_TYPE_MASK 0xfe
48
49#define DWC3_EVENT_TYPE_DEV 0
50#define DWC3_EVENT_TYPE_CARKIT 3
51#define DWC3_EVENT_TYPE_I2C 4
52
53#define DWC3_DEVICE_EVENT_DISCONNECT 0
54#define DWC3_DEVICE_EVENT_RESET 1
55#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
56#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
57#define DWC3_DEVICE_EVENT_WAKEUP 4
2c61a8ef 58#define DWC3_DEVICE_EVENT_HIBER_REQ 5
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59#define DWC3_DEVICE_EVENT_EOPF 6
60#define DWC3_DEVICE_EVENT_SOF 7
61#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
62#define DWC3_DEVICE_EVENT_CMD_CMPL 10
63#define DWC3_DEVICE_EVENT_OVERFLOW 11
64
65#define DWC3_GEVNTCOUNT_MASK 0xfffc
66#define DWC3_GSNPSID_MASK 0xffff0000
67#define DWC3_GSNPSREV_MASK 0xffff
68
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69/* DWC3 registers memory space boundries */
70#define DWC3_XHCI_REGS_START 0x0
71#define DWC3_XHCI_REGS_END 0x7fff
72#define DWC3_GLOBALS_REGS_START 0xc100
73#define DWC3_GLOBALS_REGS_END 0xc6ff
74#define DWC3_DEVICE_REGS_START 0xc700
75#define DWC3_DEVICE_REGS_END 0xcbff
76#define DWC3_OTG_REGS_START 0xcc00
77#define DWC3_OTG_REGS_END 0xccff
78
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79/* Global Registers */
80#define DWC3_GSBUSCFG0 0xc100
81#define DWC3_GSBUSCFG1 0xc104
82#define DWC3_GTXTHRCFG 0xc108
83#define DWC3_GRXTHRCFG 0xc10c
84#define DWC3_GCTL 0xc110
85#define DWC3_GEVTEN 0xc114
86#define DWC3_GSTS 0xc118
87#define DWC3_GSNPSID 0xc120
88#define DWC3_GGPIO 0xc124
89#define DWC3_GUID 0xc128
90#define DWC3_GUCTL 0xc12c
91#define DWC3_GBUSERRADDR0 0xc130
92#define DWC3_GBUSERRADDR1 0xc134
93#define DWC3_GPRTBIMAP0 0xc138
94#define DWC3_GPRTBIMAP1 0xc13c
95#define DWC3_GHWPARAMS0 0xc140
96#define DWC3_GHWPARAMS1 0xc144
97#define DWC3_GHWPARAMS2 0xc148
98#define DWC3_GHWPARAMS3 0xc14c
99#define DWC3_GHWPARAMS4 0xc150
100#define DWC3_GHWPARAMS5 0xc154
101#define DWC3_GHWPARAMS6 0xc158
102#define DWC3_GHWPARAMS7 0xc15c
103#define DWC3_GDBGFIFOSPACE 0xc160
104#define DWC3_GDBGLTSSM 0xc164
105#define DWC3_GPRTBIMAP_HS0 0xc180
106#define DWC3_GPRTBIMAP_HS1 0xc184
107#define DWC3_GPRTBIMAP_FS0 0xc188
108#define DWC3_GPRTBIMAP_FS1 0xc18c
109
110#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
111#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
112
113#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
114
115#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
116
117#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
118#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
119
120#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
121#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
122#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
123#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
124
125#define DWC3_GHWPARAMS8 0xc600
126
127/* Device Registers */
128#define DWC3_DCFG 0xc700
129#define DWC3_DCTL 0xc704
130#define DWC3_DEVTEN 0xc708
131#define DWC3_DSTS 0xc70c
132#define DWC3_DGCMDPAR 0xc710
133#define DWC3_DGCMD 0xc714
134#define DWC3_DALEPENA 0xc720
135#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
136#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
137#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
138#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
139
140/* OTG Registers */
141#define DWC3_OCFG 0xcc00
142#define DWC3_OCTL 0xcc04
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143#define DWC3_OEVT 0xcc08
144#define DWC3_OEVTEN 0xcc0C
145#define DWC3_OSTS 0xcc10
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146
147/* Bit fields */
148
149/* Global Configuration Register */
1d046793 150#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
f4aadbe4 151#define DWC3_GCTL_U2RSTECN (1 << 16)
1d046793 152#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
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153#define DWC3_GCTL_CLK_BUS (0)
154#define DWC3_GCTL_CLK_PIPE (1)
155#define DWC3_GCTL_CLK_PIPEHALF (2)
156#define DWC3_GCTL_CLK_MASK (3)
157
0b9fe32d 158#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
1d046793 159#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
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160#define DWC3_GCTL_PRTCAP_HOST 1
161#define DWC3_GCTL_PRTCAP_DEVICE 2
162#define DWC3_GCTL_PRTCAP_OTG 3
163
2c61a8ef 164#define DWC3_GCTL_CORESOFTRESET (1 << 11)
183ca111 165#define DWC3_GCTL_SOFITPSYNC (1 << 10)
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166#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
167#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
168#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
9a5b2f31 169#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
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170#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
171#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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172
173/* Global USB2 PHY Configuration Register */
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174#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
175#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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176
177/* Global USB3 PIPE Control Register */
2c61a8ef 178#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
b5a65c40 179#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
2c61a8ef 180#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
72246da4 181
457e84b6 182/* Global TX Fifo Size Register */
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183#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
184#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
457e84b6 185
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186/* Global Event Size Registers */
187#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
188#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
189
aabb7075 190/* Global HWPARAMS1 Register */
1d046793 191#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
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192#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
193#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
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194#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
195#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
196#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
197
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198/* Global HWPARAMS3 Register */
199#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
200#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
201#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
202#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
203#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
204#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
205#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
206#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
207#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
208#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
209#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
210
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211/* Global HWPARAMS4 Register */
212#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
213#define DWC3_MAX_HIBER_SCRATCHBUFS 15
aabb7075 214
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215/* Global HWPARAMS6 Register */
216#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
217
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218/* Device Configuration Register */
219#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
220#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
221
222#define DWC3_DCFG_SPEED_MASK (7 << 0)
223#define DWC3_DCFG_SUPERSPEED (4 << 0)
224#define DWC3_DCFG_HIGHSPEED (0 << 0)
225#define DWC3_DCFG_FULLSPEED2 (1 << 0)
226#define DWC3_DCFG_LOWSPEED (2 << 0)
227#define DWC3_DCFG_FULLSPEED1 (3 << 0)
228
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229#define DWC3_DCFG_LPM_CAP (1 << 22)
230
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231/* Device Control Register */
232#define DWC3_DCTL_RUN_STOP (1 << 31)
233#define DWC3_DCTL_CSFTRST (1 << 30)
234#define DWC3_DCTL_LSFTRST (1 << 29)
235
236#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
7e39b817 237#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
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238
239#define DWC3_DCTL_APPL1RES (1 << 23)
240
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241/* These apply for core versions 1.87a and earlier */
242#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
243#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
244#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
245#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
246#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
247#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
248#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
249
250/* These apply for core versions 1.94a and later */
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251#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
252#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
8db7ed15 253
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254#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
255#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
256#define DWC3_DCTL_CRS (1 << 17)
257#define DWC3_DCTL_CSS (1 << 16)
258
259#define DWC3_DCTL_INITU2ENA (1 << 12)
260#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
261#define DWC3_DCTL_INITU1ENA (1 << 10)
262#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
263#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
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264
265#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
266#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
267
268#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
269#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
270#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
271#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
272#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
273#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
274#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
275
276/* Device Event Enable Register */
277#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
278#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
279#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
280#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
281#define DWC3_DEVTEN_SOFEN (1 << 7)
282#define DWC3_DEVTEN_EOPFEN (1 << 6)
2c61a8ef 283#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
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284#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
285#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
286#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
287#define DWC3_DEVTEN_USBRSTEN (1 << 1)
288#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
289
290/* Device Status Register */
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291#define DWC3_DSTS_DCNRD (1 << 29)
292
293/* This applies for core versions 1.87a and earlier */
72246da4 294#define DWC3_DSTS_PWRUPREQ (1 << 24)
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295
296/* These apply for core versions 1.94a and later */
297#define DWC3_DSTS_RSS (1 << 25)
298#define DWC3_DSTS_SSS (1 << 24)
299
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300#define DWC3_DSTS_COREIDLE (1 << 23)
301#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
302
303#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
304#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
305
306#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
307
d05b8182 308#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
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309#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
310
311#define DWC3_DSTS_CONNECTSPD (7 << 0)
312
313#define DWC3_DSTS_SUPERSPEED (4 << 0)
314#define DWC3_DSTS_HIGHSPEED (0 << 0)
315#define DWC3_DSTS_FULLSPEED2 (1 << 0)
316#define DWC3_DSTS_LOWSPEED (2 << 0)
317#define DWC3_DSTS_FULLSPEED1 (3 << 0)
318
319/* Device Generic Command Register */
320#define DWC3_DGCMD_SET_LMP 0x01
321#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
322#define DWC3_DGCMD_XMIT_FUNCTION 0x03
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323
324/* These apply for core versions 1.94a and later */
325#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
326#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
327
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328#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
329#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
330#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
331#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
332
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333#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
334#define DWC3_DGCMD_CMDACT (1 << 10)
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335#define DWC3_DGCMD_CMDIOC (1 << 8)
336
337/* Device Generic Command Parameter Register */
338#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
339#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
340#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
341#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
342#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
343#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
b09bb642 344
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345/* Device Endpoint Command Register */
346#define DWC3_DEPCMD_PARAM_SHIFT 16
1d046793 347#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
835fadb4 348#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
b09bb642 349#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
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350#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
351#define DWC3_DEPCMD_CMDACT (1 << 10)
352#define DWC3_DEPCMD_CMDIOC (1 << 8)
353
354#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
355#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
356#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
357#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
358#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
359#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
2c61a8ef 360/* This applies for core versions 1.90a and earlier */
72246da4 361#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
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362/* This applies for core versions 1.94a and later */
363#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
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364#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
365#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
366
367/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
368#define DWC3_DALEPENA_EP(n) (1 << n)
369
370#define DWC3_DEPCMD_TYPE_CONTROL 0
371#define DWC3_DEPCMD_TYPE_ISOC 1
372#define DWC3_DEPCMD_TYPE_BULK 2
373#define DWC3_DEPCMD_TYPE_INTR 3
374
375/* Structures */
376
f6bafc6a 377struct dwc3_trb;
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378
379/**
380 * struct dwc3_event_buffer - Software event buffer representation
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381 * @buf: _THE_ buffer
382 * @length: size of this buffer
abed4118 383 * @lpos: event offset
60d04bbe 384 * @count: cache of last read event count register
abed4118 385 * @flags: flags related to this event buffer
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386 * @dma: dma_addr_t
387 * @dwc: pointer to DWC controller
388 */
389struct dwc3_event_buffer {
390 void *buf;
391 unsigned length;
392 unsigned int lpos;
60d04bbe 393 unsigned int count;
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394 unsigned int flags;
395
396#define DWC3_EVENT_PENDING BIT(0)
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397
398 dma_addr_t dma;
399
400 struct dwc3 *dwc;
401};
402
403#define DWC3_EP_FLAG_STALLED (1 << 0)
404#define DWC3_EP_FLAG_WEDGED (1 << 1)
405
406#define DWC3_EP_DIRECTION_TX true
407#define DWC3_EP_DIRECTION_RX false
408
409#define DWC3_TRB_NUM 32
410#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
411
412/**
413 * struct dwc3_ep - device side endpoint representation
414 * @endpoint: usb endpoint
415 * @request_list: list of requests for this endpoint
416 * @req_queued: list of requests on this ep which have TRBs setup
417 * @trb_pool: array of transaction buffers
418 * @trb_pool_dma: dma address of @trb_pool
419 * @free_slot: next slot which is going to be used
420 * @busy_slot: first slot which is owned by HW
421 * @desc: usb_endpoint_descriptor pointer
422 * @dwc: pointer to DWC controller
4cfcf876 423 * @saved_state: ep state saved during hibernation
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424 * @flags: endpoint flags (wedged, stalled, ...)
425 * @current_trb: index of current used trb
426 * @number: endpoint number (1 - 15)
427 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
b4996a86 428 * @resource_index: Resource transfer index
c75f52fb 429 * @interval: the interval on which the ISOC transfer is started
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430 * @name: a human readable name e.g. ep1out-bulk
431 * @direction: true for TX, false for RX
879631aa 432 * @stream_capable: true when streams are enabled
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433 */
434struct dwc3_ep {
435 struct usb_ep endpoint;
436 struct list_head request_list;
437 struct list_head req_queued;
438
f6bafc6a 439 struct dwc3_trb *trb_pool;
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440 dma_addr_t trb_pool_dma;
441 u32 free_slot;
442 u32 busy_slot;
c90bfaec 443 const struct usb_ss_ep_comp_descriptor *comp_desc;
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444 struct dwc3 *dwc;
445
4cfcf876 446 u32 saved_state;
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447 unsigned flags;
448#define DWC3_EP_ENABLED (1 << 0)
449#define DWC3_EP_STALL (1 << 1)
450#define DWC3_EP_WEDGE (1 << 2)
451#define DWC3_EP_BUSY (1 << 4)
452#define DWC3_EP_PENDING_REQUEST (1 << 5)
d6d6ec7b 453#define DWC3_EP_MISSED_ISOC (1 << 6)
72246da4 454
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455 /* This last one is specific to EP0 */
456#define DWC3_EP0_DIR_IN (1 << 31)
457
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458 unsigned current_trb;
459
460 u8 number;
461 u8 type;
b4996a86 462 u8 resource_index;
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463 u32 interval;
464
465 char name[20];
466
467 unsigned direction:1;
879631aa 468 unsigned stream_capable:1;
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469};
470
471enum dwc3_phy {
472 DWC3_PHY_UNKNOWN = 0,
473 DWC3_PHY_USB3,
474 DWC3_PHY_USB2,
475};
476
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477enum dwc3_ep0_next {
478 DWC3_EP0_UNKNOWN = 0,
479 DWC3_EP0_COMPLETE,
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480 DWC3_EP0_NRDY_DATA,
481 DWC3_EP0_NRDY_STATUS,
482};
483
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484enum dwc3_ep0_state {
485 EP0_UNCONNECTED = 0,
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486 EP0_SETUP_PHASE,
487 EP0_DATA_PHASE,
488 EP0_STATUS_PHASE,
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489};
490
491enum dwc3_link_state {
492 /* In SuperSpeed */
493 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
494 DWC3_LINK_STATE_U1 = 0x01,
495 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
496 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
497 DWC3_LINK_STATE_SS_DIS = 0x04,
498 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
499 DWC3_LINK_STATE_SS_INACT = 0x06,
500 DWC3_LINK_STATE_POLL = 0x07,
501 DWC3_LINK_STATE_RECOV = 0x08,
502 DWC3_LINK_STATE_HRESET = 0x09,
503 DWC3_LINK_STATE_CMPLY = 0x0a,
504 DWC3_LINK_STATE_LPBK = 0x0b,
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505 DWC3_LINK_STATE_RESET = 0x0e,
506 DWC3_LINK_STATE_RESUME = 0x0f,
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507 DWC3_LINK_STATE_MASK = 0x0f,
508};
509
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510/* TRB Length, PCM and Status */
511#define DWC3_TRB_SIZE_MASK (0x00ffffff)
512#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
513#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
389f2828 514#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
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515
516#define DWC3_TRBSTS_OK 0
517#define DWC3_TRBSTS_MISSED_ISOC 1
518#define DWC3_TRBSTS_SETUP_PENDING 2
2c61a8ef 519#define DWC3_TRB_STS_XFER_IN_PROG 4
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520
521/* TRB Control */
522#define DWC3_TRB_CTRL_HWO (1 << 0)
523#define DWC3_TRB_CTRL_LST (1 << 1)
524#define DWC3_TRB_CTRL_CHN (1 << 2)
525#define DWC3_TRB_CTRL_CSP (1 << 3)
526#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
527#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
528#define DWC3_TRB_CTRL_IOC (1 << 11)
529#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
530
531#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
532#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
533#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
534#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
535#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
536#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
537#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
538#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
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539
540/**
f6bafc6a 541 * struct dwc3_trb - transfer request block (hw format)
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542 * @bpl: DW0-3
543 * @bph: DW4-7
544 * @size: DW8-B
545 * @trl: DWC-F
546 */
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547struct dwc3_trb {
548 u32 bpl;
549 u32 bph;
550 u32 size;
551 u32 ctrl;
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552} __packed;
553
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554/**
555 * dwc3_hwparams - copy of HWPARAMS registers
556 * @hwparams0 - GHWPARAMS0
557 * @hwparams1 - GHWPARAMS1
558 * @hwparams2 - GHWPARAMS2
559 * @hwparams3 - GHWPARAMS3
560 * @hwparams4 - GHWPARAMS4
561 * @hwparams5 - GHWPARAMS5
562 * @hwparams6 - GHWPARAMS6
563 * @hwparams7 - GHWPARAMS7
564 * @hwparams8 - GHWPARAMS8
565 */
566struct dwc3_hwparams {
567 u32 hwparams0;
568 u32 hwparams1;
569 u32 hwparams2;
570 u32 hwparams3;
571 u32 hwparams4;
572 u32 hwparams5;
573 u32 hwparams6;
574 u32 hwparams7;
575 u32 hwparams8;
576};
577
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578/* HWPARAMS0 */
579#define DWC3_MODE(n) ((n) & 0x7)
580
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581#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
582
0949e99b 583/* HWPARAMS1 */
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584#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
585
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586/* HWPARAMS3 */
587#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
588#define DWC3_NUM_EPS_MASK (0x3f << 12)
589#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
590 (DWC3_NUM_EPS_MASK)) >> 12)
591#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
592 (DWC3_NUM_IN_EPS_MASK)) >> 18)
593
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594/* HWPARAMS7 */
595#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
9f622b2a 596
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597struct dwc3_request {
598 struct usb_request request;
599 struct list_head list;
600 struct dwc3_ep *dep;
e5ba5ec8 601 u32 start_slot;
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SAS
602
603 u8 epnum;
f6bafc6a 604 struct dwc3_trb *trb;
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605 dma_addr_t trb_dma;
606
607 unsigned direction:1;
608 unsigned mapped:1;
609 unsigned queued:1;
610};
611
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612/*
613 * struct dwc3_scratchpad_array - hibernation scratchpad array
614 * (format defined by hw)
615 */
616struct dwc3_scratchpad_array {
617 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
618};
619
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620/**
621 * struct dwc3 - representation of our controller
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622 * @ctrl_req: usb control request which is used for ep0
623 * @ep0_trb: trb which is used for the ctrl_req
5812b1c2 624 * @ep0_bounce: bounce buffer for ep0
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625 * @setup_buf: used while precessing STD USB requests
626 * @ctrl_req_addr: dma address of ctrl_req
627 * @ep0_trb: dma address of ep0_trb
628 * @ep0_usb_req: dummy req used while handling STD USB requests
5812b1c2 629 * @ep0_bounce_addr: dma address of ep0_bounce
0ffcaf37 630 * @scratch_addr: dma address of scratchbuf
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631 * @lock: for synchronizing
632 * @dev: pointer to our struct device
d07e8819 633 * @xhci: pointer to our xHCI child
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634 * @event_buffer_list: a list of event buffers
635 * @gadget: device side representation of the peripheral controller
636 * @gadget_driver: pointer to the gadget driver
637 * @regs: base address for our registers
638 * @regs_size: address space size
0ffcaf37 639 * @nr_scratch: number of scratch buffers
9f622b2a 640 * @num_event_buffers: calculated number of event buffers
fae2b904 641 * @u1u2: only used on revisions <1.83a for workaround
6c167fc9 642 * @maximum_speed: maximum speed requested (mainly for testing purposes)
72246da4 643 * @revision: revision register contents
a45c82b8 644 * @dr_mode: requested mode of operation
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645 * @usb2_phy: pointer to USB2 PHY
646 * @usb3_phy: pointer to USB3 PHY
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KVA
647 * @usb2_generic_phy: pointer to USB2 PHY
648 * @usb3_generic_phy: pointer to USB3 PHY
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649 * @dcfg: saved contents of DCFG register
650 * @gctl: saved contents of GCTL register
c12a0d86 651 * @isoch_delay: wValue from Set Isochronous Delay request;
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652 * @u2sel: parameter from Set SEL request.
653 * @u2pel: parameter from Set SEL request.
654 * @u1sel: parameter from Set SEL request.
655 * @u1pel: parameter from Set SEL request.
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656 * @num_out_eps: number of out endpoints
657 * @num_in_eps: number of in endpoints
b53c772d 658 * @ep0_next_event: hold the next expected event
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659 * @ep0state: state of endpoint zero
660 * @link_state: link state
661 * @speed: device speed (super, high, full, low)
662 * @mem: points to start of memory which is used for this struct.
a3299499 663 * @hwparams: copy of hwparams registers
72246da4 664 * @root: debugfs root folder pointer
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665 * @regset: debugfs pointer to regdump file
666 * @test_mode: true when we're entering a USB test mode
667 * @test_mode_nr: test feature selector
80caf7d2 668 * @lpm_nyet_threshold: LPM NYET response threshold
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669 * @delayed_status: true when gadget driver asks for delayed status
670 * @ep0_bounced: true when we used bounce buffer
671 * @ep0_expect_in: true when we expect a DATA IN transfer
81bc5599 672 * @has_hibernation: true when dwc3 was configured with Hibernation
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HR
673 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
674 * there's now way for software to detect this in runtime.
f2b685d5 675 * @is_selfpowered: true when we are selfpowered
946bd579 676 * @is_fpga: true when we are using the FPGA board
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677 * @needs_fifo_resize: not all users might want fifo resizing, flag it
678 * @pullups_connected: true when Run/Stop bit is set
679 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
680 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
681 * @start_config_issued: true when StartConfig command has been issued
682 * @three_stage_setup: set if we perform a three phase setup
3b81221a 683 * @disable_scramble_quirk: set if we enable the disable scramble quirk
9a5b2f31 684 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
b5a65c40 685 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
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686 */
687struct dwc3 {
688 struct usb_ctrlrequest *ctrl_req;
f6bafc6a 689 struct dwc3_trb *ep0_trb;
5812b1c2 690 void *ep0_bounce;
0ffcaf37 691 void *scratchbuf;
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692 u8 *setup_buf;
693 dma_addr_t ctrl_req_addr;
694 dma_addr_t ep0_trb_addr;
5812b1c2 695 dma_addr_t ep0_bounce_addr;
0ffcaf37 696 dma_addr_t scratch_addr;
e0ce0b0a 697 struct dwc3_request ep0_usb_req;
789451f6 698
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699 /* device lock */
700 spinlock_t lock;
789451f6 701
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702 struct device *dev;
703
d07e8819 704 struct platform_device *xhci;
51249dca 705 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
d07e8819 706
457d3f21 707 struct dwc3_event_buffer **ev_buffs;
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708 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
709
710 struct usb_gadget gadget;
711 struct usb_gadget_driver *gadget_driver;
712
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713 struct usb_phy *usb2_phy;
714 struct usb_phy *usb3_phy;
715
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716 struct phy *usb2_generic_phy;
717 struct phy *usb3_generic_phy;
718
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719 void __iomem *regs;
720 size_t regs_size;
721
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722 enum usb_dr_mode dr_mode;
723
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724 /* used for suspend/resume */
725 u32 dcfg;
726 u32 gctl;
727
0ffcaf37 728 u32 nr_scratch;
9f622b2a 729 u32 num_event_buffers;
fae2b904 730 u32 u1u2;
6c167fc9 731 u32 maximum_speed;
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732 u32 revision;
733
734#define DWC3_REVISION_173A 0x5533173a
735#define DWC3_REVISION_175A 0x5533175a
736#define DWC3_REVISION_180A 0x5533180a
737#define DWC3_REVISION_183A 0x5533183a
738#define DWC3_REVISION_185A 0x5533185a
2c61a8ef 739#define DWC3_REVISION_187A 0x5533187a
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740#define DWC3_REVISION_188A 0x5533188a
741#define DWC3_REVISION_190A 0x5533190a
2c61a8ef 742#define DWC3_REVISION_194A 0x5533194a
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743#define DWC3_REVISION_200A 0x5533200a
744#define DWC3_REVISION_202A 0x5533202a
745#define DWC3_REVISION_210A 0x5533210a
746#define DWC3_REVISION_220A 0x5533220a
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FB
747#define DWC3_REVISION_230A 0x5533230a
748#define DWC3_REVISION_240A 0x5533240a
749#define DWC3_REVISION_250A 0x5533250a
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750#define DWC3_REVISION_260A 0x5533260a
751#define DWC3_REVISION_270A 0x5533270a
752#define DWC3_REVISION_280A 0x5533280a
72246da4 753
b53c772d 754 enum dwc3_ep0_next ep0_next_event;
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FB
755 enum dwc3_ep0_state ep0state;
756 enum dwc3_link_state link_state;
72246da4 757
c12a0d86 758 u16 isoch_delay;
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FB
759 u16 u2sel;
760 u16 u2pel;
761 u8 u1sel;
762 u8 u1pel;
763
72246da4 764 u8 speed;
865e09e7 765
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FB
766 u8 num_out_eps;
767 u8 num_in_eps;
768
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FB
769 void *mem;
770
a3299499 771 struct dwc3_hwparams hwparams;
72246da4 772 struct dentry *root;
d7668024 773 struct debugfs_regset32 *regset;
3b637367
GC
774
775 u8 test_mode;
776 u8 test_mode_nr;
80caf7d2 777 u8 lpm_nyet_threshold;
f2b685d5
FB
778
779 unsigned delayed_status:1;
780 unsigned ep0_bounced:1;
781 unsigned ep0_expect_in:1;
81bc5599 782 unsigned has_hibernation:1;
80caf7d2 783 unsigned has_lpm_erratum:1;
f2b685d5 784 unsigned is_selfpowered:1;
946bd579 785 unsigned is_fpga:1;
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FB
786 unsigned needs_fifo_resize:1;
787 unsigned pullups_connected:1;
788 unsigned resize_fifos:1;
789 unsigned setup_packet_pending:1;
790 unsigned start_config_issued:1;
791 unsigned three_stage_setup:1;
3b81221a
HR
792
793 unsigned disable_scramble_quirk:1;
9a5b2f31 794 unsigned u2exit_lfps_quirk:1;
b5a65c40 795 unsigned u2ss_inp3_quirk:1;
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796};
797
798/* -------------------------------------------------------------------------- */
799
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800/* -------------------------------------------------------------------------- */
801
802struct dwc3_event_type {
803 u32 is_devspec:1;
1974d494
HR
804 u32 type:7;
805 u32 reserved8_31:24;
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FB
806} __packed;
807
808#define DWC3_DEPEVT_XFERCOMPLETE 0x01
809#define DWC3_DEPEVT_XFERINPROGRESS 0x02
810#define DWC3_DEPEVT_XFERNOTREADY 0x03
811#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
812#define DWC3_DEPEVT_STREAMEVT 0x06
813#define DWC3_DEPEVT_EPCMDCMPLT 0x07
814
815/**
816 * struct dwc3_event_depvt - Device Endpoint Events
817 * @one_bit: indicates this is an endpoint event (not used)
818 * @endpoint_number: number of the endpoint
819 * @endpoint_event: The event we have:
820 * 0x00 - Reserved
821 * 0x01 - XferComplete
822 * 0x02 - XferInProgress
823 * 0x03 - XferNotReady
824 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
825 * 0x05 - Reserved
826 * 0x06 - StreamEvt
827 * 0x07 - EPCmdCmplt
828 * @reserved11_10: Reserved, don't use.
829 * @status: Indicates the status of the event. Refer to databook for
830 * more information.
831 * @parameters: Parameters of the current event. Refer to databook for
832 * more information.
833 */
834struct dwc3_event_depevt {
835 u32 one_bit:1;
836 u32 endpoint_number:5;
837 u32 endpoint_event:4;
838 u32 reserved11_10:2;
839 u32 status:4;
40aa41fb
FB
840
841/* Within XferNotReady */
842#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
843
844/* Within XferComplete */
1d046793
PZ
845#define DEPEVT_STATUS_BUSERR (1 << 0)
846#define DEPEVT_STATUS_SHORT (1 << 1)
847#define DEPEVT_STATUS_IOC (1 << 2)
72246da4 848#define DEPEVT_STATUS_LST (1 << 3)
dc137f01 849
879631aa
FB
850/* Stream event only */
851#define DEPEVT_STREAMEVT_FOUND 1
852#define DEPEVT_STREAMEVT_NOTFOUND 2
853
dc137f01 854/* Control-only Status */
dc137f01
FB
855#define DEPEVT_STATUS_CONTROL_DATA 1
856#define DEPEVT_STATUS_CONTROL_STATUS 2
857
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FB
858 u32 parameters:16;
859} __packed;
860
861/**
862 * struct dwc3_event_devt - Device Events
863 * @one_bit: indicates this is a non-endpoint event (not used)
864 * @device_event: indicates it's a device event. Should read as 0x00
865 * @type: indicates the type of device event.
866 * 0 - DisconnEvt
867 * 1 - USBRst
868 * 2 - ConnectDone
869 * 3 - ULStChng
870 * 4 - WkUpEvt
871 * 5 - Reserved
872 * 6 - EOPF
873 * 7 - SOF
874 * 8 - Reserved
875 * 9 - ErrticErr
876 * 10 - CmdCmplt
877 * 11 - EvntOverflow
878 * 12 - VndrDevTstRcved
879 * @reserved15_12: Reserved, not used
880 * @event_info: Information about this event
06f9b6e5 881 * @reserved31_25: Reserved, not used
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FB
882 */
883struct dwc3_event_devt {
884 u32 one_bit:1;
885 u32 device_event:7;
886 u32 type:4;
887 u32 reserved15_12:4;
06f9b6e5
HR
888 u32 event_info:9;
889 u32 reserved31_25:7;
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FB
890} __packed;
891
892/**
893 * struct dwc3_event_gevt - Other Core Events
894 * @one_bit: indicates this is a non-endpoint event (not used)
895 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
896 * @phy_port_number: self-explanatory
897 * @reserved31_12: Reserved, not used.
898 */
899struct dwc3_event_gevt {
900 u32 one_bit:1;
901 u32 device_event:7;
902 u32 phy_port_number:4;
903 u32 reserved31_12:20;
904} __packed;
905
906/**
907 * union dwc3_event - representation of Event Buffer contents
908 * @raw: raw 32-bit event
909 * @type: the type of the event
910 * @depevt: Device Endpoint Event
911 * @devt: Device Event
912 * @gevt: Global Event
913 */
914union dwc3_event {
915 u32 raw;
916 struct dwc3_event_type type;
917 struct dwc3_event_depevt depevt;
918 struct dwc3_event_devt devt;
919 struct dwc3_event_gevt gevt;
920};
921
61018305
FB
922/**
923 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
924 * parameters
925 * @param2: third parameter
926 * @param1: second parameter
927 * @param0: first parameter
928 */
929struct dwc3_gadget_ep_cmd_params {
930 u32 param2;
931 u32 param1;
932 u32 param0;
933};
934
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935/*
936 * DWC3 Features to be used as Driver Data
937 */
938
939#define DWC3_HAS_PERIPHERAL BIT(0)
940#define DWC3_HAS_XHCI BIT(1)
941#define DWC3_HAS_OTG BIT(3)
942
d07e8819 943/* prototypes */
3140e8cb 944void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
457e84b6 945int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
3140e8cb 946
388e5c51 947#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
d07e8819
FB
948int dwc3_host_init(struct dwc3 *dwc);
949void dwc3_host_exit(struct dwc3 *dwc);
388e5c51
VG
950#else
951static inline int dwc3_host_init(struct dwc3 *dwc)
952{ return 0; }
953static inline void dwc3_host_exit(struct dwc3 *dwc)
954{ }
955#endif
956
957#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
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958int dwc3_gadget_init(struct dwc3 *dwc);
959void dwc3_gadget_exit(struct dwc3 *dwc);
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960int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
961int dwc3_gadget_get_link_state(struct dwc3 *dwc);
962int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
963int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
964 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
3ece0ec4 965int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
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966#else
967static inline int dwc3_gadget_init(struct dwc3 *dwc)
968{ return 0; }
969static inline void dwc3_gadget_exit(struct dwc3 *dwc)
970{ }
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971static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
972{ return 0; }
973static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
974{ return 0; }
975static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
976 enum dwc3_link_state state)
977{ return 0; }
978
979static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
980 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
981{ return 0; }
982static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
983 int cmd, u32 param)
984{ return 0; }
388e5c51 985#endif
f80b45e7 986
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987/* power management interface */
988#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
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989int dwc3_gadget_suspend(struct dwc3 *dwc);
990int dwc3_gadget_resume(struct dwc3 *dwc);
991#else
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992static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
993{
994 return 0;
995}
996
997static inline int dwc3_gadget_resume(struct dwc3 *dwc)
998{
999 return 0;
1000}
1001#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1002
72246da4 1003#endif /* __DRIVERS_USB_DWC3_CORE_H */