projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 72246da4 FB |
1 | /** |
| 2 | * core.h - DesignWare USB3 DRD Core Header | |
| 3 | * | |
| 4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
| 5 | * All rights reserved. | |
| 6 | * | |
| 7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
| 8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
| 9 | * | |
| 10 | * Redistribution and use in source and binary forms, with or without | |
| 11 | * modification, are permitted provided that the following conditions | |
| 12 | * are met: | |
| 13 | * 1. Redistributions of source code must retain the above copyright | |
| 14 | * notice, this list of conditions, and the following disclaimer, | |
| 15 | * without modification. | |
| 16 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 17 | * notice, this list of conditions and the following disclaimer in the | |
| 18 | * documentation and/or other materials provided with the distribution. | |
| 19 | * 3. The names of the above-listed copyright holders may not be used | |
| 20 | * to endorse or promote products derived from this software without | |
| 21 | * specific prior written permission. | |
| 22 | * | |
| 23 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
| 24 | * GNU General Public License ("GPL") version 2, as published by the Free | |
| 25 | * Software Foundation. | |
| 26 | * | |
| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
| 28 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
| 29 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
| 30 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
| 31 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
| 32 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
| 33 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
| 34 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
| 35 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
| 36 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
| 37 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 38 | */ | |
| 39 | ||
| 40 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
| 41 | #define __DRIVERS_USB_DWC3_CORE_H | |
| 42 | ||
| 43 | #include <linux/device.h> | |
| 44 | #include <linux/spinlock.h> | |
| 45 | #include <linux/list.h> | |
| 46 | #include <linux/dma-mapping.h> | |
| 47 | #include <linux/mm.h> | |
| 48 | #include <linux/debugfs.h> | |
| 49 | ||
| 50 | #include <linux/usb/ch9.h> | |
| 51 | #include <linux/usb/gadget.h> | |
| 52 | ||
| 53 | /* Global constants */ | |
| 54 | #define DWC3_ENDPOINTS_NUM 32 | |
| 55 | ||
| 56 | #define DWC3_EVENT_BUFFERS_NUM 2 | |
| 57 | #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE | |
| 58 | #define DWC3_EVENT_TYPE_MASK 0xfe | |
| 59 | ||
| 60 | #define DWC3_EVENT_TYPE_DEV 0 | |
| 61 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
| 62 | #define DWC3_EVENT_TYPE_I2C 4 | |
| 63 | ||
| 64 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
| 65 | #define DWC3_DEVICE_EVENT_RESET 1 | |
| 66 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
| 67 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
| 68 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
| 69 | #define DWC3_DEVICE_EVENT_EOPF 6 | |
| 70 | #define DWC3_DEVICE_EVENT_SOF 7 | |
| 71 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
| 72 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
| 73 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
| 74 | ||
| 75 | #define DWC3_GEVNTCOUNT_MASK 0xfffc | |
| 76 | #define DWC3_GSNPSID_MASK 0xffff0000 | |
| 77 | #define DWC3_GSNPSREV_MASK 0xffff | |
| 78 | ||
| 79 | /* Global Registers */ | |
| 80 | #define DWC3_GSBUSCFG0 0xc100 | |
| 81 | #define DWC3_GSBUSCFG1 0xc104 | |
| 82 | #define DWC3_GTXTHRCFG 0xc108 | |
| 83 | #define DWC3_GRXTHRCFG 0xc10c | |
| 84 | #define DWC3_GCTL 0xc110 | |
| 85 | #define DWC3_GEVTEN 0xc114 | |
| 86 | #define DWC3_GSTS 0xc118 | |
| 87 | #define DWC3_GSNPSID 0xc120 | |
| 88 | #define DWC3_GGPIO 0xc124 | |
| 89 | #define DWC3_GUID 0xc128 | |
| 90 | #define DWC3_GUCTL 0xc12c | |
| 91 | #define DWC3_GBUSERRADDR0 0xc130 | |
| 92 | #define DWC3_GBUSERRADDR1 0xc134 | |
| 93 | #define DWC3_GPRTBIMAP0 0xc138 | |
| 94 | #define DWC3_GPRTBIMAP1 0xc13c | |
| 95 | #define DWC3_GHWPARAMS0 0xc140 | |
| 96 | #define DWC3_GHWPARAMS1 0xc144 | |
| 97 | #define DWC3_GHWPARAMS2 0xc148 | |
| 98 | #define DWC3_GHWPARAMS3 0xc14c | |
| 99 | #define DWC3_GHWPARAMS4 0xc150 | |
| 100 | #define DWC3_GHWPARAMS5 0xc154 | |
| 101 | #define DWC3_GHWPARAMS6 0xc158 | |
| 102 | #define DWC3_GHWPARAMS7 0xc15c | |
| 103 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
| 104 | #define DWC3_GDBGLTSSM 0xc164 | |
| 105 | #define DWC3_GPRTBIMAP_HS0 0xc180 | |
| 106 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
| 107 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
| 108 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
| 109 | ||
| 110 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) | |
| 111 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) | |
| 112 | ||
| 113 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) | |
| 114 | ||
| 115 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) | |
| 116 | ||
| 117 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) | |
| 118 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) | |
| 119 | ||
| 120 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) | |
| 121 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) | |
| 122 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) | |
| 123 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) | |
| 124 | ||
| 125 | #define DWC3_GHWPARAMS8 0xc600 | |
| 126 | ||
| 127 | /* Device Registers */ | |
| 128 | #define DWC3_DCFG 0xc700 | |
| 129 | #define DWC3_DCTL 0xc704 | |
| 130 | #define DWC3_DEVTEN 0xc708 | |
| 131 | #define DWC3_DSTS 0xc70c | |
| 132 | #define DWC3_DGCMDPAR 0xc710 | |
| 133 | #define DWC3_DGCMD 0xc714 | |
| 134 | #define DWC3_DALEPENA 0xc720 | |
| 135 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) | |
| 136 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) | |
| 137 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) | |
| 138 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) | |
| 139 | ||
| 140 | /* OTG Registers */ | |
| 141 | #define DWC3_OCFG 0xcc00 | |
| 142 | #define DWC3_OCTL 0xcc04 | |
| 143 | #define DWC3_OEVTEN 0xcc08 | |
| 144 | #define DWC3_OSTS 0xcc0C | |
| 145 | ||
| 146 | /* Bit fields */ | |
| 147 | ||
| 148 | /* Global Configuration Register */ | |
| 149 | #define DWC3_GCTL_PWRDNSCALE(n) (n << 19) | |
| 150 | #define DWC3_GCTL_U2RSTECN 16 | |
| 151 | #define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6) | |
| 152 | #define DWC3_GCTL_CLK_BUS (0) | |
| 153 | #define DWC3_GCTL_CLK_PIPE (1) | |
| 154 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
| 155 | #define DWC3_GCTL_CLK_MASK (3) | |
| 156 | ||
| 157 | #define DWC3_GCTL_PRTCAPDIR(n) (n << 12) | |
| 158 | #define DWC3_GCTL_PRTCAP_HOST 1 | |
| 159 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
| 160 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
| 161 | ||
| 162 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) | |
| 163 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) | |
| 164 | ||
| 165 | /* Global USB2 PHY Configuration Register */ | |
| 166 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) | |
| 167 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) | |
| 168 | ||
| 169 | /* Global USB3 PIPE Control Register */ | |
| 170 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) | |
| 171 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) | |
| 172 | ||
| 173 | /* Device Configuration Register */ | |
| 174 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
| 175 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
| 176 | ||
| 177 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
| 178 | #define DWC3_DCFG_SUPERSPEED (4 << 0) | |
| 179 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
| 180 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) | |
| 181 | #define DWC3_DCFG_LOWSPEED (2 << 0) | |
| 182 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) | |
| 183 | ||
| 184 | /* Device Control Register */ | |
| 185 | #define DWC3_DCTL_RUN_STOP (1 << 31) | |
| 186 | #define DWC3_DCTL_CSFTRST (1 << 30) | |
| 187 | #define DWC3_DCTL_LSFTRST (1 << 29) | |
| 188 | ||
| 189 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
| 190 | #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24) | |
| 191 | ||
| 192 | #define DWC3_DCTL_APPL1RES (1 << 23) | |
| 193 | ||
| 194 | #define DWC3_DCTL_INITU2ENA (1 << 12) | |
| 195 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | |
| 196 | #define DWC3_DCTL_INITU1ENA (1 << 10) | |
| 197 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | |
| 198 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | |
| 199 | ||
| 200 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
| 201 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
| 202 | ||
| 203 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
| 204 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
| 205 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
| 206 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
| 207 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
| 208 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
| 209 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
| 210 | ||
| 211 | /* Device Event Enable Register */ | |
| 212 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) | |
| 213 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) | |
| 214 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) | |
| 215 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) | |
| 216 | #define DWC3_DEVTEN_SOFEN (1 << 7) | |
| 217 | #define DWC3_DEVTEN_EOPFEN (1 << 6) | |
| 218 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) | |
| 219 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) | |
| 220 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) | |
| 221 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) | |
| 222 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) | |
| 223 | ||
| 224 | /* Device Status Register */ | |
| 225 | #define DWC3_DSTS_PWRUPREQ (1 << 24) | |
| 226 | #define DWC3_DSTS_COREIDLE (1 << 23) | |
| 227 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) | |
| 228 | ||
| 229 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
| 230 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
| 231 | ||
| 232 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) | |
| 233 | ||
| 234 | #define DWC3_DSTS_SOFFN_MASK (0x3ff << 3) | |
| 235 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) | |
| 236 | ||
| 237 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
| 238 | ||
| 239 | #define DWC3_DSTS_SUPERSPEED (4 << 0) | |
| 240 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
| 241 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) | |
| 242 | #define DWC3_DSTS_LOWSPEED (2 << 0) | |
| 243 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) | |
| 244 | ||
| 245 | /* Device Generic Command Register */ | |
| 246 | #define DWC3_DGCMD_SET_LMP 0x01 | |
| 247 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
| 248 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
| 249 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 | |
| 250 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
| 251 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
| 252 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
| 253 | ||
| 254 | /* Device Endpoint Command Register */ | |
| 255 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
| 256 | #define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT) | |
| 257 | #define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) | |
| 258 | #define DWC3_DEPCMD_STATUS_MASK (0x0f << 12) | |
| 259 | #define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12) | |
| 260 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) | |
| 261 | #define DWC3_DEPCMD_CMDACT (1 << 10) | |
| 262 | #define DWC3_DEPCMD_CMDIOC (1 << 8) | |
| 263 | ||
| 264 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
| 265 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
| 266 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
| 267 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
| 268 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
| 269 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
| 270 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) | |
| 271 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) | |
| 272 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
| 273 | ||
| 274 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ | |
| 275 | #define DWC3_DALEPENA_EP(n) (1 << n) | |
| 276 | ||
| 277 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
| 278 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
| 279 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
| 280 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
| 281 | ||
| 282 | /* Structures */ | |
| 283 | ||
| 284 | struct dwc3_trb_hw; | |
| 285 | ||
| 286 | /** | |
| 287 | * struct dwc3_event_buffer - Software event buffer representation | |
| 288 | * @list: a list of event buffers | |
| 289 | * @buf: _THE_ buffer | |
| 290 | * @length: size of this buffer | |
| 291 | * @dma: dma_addr_t | |
| 292 | * @dwc: pointer to DWC controller | |
| 293 | */ | |
| 294 | struct dwc3_event_buffer { | |
| 295 | void *buf; | |
| 296 | unsigned length; | |
| 297 | unsigned int lpos; | |
| 298 | ||
| 299 | dma_addr_t dma; | |
| 300 | ||
| 301 | struct dwc3 *dwc; | |
| 302 | }; | |
| 303 | ||
| 304 | #define DWC3_EP_FLAG_STALLED (1 << 0) | |
| 305 | #define DWC3_EP_FLAG_WEDGED (1 << 1) | |
| 306 | ||
| 307 | #define DWC3_EP_DIRECTION_TX true | |
| 308 | #define DWC3_EP_DIRECTION_RX false | |
| 309 | ||
| 310 | #define DWC3_TRB_NUM 32 | |
| 311 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) | |
| 312 | ||
| 313 | /** | |
| 314 | * struct dwc3_ep - device side endpoint representation | |
| 315 | * @endpoint: usb endpoint | |
| 316 | * @request_list: list of requests for this endpoint | |
| 317 | * @req_queued: list of requests on this ep which have TRBs setup | |
| 318 | * @trb_pool: array of transaction buffers | |
| 319 | * @trb_pool_dma: dma address of @trb_pool | |
| 320 | * @free_slot: next slot which is going to be used | |
| 321 | * @busy_slot: first slot which is owned by HW | |
| 322 | * @desc: usb_endpoint_descriptor pointer | |
| 323 | * @dwc: pointer to DWC controller | |
| 324 | * @flags: endpoint flags (wedged, stalled, ...) | |
| 325 | * @current_trb: index of current used trb | |
| 326 | * @number: endpoint number (1 - 15) | |
| 327 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
| 328 | * @res_trans_idx: Resource transfer index | |
| 329 | * @interval: the intervall on which the ISOC transfer is started | |
| 330 | * @name: a human readable name e.g. ep1out-bulk | |
| 331 | * @direction: true for TX, false for RX | |
| 332 | */ | |
| 333 | struct dwc3_ep { | |
| 334 | struct usb_ep endpoint; | |
| 335 | struct list_head request_list; | |
| 336 | struct list_head req_queued; | |
| 337 | ||
| 338 | struct dwc3_trb_hw *trb_pool; | |
| 339 | dma_addr_t trb_pool_dma; | |
| 340 | u32 free_slot; | |
| 341 | u32 busy_slot; | |
| 342 | const struct usb_endpoint_descriptor *desc; | |
| 343 | struct dwc3 *dwc; | |
| 344 | ||
| 345 | unsigned flags; | |
| 346 | #define DWC3_EP_ENABLED (1 << 0) | |
| 347 | #define DWC3_EP_STALL (1 << 1) | |
| 348 | #define DWC3_EP_WEDGE (1 << 2) | |
| 349 | #define DWC3_EP_BUSY (1 << 4) | |
| 350 | #define DWC3_EP_PENDING_REQUEST (1 << 5) | |
| 351 | #define DWC3_EP_WILL_SHUTDOWN (1 << 6) | |
| 352 | ||
| 353 | unsigned current_trb; | |
| 354 | ||
| 355 | u8 number; | |
| 356 | u8 type; | |
| 357 | u8 res_trans_idx; | |
| 358 | u32 interval; | |
| 359 | ||
| 360 | char name[20]; | |
| 361 | ||
| 362 | unsigned direction:1; | |
| 363 | }; | |
| 364 | ||
| 365 | enum dwc3_phy { | |
| 366 | DWC3_PHY_UNKNOWN = 0, | |
| 367 | DWC3_PHY_USB3, | |
| 368 | DWC3_PHY_USB2, | |
| 369 | }; | |
| 370 | ||
| 371 | enum dwc3_ep0_state { | |
| 372 | EP0_UNCONNECTED = 0, | |
| 373 | EP0_IDLE, | |
| 374 | EP0_IN_DATA_PHASE, | |
| 375 | EP0_OUT_DATA_PHASE, | |
| 376 | EP0_IN_WAIT_GADGET, | |
| 377 | EP0_OUT_WAIT_GADGET, | |
| 378 | EP0_IN_WAIT_NRDY, | |
| 379 | EP0_OUT_WAIT_NRDY, | |
| 380 | EP0_IN_STATUS_PHASE, | |
| 381 | EP0_OUT_STATUS_PHASE, | |
| 382 | EP0_STALL, | |
| 383 | }; | |
| 384 | ||
| 385 | enum dwc3_link_state { | |
| 386 | /* In SuperSpeed */ | |
| 387 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
| 388 | DWC3_LINK_STATE_U1 = 0x01, | |
| 389 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
| 390 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
| 391 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
| 392 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
| 393 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
| 394 | DWC3_LINK_STATE_POLL = 0x07, | |
| 395 | DWC3_LINK_STATE_RECOV = 0x08, | |
| 396 | DWC3_LINK_STATE_HRESET = 0x09, | |
| 397 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
| 398 | DWC3_LINK_STATE_LPBK = 0x0b, | |
| 399 | DWC3_LINK_STATE_MASK = 0x0f, | |
| 400 | }; | |
| 401 | ||
| 402 | enum dwc3_device_state { | |
| 403 | DWC3_DEFAULT_STATE, | |
| 404 | DWC3_ADDRESS_STATE, | |
| 405 | DWC3_CONFIGURED_STATE, | |
| 406 | }; | |
| 407 | ||
| 408 | /** | |
| 409 | * struct dwc3_trb - transfer request block | |
| 410 | * @bpl: lower 32bit of the buffer | |
| 411 | * @bph: higher 32bit of the buffer | |
| 412 | * @length: buffer size (up to 16mb - 1) | |
| 413 | * @pcm1: packet count m1 | |
| 414 | * @trbsts: trb status | |
| 415 | * 0 = ok | |
| 416 | * 1 = missed isoc | |
| 417 | * 2 = setup pending | |
| 418 | * @hwo: hardware owner of descriptor | |
| 419 | * @lst: last trb | |
| 420 | * @chn: chain buffers | |
| 421 | * @csp: continue on short packets (only supported on isoc eps) | |
| 422 | * @trbctl: trb control | |
| 423 | * 1 = normal | |
| 424 | * 2 = control-setup | |
| 425 | * 3 = control-status-2 | |
| 426 | * 4 = control-status-3 | |
| 427 | * 5 = control-data (first trb of data stage) | |
| 428 | * 6 = isochronous-first (first trb of service interval) | |
| 429 | * 7 = isochronous | |
| 430 | * 8 = link trb | |
| 431 | * others = reserved | |
| 432 | * @isp_imi: interrupt on short packet / interrupt on missed isoc | |
| 433 | * @ioc: interrupt on complete | |
| 434 | * @sid_sofn: Stream ID / SOF Number | |
| 435 | */ | |
| 436 | struct dwc3_trb { | |
| 437 | u64 bplh; | |
| 438 | ||
| 439 | union { | |
| 440 | struct { | |
| 441 | u32 length:24; | |
| 442 | u32 pcm1:2; | |
| 443 | u32 reserved27_26:2; | |
| 444 | u32 trbsts:4; | |
| 445 | #define DWC3_TRB_STS_OKAY 0 | |
| 446 | #define DWC3_TRB_STS_MISSED_ISOC 1 | |
| 447 | #define DWC3_TRB_STS_SETUP_PENDING 2 | |
| 448 | }; | |
| 449 | u32 len_pcm; | |
| 450 | }; | |
| 451 | ||
| 452 | union { | |
| 453 | struct { | |
| 454 | u32 hwo:1; | |
| 455 | u32 lst:1; | |
| 456 | u32 chn:1; | |
| 457 | u32 csp:1; | |
| 458 | u32 trbctl:6; | |
| 459 | u32 isp_imi:1; | |
| 460 | u32 ioc:1; | |
| 461 | u32 reserved13_12:2; | |
| 462 | u32 sid_sofn:16; | |
| 463 | u32 reserved31_30:2; | |
| 464 | }; | |
| 465 | u32 control; | |
| 466 | }; | |
| 467 | } __packed; | |
| 468 | ||
| 469 | /** | |
| 470 | * struct dwc3_trb_hw - transfer request block (hw format) | |
| 471 | * @bpl: DW0-3 | |
| 472 | * @bph: DW4-7 | |
| 473 | * @size: DW8-B | |
| 474 | * @trl: DWC-F | |
| 475 | */ | |
| 476 | struct dwc3_trb_hw { | |
| 477 | __le32 bpl; | |
| 478 | __le32 bph; | |
| 479 | __le32 size; | |
| 480 | __le32 ctrl; | |
| 481 | } __packed; | |
| 482 | ||
| 483 | static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw) | |
| 484 | { | |
| 485 | hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh)); | |
| 486 | hw->bph = cpu_to_le32(upper_32_bits(nat->bplh)); | |
| 487 | hw->size = cpu_to_le32p(&nat->len_pcm); | |
| 488 | /* HWO is written last */ | |
| 489 | hw->ctrl = cpu_to_le32p(&nat->control); | |
| 490 | } | |
| 491 | ||
| 492 | static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat) | |
| 493 | { | |
| 494 | u64 bplh; | |
| 495 | ||
| 496 | bplh = le32_to_cpup(&hw->bpl); | |
| 497 | bplh |= (u64) le32_to_cpup(&hw->bph) << 32; | |
| 498 | nat->bplh = bplh; | |
| 499 | ||
| 500 | nat->len_pcm = le32_to_cpup(&hw->size); | |
| 501 | nat->control = le32_to_cpup(&hw->ctrl); | |
| 502 | } | |
| 503 | ||
| 504 | /** | |
| 505 | * struct dwc3 - representation of our controller | |
| 506 | * ctrl_req: usb control request which is used for ep0 | |
| 507 | * ep0_trb: trb which is used for the ctrl_req | |
| 508 | * setup_buf: used while precessing STD USB requests | |
| 509 | * ctrl_req_addr: dma address of ctrl_req | |
| 510 | * ep0_trb: dma address of ep0_trb | |
| 511 | * ep0_usb_req: dummy req used while handling STD USB requests | |
| 512 | * setup_buf_addr: dma address of setup_buf | |
| 513 | * @lock: for synchronizing | |
| 514 | * @dev: pointer to our struct device | |
| 515 | * @event_buffer_list: a list of event buffers | |
| 516 | * @gadget: device side representation of the peripheral controller | |
| 517 | * @gadget_driver: pointer to the gadget driver | |
| 518 | * @regs: base address for our registers | |
| 519 | * @regs_size: address space size | |
| 520 | * @irq: IRQ number | |
| 521 | * @revision: revision register contents | |
| 522 | * @is_selfpowered: true when we are selfpowered | |
| 523 | * @three_stage_setup: set if we perform a three phase setup | |
| 524 | * @ep0_status_pending: ep0 status response without a req is pending | |
| 525 | * @ep0state: state of endpoint zero | |
| 526 | * @link_state: link state | |
| 527 | * @speed: device speed (super, high, full, low) | |
| 528 | * @mem: points to start of memory which is used for this struct. | |
| 529 | * @root: debugfs root folder pointer | |
| 530 | */ | |
| 531 | struct dwc3 { | |
| 532 | struct usb_ctrlrequest *ctrl_req; | |
| 533 | struct dwc3_trb_hw *ep0_trb; | |
| 534 | u8 *setup_buf; | |
| 535 | dma_addr_t ctrl_req_addr; | |
| 536 | dma_addr_t ep0_trb_addr; | |
| 537 | dma_addr_t setup_buf_addr; | |
| 538 | struct usb_request ep0_usb_req; | |
| 539 | /* device lock */ | |
| 540 | spinlock_t lock; | |
| 541 | struct device *dev; | |
| 542 | ||
| 543 | struct dwc3_event_buffer *ev_buffs[DWC3_EVENT_BUFFERS_NUM]; | |
| 544 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; | |
| 545 | ||
| 546 | struct usb_gadget gadget; | |
| 547 | struct usb_gadget_driver *gadget_driver; | |
| 548 | ||
| 549 | void __iomem *regs; | |
| 550 | size_t regs_size; | |
| 551 | ||
| 552 | int irq; | |
| 553 | ||
| 554 | u32 revision; | |
| 555 | ||
| 556 | #define DWC3_REVISION_173A 0x5533173a | |
| 557 | #define DWC3_REVISION_175A 0x5533175a | |
| 558 | #define DWC3_REVISION_180A 0x5533180a | |
| 559 | #define DWC3_REVISION_183A 0x5533183a | |
| 560 | #define DWC3_REVISION_185A 0x5533185a | |
| 561 | #define DWC3_REVISION_188A 0x5533188a | |
| 562 | #define DWC3_REVISION_190A 0x5533190a | |
| 563 | ||
| 564 | unsigned is_selfpowered:1; | |
| 565 | unsigned three_stage_setup:1; | |
| 566 | unsigned ep0_status_pending:1; | |
| 567 | ||
| 568 | enum dwc3_ep0_state ep0state; | |
| 569 | enum dwc3_link_state link_state; | |
| 570 | enum dwc3_device_state dev_state; | |
| 571 | ||
| 572 | u8 speed; | |
| 573 | void *mem; | |
| 574 | ||
| 575 | struct dentry *root; | |
| 576 | }; | |
| 577 | ||
| 578 | /* -------------------------------------------------------------------------- */ | |
| 579 | ||
| 580 | #define DWC3_TRBSTS_OK 0 | |
| 581 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
| 582 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
| 583 | ||
| 584 | #define DWC3_TRBCTL_NORMAL 1 | |
| 585 | #define DWC3_TRBCTL_CONTROL_SETUP 2 | |
| 586 | #define DWC3_TRBCTL_CONTROL_STATUS2 3 | |
| 587 | #define DWC3_TRBCTL_CONTROL_STATUS3 4 | |
| 588 | #define DWC3_TRBCTL_CONTROL_DATA 5 | |
| 589 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST 6 | |
| 590 | #define DWC3_TRBCTL_ISOCHRONOUS 7 | |
| 591 | #define DWC3_TRBCTL_LINK_TRB 8 | |
| 592 | ||
| 593 | /* -------------------------------------------------------------------------- */ | |
| 594 | ||
| 595 | struct dwc3_event_type { | |
| 596 | u32 is_devspec:1; | |
| 597 | u32 type:6; | |
| 598 | u32 reserved8_31:25; | |
| 599 | } __packed; | |
| 600 | ||
| 601 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
| 602 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
| 603 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
| 604 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
| 605 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
| 606 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
| 607 | ||
| 608 | /** | |
| 609 | * struct dwc3_event_depvt - Device Endpoint Events | |
| 610 | * @one_bit: indicates this is an endpoint event (not used) | |
| 611 | * @endpoint_number: number of the endpoint | |
| 612 | * @endpoint_event: The event we have: | |
| 613 | * 0x00 - Reserved | |
| 614 | * 0x01 - XferComplete | |
| 615 | * 0x02 - XferInProgress | |
| 616 | * 0x03 - XferNotReady | |
| 617 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
| 618 | * 0x05 - Reserved | |
| 619 | * 0x06 - StreamEvt | |
| 620 | * 0x07 - EPCmdCmplt | |
| 621 | * @reserved11_10: Reserved, don't use. | |
| 622 | * @status: Indicates the status of the event. Refer to databook for | |
| 623 | * more information. | |
| 624 | * @parameters: Parameters of the current event. Refer to databook for | |
| 625 | * more information. | |
| 626 | */ | |
| 627 | struct dwc3_event_depevt { | |
| 628 | u32 one_bit:1; | |
| 629 | u32 endpoint_number:5; | |
| 630 | u32 endpoint_event:4; | |
| 631 | u32 reserved11_10:2; | |
| 632 | u32 status:4; | |
| 633 | #define DEPEVT_STATUS_BUSERR (1 << 0) | |
| 634 | #define DEPEVT_STATUS_SHORT (1 << 1) | |
| 635 | #define DEPEVT_STATUS_IOC (1 << 2) | |
| 636 | #define DEPEVT_STATUS_LST (1 << 3) | |
| 637 | u32 parameters:16; | |
| 638 | } __packed; | |
| 639 | ||
| 640 | /** | |
| 641 | * struct dwc3_event_devt - Device Events | |
| 642 | * @one_bit: indicates this is a non-endpoint event (not used) | |
| 643 | * @device_event: indicates it's a device event. Should read as 0x00 | |
| 644 | * @type: indicates the type of device event. | |
| 645 | * 0 - DisconnEvt | |
| 646 | * 1 - USBRst | |
| 647 | * 2 - ConnectDone | |
| 648 | * 3 - ULStChng | |
| 649 | * 4 - WkUpEvt | |
| 650 | * 5 - Reserved | |
| 651 | * 6 - EOPF | |
| 652 | * 7 - SOF | |
| 653 | * 8 - Reserved | |
| 654 | * 9 - ErrticErr | |
| 655 | * 10 - CmdCmplt | |
| 656 | * 11 - EvntOverflow | |
| 657 | * 12 - VndrDevTstRcved | |
| 658 | * @reserved15_12: Reserved, not used | |
| 659 | * @event_info: Information about this event | |
| 660 | * @reserved31_24: Reserved, not used | |
| 661 | */ | |
| 662 | struct dwc3_event_devt { | |
| 663 | u32 one_bit:1; | |
| 664 | u32 device_event:7; | |
| 665 | u32 type:4; | |
| 666 | u32 reserved15_12:4; | |
| 667 | u32 event_info:8; | |
| 668 | u32 reserved31_24:8; | |
| 669 | } __packed; | |
| 670 | ||
| 671 | /** | |
| 672 | * struct dwc3_event_gevt - Other Core Events | |
| 673 | * @one_bit: indicates this is a non-endpoint event (not used) | |
| 674 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
| 675 | * @phy_port_number: self-explanatory | |
| 676 | * @reserved31_12: Reserved, not used. | |
| 677 | */ | |
| 678 | struct dwc3_event_gevt { | |
| 679 | u32 one_bit:1; | |
| 680 | u32 device_event:7; | |
| 681 | u32 phy_port_number:4; | |
| 682 | u32 reserved31_12:20; | |
| 683 | } __packed; | |
| 684 | ||
| 685 | /** | |
| 686 | * union dwc3_event - representation of Event Buffer contents | |
| 687 | * @raw: raw 32-bit event | |
| 688 | * @type: the type of the event | |
| 689 | * @depevt: Device Endpoint Event | |
| 690 | * @devt: Device Event | |
| 691 | * @gevt: Global Event | |
| 692 | */ | |
| 693 | union dwc3_event { | |
| 694 | u32 raw; | |
| 695 | struct dwc3_event_type type; | |
| 696 | struct dwc3_event_depevt depevt; | |
| 697 | struct dwc3_event_devt devt; | |
| 698 | struct dwc3_event_gevt gevt; | |
| 699 | }; | |
| 700 | ||
| 701 | /* | |
| 702 | * DWC3 Features to be used as Driver Data | |
| 703 | */ | |
| 704 | ||
| 705 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
| 706 | #define DWC3_HAS_XHCI BIT(1) | |
| 707 | #define DWC3_HAS_OTG BIT(3) | |
| 708 | ||
| 709 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |