Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * core.h - DesignWare USB3 DRD Core Header | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
40 | #define __DRIVERS_USB_DWC3_CORE_H | |
41 | ||
42 | #include <linux/device.h> | |
43 | #include <linux/spinlock.h> | |
d07e8819 | 44 | #include <linux/ioport.h> |
72246da4 FB |
45 | #include <linux/list.h> |
46 | #include <linux/dma-mapping.h> | |
47 | #include <linux/mm.h> | |
48 | #include <linux/debugfs.h> | |
49 | ||
50 | #include <linux/usb/ch9.h> | |
51 | #include <linux/usb/gadget.h> | |
52 | ||
53 | /* Global constants */ | |
54 | #define DWC3_ENDPOINTS_NUM 32 | |
55 | ||
72246da4 FB |
56 | #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE |
57 | #define DWC3_EVENT_TYPE_MASK 0xfe | |
58 | ||
59 | #define DWC3_EVENT_TYPE_DEV 0 | |
60 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
61 | #define DWC3_EVENT_TYPE_I2C 4 | |
62 | ||
63 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
64 | #define DWC3_DEVICE_EVENT_RESET 1 | |
65 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
66 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
67 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
68 | #define DWC3_DEVICE_EVENT_EOPF 6 | |
69 | #define DWC3_DEVICE_EVENT_SOF 7 | |
70 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
71 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
72 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
73 | ||
74 | #define DWC3_GEVNTCOUNT_MASK 0xfffc | |
75 | #define DWC3_GSNPSID_MASK 0xffff0000 | |
76 | #define DWC3_GSNPSREV_MASK 0xffff | |
77 | ||
78 | /* Global Registers */ | |
79 | #define DWC3_GSBUSCFG0 0xc100 | |
80 | #define DWC3_GSBUSCFG1 0xc104 | |
81 | #define DWC3_GTXTHRCFG 0xc108 | |
82 | #define DWC3_GRXTHRCFG 0xc10c | |
83 | #define DWC3_GCTL 0xc110 | |
84 | #define DWC3_GEVTEN 0xc114 | |
85 | #define DWC3_GSTS 0xc118 | |
86 | #define DWC3_GSNPSID 0xc120 | |
87 | #define DWC3_GGPIO 0xc124 | |
88 | #define DWC3_GUID 0xc128 | |
89 | #define DWC3_GUCTL 0xc12c | |
90 | #define DWC3_GBUSERRADDR0 0xc130 | |
91 | #define DWC3_GBUSERRADDR1 0xc134 | |
92 | #define DWC3_GPRTBIMAP0 0xc138 | |
93 | #define DWC3_GPRTBIMAP1 0xc13c | |
94 | #define DWC3_GHWPARAMS0 0xc140 | |
95 | #define DWC3_GHWPARAMS1 0xc144 | |
96 | #define DWC3_GHWPARAMS2 0xc148 | |
97 | #define DWC3_GHWPARAMS3 0xc14c | |
98 | #define DWC3_GHWPARAMS4 0xc150 | |
99 | #define DWC3_GHWPARAMS5 0xc154 | |
100 | #define DWC3_GHWPARAMS6 0xc158 | |
101 | #define DWC3_GHWPARAMS7 0xc15c | |
102 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
103 | #define DWC3_GDBGLTSSM 0xc164 | |
104 | #define DWC3_GPRTBIMAP_HS0 0xc180 | |
105 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
106 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
107 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
108 | ||
109 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) | |
110 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) | |
111 | ||
112 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) | |
113 | ||
114 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) | |
115 | ||
116 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) | |
117 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) | |
118 | ||
119 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) | |
120 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) | |
121 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) | |
122 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) | |
123 | ||
124 | #define DWC3_GHWPARAMS8 0xc600 | |
125 | ||
126 | /* Device Registers */ | |
127 | #define DWC3_DCFG 0xc700 | |
128 | #define DWC3_DCTL 0xc704 | |
129 | #define DWC3_DEVTEN 0xc708 | |
130 | #define DWC3_DSTS 0xc70c | |
131 | #define DWC3_DGCMDPAR 0xc710 | |
132 | #define DWC3_DGCMD 0xc714 | |
133 | #define DWC3_DALEPENA 0xc720 | |
134 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) | |
135 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) | |
136 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) | |
137 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) | |
138 | ||
139 | /* OTG Registers */ | |
140 | #define DWC3_OCFG 0xcc00 | |
141 | #define DWC3_OCTL 0xcc04 | |
142 | #define DWC3_OEVTEN 0xcc08 | |
143 | #define DWC3_OSTS 0xcc0C | |
144 | ||
145 | /* Bit fields */ | |
146 | ||
147 | /* Global Configuration Register */ | |
148 | #define DWC3_GCTL_PWRDNSCALE(n) (n << 19) | |
f4aadbe4 | 149 | #define DWC3_GCTL_U2RSTECN (1 << 16) |
72246da4 FB |
150 | #define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6) |
151 | #define DWC3_GCTL_CLK_BUS (0) | |
152 | #define DWC3_GCTL_CLK_PIPE (1) | |
153 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
154 | #define DWC3_GCTL_CLK_MASK (3) | |
155 | ||
0b9fe32d | 156 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
72246da4 FB |
157 | #define DWC3_GCTL_PRTCAPDIR(n) (n << 12) |
158 | #define DWC3_GCTL_PRTCAP_HOST 1 | |
159 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
160 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
161 | ||
162 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) | |
f78d32e7 | 163 | #define DWC3_GCTL_SCALEDOWN(n) (n << 4) |
72246da4 | 164 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) |
aabb7075 | 165 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) |
72246da4 FB |
166 | |
167 | /* Global USB2 PHY Configuration Register */ | |
168 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) | |
169 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) | |
170 | ||
171 | /* Global USB3 PIPE Control Register */ | |
172 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) | |
173 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) | |
174 | ||
457e84b6 FB |
175 | /* Global TX Fifo Size Register */ |
176 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) | |
177 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) | |
178 | ||
aabb7075 FB |
179 | /* Global HWPARAMS1 Register */ |
180 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) ((n & (3 << 24)) >> 24) | |
181 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 | |
182 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
183 | ||
72246da4 FB |
184 | /* Device Configuration Register */ |
185 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
186 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
187 | ||
188 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
189 | #define DWC3_DCFG_SUPERSPEED (4 << 0) | |
190 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
191 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) | |
192 | #define DWC3_DCFG_LOWSPEED (2 << 0) | |
193 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) | |
194 | ||
195 | /* Device Control Register */ | |
196 | #define DWC3_DCTL_RUN_STOP (1 << 31) | |
197 | #define DWC3_DCTL_CSFTRST (1 << 30) | |
198 | #define DWC3_DCTL_LSFTRST (1 << 29) | |
199 | ||
200 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
201 | #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24) | |
202 | ||
203 | #define DWC3_DCTL_APPL1RES (1 << 23) | |
204 | ||
8db7ed15 FB |
205 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) |
206 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
207 | ||
208 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
209 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
210 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
211 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
212 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
213 | ||
72246da4 FB |
214 | #define DWC3_DCTL_INITU2ENA (1 << 12) |
215 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | |
216 | #define DWC3_DCTL_INITU1ENA (1 << 10) | |
217 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | |
218 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | |
219 | ||
220 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
221 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
222 | ||
223 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
224 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
225 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
226 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
227 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
228 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
229 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
230 | ||
231 | /* Device Event Enable Register */ | |
232 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) | |
233 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) | |
234 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) | |
235 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) | |
236 | #define DWC3_DEVTEN_SOFEN (1 << 7) | |
237 | #define DWC3_DEVTEN_EOPFEN (1 << 6) | |
238 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) | |
239 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) | |
240 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) | |
241 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) | |
242 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) | |
243 | ||
244 | /* Device Status Register */ | |
245 | #define DWC3_DSTS_PWRUPREQ (1 << 24) | |
246 | #define DWC3_DSTS_COREIDLE (1 << 23) | |
247 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) | |
248 | ||
249 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
250 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
251 | ||
252 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) | |
253 | ||
254 | #define DWC3_DSTS_SOFFN_MASK (0x3ff << 3) | |
255 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) | |
256 | ||
257 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
258 | ||
259 | #define DWC3_DSTS_SUPERSPEED (4 << 0) | |
260 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
261 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) | |
262 | #define DWC3_DSTS_LOWSPEED (2 << 0) | |
263 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) | |
264 | ||
265 | /* Device Generic Command Register */ | |
266 | #define DWC3_DGCMD_SET_LMP 0x01 | |
267 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
268 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
269 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 | |
270 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
271 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
272 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
273 | ||
274 | /* Device Endpoint Command Register */ | |
275 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
276 | #define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT) | |
277 | #define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) | |
278 | #define DWC3_DEPCMD_STATUS_MASK (0x0f << 12) | |
279 | #define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12) | |
280 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) | |
281 | #define DWC3_DEPCMD_CMDACT (1 << 10) | |
282 | #define DWC3_DEPCMD_CMDIOC (1 << 8) | |
283 | ||
284 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
285 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
286 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
287 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
288 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
289 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
290 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) | |
291 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) | |
292 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
293 | ||
294 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ | |
295 | #define DWC3_DALEPENA_EP(n) (1 << n) | |
296 | ||
297 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
298 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
299 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
300 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
301 | ||
302 | /* Structures */ | |
303 | ||
f6bafc6a | 304 | struct dwc3_trb; |
72246da4 FB |
305 | |
306 | /** | |
307 | * struct dwc3_event_buffer - Software event buffer representation | |
308 | * @list: a list of event buffers | |
309 | * @buf: _THE_ buffer | |
310 | * @length: size of this buffer | |
311 | * @dma: dma_addr_t | |
312 | * @dwc: pointer to DWC controller | |
313 | */ | |
314 | struct dwc3_event_buffer { | |
315 | void *buf; | |
316 | unsigned length; | |
317 | unsigned int lpos; | |
318 | ||
319 | dma_addr_t dma; | |
320 | ||
321 | struct dwc3 *dwc; | |
322 | }; | |
323 | ||
324 | #define DWC3_EP_FLAG_STALLED (1 << 0) | |
325 | #define DWC3_EP_FLAG_WEDGED (1 << 1) | |
326 | ||
327 | #define DWC3_EP_DIRECTION_TX true | |
328 | #define DWC3_EP_DIRECTION_RX false | |
329 | ||
330 | #define DWC3_TRB_NUM 32 | |
331 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) | |
332 | ||
333 | /** | |
334 | * struct dwc3_ep - device side endpoint representation | |
335 | * @endpoint: usb endpoint | |
336 | * @request_list: list of requests for this endpoint | |
337 | * @req_queued: list of requests on this ep which have TRBs setup | |
338 | * @trb_pool: array of transaction buffers | |
339 | * @trb_pool_dma: dma address of @trb_pool | |
340 | * @free_slot: next slot which is going to be used | |
341 | * @busy_slot: first slot which is owned by HW | |
342 | * @desc: usb_endpoint_descriptor pointer | |
343 | * @dwc: pointer to DWC controller | |
344 | * @flags: endpoint flags (wedged, stalled, ...) | |
345 | * @current_trb: index of current used trb | |
346 | * @number: endpoint number (1 - 15) | |
347 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
348 | * @res_trans_idx: Resource transfer index | |
349 | * @interval: the intervall on which the ISOC transfer is started | |
350 | * @name: a human readable name e.g. ep1out-bulk | |
351 | * @direction: true for TX, false for RX | |
879631aa | 352 | * @stream_capable: true when streams are enabled |
72246da4 FB |
353 | */ |
354 | struct dwc3_ep { | |
355 | struct usb_ep endpoint; | |
356 | struct list_head request_list; | |
357 | struct list_head req_queued; | |
358 | ||
f6bafc6a | 359 | struct dwc3_trb *trb_pool; |
72246da4 FB |
360 | dma_addr_t trb_pool_dma; |
361 | u32 free_slot; | |
362 | u32 busy_slot; | |
363 | const struct usb_endpoint_descriptor *desc; | |
c90bfaec | 364 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
72246da4 FB |
365 | struct dwc3 *dwc; |
366 | ||
367 | unsigned flags; | |
368 | #define DWC3_EP_ENABLED (1 << 0) | |
369 | #define DWC3_EP_STALL (1 << 1) | |
370 | #define DWC3_EP_WEDGE (1 << 2) | |
371 | #define DWC3_EP_BUSY (1 << 4) | |
372 | #define DWC3_EP_PENDING_REQUEST (1 << 5) | |
72246da4 | 373 | |
984f66a6 FB |
374 | /* This last one is specific to EP0 */ |
375 | #define DWC3_EP0_DIR_IN (1 << 31) | |
376 | ||
72246da4 FB |
377 | unsigned current_trb; |
378 | ||
379 | u8 number; | |
380 | u8 type; | |
381 | u8 res_trans_idx; | |
382 | u32 interval; | |
383 | ||
384 | char name[20]; | |
385 | ||
386 | unsigned direction:1; | |
879631aa | 387 | unsigned stream_capable:1; |
72246da4 FB |
388 | }; |
389 | ||
390 | enum dwc3_phy { | |
391 | DWC3_PHY_UNKNOWN = 0, | |
392 | DWC3_PHY_USB3, | |
393 | DWC3_PHY_USB2, | |
394 | }; | |
395 | ||
b53c772d FB |
396 | enum dwc3_ep0_next { |
397 | DWC3_EP0_UNKNOWN = 0, | |
398 | DWC3_EP0_COMPLETE, | |
399 | DWC3_EP0_NRDY_SETUP, | |
400 | DWC3_EP0_NRDY_DATA, | |
401 | DWC3_EP0_NRDY_STATUS, | |
402 | }; | |
403 | ||
72246da4 FB |
404 | enum dwc3_ep0_state { |
405 | EP0_UNCONNECTED = 0, | |
c7fcdeb2 FB |
406 | EP0_SETUP_PHASE, |
407 | EP0_DATA_PHASE, | |
408 | EP0_STATUS_PHASE, | |
72246da4 FB |
409 | }; |
410 | ||
411 | enum dwc3_link_state { | |
412 | /* In SuperSpeed */ | |
413 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
414 | DWC3_LINK_STATE_U1 = 0x01, | |
415 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
416 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
417 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
418 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
419 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
420 | DWC3_LINK_STATE_POLL = 0x07, | |
421 | DWC3_LINK_STATE_RECOV = 0x08, | |
422 | DWC3_LINK_STATE_HRESET = 0x09, | |
423 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
424 | DWC3_LINK_STATE_LPBK = 0x0b, | |
425 | DWC3_LINK_STATE_MASK = 0x0f, | |
426 | }; | |
427 | ||
428 | enum dwc3_device_state { | |
429 | DWC3_DEFAULT_STATE, | |
430 | DWC3_ADDRESS_STATE, | |
431 | DWC3_CONFIGURED_STATE, | |
432 | }; | |
433 | ||
f6bafc6a FB |
434 | /* TRB Length, PCM and Status */ |
435 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
436 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
437 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
438 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28) >> 28)) | |
439 | ||
440 | #define DWC3_TRBSTS_OK 0 | |
441 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
442 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
443 | ||
444 | /* TRB Control */ | |
445 | #define DWC3_TRB_CTRL_HWO (1 << 0) | |
446 | #define DWC3_TRB_CTRL_LST (1 << 1) | |
447 | #define DWC3_TRB_CTRL_CHN (1 << 2) | |
448 | #define DWC3_TRB_CTRL_CSP (1 << 3) | |
449 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) | |
450 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) | |
451 | #define DWC3_TRB_CTRL_IOC (1 << 11) | |
452 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) | |
453 | ||
454 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) | |
455 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
456 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
457 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
458 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
459 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
460 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
461 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
72246da4 FB |
462 | |
463 | /** | |
f6bafc6a | 464 | * struct dwc3_trb - transfer request block (hw format) |
72246da4 FB |
465 | * @bpl: DW0-3 |
466 | * @bph: DW4-7 | |
467 | * @size: DW8-B | |
468 | * @trl: DWC-F | |
469 | */ | |
f6bafc6a FB |
470 | struct dwc3_trb { |
471 | u32 bpl; | |
472 | u32 bph; | |
473 | u32 size; | |
474 | u32 ctrl; | |
72246da4 FB |
475 | } __packed; |
476 | ||
a3299499 FB |
477 | /** |
478 | * dwc3_hwparams - copy of HWPARAMS registers | |
479 | * @hwparams0 - GHWPARAMS0 | |
480 | * @hwparams1 - GHWPARAMS1 | |
481 | * @hwparams2 - GHWPARAMS2 | |
482 | * @hwparams3 - GHWPARAMS3 | |
483 | * @hwparams4 - GHWPARAMS4 | |
484 | * @hwparams5 - GHWPARAMS5 | |
485 | * @hwparams6 - GHWPARAMS6 | |
486 | * @hwparams7 - GHWPARAMS7 | |
487 | * @hwparams8 - GHWPARAMS8 | |
488 | */ | |
489 | struct dwc3_hwparams { | |
490 | u32 hwparams0; | |
491 | u32 hwparams1; | |
492 | u32 hwparams2; | |
493 | u32 hwparams3; | |
494 | u32 hwparams4; | |
495 | u32 hwparams5; | |
496 | u32 hwparams6; | |
497 | u32 hwparams7; | |
498 | u32 hwparams8; | |
499 | }; | |
500 | ||
0949e99b FB |
501 | /* HWPARAMS0 */ |
502 | #define DWC3_MODE(n) ((n) & 0x7) | |
503 | ||
504 | #define DWC3_MODE_DEVICE 0 | |
505 | #define DWC3_MODE_HOST 1 | |
506 | #define DWC3_MODE_DRD 2 | |
507 | #define DWC3_MODE_HUB 3 | |
508 | ||
457e84b6 FB |
509 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
510 | ||
0949e99b | 511 | /* HWPARAMS1 */ |
457e84b6 FB |
512 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
513 | ||
514 | /* HWPARAMS7 */ | |
515 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
9f622b2a | 516 | |
e0ce0b0a SAS |
517 | struct dwc3_request { |
518 | struct usb_request request; | |
519 | struct list_head list; | |
520 | struct dwc3_ep *dep; | |
521 | ||
522 | u8 epnum; | |
f6bafc6a | 523 | struct dwc3_trb *trb; |
e0ce0b0a SAS |
524 | dma_addr_t trb_dma; |
525 | ||
526 | unsigned direction:1; | |
527 | unsigned mapped:1; | |
528 | unsigned queued:1; | |
529 | }; | |
530 | ||
72246da4 FB |
531 | /** |
532 | * struct dwc3 - representation of our controller | |
91db07dc FB |
533 | * @ctrl_req: usb control request which is used for ep0 |
534 | * @ep0_trb: trb which is used for the ctrl_req | |
5812b1c2 | 535 | * @ep0_bounce: bounce buffer for ep0 |
91db07dc FB |
536 | * @setup_buf: used while precessing STD USB requests |
537 | * @ctrl_req_addr: dma address of ctrl_req | |
538 | * @ep0_trb: dma address of ep0_trb | |
539 | * @ep0_usb_req: dummy req used while handling STD USB requests | |
540 | * @setup_buf_addr: dma address of setup_buf | |
5812b1c2 | 541 | * @ep0_bounce_addr: dma address of ep0_bounce |
72246da4 FB |
542 | * @lock: for synchronizing |
543 | * @dev: pointer to our struct device | |
d07e8819 | 544 | * @xhci: pointer to our xHCI child |
72246da4 FB |
545 | * @event_buffer_list: a list of event buffers |
546 | * @gadget: device side representation of the peripheral controller | |
547 | * @gadget_driver: pointer to the gadget driver | |
548 | * @regs: base address for our registers | |
549 | * @regs_size: address space size | |
550 | * @irq: IRQ number | |
9f622b2a | 551 | * @num_event_buffers: calculated number of event buffers |
fae2b904 | 552 | * @u1u2: only used on revisions <1.83a for workaround |
6c167fc9 | 553 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
72246da4 | 554 | * @revision: revision register contents |
0949e99b | 555 | * @mode: mode of operation |
72246da4 FB |
556 | * @is_selfpowered: true when we are selfpowered |
557 | * @three_stage_setup: set if we perform a three phase setup | |
5812b1c2 | 558 | * @ep0_bounced: true when we used bounce buffer |
55f3fba6 | 559 | * @ep0_expect_in: true when we expect a DATA IN transfer |
b23c8439 | 560 | * @start_config_issued: true when StartConfig command has been issued |
df62df56 | 561 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
457e84b6 FB |
562 | * @needs_fifo_resize: not all users might want fifo resizing, flag it |
563 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. | |
b53c772d | 564 | * @ep0_next_event: hold the next expected event |
72246da4 FB |
565 | * @ep0state: state of endpoint zero |
566 | * @link_state: link state | |
567 | * @speed: device speed (super, high, full, low) | |
568 | * @mem: points to start of memory which is used for this struct. | |
a3299499 | 569 | * @hwparams: copy of hwparams registers |
72246da4 FB |
570 | * @root: debugfs root folder pointer |
571 | */ | |
572 | struct dwc3 { | |
573 | struct usb_ctrlrequest *ctrl_req; | |
f6bafc6a | 574 | struct dwc3_trb *ep0_trb; |
5812b1c2 | 575 | void *ep0_bounce; |
72246da4 FB |
576 | u8 *setup_buf; |
577 | dma_addr_t ctrl_req_addr; | |
578 | dma_addr_t ep0_trb_addr; | |
579 | dma_addr_t setup_buf_addr; | |
5812b1c2 | 580 | dma_addr_t ep0_bounce_addr; |
e0ce0b0a | 581 | struct dwc3_request ep0_usb_req; |
72246da4 FB |
582 | /* device lock */ |
583 | spinlock_t lock; | |
584 | struct device *dev; | |
585 | ||
d07e8819 FB |
586 | struct platform_device *xhci; |
587 | struct resource *res; | |
588 | ||
457d3f21 | 589 | struct dwc3_event_buffer **ev_buffs; |
72246da4 FB |
590 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
591 | ||
592 | struct usb_gadget gadget; | |
593 | struct usb_gadget_driver *gadget_driver; | |
594 | ||
595 | void __iomem *regs; | |
596 | size_t regs_size; | |
597 | ||
598 | int irq; | |
599 | ||
9f622b2a | 600 | u32 num_event_buffers; |
fae2b904 | 601 | u32 u1u2; |
6c167fc9 | 602 | u32 maximum_speed; |
72246da4 | 603 | u32 revision; |
0949e99b | 604 | u32 mode; |
72246da4 FB |
605 | |
606 | #define DWC3_REVISION_173A 0x5533173a | |
607 | #define DWC3_REVISION_175A 0x5533175a | |
608 | #define DWC3_REVISION_180A 0x5533180a | |
609 | #define DWC3_REVISION_183A 0x5533183a | |
610 | #define DWC3_REVISION_185A 0x5533185a | |
611 | #define DWC3_REVISION_188A 0x5533188a | |
612 | #define DWC3_REVISION_190A 0x5533190a | |
613 | ||
614 | unsigned is_selfpowered:1; | |
615 | unsigned three_stage_setup:1; | |
5812b1c2 | 616 | unsigned ep0_bounced:1; |
55f3fba6 | 617 | unsigned ep0_expect_in:1; |
b23c8439 | 618 | unsigned start_config_issued:1; |
df62df56 | 619 | unsigned setup_packet_pending:1; |
5bdb1dcc | 620 | unsigned delayed_status:1; |
457e84b6 FB |
621 | unsigned needs_fifo_resize:1; |
622 | unsigned resize_fifos:1; | |
72246da4 | 623 | |
b53c772d | 624 | enum dwc3_ep0_next ep0_next_event; |
72246da4 FB |
625 | enum dwc3_ep0_state ep0state; |
626 | enum dwc3_link_state link_state; | |
627 | enum dwc3_device_state dev_state; | |
628 | ||
629 | u8 speed; | |
630 | void *mem; | |
631 | ||
a3299499 | 632 | struct dwc3_hwparams hwparams; |
72246da4 | 633 | struct dentry *root; |
3b637367 GC |
634 | |
635 | u8 test_mode; | |
636 | u8 test_mode_nr; | |
72246da4 FB |
637 | }; |
638 | ||
639 | /* -------------------------------------------------------------------------- */ | |
640 | ||
72246da4 FB |
641 | /* -------------------------------------------------------------------------- */ |
642 | ||
643 | struct dwc3_event_type { | |
644 | u32 is_devspec:1; | |
645 | u32 type:6; | |
646 | u32 reserved8_31:25; | |
647 | } __packed; | |
648 | ||
649 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
650 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
651 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
652 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
653 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
654 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
655 | ||
656 | /** | |
657 | * struct dwc3_event_depvt - Device Endpoint Events | |
658 | * @one_bit: indicates this is an endpoint event (not used) | |
659 | * @endpoint_number: number of the endpoint | |
660 | * @endpoint_event: The event we have: | |
661 | * 0x00 - Reserved | |
662 | * 0x01 - XferComplete | |
663 | * 0x02 - XferInProgress | |
664 | * 0x03 - XferNotReady | |
665 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
666 | * 0x05 - Reserved | |
667 | * 0x06 - StreamEvt | |
668 | * 0x07 - EPCmdCmplt | |
669 | * @reserved11_10: Reserved, don't use. | |
670 | * @status: Indicates the status of the event. Refer to databook for | |
671 | * more information. | |
672 | * @parameters: Parameters of the current event. Refer to databook for | |
673 | * more information. | |
674 | */ | |
675 | struct dwc3_event_depevt { | |
676 | u32 one_bit:1; | |
677 | u32 endpoint_number:5; | |
678 | u32 endpoint_event:4; | |
679 | u32 reserved11_10:2; | |
680 | u32 status:4; | |
40aa41fb FB |
681 | |
682 | /* Within XferNotReady */ | |
683 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) | |
684 | ||
685 | /* Within XferComplete */ | |
72246da4 FB |
686 | #define DEPEVT_STATUS_BUSERR (1 << 0) |
687 | #define DEPEVT_STATUS_SHORT (1 << 1) | |
688 | #define DEPEVT_STATUS_IOC (1 << 2) | |
689 | #define DEPEVT_STATUS_LST (1 << 3) | |
dc137f01 | 690 | |
879631aa FB |
691 | /* Stream event only */ |
692 | #define DEPEVT_STREAMEVT_FOUND 1 | |
693 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
694 | ||
dc137f01 FB |
695 | /* Control-only Status */ |
696 | #define DEPEVT_STATUS_CONTROL_SETUP 0 | |
697 | #define DEPEVT_STATUS_CONTROL_DATA 1 | |
698 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
699 | ||
72246da4 FB |
700 | u32 parameters:16; |
701 | } __packed; | |
702 | ||
703 | /** | |
704 | * struct dwc3_event_devt - Device Events | |
705 | * @one_bit: indicates this is a non-endpoint event (not used) | |
706 | * @device_event: indicates it's a device event. Should read as 0x00 | |
707 | * @type: indicates the type of device event. | |
708 | * 0 - DisconnEvt | |
709 | * 1 - USBRst | |
710 | * 2 - ConnectDone | |
711 | * 3 - ULStChng | |
712 | * 4 - WkUpEvt | |
713 | * 5 - Reserved | |
714 | * 6 - EOPF | |
715 | * 7 - SOF | |
716 | * 8 - Reserved | |
717 | * 9 - ErrticErr | |
718 | * 10 - CmdCmplt | |
719 | * 11 - EvntOverflow | |
720 | * 12 - VndrDevTstRcved | |
721 | * @reserved15_12: Reserved, not used | |
722 | * @event_info: Information about this event | |
723 | * @reserved31_24: Reserved, not used | |
724 | */ | |
725 | struct dwc3_event_devt { | |
726 | u32 one_bit:1; | |
727 | u32 device_event:7; | |
728 | u32 type:4; | |
729 | u32 reserved15_12:4; | |
730 | u32 event_info:8; | |
731 | u32 reserved31_24:8; | |
732 | } __packed; | |
733 | ||
734 | /** | |
735 | * struct dwc3_event_gevt - Other Core Events | |
736 | * @one_bit: indicates this is a non-endpoint event (not used) | |
737 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
738 | * @phy_port_number: self-explanatory | |
739 | * @reserved31_12: Reserved, not used. | |
740 | */ | |
741 | struct dwc3_event_gevt { | |
742 | u32 one_bit:1; | |
743 | u32 device_event:7; | |
744 | u32 phy_port_number:4; | |
745 | u32 reserved31_12:20; | |
746 | } __packed; | |
747 | ||
748 | /** | |
749 | * union dwc3_event - representation of Event Buffer contents | |
750 | * @raw: raw 32-bit event | |
751 | * @type: the type of the event | |
752 | * @depevt: Device Endpoint Event | |
753 | * @devt: Device Event | |
754 | * @gevt: Global Event | |
755 | */ | |
756 | union dwc3_event { | |
757 | u32 raw; | |
758 | struct dwc3_event_type type; | |
759 | struct dwc3_event_depevt depevt; | |
760 | struct dwc3_event_devt devt; | |
761 | struct dwc3_event_gevt gevt; | |
762 | }; | |
763 | ||
764 | /* | |
765 | * DWC3 Features to be used as Driver Data | |
766 | */ | |
767 | ||
768 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
769 | #define DWC3_HAS_XHCI BIT(1) | |
770 | #define DWC3_HAS_OTG BIT(3) | |
771 | ||
d07e8819 | 772 | /* prototypes */ |
3140e8cb | 773 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
457e84b6 | 774 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); |
3140e8cb | 775 | |
d07e8819 FB |
776 | int dwc3_host_init(struct dwc3 *dwc); |
777 | void dwc3_host_exit(struct dwc3 *dwc); | |
778 | ||
f80b45e7 FB |
779 | int dwc3_gadget_init(struct dwc3 *dwc); |
780 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
781 | ||
8300dd23 FB |
782 | extern int dwc3_get_device_id(void); |
783 | extern void dwc3_put_device_id(int id); | |
784 | ||
72246da4 | 785 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |