Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
fa0ea13e | 22 | #include <linux/version.h> |
a72e658b | 23 | #include <linux/module.h> |
72246da4 FB |
24 | #include <linux/kernel.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
457e84b6 | 35 | #include <linux/of.h> |
404905a6 | 36 | #include <linux/acpi.h> |
6344475f | 37 | #include <linux/pinctrl/consumer.h> |
72246da4 FB |
38 | |
39 | #include <linux/usb/ch9.h> | |
40 | #include <linux/usb/gadget.h> | |
f7e846f0 | 41 | #include <linux/usb/of.h> |
a45c82b8 | 42 | #include <linux/usb/otg.h> |
72246da4 | 43 | |
6462cbd5 | 44 | #include "platform_data.h" |
72246da4 FB |
45 | #include "core.h" |
46 | #include "gadget.h" | |
47 | #include "io.h" | |
48 | ||
49 | #include "debug.h" | |
50 | ||
8300dd23 FB |
51 | /* -------------------------------------------------------------------------- */ |
52 | ||
3140e8cb SAS |
53 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
54 | { | |
55 | u32 reg; | |
56 | ||
57 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
58 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
59 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
60 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
61 | } | |
8300dd23 | 62 | |
72246da4 FB |
63 | /** |
64 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
65 | * @dwc: pointer to our context structure | |
66 | */ | |
57303488 | 67 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
68 | { |
69 | u32 reg; | |
f59dcab1 | 70 | int retries = 1000; |
57303488 | 71 | int ret; |
72246da4 | 72 | |
51e1e7bc FB |
73 | usb_phy_init(dwc->usb2_phy); |
74 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
75 | ret = phy_init(dwc->usb2_generic_phy); |
76 | if (ret < 0) | |
77 | return ret; | |
78 | ||
79 | ret = phy_init(dwc->usb3_generic_phy); | |
80 | if (ret < 0) { | |
81 | phy_exit(dwc->usb2_generic_phy); | |
82 | return ret; | |
83 | } | |
72246da4 | 84 | |
f59dcab1 FB |
85 | /* |
86 | * We're resetting only the device side because, if we're in host mode, | |
87 | * XHCI driver will reset the host block. If dwc3 was configured for | |
88 | * host-only mode, then we can return early. | |
89 | */ | |
90 | if (dwc->dr_mode == USB_DR_MODE_HOST) | |
91 | return 0; | |
72246da4 | 92 | |
f59dcab1 FB |
93 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
94 | reg |= DWC3_DCTL_CSFTRST; | |
95 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 96 | |
f59dcab1 FB |
97 | do { |
98 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
99 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
100 | return 0; | |
45627ac6 | 101 | |
f59dcab1 FB |
102 | udelay(1); |
103 | } while (--retries); | |
57303488 | 104 | |
f59dcab1 | 105 | return -ETIMEDOUT; |
72246da4 FB |
106 | } |
107 | ||
c5cc74e8 HK |
108 | /** |
109 | * dwc3_soft_reset - Issue soft reset | |
110 | * @dwc: Pointer to our controller context structure | |
111 | */ | |
112 | static int dwc3_soft_reset(struct dwc3 *dwc) | |
113 | { | |
114 | unsigned long timeout; | |
115 | u32 reg; | |
116 | ||
117 | timeout = jiffies + msecs_to_jiffies(500); | |
118 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
119 | do { | |
120 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
121 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
122 | break; | |
123 | ||
124 | if (time_after(jiffies, timeout)) { | |
125 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
126 | return -ETIMEDOUT; | |
127 | } | |
128 | ||
129 | cpu_relax(); | |
130 | } while (true); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
db2be4e9 NB |
135 | /* |
136 | * dwc3_frame_length_adjustment - Adjusts frame length if required | |
137 | * @dwc3: Pointer to our controller context structure | |
138 | * @fladj: Value of GFLADJ_30MHZ to adjust frame length | |
139 | */ | |
140 | static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj) | |
141 | { | |
142 | u32 reg; | |
143 | u32 dft; | |
144 | ||
145 | if (dwc->revision < DWC3_REVISION_250A) | |
146 | return; | |
147 | ||
148 | if (fladj == 0) | |
149 | return; | |
150 | ||
151 | reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); | |
152 | dft = reg & DWC3_GFLADJ_30MHZ_MASK; | |
153 | if (!dev_WARN_ONCE(dwc->dev, dft == fladj, | |
154 | "request value same as default, ignoring\n")) { | |
155 | reg &= ~DWC3_GFLADJ_30MHZ_MASK; | |
156 | reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj; | |
157 | dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); | |
158 | } | |
159 | } | |
160 | ||
72246da4 FB |
161 | /** |
162 | * dwc3_free_one_event_buffer - Frees one event buffer | |
163 | * @dwc: Pointer to our controller context structure | |
164 | * @evt: Pointer to event buffer to be freed | |
165 | */ | |
166 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
167 | struct dwc3_event_buffer *evt) | |
168 | { | |
169 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
170 | } |
171 | ||
172 | /** | |
1d046793 | 173 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
174 | * @dwc: Pointer to our controller context structure |
175 | * @length: size of the event buffer | |
176 | * | |
1d046793 | 177 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
178 | * otherwise ERR_PTR(errno). |
179 | */ | |
67d0b500 FB |
180 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
181 | unsigned length) | |
72246da4 FB |
182 | { |
183 | struct dwc3_event_buffer *evt; | |
184 | ||
380f0d28 | 185 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
186 | if (!evt) |
187 | return ERR_PTR(-ENOMEM); | |
188 | ||
189 | evt->dwc = dwc; | |
190 | evt->length = length; | |
191 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
192 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 193 | if (!evt->buf) |
72246da4 | 194 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
195 | |
196 | return evt; | |
197 | } | |
198 | ||
199 | /** | |
200 | * dwc3_free_event_buffers - frees all allocated event buffers | |
201 | * @dwc: Pointer to our controller context structure | |
202 | */ | |
203 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
204 | { | |
205 | struct dwc3_event_buffer *evt; | |
72246da4 | 206 | |
696c8b12 | 207 | evt = dwc->ev_buf; |
660e9bde FB |
208 | if (evt) |
209 | dwc3_free_one_event_buffer(dwc, evt); | |
72246da4 FB |
210 | } |
211 | ||
212 | /** | |
213 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 214 | * @dwc: pointer to our controller context structure |
72246da4 FB |
215 | * @length: size of event buffer |
216 | * | |
1d046793 | 217 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
218 | * may contain some buffers allocated but not all which were requested. |
219 | */ | |
41ac7b3a | 220 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 221 | { |
660e9bde | 222 | struct dwc3_event_buffer *evt; |
9f622b2a | 223 | |
660e9bde FB |
224 | evt = dwc3_alloc_one_event_buffer(dwc, length); |
225 | if (IS_ERR(evt)) { | |
226 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
227 | return PTR_ERR(evt); | |
72246da4 | 228 | } |
696c8b12 | 229 | dwc->ev_buf = evt; |
72246da4 FB |
230 | |
231 | return 0; | |
232 | } | |
233 | ||
234 | /** | |
235 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 236 | * @dwc: pointer to our controller context structure |
72246da4 FB |
237 | * |
238 | * Returns 0 on success otherwise negative errno. | |
239 | */ | |
7acd85e0 | 240 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
241 | { |
242 | struct dwc3_event_buffer *evt; | |
660e9bde | 243 | |
696c8b12 | 244 | evt = dwc->ev_buf; |
660e9bde FB |
245 | dwc3_trace(trace_dwc3_core, |
246 | "Event buf %p dma %08llx length %d\n", | |
247 | evt->buf, (unsigned long long) evt->dma, | |
248 | evt->length); | |
249 | ||
250 | evt->lpos = 0; | |
251 | ||
252 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), | |
253 | lower_32_bits(evt->dma)); | |
254 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), | |
255 | upper_32_bits(evt->dma)); | |
256 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), | |
257 | DWC3_GEVNTSIZ_SIZE(evt->length)); | |
258 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
263 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
264 | { | |
265 | struct dwc3_event_buffer *evt; | |
72246da4 | 266 | |
696c8b12 | 267 | evt = dwc->ev_buf; |
7acd85e0 | 268 | |
660e9bde | 269 | evt->lpos = 0; |
7acd85e0 | 270 | |
660e9bde FB |
271 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); |
272 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); | |
273 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | |
274 | | DWC3_GEVNTSIZ_SIZE(0)); | |
275 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
276 | } |
277 | ||
0ffcaf37 FB |
278 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
279 | { | |
280 | if (!dwc->has_hibernation) | |
281 | return 0; | |
282 | ||
283 | if (!dwc->nr_scratch) | |
284 | return 0; | |
285 | ||
286 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
287 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
288 | if (!dwc->scratchbuf) | |
289 | return -ENOMEM; | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
295 | { | |
296 | dma_addr_t scratch_addr; | |
297 | u32 param; | |
298 | int ret; | |
299 | ||
300 | if (!dwc->has_hibernation) | |
301 | return 0; | |
302 | ||
303 | if (!dwc->nr_scratch) | |
304 | return 0; | |
305 | ||
306 | /* should never fall here */ | |
307 | if (!WARN_ON(dwc->scratchbuf)) | |
308 | return 0; | |
309 | ||
310 | scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, | |
311 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, | |
312 | DMA_BIDIRECTIONAL); | |
313 | if (dma_mapping_error(dwc->dev, scratch_addr)) { | |
314 | dev_err(dwc->dev, "failed to map scratch buffer\n"); | |
315 | ret = -EFAULT; | |
316 | goto err0; | |
317 | } | |
318 | ||
319 | dwc->scratch_addr = scratch_addr; | |
320 | ||
321 | param = lower_32_bits(scratch_addr); | |
322 | ||
323 | ret = dwc3_send_gadget_generic_command(dwc, | |
324 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
325 | if (ret < 0) | |
326 | goto err1; | |
327 | ||
328 | param = upper_32_bits(scratch_addr); | |
329 | ||
330 | ret = dwc3_send_gadget_generic_command(dwc, | |
331 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
332 | if (ret < 0) | |
333 | goto err1; | |
334 | ||
335 | return 0; | |
336 | ||
337 | err1: | |
338 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
339 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
340 | ||
341 | err0: | |
342 | return ret; | |
343 | } | |
344 | ||
345 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
346 | { | |
347 | if (!dwc->has_hibernation) | |
348 | return; | |
349 | ||
350 | if (!dwc->nr_scratch) | |
351 | return; | |
352 | ||
353 | /* should never fall here */ | |
354 | if (!WARN_ON(dwc->scratchbuf)) | |
355 | return; | |
356 | ||
357 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
358 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
359 | kfree(dwc->scratchbuf); | |
360 | } | |
361 | ||
789451f6 FB |
362 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
363 | { | |
364 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
365 | ||
366 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
367 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
368 | ||
73815280 | 369 | dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints", |
789451f6 FB |
370 | dwc->num_in_eps, dwc->num_out_eps); |
371 | } | |
372 | ||
41ac7b3a | 373 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
374 | { |
375 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
376 | ||
377 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
378 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
379 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
380 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
381 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
382 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
383 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
384 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
385 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
386 | } | |
387 | ||
b5a65c40 HR |
388 | /** |
389 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
390 | * @dwc: Pointer to our controller context structure | |
88bc9d19 HK |
391 | * |
392 | * Returns 0 on success. The USB PHY interfaces are configured but not | |
393 | * initialized. The PHY interfaces and the PHYs get initialized together with | |
394 | * the core in dwc3_core_init. | |
b5a65c40 | 395 | */ |
88bc9d19 | 396 | static int dwc3_phy_setup(struct dwc3 *dwc) |
b5a65c40 HR |
397 | { |
398 | u32 reg; | |
88bc9d19 | 399 | int ret; |
b5a65c40 HR |
400 | |
401 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
402 | ||
2164a476 HR |
403 | /* |
404 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
405 | * to '0' during coreConsultant configuration. So default value | |
406 | * will be '0' when the core is reset. Application needs to set it | |
407 | * to '1' after the core initialization is completed. | |
408 | */ | |
409 | if (dwc->revision > DWC3_REVISION_194A) | |
410 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
411 | ||
b5a65c40 HR |
412 | if (dwc->u2ss_inp3_quirk) |
413 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
414 | ||
df31f5b3 HR |
415 | if (dwc->req_p1p2p3_quirk) |
416 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
417 | ||
a2a1d0f5 HR |
418 | if (dwc->del_p1p2p3_quirk) |
419 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
420 | ||
41c06ffd HR |
421 | if (dwc->del_phy_power_chg_quirk) |
422 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
423 | ||
fb67afca HR |
424 | if (dwc->lfps_filter_quirk) |
425 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
426 | ||
14f4ac53 HR |
427 | if (dwc->rx_detect_poll_quirk) |
428 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
429 | ||
6b6a0c9a HR |
430 | if (dwc->tx_de_emphasis_quirk) |
431 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
432 | ||
cd72f890 | 433 | if (dwc->dis_u3_susphy_quirk) |
59acfa20 HR |
434 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; |
435 | ||
b5a65c40 HR |
436 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
437 | ||
2164a476 HR |
438 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
439 | ||
3e10a2ce HK |
440 | /* Select the HS PHY interface */ |
441 | switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { | |
442 | case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: | |
43cacb03 FB |
443 | if (dwc->hsphy_interface && |
444 | !strncmp(dwc->hsphy_interface, "utmi", 4)) { | |
3e10a2ce | 445 | reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 446 | break; |
43cacb03 FB |
447 | } else if (dwc->hsphy_interface && |
448 | !strncmp(dwc->hsphy_interface, "ulpi", 4)) { | |
3e10a2ce | 449 | reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 450 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
3e10a2ce | 451 | } else { |
88bc9d19 HK |
452 | /* Relying on default value. */ |
453 | if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) | |
454 | break; | |
3e10a2ce HK |
455 | } |
456 | /* FALLTHROUGH */ | |
88bc9d19 HK |
457 | case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: |
458 | /* Making sure the interface and PHY are operational */ | |
459 | ret = dwc3_soft_reset(dwc); | |
460 | if (ret) | |
461 | return ret; | |
462 | ||
463 | udelay(1); | |
464 | ||
465 | ret = dwc3_ulpi_init(dwc); | |
466 | if (ret) | |
467 | return ret; | |
468 | /* FALLTHROUGH */ | |
3e10a2ce HK |
469 | default: |
470 | break; | |
471 | } | |
472 | ||
2164a476 HR |
473 | /* |
474 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
475 | * '0' during coreConsultant configuration. So default value will | |
476 | * be '0' when the core is reset. Application needs to set it to | |
477 | * '1' after the core initialization is completed. | |
478 | */ | |
479 | if (dwc->revision > DWC3_REVISION_194A) | |
480 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
481 | ||
cd72f890 | 482 | if (dwc->dis_u2_susphy_quirk) |
0effe0a3 HR |
483 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
484 | ||
ec791d14 JY |
485 | if (dwc->dis_enblslpm_quirk) |
486 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
487 | ||
2164a476 | 488 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
88bc9d19 HK |
489 | |
490 | return 0; | |
b5a65c40 HR |
491 | } |
492 | ||
72246da4 FB |
493 | /** |
494 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
495 | * @dwc: Pointer to our controller context structure | |
496 | * | |
497 | * Returns 0 on success otherwise negative errno. | |
498 | */ | |
41ac7b3a | 499 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 | 500 | { |
0ffcaf37 | 501 | u32 hwparams4 = dwc->hwparams.hwparams4; |
72246da4 FB |
502 | u32 reg; |
503 | int ret; | |
504 | ||
7650bd74 SAS |
505 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
506 | /* This should read as U3 followed by revision number */ | |
690fb371 JY |
507 | if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { |
508 | /* Detected DWC_usb3 IP */ | |
509 | dwc->revision = reg; | |
510 | } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { | |
511 | /* Detected DWC_usb31 IP */ | |
512 | dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); | |
513 | dwc->revision |= DWC3_REVISION_IS_DWC31; | |
514 | } else { | |
7650bd74 SAS |
515 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); |
516 | ret = -ENODEV; | |
517 | goto err0; | |
518 | } | |
7650bd74 | 519 | |
fa0ea13e FB |
520 | /* |
521 | * Write Linux Version Code to our GUID register so it's easy to figure | |
522 | * out which kernel version a bug was found. | |
523 | */ | |
524 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
525 | ||
0e1e5c47 PZ |
526 | /* Handle USB2.0-only core configuration */ |
527 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
528 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
529 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
530 | dwc->maximum_speed = USB_SPEED_HIGH; | |
531 | } | |
532 | ||
72246da4 | 533 | /* issue device SoftReset too */ |
c5cc74e8 HK |
534 | ret = dwc3_soft_reset(dwc); |
535 | if (ret) | |
536 | goto err0; | |
72246da4 | 537 | |
57303488 KVA |
538 | ret = dwc3_core_soft_reset(dwc); |
539 | if (ret) | |
540 | goto err0; | |
58a0f23f | 541 | |
4878a028 | 542 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 543 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 544 | |
164d7731 | 545 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 546 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
547 | /** |
548 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
549 | * issue which would cause xHCI compliance tests to fail. | |
550 | * | |
551 | * Because of that we cannot enable clock gating on such | |
552 | * configurations. | |
553 | * | |
554 | * Refers to: | |
555 | * | |
556 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
557 | * SOF/ITP Mode Used | |
558 | */ | |
559 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
560 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
561 | (dwc->revision >= DWC3_REVISION_210A && | |
562 | dwc->revision <= DWC3_REVISION_250A)) | |
563 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
564 | else | |
565 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 566 | break; |
0ffcaf37 FB |
567 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
568 | /* enable hibernation here */ | |
569 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
570 | |
571 | /* | |
572 | * REVISIT Enabling this bit so that host-mode hibernation | |
573 | * will work. Device-mode hibernation is not yet implemented. | |
574 | */ | |
575 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 576 | break; |
4878a028 | 577 | default: |
1407bf13 | 578 | dwc3_trace(trace_dwc3_core, "No power optimization available\n"); |
4878a028 SAS |
579 | } |
580 | ||
946bd579 HR |
581 | /* check if current dwc3 is on simulation board */ |
582 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
1407bf13 FB |
583 | dwc3_trace(trace_dwc3_core, |
584 | "running on FPGA platform\n"); | |
946bd579 HR |
585 | dwc->is_fpga = true; |
586 | } | |
587 | ||
3b81221a HR |
588 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
589 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
590 | ||
591 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
592 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
593 | else | |
594 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
595 | ||
9a5b2f31 HR |
596 | if (dwc->u2exit_lfps_quirk) |
597 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
598 | ||
4878a028 SAS |
599 | /* |
600 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 601 | * where the device can fail to connect at SuperSpeed |
4878a028 | 602 | * and falls back to high-speed mode which causes |
1d046793 | 603 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
604 | */ |
605 | if (dwc->revision < DWC3_REVISION_190A) | |
606 | reg |= DWC3_GCTL_U2RSTECN; | |
607 | ||
789451f6 FB |
608 | dwc3_core_num_eps(dwc); |
609 | ||
4878a028 SAS |
610 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
611 | ||
0ffcaf37 FB |
612 | ret = dwc3_alloc_scratch_buffers(dwc); |
613 | if (ret) | |
614 | goto err1; | |
615 | ||
616 | ret = dwc3_setup_scratch_buffers(dwc); | |
617 | if (ret) | |
618 | goto err2; | |
619 | ||
72246da4 FB |
620 | return 0; |
621 | ||
0ffcaf37 FB |
622 | err2: |
623 | dwc3_free_scratch_buffers(dwc); | |
624 | ||
625 | err1: | |
626 | usb_phy_shutdown(dwc->usb2_phy); | |
627 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
628 | phy_exit(dwc->usb2_generic_phy); |
629 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 630 | |
72246da4 FB |
631 | err0: |
632 | return ret; | |
633 | } | |
634 | ||
635 | static void dwc3_core_exit(struct dwc3 *dwc) | |
636 | { | |
0ffcaf37 | 637 | dwc3_free_scratch_buffers(dwc); |
01b8daf7 VG |
638 | usb_phy_shutdown(dwc->usb2_phy); |
639 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
640 | phy_exit(dwc->usb2_generic_phy); |
641 | phy_exit(dwc->usb3_generic_phy); | |
72246da4 FB |
642 | } |
643 | ||
3c9f94ac | 644 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 645 | { |
3c9f94ac | 646 | struct device *dev = dwc->dev; |
941ea361 | 647 | struct device_node *node = dev->of_node; |
3c9f94ac | 648 | int ret; |
72246da4 | 649 | |
5088b6f5 KVA |
650 | if (node) { |
651 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
652 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
653 | } else { |
654 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
655 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
656 | } |
657 | ||
d105e7f8 FB |
658 | if (IS_ERR(dwc->usb2_phy)) { |
659 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
660 | if (ret == -ENXIO || ret == -ENODEV) { |
661 | dwc->usb2_phy = NULL; | |
662 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 663 | return ret; |
122f06e6 KVA |
664 | } else { |
665 | dev_err(dev, "no usb2 phy configured\n"); | |
666 | return ret; | |
667 | } | |
51e1e7bc FB |
668 | } |
669 | ||
d105e7f8 | 670 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 671 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
672 | if (ret == -ENXIO || ret == -ENODEV) { |
673 | dwc->usb3_phy = NULL; | |
674 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 675 | return ret; |
122f06e6 KVA |
676 | } else { |
677 | dev_err(dev, "no usb3 phy configured\n"); | |
678 | return ret; | |
679 | } | |
51e1e7bc FB |
680 | } |
681 | ||
57303488 KVA |
682 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
683 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
684 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
685 | if (ret == -ENOSYS || ret == -ENODEV) { | |
686 | dwc->usb2_generic_phy = NULL; | |
687 | } else if (ret == -EPROBE_DEFER) { | |
688 | return ret; | |
689 | } else { | |
690 | dev_err(dev, "no usb2 phy configured\n"); | |
691 | return ret; | |
692 | } | |
693 | } | |
694 | ||
695 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
696 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
697 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
698 | if (ret == -ENOSYS || ret == -ENODEV) { | |
699 | dwc->usb3_generic_phy = NULL; | |
700 | } else if (ret == -EPROBE_DEFER) { | |
701 | return ret; | |
702 | } else { | |
703 | dev_err(dev, "no usb3 phy configured\n"); | |
704 | return ret; | |
705 | } | |
706 | } | |
707 | ||
3c9f94ac FB |
708 | return 0; |
709 | } | |
710 | ||
5f94adfe FB |
711 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
712 | { | |
713 | struct device *dev = dwc->dev; | |
714 | int ret; | |
715 | ||
716 | switch (dwc->dr_mode) { | |
717 | case USB_DR_MODE_PERIPHERAL: | |
718 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
719 | ret = dwc3_gadget_init(dwc); | |
720 | if (ret) { | |
721 | dev_err(dev, "failed to initialize gadget\n"); | |
722 | return ret; | |
723 | } | |
724 | break; | |
725 | case USB_DR_MODE_HOST: | |
726 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); | |
727 | ret = dwc3_host_init(dwc); | |
728 | if (ret) { | |
729 | dev_err(dev, "failed to initialize host\n"); | |
730 | return ret; | |
731 | } | |
732 | break; | |
733 | case USB_DR_MODE_OTG: | |
734 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); | |
735 | ret = dwc3_host_init(dwc); | |
736 | if (ret) { | |
737 | dev_err(dev, "failed to initialize host\n"); | |
738 | return ret; | |
739 | } | |
740 | ||
741 | ret = dwc3_gadget_init(dwc); | |
742 | if (ret) { | |
743 | dev_err(dev, "failed to initialize gadget\n"); | |
744 | return ret; | |
745 | } | |
746 | break; | |
747 | default: | |
748 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
749 | return -EINVAL; | |
750 | } | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
756 | { | |
757 | switch (dwc->dr_mode) { | |
758 | case USB_DR_MODE_PERIPHERAL: | |
759 | dwc3_gadget_exit(dwc); | |
760 | break; | |
761 | case USB_DR_MODE_HOST: | |
762 | dwc3_host_exit(dwc); | |
763 | break; | |
764 | case USB_DR_MODE_OTG: | |
765 | dwc3_host_exit(dwc); | |
766 | dwc3_gadget_exit(dwc); | |
767 | break; | |
768 | default: | |
769 | /* do nothing */ | |
770 | break; | |
771 | } | |
772 | } | |
773 | ||
3c9f94ac FB |
774 | #define DWC3_ALIGN_MASK (16 - 1) |
775 | ||
776 | static int dwc3_probe(struct platform_device *pdev) | |
777 | { | |
778 | struct device *dev = &pdev->dev; | |
779 | struct dwc3_platform_data *pdata = dev_get_platdata(dev); | |
3c9f94ac FB |
780 | struct resource *res; |
781 | struct dwc3 *dwc; | |
80caf7d2 | 782 | u8 lpm_nyet_threshold; |
6b6a0c9a | 783 | u8 tx_de_emphasis; |
460d098c | 784 | u8 hird_threshold; |
db2be4e9 | 785 | u32 fladj = 0; |
3c9f94ac | 786 | |
b09e99ee | 787 | int ret; |
3c9f94ac FB |
788 | |
789 | void __iomem *regs; | |
790 | void *mem; | |
791 | ||
792 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); | |
734d5a53 | 793 | if (!mem) |
3c9f94ac | 794 | return -ENOMEM; |
734d5a53 | 795 | |
3c9f94ac FB |
796 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); |
797 | dwc->mem = mem; | |
798 | dwc->dev = dev; | |
799 | ||
800 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
801 | if (!res) { | |
802 | dev_err(dev, "missing IRQ\n"); | |
803 | return -ENODEV; | |
804 | } | |
805 | dwc->xhci_resources[1].start = res->start; | |
806 | dwc->xhci_resources[1].end = res->end; | |
807 | dwc->xhci_resources[1].flags = res->flags; | |
808 | dwc->xhci_resources[1].name = res->name; | |
809 | ||
810 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
811 | if (!res) { | |
812 | dev_err(dev, "missing memory resource\n"); | |
813 | return -ENODEV; | |
814 | } | |
815 | ||
f32a5e23 VG |
816 | dwc->xhci_resources[0].start = res->start; |
817 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
818 | DWC3_XHCI_REGS_END; | |
819 | dwc->xhci_resources[0].flags = res->flags; | |
820 | dwc->xhci_resources[0].name = res->name; | |
821 | ||
822 | res->start += DWC3_GLOBALS_REGS_START; | |
823 | ||
824 | /* | |
825 | * Request memory region but exclude xHCI regs, | |
826 | * since it will be requested by the xhci-plat driver. | |
827 | */ | |
828 | regs = devm_ioremap_resource(dev, res); | |
3da1f6ee FB |
829 | if (IS_ERR(regs)) { |
830 | ret = PTR_ERR(regs); | |
831 | goto err0; | |
832 | } | |
f32a5e23 VG |
833 | |
834 | dwc->regs = regs; | |
835 | dwc->regs_size = resource_size(res); | |
f32a5e23 | 836 | |
80caf7d2 HR |
837 | /* default to highest possible threshold */ |
838 | lpm_nyet_threshold = 0xff; | |
839 | ||
6b6a0c9a HR |
840 | /* default to -3.5dB de-emphasis */ |
841 | tx_de_emphasis = 1; | |
842 | ||
460d098c HR |
843 | /* |
844 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
845 | * threshold value of 0b1100 | |
846 | */ | |
847 | hird_threshold = 12; | |
848 | ||
63863b98 | 849 | dwc->maximum_speed = usb_get_maximum_speed(dev); |
06e7114f | 850 | dwc->dr_mode = usb_get_dr_mode(dev); |
63863b98 | 851 | |
3d128919 | 852 | dwc->has_lpm_erratum = device_property_read_bool(dev, |
80caf7d2 | 853 | "snps,has-lpm-erratum"); |
3d128919 | 854 | device_property_read_u8(dev, "snps,lpm-nyet-threshold", |
80caf7d2 | 855 | &lpm_nyet_threshold); |
3d128919 | 856 | dwc->is_utmi_l1_suspend = device_property_read_bool(dev, |
460d098c | 857 | "snps,is-utmi-l1-suspend"); |
3d128919 | 858 | device_property_read_u8(dev, "snps,hird-threshold", |
460d098c | 859 | &hird_threshold); |
3d128919 | 860 | dwc->usb3_lpm_capable = device_property_read_bool(dev, |
eac68e8f | 861 | "snps,usb3_lpm_capable"); |
3c9f94ac | 862 | |
3d128919 | 863 | dwc->disable_scramble_quirk = device_property_read_bool(dev, |
3b81221a | 864 | "snps,disable_scramble_quirk"); |
3d128919 | 865 | dwc->u2exit_lfps_quirk = device_property_read_bool(dev, |
9a5b2f31 | 866 | "snps,u2exit_lfps_quirk"); |
3d128919 | 867 | dwc->u2ss_inp3_quirk = device_property_read_bool(dev, |
b5a65c40 | 868 | "snps,u2ss_inp3_quirk"); |
3d128919 | 869 | dwc->req_p1p2p3_quirk = device_property_read_bool(dev, |
df31f5b3 | 870 | "snps,req_p1p2p3_quirk"); |
3d128919 | 871 | dwc->del_p1p2p3_quirk = device_property_read_bool(dev, |
a2a1d0f5 | 872 | "snps,del_p1p2p3_quirk"); |
3d128919 | 873 | dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, |
41c06ffd | 874 | "snps,del_phy_power_chg_quirk"); |
3d128919 | 875 | dwc->lfps_filter_quirk = device_property_read_bool(dev, |
fb67afca | 876 | "snps,lfps_filter_quirk"); |
3d128919 | 877 | dwc->rx_detect_poll_quirk = device_property_read_bool(dev, |
14f4ac53 | 878 | "snps,rx_detect_poll_quirk"); |
3d128919 | 879 | dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, |
59acfa20 | 880 | "snps,dis_u3_susphy_quirk"); |
3d128919 | 881 | dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, |
0effe0a3 | 882 | "snps,dis_u2_susphy_quirk"); |
ec791d14 JY |
883 | dwc->dis_enblslpm_quirk = device_property_read_bool(dev, |
884 | "snps,dis_enblslpm_quirk"); | |
6b6a0c9a | 885 | |
3d128919 | 886 | dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, |
6b6a0c9a | 887 | "snps,tx_de_emphasis_quirk"); |
3d128919 | 888 | device_property_read_u8(dev, "snps,tx_de_emphasis", |
6b6a0c9a | 889 | &tx_de_emphasis); |
3d128919 HK |
890 | device_property_read_string(dev, "snps,hsphy_interface", |
891 | &dwc->hsphy_interface); | |
892 | device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", | |
893 | &fladj); | |
894 | ||
895 | if (pdata) { | |
3c9f94ac | 896 | dwc->maximum_speed = pdata->maximum_speed; |
80caf7d2 HR |
897 | dwc->has_lpm_erratum = pdata->has_lpm_erratum; |
898 | if (pdata->lpm_nyet_threshold) | |
899 | lpm_nyet_threshold = pdata->lpm_nyet_threshold; | |
460d098c HR |
900 | dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend; |
901 | if (pdata->hird_threshold) | |
902 | hird_threshold = pdata->hird_threshold; | |
3c9f94ac | 903 | |
eac68e8f | 904 | dwc->usb3_lpm_capable = pdata->usb3_lpm_capable; |
3c9f94ac | 905 | dwc->dr_mode = pdata->dr_mode; |
3b81221a HR |
906 | |
907 | dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; | |
9a5b2f31 | 908 | dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; |
b5a65c40 | 909 | dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; |
df31f5b3 | 910 | dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; |
a2a1d0f5 | 911 | dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; |
41c06ffd | 912 | dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; |
fb67afca | 913 | dwc->lfps_filter_quirk = pdata->lfps_filter_quirk; |
14f4ac53 | 914 | dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk; |
59acfa20 | 915 | dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk; |
0effe0a3 | 916 | dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; |
ec791d14 | 917 | dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk; |
6b6a0c9a HR |
918 | |
919 | dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; | |
920 | if (pdata->tx_de_emphasis) | |
921 | tx_de_emphasis = pdata->tx_de_emphasis; | |
3e10a2ce HK |
922 | |
923 | dwc->hsphy_interface = pdata->hsphy_interface; | |
db2be4e9 | 924 | fladj = pdata->fladj_value; |
3c9f94ac FB |
925 | } |
926 | ||
80caf7d2 | 927 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
6b6a0c9a | 928 | dwc->tx_de_emphasis = tx_de_emphasis; |
80caf7d2 | 929 | |
460d098c HR |
930 | dwc->hird_threshold = hird_threshold |
931 | | (dwc->is_utmi_l1_suspend << 4); | |
932 | ||
6c89cce0 | 933 | platform_set_drvdata(pdev, dwc); |
2917e718 | 934 | dwc3_cache_hwparams(dwc); |
6c89cce0 | 935 | |
88bc9d19 HK |
936 | ret = dwc3_phy_setup(dwc); |
937 | if (ret) | |
938 | goto err0; | |
45bb7de2 | 939 | |
3c9f94ac FB |
940 | ret = dwc3_core_get_phy(dwc); |
941 | if (ret) | |
3da1f6ee | 942 | goto err0; |
3c9f94ac | 943 | |
72246da4 | 944 | spin_lock_init(&dwc->lock); |
72246da4 | 945 | |
19bacdc9 HK |
946 | if (!dev->dma_mask) { |
947 | dev->dma_mask = dev->parent->dma_mask; | |
948 | dev->dma_parms = dev->parent->dma_parms; | |
949 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
950 | } | |
ddff14f1 | 951 | |
802ca850 CP |
952 | pm_runtime_enable(dev); |
953 | pm_runtime_get_sync(dev); | |
954 | pm_runtime_forbid(dev); | |
72246da4 | 955 | |
3921426b FB |
956 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
957 | if (ret) { | |
958 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
959 | ret = -ENOMEM; | |
3da1f6ee | 960 | goto err1; |
3921426b FB |
961 | } |
962 | ||
32a4a135 FB |
963 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
964 | dwc->dr_mode = USB_DR_MODE_HOST; | |
965 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
966 | dwc->dr_mode = USB_DR_MODE_PERIPHERAL; | |
967 | ||
968 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
969 | dwc->dr_mode = USB_DR_MODE_OTG; | |
970 | ||
72246da4 FB |
971 | ret = dwc3_core_init(dwc); |
972 | if (ret) { | |
802ca850 | 973 | dev_err(dev, "failed to initialize core\n"); |
3da1f6ee | 974 | goto err1; |
72246da4 FB |
975 | } |
976 | ||
77966eb8 JY |
977 | /* Check the maximum_speed parameter */ |
978 | switch (dwc->maximum_speed) { | |
979 | case USB_SPEED_LOW: | |
980 | case USB_SPEED_FULL: | |
981 | case USB_SPEED_HIGH: | |
982 | case USB_SPEED_SUPER: | |
983 | case USB_SPEED_SUPER_PLUS: | |
984 | break; | |
985 | default: | |
986 | dev_err(dev, "invalid maximum_speed parameter %d\n", | |
987 | dwc->maximum_speed); | |
988 | /* fall through */ | |
989 | case USB_SPEED_UNKNOWN: | |
990 | /* default to superspeed */ | |
2c7f1bd9 JY |
991 | dwc->maximum_speed = USB_SPEED_SUPER; |
992 | ||
993 | /* | |
994 | * default to superspeed plus if we are capable. | |
995 | */ | |
996 | if (dwc3_is_usb31(dwc) && | |
997 | (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
998 | DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) | |
999 | dwc->maximum_speed = USB_SPEED_SUPER_PLUS; | |
77966eb8 JY |
1000 | |
1001 | break; | |
2c7f1bd9 JY |
1002 | } |
1003 | ||
db2be4e9 NB |
1004 | /* Adjust Frame Length */ |
1005 | dwc3_frame_length_adjustment(dwc, fladj); | |
1006 | ||
3088f108 KVA |
1007 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
1008 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
57303488 KVA |
1009 | ret = phy_power_on(dwc->usb2_generic_phy); |
1010 | if (ret < 0) | |
3da1f6ee | 1011 | goto err2; |
57303488 KVA |
1012 | |
1013 | ret = phy_power_on(dwc->usb3_generic_phy); | |
1014 | if (ret < 0) | |
3da1f6ee | 1015 | goto err3; |
3088f108 | 1016 | |
f122d33e FB |
1017 | ret = dwc3_event_buffers_setup(dwc); |
1018 | if (ret) { | |
1019 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
3da1f6ee | 1020 | goto err4; |
f122d33e FB |
1021 | } |
1022 | ||
5f94adfe FB |
1023 | ret = dwc3_core_init_mode(dwc); |
1024 | if (ret) | |
3da1f6ee | 1025 | goto err5; |
72246da4 FB |
1026 | |
1027 | ret = dwc3_debugfs_init(dwc); | |
1028 | if (ret) { | |
802ca850 | 1029 | dev_err(dev, "failed to initialize debugfs\n"); |
3da1f6ee | 1030 | goto err6; |
72246da4 FB |
1031 | } |
1032 | ||
802ca850 | 1033 | pm_runtime_allow(dev); |
72246da4 FB |
1034 | |
1035 | return 0; | |
1036 | ||
3da1f6ee | 1037 | err6: |
5f94adfe | 1038 | dwc3_core_exit_mode(dwc); |
72246da4 | 1039 | |
3da1f6ee | 1040 | err5: |
f122d33e FB |
1041 | dwc3_event_buffers_cleanup(dwc); |
1042 | ||
3da1f6ee | 1043 | err4: |
57303488 KVA |
1044 | phy_power_off(dwc->usb3_generic_phy); |
1045 | ||
3da1f6ee | 1046 | err3: |
57303488 KVA |
1047 | phy_power_off(dwc->usb2_generic_phy); |
1048 | ||
3da1f6ee | 1049 | err2: |
501fae51 KVA |
1050 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
1051 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
802ca850 | 1052 | dwc3_core_exit(dwc); |
72246da4 | 1053 | |
3da1f6ee | 1054 | err1: |
3921426b | 1055 | dwc3_free_event_buffers(dwc); |
88bc9d19 | 1056 | dwc3_ulpi_exit(dwc); |
3921426b | 1057 | |
3da1f6ee FB |
1058 | err0: |
1059 | /* | |
1060 | * restore res->start back to its original value so that, in case the | |
1061 | * probe is deferred, we don't end up getting error in request the | |
1062 | * memory region the next time probe is called. | |
1063 | */ | |
1064 | res->start -= DWC3_GLOBALS_REGS_START; | |
1065 | ||
72246da4 FB |
1066 | return ret; |
1067 | } | |
1068 | ||
fb4e98ab | 1069 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 1070 | { |
72246da4 | 1071 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
3da1f6ee FB |
1072 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1073 | ||
1074 | /* | |
1075 | * restore res->start back to its original value so that, in case the | |
1076 | * probe is deferred, we don't end up getting error in request the | |
1077 | * memory region the next time probe is called. | |
1078 | */ | |
1079 | res->start -= DWC3_GLOBALS_REGS_START; | |
72246da4 | 1080 | |
dc99f16f FB |
1081 | dwc3_debugfs_exit(dwc); |
1082 | dwc3_core_exit_mode(dwc); | |
1083 | dwc3_event_buffers_cleanup(dwc); | |
1084 | dwc3_free_event_buffers(dwc); | |
1085 | ||
8ba007a9 KVA |
1086 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
1087 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
57303488 KVA |
1088 | phy_power_off(dwc->usb2_generic_phy); |
1089 | phy_power_off(dwc->usb3_generic_phy); | |
8ba007a9 | 1090 | |
72246da4 | 1091 | dwc3_core_exit(dwc); |
88bc9d19 | 1092 | dwc3_ulpi_exit(dwc); |
72246da4 | 1093 | |
16b972a5 | 1094 | pm_runtime_put_sync(&pdev->dev); |
72246da4 FB |
1095 | pm_runtime_disable(&pdev->dev); |
1096 | ||
72246da4 FB |
1097 | return 0; |
1098 | } | |
1099 | ||
19fda7cd | 1100 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
1101 | static int dwc3_suspend(struct device *dev) |
1102 | { | |
1103 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1104 | unsigned long flags; | |
1105 | ||
1106 | spin_lock_irqsave(&dwc->lock, flags); | |
1107 | ||
a45c82b8 RK |
1108 | switch (dwc->dr_mode) { |
1109 | case USB_DR_MODE_PERIPHERAL: | |
1110 | case USB_DR_MODE_OTG: | |
7415f17c FB |
1111 | dwc3_gadget_suspend(dwc); |
1112 | /* FALLTHROUGH */ | |
a45c82b8 | 1113 | case USB_DR_MODE_HOST: |
7415f17c | 1114 | default: |
0b0231aa | 1115 | dwc3_event_buffers_cleanup(dwc); |
7415f17c FB |
1116 | break; |
1117 | } | |
1118 | ||
1119 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
1120 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1121 | ||
1122 | usb_phy_shutdown(dwc->usb3_phy); | |
1123 | usb_phy_shutdown(dwc->usb2_phy); | |
57303488 KVA |
1124 | phy_exit(dwc->usb2_generic_phy); |
1125 | phy_exit(dwc->usb3_generic_phy); | |
7415f17c | 1126 | |
6344475f SN |
1127 | pinctrl_pm_select_sleep_state(dev); |
1128 | ||
7415f17c FB |
1129 | return 0; |
1130 | } | |
1131 | ||
1132 | static int dwc3_resume(struct device *dev) | |
1133 | { | |
1134 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1135 | unsigned long flags; | |
57303488 | 1136 | int ret; |
7415f17c | 1137 | |
6344475f SN |
1138 | pinctrl_pm_select_default_state(dev); |
1139 | ||
7415f17c FB |
1140 | usb_phy_init(dwc->usb3_phy); |
1141 | usb_phy_init(dwc->usb2_phy); | |
57303488 KVA |
1142 | ret = phy_init(dwc->usb2_generic_phy); |
1143 | if (ret < 0) | |
1144 | return ret; | |
1145 | ||
1146 | ret = phy_init(dwc->usb3_generic_phy); | |
1147 | if (ret < 0) | |
1148 | goto err_usb2phy_init; | |
7415f17c FB |
1149 | |
1150 | spin_lock_irqsave(&dwc->lock, flags); | |
1151 | ||
0b0231aa | 1152 | dwc3_event_buffers_setup(dwc); |
7415f17c FB |
1153 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); |
1154 | ||
a45c82b8 RK |
1155 | switch (dwc->dr_mode) { |
1156 | case USB_DR_MODE_PERIPHERAL: | |
1157 | case USB_DR_MODE_OTG: | |
7415f17c FB |
1158 | dwc3_gadget_resume(dwc); |
1159 | /* FALLTHROUGH */ | |
a45c82b8 | 1160 | case USB_DR_MODE_HOST: |
7415f17c FB |
1161 | default: |
1162 | /* do nothing */ | |
1163 | break; | |
1164 | } | |
1165 | ||
1166 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1167 | ||
1168 | pm_runtime_disable(dev); | |
1169 | pm_runtime_set_active(dev); | |
1170 | pm_runtime_enable(dev); | |
1171 | ||
1172 | return 0; | |
57303488 KVA |
1173 | |
1174 | err_usb2phy_init: | |
1175 | phy_exit(dwc->usb2_generic_phy); | |
1176 | ||
1177 | return ret; | |
7415f17c FB |
1178 | } |
1179 | ||
1180 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c FB |
1181 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
1182 | }; | |
1183 | ||
1184 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
1185 | #else | |
1186 | #define DWC3_PM_OPS NULL | |
1187 | #endif | |
1188 | ||
5088b6f5 KVA |
1189 | #ifdef CONFIG_OF |
1190 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
1191 | { |
1192 | .compatible = "snps,dwc3" | |
1193 | }, | |
5088b6f5 KVA |
1194 | { |
1195 | .compatible = "synopsys,dwc3" | |
1196 | }, | |
1197 | { }, | |
1198 | }; | |
1199 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
1200 | #endif | |
1201 | ||
404905a6 HK |
1202 | #ifdef CONFIG_ACPI |
1203 | ||
1204 | #define ACPI_ID_INTEL_BSW "808622B7" | |
1205 | ||
1206 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
1207 | { ACPI_ID_INTEL_BSW, 0 }, | |
1208 | { }, | |
1209 | }; | |
1210 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
1211 | #endif | |
1212 | ||
72246da4 FB |
1213 | static struct platform_driver dwc3_driver = { |
1214 | .probe = dwc3_probe, | |
7690417d | 1215 | .remove = dwc3_remove, |
72246da4 FB |
1216 | .driver = { |
1217 | .name = "dwc3", | |
5088b6f5 | 1218 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 1219 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7415f17c | 1220 | .pm = DWC3_PM_OPS, |
72246da4 | 1221 | }, |
72246da4 FB |
1222 | }; |
1223 | ||
b1116dcc TK |
1224 | module_platform_driver(dwc3_driver); |
1225 | ||
7ae4fc4d | 1226 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 1227 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 1228 | MODULE_LICENSE("GPL v2"); |
72246da4 | 1229 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |