[linux-2.6-block.git] / drivers / usb / dwc3 / core.c

/**
 * core.c - DesignWare USB3 DRD Controller Core file
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>

#include <linux/usb/otg.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>

#include "core.h"
#include "gadget.h"
#include "io.h"

#include "debug.h"

static char *maximum_speed = "super";
module_param(maximum_speed, charp, 0);
MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");

/* -------------------------------------------------------------------------- */

void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
{
	u32 reg;

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
	reg |= DWC3_GCTL_PRTCAPDIR(mode);
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 * @dwc: pointer to our context structure
 */
static void dwc3_core_soft_reset(struct dwc3 *dwc)
{
	u32		reg;

	/* Before Resetting PHY, put Core in Reset */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg |= DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	/* Assert USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Assert USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	usb_phy_init(dwc->usb2_phy);
	usb_phy_init(dwc->usb3_phy);
	mdelay(100);

	/* Clear USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Clear USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	mdelay(100);

	/* After PHYs are stable we can take Core out of reset state */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_free_one_event_buffer - Frees one event buffer
 * @dwc: Pointer to our controller context structure
 * @evt: Pointer to event buffer to be freed
 */
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
		struct dwc3_event_buffer *evt)
{
	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
}

/**
 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 * @dwc: Pointer to our controller context structure
 * @length: size of the event buffer
 *
 * Returns a pointer to the allocated event buffer structure on success
 * otherwise ERR_PTR(errno).
 */
static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
{
	struct dwc3_event_buffer	*evt;

	evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
	if (!evt)
		return ERR_PTR(-ENOMEM);

	evt->dwc	= dwc;
	evt->length	= length;
	evt->buf	= dma_alloc_coherent(dwc->dev, length,
			&evt->dma, GFP_KERNEL);
	if (!evt->buf)
		return ERR_PTR(-ENOMEM);

	return evt;
}

/**
 * dwc3_free_event_buffers - frees all allocated event buffers
 * @dwc: Pointer to our controller context structure
 */
static void dwc3_free_event_buffers(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int i;

	for (i = 0; i < dwc->num_event_buffers; i++) {
		evt = dwc->ev_buffs[i];
		if (evt)
			dwc3_free_one_event_buffer(dwc, evt);
	}
}

/**
 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 * @dwc: pointer to our controller context structure
 * @length: size of event buffer
 *
 * Returns 0 on success otherwise negative errno. In the error case, dwc
 * may contain some buffers allocated but not all which were requested.
 */
static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
{
	int			num;
	int			i;

	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	dwc->num_event_buffers = num;

	dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
			GFP_KERNEL);
	if (!dwc->ev_buffs) {
		dev_err(dwc->dev, "can't allocate event buffers array\n");
		return -ENOMEM;
	}

	for (i = 0; i < num; i++) {
		struct dwc3_event_buffer	*evt;

		evt = dwc3_alloc_one_event_buffer(dwc, length);
		if (IS_ERR(evt)) {
			dev_err(dwc->dev, "can't allocate event buffer\n");
			return PTR_ERR(evt);
		}
		dwc->ev_buffs[i] = evt;
	}

	return 0;
}

/**
 * dwc3_event_buffers_setup - setup our allocated event buffers
 * @dwc: pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int dwc3_event_buffers_setup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];
		dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
				evt->buf, (unsigned long long) evt->dma,
				evt->length);

		evt->lpos = 0;

		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
				lower_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
				upper_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
				evt->length & 0xffff);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}

	return 0;
}

static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];

		evt->lpos = 0;

		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}
}

static void dwc3_cache_hwparams(struct dwc3 *dwc)
{
	struct dwc3_hwparams	*parms = &dwc->hwparams;

	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
}

/**
 * dwc3_core_init - Low-level initialization of DWC3 Core
 * @dwc: Pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int dwc3_core_init(struct dwc3 *dwc)
{
	unsigned long		timeout;
	u32			reg;
	int			ret;

	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	/* This should read as U3 followed by revision number */
	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
		ret = -ENODEV;
		goto err0;
	}
	dwc->revision = reg;

	/* issue device SoftReset too */
	timeout = jiffies + msecs_to_jiffies(500);
	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	do {
		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		if (!(reg & DWC3_DCTL_CSFTRST))
			break;

		if (time_after(jiffies, timeout)) {
			dev_err(dwc->dev, "Reset Timed Out\n");
			ret = -ETIMEDOUT;
			goto err0;
		}

		cpu_relax();
	} while (true);

	dwc3_core_soft_reset(dwc);

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	reg &= ~DWC3_GCTL_DISSCRAMBLE;

	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
		break;
	default:
		dev_dbg(dwc->dev, "No power optimization available\n");
	}

	/*
	 * WORKAROUND: DWC3 revisions <1.90a have a bug
	 * where the device can fail to connect at SuperSpeed
	 * and falls back to high-speed mode which causes
	 * the device to enter a Connect/Disconnect loop
	 */
	if (dwc->revision < DWC3_REVISION_190A)
		reg |= DWC3_GCTL_U2RSTECN;

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	ret = dwc3_event_buffers_setup(dwc);
	if (ret) {
		dev_err(dwc->dev, "failed to setup event buffers\n");
		goto err0;
	}

	return 0;

err0:
	return ret;
}

static void dwc3_core_exit(struct dwc3 *dwc)
{
	dwc3_event_buffers_cleanup(dwc);

	usb_phy_shutdown(dwc->usb2_phy);
	usb_phy_shutdown(dwc->usb3_phy);
}

#define DWC3_ALIGN_MASK		(16 - 1)

static int dwc3_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;
	struct resource		*res;
	struct dwc3		*dwc;
	struct device		*dev = &pdev->dev;

	int			ret = -ENOMEM;

	void __iomem		*regs;
	void			*mem;

	u8			mode;

	mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	if (!mem) {
		dev_err(dev, "not enough memory\n");
		return -ENOMEM;
	}
	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	dwc->mem = mem;

	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res) {
		dev_err(dev, "missing IRQ\n");
		return -ENODEV;
	}
	dwc->xhci_resources[1].start = res->start;
	dwc->xhci_resources[1].end = res->end;
	dwc->xhci_resources[1].flags = res->flags;
	dwc->xhci_resources[1].name = res->name;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "missing memory resource\n");
		return -ENODEV;
	}
	dwc->xhci_resources[0].start = res->start;
	dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
					DWC3_XHCI_REGS_END;
	dwc->xhci_resources[0].flags = res->flags;
	dwc->xhci_resources[0].name = res->name;

	 /*
	  * Request memory region but exclude xHCI regs,
	  * since it will be requested by the xhci-plat driver.
	  */
	res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
			resource_size(res) - DWC3_GLOBALS_REGS_START,
			dev_name(dev));
	if (!res) {
		dev_err(dev, "can't request mem region\n");
		return -ENOMEM;
	}

	regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
	if (!regs) {
		dev_err(dev, "ioremap failed\n");
		return -ENOMEM;
	}

	dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
		dev_err(dev, "no usb2 phy configured\n");
		return -EPROBE_DEFER;
	}

	dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
	if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
		dev_err(dev, "no usb3 phy configured\n");
		return -EPROBE_DEFER;
	}

	spin_lock_init(&dwc->lock);
	platform_set_drvdata(pdev, dwc);

	dwc->regs	= regs;
	dwc->regs_size	= resource_size(res);
	dwc->dev	= dev;

	if (!strncmp("super", maximum_speed, 5))
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	else if (!strncmp("high", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	else if (!strncmp("full", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	else if (!strncmp("low", maximum_speed, 3))
		dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	else
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;

	if (of_get_property(node, "tx-fifo-resize", NULL))
		dwc->needs_fifo_resize = true;

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);
	pm_runtime_forbid(dev);

	dwc3_cache_hwparams(dwc);

	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
	if (ret) {
		dev_err(dwc->dev, "failed to allocate event buffers\n");
		ret = -ENOMEM;
		goto err0;
	}

	ret = dwc3_core_init(dwc);
	if (ret) {
		dev_err(dev, "failed to initialize core\n");
		goto err0;
	}

	mode = DWC3_MODE(dwc->hwparams.hwparams0);

	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto err1;
		}
		break;
	case DWC3_MODE_HOST:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto err1;
		}
		break;
	case DWC3_MODE_DRD:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto err1;
		}

		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto err1;
		}
		break;
	default:
		dev_err(dev, "Unsupported mode of operation %d\n", mode);
		goto err1;
	}
	dwc->mode = mode;

	ret = dwc3_debugfs_init(dwc);
	if (ret) {
		dev_err(dev, "failed to initialize debugfs\n");
		goto err2;
	}

	pm_runtime_allow(dev);

	return 0;

err2:
	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

err1:
	dwc3_core_exit(dwc);

err0:
	dwc3_free_event_buffers(dwc);

	return ret;
}

static int dwc3_remove(struct platform_device *pdev)
{
	struct dwc3	*dwc = platform_get_drvdata(pdev);
	struct resource	*res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	dwc3_debugfs_exit(dwc);

	switch (dwc->mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

	dwc3_core_exit(dwc);

	return 0;
}

static struct platform_driver dwc3_driver = {
	.probe		= dwc3_probe,
	.remove		= dwc3_remove,
	.driver		= {
		.name	= "dwc3",
	},
};

module_platform_driver(dwc3_driver);

MODULE_ALIAS("platform:dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Commit	Line	Data
72246da4 FB	1	/**
	2	* core.c - DesignWare USB3 DRD Controller Core file
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/platform_device.h>
	44	#include <linux/pm_runtime.h>
	45	#include <linux/interrupt.h>
	46	#include <linux/ioport.h>
	47	#include <linux/io.h>
	48	#include <linux/list.h>
	49	#include <linux/delay.h>
	50	#include <linux/dma-mapping.h>
457e84b6	51	#include <linux/of.h>
72246da4	52
51e1e7bc	53	#include <linux/usb/otg.h>
72246da4 FB	54	#include <linux/usb/ch9.h>
	55	#include <linux/usb/gadget.h>
	56
	57	#include "core.h"
	58	#include "gadget.h"
	59	#include "io.h"
	60
	61	#include "debug.h"
	62
6c167fc9 FB	63	static char *maximum_speed = "super";
	64	module_param(maximum_speed, charp, 0);
	65	MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
	66
8300dd23 FB	67	/* -------------------------------------------------------------------------- */
8300dd23 FB	68
3140e8cb SAS	69	void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
	70	{
	71	u32 reg;
	72
	73	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	74	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
	75	reg \|= DWC3_GCTL_PRTCAPDIR(mode);
	76	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	77	}
8300dd23	78
72246da4 FB	79	/**
	80	* dwc3_core_soft_reset - Issues core soft reset and PHY reset
	81	* @dwc: pointer to our context structure
	82	*/
	83	static void dwc3_core_soft_reset(struct dwc3 *dwc)
	84	{
	85	u32 reg;
	86
	87	/* Before Resetting PHY, put Core in Reset */
	88	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	89	reg \|= DWC3_GCTL_CORESOFTRESET;
	90	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	91
	92	/* Assert USB3 PHY reset */
	93	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	94	reg \|= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	95	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	96
	97	/* Assert USB2 PHY reset */
	98	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	99	reg \|= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	100	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	101
51e1e7bc FB	102	usb_phy_init(dwc->usb2_phy);
51e1e7bc FB	103	usb_phy_init(dwc->usb3_phy);
72246da4 FB	104	mdelay(100);
	105
	106	/* Clear USB3 PHY reset */
	107	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	108	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	109	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	110
	111	/* Clear USB2 PHY reset */
	112	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	113	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	114	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	115
45627ac6 PA	116	mdelay(100);
45627ac6 PA	117
72246da4 FB	118	/* After PHYs are stable we can take Core out of reset state */
	119	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	120	reg &= ~DWC3_GCTL_CORESOFTRESET;
	121	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	122	}
	123
	124	/**
	125	* dwc3_free_one_event_buffer - Frees one event buffer
	126	* @dwc: Pointer to our controller context structure
	127	* @evt: Pointer to event buffer to be freed
	128	*/
	129	static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
	130	struct dwc3_event_buffer *evt)
	131	{
	132	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
72246da4 FB	133	}
	134
	135	/**
1d046793	136	* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4 FB	137	* @dwc: Pointer to our controller context structure
	138	* @length: size of the event buffer
	139	*
1d046793	140	* Returns a pointer to the allocated event buffer structure on success
72246da4 FB	141	* otherwise ERR_PTR(errno).
72246da4 FB	142	*/
41ac7b3a	143	static struct dwc3_event_buffer dwc3_alloc_one_event_buffer(struct dwc3 dwc, unsigned length)
72246da4 FB	144	{
	145	struct dwc3_event_buffer *evt;
	146
380f0d28	147	evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4 FB	148	if (!evt)
	149	return ERR_PTR(-ENOMEM);
	150
	151	evt->dwc = dwc;
	152	evt->length = length;
	153	evt->buf = dma_alloc_coherent(dwc->dev, length,
	154	&evt->dma, GFP_KERNEL);
e32672f0	155	if (!evt->buf)
72246da4	156	return ERR_PTR(-ENOMEM);
72246da4 FB	157
	158	return evt;
	159	}
	160
	161	/**
	162	* dwc3_free_event_buffers - frees all allocated event buffers
	163	* @dwc: Pointer to our controller context structure
	164	*/
	165	static void dwc3_free_event_buffers(struct dwc3 *dwc)
	166	{
	167	struct dwc3_event_buffer *evt;
	168	int i;
	169
9f622b2a	170	for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4	171	evt = dwc->ev_buffs[i];
64b6c8a7	172	if (evt)
72246da4	173	dwc3_free_one_event_buffer(dwc, evt);
72246da4 FB	174	}
	175	}
	176
	177	/**
	178	* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793	179	* @dwc: pointer to our controller context structure
72246da4 FB	180	* @length: size of event buffer
72246da4 FB	181	*
1d046793	182	* Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4 FB	183	* may contain some buffers allocated but not all which were requested.
72246da4 FB	184	*/
41ac7b3a	185	static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4	186	{
9f622b2a	187	int num;
72246da4 FB	188	int i;
72246da4 FB	189
9f622b2a FB	190	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	191	dwc->num_event_buffers = num;
	192
380f0d28 FB	193	dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(dwc->ev_buffs) num,
380f0d28 FB	194	GFP_KERNEL);
457d3f21 FB	195	if (!dwc->ev_buffs) {
	196	dev_err(dwc->dev, "can't allocate event buffers array\n");
	197	return -ENOMEM;
	198	}
	199
72246da4 FB	200	for (i = 0; i < num; i++) {
	201	struct dwc3_event_buffer *evt;
	202
	203	evt = dwc3_alloc_one_event_buffer(dwc, length);
	204	if (IS_ERR(evt)) {
	205	dev_err(dwc->dev, "can't allocate event buffer\n");
	206	return PTR_ERR(evt);
	207	}
	208	dwc->ev_buffs[i] = evt;
	209	}
	210
	211	return 0;
	212	}
	213
	214	/**
	215	* dwc3_event_buffers_setup - setup our allocated event buffers
1d046793	216	* @dwc: pointer to our controller context structure
72246da4 FB	217	*
	218	* Returns 0 on success otherwise negative errno.
	219	*/
7acd85e0	220	static int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4 FB	221	{
	222	struct dwc3_event_buffer *evt;
	223	int n;
	224
9f622b2a	225	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4 FB	226	evt = dwc->ev_buffs[n];
	227	dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
	228	evt->buf, (unsigned long long) evt->dma,
	229	evt->length);
	230
7acd85e0 PZ	231	evt->lpos = 0;
7acd85e0 PZ	232
72246da4 FB	233	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
	234	lower_32_bits(evt->dma));
	235	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
	236	upper_32_bits(evt->dma));
	237	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
	238	evt->length & 0xffff);
	239	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	240	}
	241
	242	return 0;
	243	}
	244
	245	static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
	246	{
	247	struct dwc3_event_buffer *evt;
	248	int n;
	249
9f622b2a	250	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4	251	evt = dwc->ev_buffs[n];
7acd85e0 PZ	252
	253	evt->lpos = 0;
	254
72246da4 FB	255	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
	256	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
	257	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
	258	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	259	}
	260	}
	261
41ac7b3a	262	static void dwc3_cache_hwparams(struct dwc3 *dwc)
26ceca97 FB	263	{
	264	struct dwc3_hwparams *parms = &dwc->hwparams;
	265
	266	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	267	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	268	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	269	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	270	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	271	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	272	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	273	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	274	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
	275	}
	276
72246da4 FB	277	/**
	278	* dwc3_core_init - Low-level initialization of DWC3 Core
	279	* @dwc: Pointer to our controller context structure
	280	*
	281	* Returns 0 on success otherwise negative errno.
	282	*/
41ac7b3a	283	static int dwc3_core_init(struct dwc3 *dwc)
72246da4 FB	284	{
	285	unsigned long timeout;
	286	u32 reg;
	287	int ret;
	288
7650bd74 SAS	289	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	290	/* This should read as U3 followed by revision number */
	291	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
	292	dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
	293	ret = -ENODEV;
	294	goto err0;
	295	}
248b122b	296	dwc->revision = reg;
7650bd74	297
72246da4 FB	298	/* issue device SoftReset too */
	299	timeout = jiffies + msecs_to_jiffies(500);
	300	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	301	do {
	302	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	303	if (!(reg & DWC3_DCTL_CSFTRST))
	304	break;
	305
	306	if (time_after(jiffies, timeout)) {
	307	dev_err(dwc->dev, "Reset Timed Out\n");
	308	ret = -ETIMEDOUT;
	309	goto err0;
	310	}
	311
	312	cpu_relax();
	313	} while (true);
	314
58a0f23f PA	315	dwc3_core_soft_reset(dwc);
58a0f23f PA	316
4878a028	317	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a	318	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 SAS	319	reg &= ~DWC3_GCTL_DISSCRAMBLE;
4878a028 SAS	320
164d7731	321	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 SAS	322	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
	323	reg &= ~DWC3_GCTL_DSBLCLKGTNG;
	324	break;
	325	default:
	326	dev_dbg(dwc->dev, "No power optimization available\n");
	327	}
	328
	329	/*
	330	* WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793	331	* where the device can fail to connect at SuperSpeed
4878a028	332	* and falls back to high-speed mode which causes
1d046793	333	* the device to enter a Connect/Disconnect loop
4878a028 SAS	334	*/
	335	if (dwc->revision < DWC3_REVISION_190A)
	336	reg \|= DWC3_GCTL_U2RSTECN;
	337
	338	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	339
72246da4 FB	340	ret = dwc3_event_buffers_setup(dwc);
	341	if (ret) {
	342	dev_err(dwc->dev, "failed to setup event buffers\n");
3921426b	343	goto err0;
72246da4 FB	344	}
	345
	346	return 0;
	347
72246da4 FB	348	err0:
	349	return ret;
	350	}
	351
	352	static void dwc3_core_exit(struct dwc3 *dwc)
	353	{
	354	dwc3_event_buffers_cleanup(dwc);
01b8daf7 VG	355
	356	usb_phy_shutdown(dwc->usb2_phy);
	357	usb_phy_shutdown(dwc->usb3_phy);
72246da4 FB	358	}
	359
	360	#define DWC3_ALIGN_MASK (16 - 1)
	361
41ac7b3a	362	static int dwc3_probe(struct platform_device *pdev)
72246da4	363	{
457e84b6	364	struct device_node *node = pdev->dev.of_node;
72246da4 FB	365	struct resource *res;
72246da4 FB	366	struct dwc3 *dwc;
802ca850	367	struct device *dev = &pdev->dev;
0949e99b	368
72246da4	369	int ret = -ENOMEM;
0949e99b FB	370
0949e99b FB	371	void __iomem *regs;
72246da4 FB	372	void *mem;
72246da4 FB	373
0949e99b FB	374	u8 mode;
0949e99b FB	375
802ca850	376	mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
72246da4	377	if (!mem) {
802ca850 CP	378	dev_err(dev, "not enough memory\n");
802ca850 CP	379	return -ENOMEM;
72246da4 FB	380	}
	381	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	382	dwc->mem = mem;
	383
51249dca	384	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
72246da4	385	if (!res) {
51249dca	386	dev_err(dev, "missing IRQ\n");
802ca850	387	return -ENODEV;
72246da4	388	}
066618bc KVA	389	dwc->xhci_resources[1].start = res->start;
	390	dwc->xhci_resources[1].end = res->end;
	391	dwc->xhci_resources[1].flags = res->flags;
	392	dwc->xhci_resources[1].name = res->name;
72246da4	393
51249dca IS	394	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	395	if (!res) {
	396	dev_err(dev, "missing memory resource\n");
	397	return -ENODEV;
	398	}
066618bc	399	dwc->xhci_resources[0].start = res->start;
51249dca IS	400	dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
51249dca IS	401	DWC3_XHCI_REGS_END;
066618bc KVA	402	dwc->xhci_resources[0].flags = res->flags;
066618bc KVA	403	dwc->xhci_resources[0].name = res->name;
51249dca IS	404
	405	/*
	406	* Request memory region but exclude xHCI regs,
	407	* since it will be requested by the xhci-plat driver.
	408	*/
	409	res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
	410	resource_size(res) - DWC3_GLOBALS_REGS_START,
802ca850	411	dev_name(dev));
72246da4	412	if (!res) {
802ca850 CP	413	dev_err(dev, "can't request mem region\n");
802ca850 CP	414	return -ENOMEM;
72246da4 FB	415	}
72246da4 FB	416
b7e38aa6	417	regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
72246da4	418	if (!regs) {
802ca850 CP	419	dev_err(dev, "ioremap failed\n");
802ca850 CP	420	return -ENOMEM;
72246da4 FB	421	}
72246da4 FB	422
51e1e7bc FB	423	dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
	424	if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
	425	dev_err(dev, "no usb2 phy configured\n");
	426	return -EPROBE_DEFER;
	427	}
	428
	429	dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
	430	if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
	431	dev_err(dev, "no usb3 phy configured\n");
	432	return -EPROBE_DEFER;
	433	}
	434
72246da4 FB	435	spin_lock_init(&dwc->lock);
	436	platform_set_drvdata(pdev, dwc);
	437
	438	dwc->regs = regs;
	439	dwc->regs_size = resource_size(res);
802ca850	440	dwc->dev = dev;
72246da4	441
6c167fc9 FB	442	if (!strncmp("super", maximum_speed, 5))
	443	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	444	else if (!strncmp("high", maximum_speed, 4))
	445	dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	446	else if (!strncmp("full", maximum_speed, 4))
	447	dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	448	else if (!strncmp("low", maximum_speed, 3))
	449	dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	450	else
	451	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	452
457e84b6 FB	453	if (of_get_property(node, "tx-fifo-resize", NULL))
	454	dwc->needs_fifo_resize = true;
	455
802ca850 CP	456	pm_runtime_enable(dev);
	457	pm_runtime_get_sync(dev);
	458	pm_runtime_forbid(dev);
72246da4	459
4fd24483 KVA	460	dwc3_cache_hwparams(dwc);
4fd24483 KVA	461
3921426b FB	462	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
	463	if (ret) {
	464	dev_err(dwc->dev, "failed to allocate event buffers\n");
	465	ret = -ENOMEM;
	466	goto err0;
	467	}
	468
72246da4 FB	469	ret = dwc3_core_init(dwc);
72246da4 FB	470	if (ret) {
802ca850	471	dev_err(dev, "failed to initialize core\n");
3921426b	472	goto err0;
72246da4 FB	473	}
72246da4 FB	474
0949e99b FB	475	mode = DWC3_MODE(dwc->hwparams.hwparams0);
	476
	477	switch (mode) {
0949e99b	478	case DWC3_MODE_DEVICE:
3140e8cb	479	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
72246da4 FB	480	ret = dwc3_gadget_init(dwc);
72246da4 FB	481	if (ret) {
802ca850 CP	482	dev_err(dev, "failed to initialize gadget\n");
802ca850 CP	483	goto err1;
72246da4	484	}
d07e8819 FB	485	break;
d07e8819 FB	486	case DWC3_MODE_HOST:
3140e8cb	487	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
d07e8819 FB	488	ret = dwc3_host_init(dwc);
d07e8819 FB	489	if (ret) {
802ca850 CP	490	dev_err(dev, "failed to initialize host\n");
802ca850 CP	491	goto err1;
d07e8819 FB	492	}
	493	break;
	494	case DWC3_MODE_DRD:
3140e8cb	495	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
d07e8819 FB	496	ret = dwc3_host_init(dwc);
d07e8819 FB	497	if (ret) {
802ca850 CP	498	dev_err(dev, "failed to initialize host\n");
802ca850 CP	499	goto err1;
d07e8819 FB	500	}
d07e8819 FB	501
72246da4 FB	502	ret = dwc3_gadget_init(dwc);
72246da4 FB	503	if (ret) {
802ca850 CP	504	dev_err(dev, "failed to initialize gadget\n");
802ca850 CP	505	goto err1;
72246da4	506	}
0949e99b FB	507	break;
0949e99b FB	508	default:
802ca850 CP	509	dev_err(dev, "Unsupported mode of operation %d\n", mode);
802ca850 CP	510	goto err1;
72246da4	511	}
0949e99b	512	dwc->mode = mode;
72246da4 FB	513
	514	ret = dwc3_debugfs_init(dwc);
	515	if (ret) {
802ca850 CP	516	dev_err(dev, "failed to initialize debugfs\n");
802ca850 CP	517	goto err2;
72246da4 FB	518	}
72246da4 FB	519
802ca850	520	pm_runtime_allow(dev);
72246da4 FB	521
	522	return 0;
	523
802ca850	524	err2:
0949e99b	525	switch (mode) {
0949e99b	526	case DWC3_MODE_DEVICE:
72246da4	527	dwc3_gadget_exit(dwc);
0949e99b	528	break;
d07e8819 FB	529	case DWC3_MODE_HOST:
	530	dwc3_host_exit(dwc);
	531	break;
	532	case DWC3_MODE_DRD:
	533	dwc3_host_exit(dwc);
72246da4	534	dwc3_gadget_exit(dwc);
d07e8819	535	break;
0949e99b FB	536	default:
	537	/* do nothing */
	538	break;
	539	}
72246da4	540
72246da4	541	err1:
802ca850	542	dwc3_core_exit(dwc);
72246da4	543
3921426b FB	544	err0:
	545	dwc3_free_event_buffers(dwc);
	546
72246da4 FB	547	return ret;
	548	}
	549
fb4e98ab	550	static int dwc3_remove(struct platform_device *pdev)
72246da4	551	{
72246da4 FB	552	struct dwc3 *dwc = platform_get_drvdata(pdev);
72246da4 FB	553	struct resource *res;
72246da4 FB	554
	555	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	556
	557	pm_runtime_put(&pdev->dev);
	558	pm_runtime_disable(&pdev->dev);
	559
	560	dwc3_debugfs_exit(dwc);
	561
0949e99b	562	switch (dwc->mode) {
0949e99b	563	case DWC3_MODE_DEVICE:
72246da4	564	dwc3_gadget_exit(dwc);
0949e99b	565	break;
d07e8819 FB	566	case DWC3_MODE_HOST:
	567	dwc3_host_exit(dwc);
	568	break;
	569	case DWC3_MODE_DRD:
	570	dwc3_host_exit(dwc);
72246da4	571	dwc3_gadget_exit(dwc);
d07e8819	572	break;
0949e99b FB	573	default:
	574	/* do nothing */
	575	break;
	576	}
72246da4 FB	577
72246da4 FB	578	dwc3_core_exit(dwc);
72246da4 FB	579
	580	return 0;
	581	}
	582
72246da4 FB	583	static struct platform_driver dwc3_driver = {
72246da4 FB	584	.probe = dwc3_probe,
7690417d	585	.remove = dwc3_remove,
72246da4 FB	586	.driver = {
	587	.name = "dwc3",
	588	},
72246da4 FB	589	};
72246da4 FB	590
b1116dcc TK	591	module_platform_driver(dwc3_driver);
b1116dcc TK	592
7ae4fc4d	593	MODULE_ALIAS("platform:dwc3");
72246da4 FB	594	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	595	MODULE_LICENSE("Dual BSD/GPL");
	596	MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");