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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[linux-2.6-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
47#ifdef DWC2_LOG_WRITES
48static inline void do_write(u32 value, void *addr)
49{
50 writel(value, addr);
51 pr_info("INFO:: wrote %08x to %p\n", value, addr);
52}
53
54#undef writel
55#define writel(v, a) do_write(v, a)
56#endif
57
58/* Maximum number of Endpoints/HostChannels */
59#define MAX_EPS_CHANNELS 16
60
f7c0b143
DN		 61/* s3c-hsotg declarations */
62static const char * const s3c_hsotg_supply_names[] = {
63 "vusb_d", /* digital USB supply, 1.2V */
64 "vusb_a", /* analog USB supply, 1.1V */
65};
66
67/*
68 * EP0_MPS_LIMIT
69 *
70 * Unfortunately there seems to be a limit of the amount of data that can
71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
72 * packets (which practically means 1 packet and 63 bytes of data) when the
73 * MPS is set to 64.
74 *
75 * This means if we are wanting to move >127 bytes of data, we need to
76 * split the transactions up, but just doing one packet at a time does
77 * not work (this may be an implicit DATA0 PID on first packet of the
78 * transaction) and doing 2 packets is outside the controller's limits.
79 *
80 * If we try to lower the MPS size for EP0, then no transfers work properly
81 * for EP0, and the system will fail basic enumeration. As no cause for this
82 * has currently been found, we cannot support any large IN transfers for
83 * EP0.
84 */
85#define EP0_MPS_LIMIT 64
86
941fcce4 87struct dwc2_hsotg;
f7c0b143
DN		 88struct s3c_hsotg_req;
89
90/**
91 * struct s3c_hsotg_ep - driver endpoint definition.
92 * @ep: The gadget layer representation of the endpoint.
93 * @name: The driver generated name for the endpoint.
94 * @queue: Queue of requests for this endpoint.
95 * @parent: Reference back to the parent device structure.
96 * @req: The current request that the endpoint is processing. This is
97 * used to indicate an request has been loaded onto the endpoint
98 * and has yet to be completed (maybe due to data move, or simply
99 * awaiting an ack from the core all the data has been completed).
100 * @debugfs: File entry for debugfs file for this endpoint.
101 * @lock: State lock to protect contents of endpoint.
102 * @dir_in: Set to true if this endpoint is of the IN direction, which
103 * means that it is sending data to the Host.
104 * @index: The index for the endpoint registers.
105 * @mc: Multi Count - number of transactions per microframe
106 * @interval - Interval for periodic endpoints
107 * @name: The name array passed to the USB core.
108 * @halted: Set if the endpoint has been halted.
109 * @periodic: Set if this is a periodic ep, such as Interrupt
110 * @isochronous: Set if this is a isochronous ep
8a20fa45 111 * @send_zlp: Set if we need to send a zero-length packet.
f7c0b143
DN		 112 * @total_data: The total number of data bytes done.
113 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
115 * @last_load: The offset of data for the last start of request.
116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
117 *
118 * This is the driver's state for each registered enpoint, allowing it
119 * to keep track of transactions that need doing. Each endpoint has a
120 * lock to protect the state, to try and avoid using an overall lock
121 * for the host controller as much as possible.
122 *
123 * For periodic IN endpoints, we have fifo_size and fifo_load to try
124 * and keep track of the amount of data in the periodic FIFO for each
125 * of these as we don't have a status register that tells us how much
126 * is in each of them. (note, this may actually be useless information
127 * as in shared-fifo mode periodic in acts like a single-frame packet
128 * buffer than a fifo)
129 */
130struct s3c_hsotg_ep {
131 struct usb_ep ep;
132 struct list_head queue;
941fcce4 133 struct dwc2_hsotg *parent;
f7c0b143
DN		 134 struct s3c_hsotg_req *req;
135 struct dentry *debugfs;
136
137 unsigned long total_data;
138 unsigned int size_loaded;
139 unsigned int last_load;
140 unsigned int fifo_load;
141 unsigned short fifo_size;
b203d0a2 142 unsigned short fifo_index;
f7c0b143
DN		 143
144 unsigned char dir_in;
145 unsigned char index;
146 unsigned char mc;
147 unsigned char interval;
148
149 unsigned int halted:1;
150 unsigned int periodic:1;
151 unsigned int isochronous:1;
8a20fa45 152 unsigned int send_zlp:1;
f7c0b143
DN		 153
154 char name[10];
155};
156
f7c0b143
DN		 157/**
158 * struct s3c_hsotg_req - data transfer request
159 * @req: The USB gadget request
160 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 161 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143
DN		 162 */
163struct s3c_hsotg_req {
164 struct usb_request req;
165 struct list_head queue;
7d24c1b5 166 void *saved_req_buf;
f7c0b143
DN		 167};
168
941fcce4 169#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 170#define call_gadget(_hs, _entry) \
171do { \
172 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
173 (_hs)->driver && (_hs)->driver->_entry) { \
174 spin_unlock(&_hs->lock); \
175 (_hs)->driver->_entry(&(_hs)->gadget); \
176 spin_lock(&_hs->lock); \
177 } \
178} while (0)
941fcce4
DN		 179#else
180#define call_gadget(_hs, _entry) do {} while (0)
181#endif
f7c0b143 182
56f5b1cf
PZ		 183struct dwc2_hsotg;
184struct dwc2_host_chan;
185
186/* Device States */
187enum dwc2_lx_state {
188 DWC2_L0, /* On state */
189 DWC2_L1, /* LPM sleep state */
190 DWC2_L2, /* USB suspend state */
191 DWC2_L3, /* Off state */
192};
193
0a176279
GH		 194/*
195 * Gadget periodic tx fifo sizes as used by legacy driver
196 * EP0 is not included
197 */
198#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
199 768, 0, 0, 0, 0, 0, 0, 0}
200
fe0b94ab
MYK		 201/* Gadget ep0 states */
202enum dwc2_ep0_state {
203 DWC2_EP0_SETUP,
204 DWC2_EP0_DATA_IN,
205 DWC2_EP0_DATA_OUT,
206 DWC2_EP0_STATUS_IN,
207 DWC2_EP0_STATUS_OUT,
208};
209
56f5b1cf
PZ		 210/**
211 * struct dwc2_core_params - Parameters for configuring the core
212 *
91121c10
MK		 213 * @otg_cap: Specifies the OTG capabilities.
214 * 0 - HNP and SRP capable
56f5b1cf 215 * 1 - SRP Only capable
91121c10
MK		 216 * 2 - No HNP/SRP capable (always available)
217 * Defaults to best available option (0, 1, then 2)
725acc86 218 * @otg_ver: OTG version supported
91121c10 219 * 0 - 1.3 (default)
725acc86 220 * 1 - 2.0
56f5b1cf
PZ		 221 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
222 * the data FIFOs. The driver will automatically detect the
223 * value for this parameter if none is specified.
91121c10 224 * 0 - Slave (always available)
56f5b1cf
PZ		 225 * 1 - DMA (default, if available)
226 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
227 * address DMA mode or descriptor DMA mode for accessing
228 * the data FIFOs. The driver will automatically detect the
229 * value for this if none is specified.
230 * 0 - Address DMA
231 * 1 - Descriptor DMA (default, if available)
232 * @speed: Specifies the maximum speed of operation in host and
233 * device mode. The actual speed depends on the speed of
234 * the attached device and the value of phy_type.
91121c10
MK		 235 * 0 - High Speed
236 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 237 * 1 - Full Speed
91121c10 238 * (default when phy_type is Full Speed)
56f5b1cf 239 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 240 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86
PZ		 241 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
242 * are enabled
56f5b1cf
PZ		 243 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
244 * dynamic FIFO sizing is enabled
91121c10
MK		 245 * 16 to 32768
246 * Actual maximum value is autodetected and also
247 * the default.
56f5b1cf
PZ		 248 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
249 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 250 * 16 to 32768
251 * Actual maximum value is autodetected and also
252 * the default.
56f5b1cf
PZ		 253 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
254 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 255 * 16 to 32768
256 * Actual maximum value is autodetected and also
257 * the default.
56f5b1cf 258 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 259 * 2047 to 65,535
260 * Actual maximum value is autodetected and also
261 * the default.
56f5b1cf 262 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 263 * 15 to 511
264 * Actual maximum value is autodetected and also
265 * the default.
56f5b1cf 266 * @host_channels: The number of host channel registers to use
91121c10
MK		 267 * 1 to 16
268 * Actual maximum value is autodetected and also
269 * the default.
56f5b1cf
PZ		 270 * @phy_type: Specifies the type of PHY interface to use. By default,
271 * the driver will automatically detect the phy_type.
91121c10
MK		 272 * 0 - Full Speed Phy
273 * 1 - UTMI+ Phy
274 * 2 - ULPI Phy
275 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 276 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
277 * is applicable for a phy_type of UTMI+ or ULPI. (For a
278 * ULPI phy_type, this parameter indicates the data width
279 * between the MAC and the ULPI Wrapper.) Also, this
280 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
281 * parameter was set to "8 and 16 bits", meaning that the
282 * core has been configured to work at either data path
283 * width.
91121c10 284 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 285 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
286 * data rate. This parameter is only applicable if phy_type
287 * is ULPI.
288 * 0 - single data rate ULPI interface with 8 bit wide
289 * data bus (default)
290 * 1 - double data rate ULPI interface with 4 bit wide
291 * data bus
292 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
293 * external supply to drive the VBus
91121c10
MK		 294 * 0 - Internal supply (default)
295 * 1 - External supply
56f5b1cf
PZ		 296 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
297 * speed PHY. This parameter is only applicable if phy_type
298 * is FS.
299 * 0 - No (default)
300 * 1 - Yes
91121c10
MK		 301 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
302 * 0 - No (default)
303 * 1 - Yes
725acc86
PZ		 304 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
305 * when attached to a Full Speed or Low Speed device in
306 * host mode.
307 * 0 - Don't support low power mode (default)
308 * 1 - Support low power mode
309 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 310 * when connected to a Low Speed device in host
311 * mode. This parameter is applicable only if
312 * host_support_fs_ls_low_power is enabled.
725acc86 313 * 0 - 48 MHz
91121c10 314 * (default when phy_type is UTMI+ or ULPI)
725acc86 315 * 1 - 6 MHz
91121c10
MK		 316 * (default when phy_type is Full Speed)
317 * @ts_dline: Enable Term Select Dline pulsing
318 * 0 - No (default)
319 * 1 - Yes
320 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
321 * 0 - No (default for core < 2.92a)
322 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 323 * @ahbcfg: This field allows the default value of the GAHBCFG
324 * register to be overridden
91121c10
MK		 325 * -1 - GAHBCFG value will be set to 0x06
326 * (INCR4, default)
4d3190e1
PZ		 327 * all others - GAHBCFG value will be overridden with
328 * this value
91121c10
MK		 329 * Not all bits can be controlled like this, the
330 * bits defined by GAHBCFG_CTRL_MASK are controlled
331 * by the driver and are ignored in this
332 * configuration value.
20f2eb9c 333 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 334 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
335 * Disable CONIDSTSCHNG controller interrupt in such
336 * case.
337 * 0 - No (default)
338 * 1 - Yes
285046aa
GH		 339 * @hibernation: Specifies whether the controller support hibernation.
340 * If hibernation is enabled, the controller will enter
341 * hibernation in both peripheral and host mode when
342 * needed.
343 * 0 - No (default)
344 * 1 - Yes
56f5b1cf
PZ		 345 *
346 * The following parameters may be specified when starting the module. These
91121c10
MK		 347 * parameters define how the DWC_otg controller should be configured. A
348 * value of -1 (or any other out of range value) for any parameter means
349 * to read the value from hardware (if possible) or use the builtin
350 * default described above.
56f5b1cf
PZ		 351 */
352struct dwc2_core_params {
8284f93b
MK		 353 /*
354 * Don't add any non-int members here, this will break
355 * dwc2_set_all_params!
356 */
56f5b1cf
PZ		 357 int otg_cap;
358 int otg_ver;
359 int dma_enable;
360 int dma_desc_enable;
361 int speed;
362 int enable_dynamic_fifo;
363 int en_multiple_tx_fifo;
364 int host_rx_fifo_size;
365 int host_nperio_tx_fifo_size;
366 int host_perio_tx_fifo_size;
367 int max_transfer_size;
368 int max_packet_count;
369 int host_channels;
370 int phy_type;
371 int phy_utmi_width;
372 int phy_ulpi_ddr;
373 int phy_ulpi_ext_vbus;
374 int i2c_enable;
375 int ulpi_fs_ls;
376 int host_support_fs_ls_low_power;
377 int host_ls_low_power_phy_clk;
378 int ts_dline;
379 int reload_ctl;
4d3190e1 380 int ahbcfg;
20f2eb9c 381 int uframe_sched;
a6d249d8 382 int external_id_pin_ctl;
285046aa 383 int hibernation;
56f5b1cf
PZ		 384};
385
9badec2f
MK		 386/**
387 * struct dwc2_hw_params - Autodetected parameters.
388 *
389 * These parameters are the various parameters read from hardware
390 * registers during initialization. They typically contain the best
391 * supported or maximum value that can be configured in the
392 * corresponding dwc2_core_params value.
393 *
394 * The values that are not in dwc2_core_params are documented below.
395 *
396 * @op_mode Mode of Operation
397 * 0 - HNP- and SRP-Capable OTG (Host & Device)
398 * 1 - SRP-Capable OTG (Host & Device)
399 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
400 * 3 - SRP-Capable Device
401 * 4 - Non-OTG Device
402 * 5 - SRP-Capable Host
403 * 6 - Non-OTG Host
404 * @arch Architecture
405 * 0 - Slave only
406 * 1 - External DMA
407 * 2 - Internal DMA
408 * @power_optimized Are power optimizations enabled?
409 * @num_dev_ep Number of device endpoints available
410 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 411 * available
9badec2f
MK		 412 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
413 * Depth
414 * 0 to 30
415 * @host_perio_tx_q_depth
416 * Host Mode Periodic Request Queue Depth
417 * 2, 4 or 8
418 * @nperio_tx_q_depth
419 * Non-Periodic Request Queue Depth
420 * 2, 4 or 8
421 * @hs_phy_type High-speed PHY interface type
422 * 0 - High-speed interface not supported
423 * 1 - UTMI+
424 * 2 - ULPI
425 * 3 - UTMI+ and ULPI
426 * @fs_phy_type Full-speed PHY interface type
427 * 0 - Full speed interface not supported
428 * 1 - Dedicated full speed interface
429 * 2 - FS pins shared with UTMI+ pins
430 * 3 - FS pins shared with ULPI pins
431 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 432 * @utmi_phy_data_width UTMI+ PHY data width
433 * 0 - 8 bits
434 * 1 - 16 bits
435 * 2 - 8 or 16 bits
9badec2f
MK		 436 * @snpsid: Value from SNPSID register
437 */
438struct dwc2_hw_params {
439 unsigned op_mode:3;
440 unsigned arch:2;
441 unsigned dma_desc_enable:1;
442 unsigned enable_dynamic_fifo:1;
443 unsigned en_multiple_tx_fifo:1;
444 unsigned host_rx_fifo_size:16;
445 unsigned host_nperio_tx_fifo_size:16;
446 unsigned host_perio_tx_fifo_size:16;
447 unsigned nperio_tx_q_depth:3;
448 unsigned host_perio_tx_q_depth:3;
449 unsigned dev_token_q_depth:5;
450 unsigned max_transfer_size:26;
451 unsigned max_packet_count:11;
2d115547 452 unsigned host_channels:5;
9badec2f
MK		 453 unsigned hs_phy_type:2;
454 unsigned fs_phy_type:2;
455 unsigned i2c_enable:1;
456 unsigned num_dev_ep:4;
457 unsigned num_dev_perio_in_ep:4;
458 unsigned total_fifo_size:16;
459 unsigned power_optimized:1;
de4a1931 460 unsigned utmi_phy_data_width:2;
9badec2f
MK		 461 u32 snpsid;
462};
463
3f95001d
MYK		 464/* Size of control and EP0 buffers */
465#define DWC2_CTRL_BUFF_SIZE 8
466
d17ee77b
GH		 467/**
468 * struct dwc2_gregs_backup - Holds global registers state before entering partial
469 * power down
470 * @gotgctl: Backup of GOTGCTL register
471 * @gintmsk: Backup of GINTMSK register
472 * @gahbcfg: Backup of GAHBCFG register
473 * @gusbcfg: Backup of GUSBCFG register
474 * @grxfsiz: Backup of GRXFSIZ register
475 * @gnptxfsiz: Backup of GNPTXFSIZ register
476 * @gi2cctl: Backup of GI2CCTL register
477 * @hptxfsiz: Backup of HPTXFSIZ register
478 * @gdfifocfg: Backup of GDFIFOCFG register
479 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
480 * @gpwrdn: Backup of GPWRDN register
481 */
482struct dwc2_gregs_backup {
483 u32 gotgctl;
484 u32 gintmsk;
485 u32 gahbcfg;
486 u32 gusbcfg;
487 u32 grxfsiz;
488 u32 gnptxfsiz;
489 u32 gi2cctl;
490 u32 hptxfsiz;
491 u32 pcgcctl;
492 u32 gdfifocfg;
493 u32 dtxfsiz[MAX_EPS_CHANNELS];
494 u32 gpwrdn;
cc1e204c 495 bool valid;
d17ee77b
GH		 496};
497
498/**
499 * struct dwc2_dregs_backup - Holds device registers state before entering partial
500 * power down
501 * @dcfg: Backup of DCFG register
502 * @dctl: Backup of DCTL register
503 * @daintmsk: Backup of DAINTMSK register
504 * @diepmsk: Backup of DIEPMSK register
505 * @doepmsk: Backup of DOEPMSK register
506 * @diepctl: Backup of DIEPCTL register
507 * @dieptsiz: Backup of DIEPTSIZ register
508 * @diepdma: Backup of DIEPDMA register
509 * @doepctl: Backup of DOEPCTL register
510 * @doeptsiz: Backup of DOEPTSIZ register
511 * @doepdma: Backup of DOEPDMA register
512 */
513struct dwc2_dregs_backup {
514 u32 dcfg;
515 u32 dctl;
516 u32 daintmsk;
517 u32 diepmsk;
518 u32 doepmsk;
519 u32 diepctl[MAX_EPS_CHANNELS];
520 u32 dieptsiz[MAX_EPS_CHANNELS];
521 u32 diepdma[MAX_EPS_CHANNELS];
522 u32 doepctl[MAX_EPS_CHANNELS];
523 u32 doeptsiz[MAX_EPS_CHANNELS];
524 u32 doepdma[MAX_EPS_CHANNELS];
cc1e204c 525 bool valid;
d17ee77b
GH		 526};
527
528/**
529 * struct dwc2_hregs_backup - Holds host registers state before entering partial
530 * power down
531 * @hcfg: Backup of HCFG register
532 * @haintmsk: Backup of HAINTMSK register
533 * @hcintmsk: Backup of HCINTMSK register
534 * @hptr0: Backup of HPTR0 register
535 * @hfir: Backup of HFIR register
536 */
537struct dwc2_hregs_backup {
538 u32 hcfg;
539 u32 haintmsk;
540 u32 hcintmsk[MAX_EPS_CHANNELS];
541 u32 hprt0;
542 u32 hfir;
cc1e204c 543 bool valid;
d17ee77b
GH		 544};
545
56f5b1cf
PZ		 546/**
547 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
548 * and periodic schedules
549 *
941fcce4
DN		 550 * These are common for both host and peripheral modes:
551 *
56f5b1cf
PZ		 552 * @dev: The struct device pointer
553 * @regs: Pointer to controller regs
9badec2f
MK		 554 * @hw_params: Parameters that were autodetected from the
555 * hardware registers
941fcce4 556 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 557 * @op_state: The operational State, during transitions (a_host=>
558 * a_peripheral and b_device=>b_host) this may not match
559 * the core, but allows the software to determine
560 * transitions
c0155b9d
KY		 561 * @dr_mode: Requested mode of operation, one of following:
562 * - USB_DR_MODE_PERIPHERAL
563 * - USB_DR_MODE_HOST
564 * - USB_DR_MODE_OTG
941fcce4
DN		 565 * @lock: Spinlock that protects all the driver data structures
566 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 567 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
568 * transfer are in process of being queued
569 * @srp_success: Stores status of SRP request in the case of a FS PHY
570 * with an I2C interface
571 * @wq_otg: Workqueue object used for handling of some interrupts
572 * @wf_otg: Work object for handling Connector ID Status Change
573 * interrupt
574 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
575 * @lx_state: Lx state of connected device
d17ee77b
GH		 576 * @gregs_backup: Backup of global registers during suspend
577 * @dregs_backup: Backup of device registers during suspend
578 * @hregs_backup: Backup of host registers during suspend
941fcce4
DN		 579 *
580 * These are for host mode:
581 *
56f5b1cf
PZ		 582 * @flags: Flags for handling root port state changes
583 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
584 * Transfers associated with these QHs are not currently
585 * assigned to a host channel.
586 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
587 * Transfers associated with these QHs are currently
588 * assigned to a host channel.
589 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
590 * non-periodic schedule
591 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
592 * list of QHs for periodic transfers that are _not_
593 * scheduled for the next frame. Each QH in the list has an
594 * interval counter that determines when it needs to be
595 * scheduled for execution. This scheduling mechanism
596 * allows only a simple calculation for periodic bandwidth
597 * used (i.e. must assume that all periodic transfers may
598 * need to execute in the same frame). However, it greatly
599 * simplifies scheduling and should be sufficient for the
600 * vast majority of OTG hosts, which need to connect to a
601 * small number of peripherals at one time. Items move from
602 * this list to periodic_sched_ready when the QH interval
603 * counter is 0 at SOF.
604 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
605 * the next frame, but have not yet been assigned to host
606 * channels. Items move from this list to
607 * periodic_sched_assigned as host channels become
608 * available during the current frame.
609 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
610 * frame that are assigned to host channels. Items move
611 * from this list to periodic_sched_queued as the
612 * transactions for the QH are queued to the DWC_otg
613 * controller.
614 * @periodic_sched_queued: List of periodic QHs that have been queued for
615 * execution. Items move from this list to either
616 * periodic_sched_inactive or periodic_sched_ready when the
617 * channel associated with the transfer is released. If the
618 * interval for the QH is 1, the item moves to
619 * periodic_sched_ready because it must be rescheduled for
620 * the next frame. Otherwise, the item moves to
621 * periodic_sched_inactive.
622 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
623 * This value is in microseconds per (micro)frame. The
624 * assumption is that all periodic transfers may occur in
625 * the same (micro)frame.
20f2eb9c 626 * @frame_usecs: Internal variable used by the microframe scheduler
56f5b1cf
PZ		 627 * @frame_number: Frame number read from the core at SOF. The value ranges
628 * from 0 to HFNUM_MAX_FRNUM.
629 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
630 * SOF enable/disable.
631 * @free_hc_list: Free host channels in the controller. This is a list of
632 * struct dwc2_host_chan items.
633 * @periodic_channels: Number of host channels assigned to periodic transfers.
634 * Currently assuming that there is a dedicated host
635 * channel for each periodic transaction and at least one
636 * host channel is available for non-periodic transactions.
637 * @non_periodic_channels: Number of host channels assigned to non-periodic
638 * transfers
20f2eb9c
DC		 639 * @available_host_channels Number of host channels available for the microframe
640 * scheduler to use
56f5b1cf
PZ		 641 * @hc_ptr_array: Array of pointers to the host channel descriptors.
642 * Allows accessing a host channel descriptor given the
643 * host channel number. This is useful in interrupt
644 * handlers.
645 * @status_buf: Buffer used for data received during the status phase of
646 * a control transfer.
647 * @status_buf_dma: DMA address for status_buf
648 * @start_work: Delayed work for handling host A-cable connection
649 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 650 * @otg_port: OTG port number
651 * @frame_list: Frame list
652 * @frame_list_dma: Frame list DMA address
941fcce4
DN		 653 *
654 * These are for peripheral mode:
655 *
656 * @driver: USB gadget driver
657 * @phy: The otg phy transceiver structure for phy control.
658 * @uphy: The otg phy transceiver structure for old USB phy control.
659 * @plat: The platform specific configuration data. This can be removed once
660 * all SoCs support usb transceiver.
661 * @supplies: Definition of USB power supplies
662 * @phyif: PHY interface width
663 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
664 * @num_of_eps: Number of available EPs (excluding EP0)
665 * @debug_root: Root directrory for debugfs.
666 * @debug_file: Main status file for debugfs.
9e14d0a5 667 * @debug_testmode: Testmode status file for debugfs.
941fcce4
DN		 668 * @debug_fifo: FIFO status file for debugfs.
669 * @ep0_reply: Request used for ep0 reply.
670 * @ep0_buff: Buffer for EP0 reply data, if needed.
671 * @ctrl_buff: Buffer for EP0 control requests.
672 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 673 * @ep0_state: EP0 control transfers state
9e14d0a5 674 * @test_mode: USB test mode requested by the host
941fcce4
DN		 675 * @last_rst: Time of last reset
676 * @eps: The endpoints being supplied to the gadget framework
edd74be8 677 * @g_using_dma: Indicate if dma usage is enabled
0a176279
GH		 678 * @g_rx_fifo_sz: Contains rx fifo size value
679 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
680 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
56f5b1cf
PZ		 681 */
682struct dwc2_hsotg {
683 struct device *dev;
684 void __iomem *regs;
9badec2f
MK		 685 /** Params detected from hardware */
686 struct dwc2_hw_params hw_params;
687 /** Params to actually use */
56f5b1cf 688 struct dwc2_core_params *core_params;
56f5b1cf 689 enum usb_otg_state op_state;
c0155b9d 690 enum usb_dr_mode dr_mode;
e39af88f
MS		 691 unsigned int hcd_enabled:1;
692 unsigned int gadget_enabled:1;
56f5b1cf 693
941fcce4
DN		 694 struct phy *phy;
695 struct usb_phy *uphy;
696 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
697
698 spinlock_t lock;
7ad8096e 699 struct mutex init_mutex;
941fcce4
DN		 700 void *priv;
701 int irq;
702 struct clk *clk;
703
56f5b1cf
PZ		 704 unsigned int queuing_high_bandwidth:1;
705 unsigned int srp_success:1;
706
707 struct workqueue_struct *wq_otg;
708 struct work_struct wf_otg;
709 struct timer_list wkp_timer;
710 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 711 struct dwc2_gregs_backup gr_backup;
712 struct dwc2_dregs_backup dr_backup;
713 struct dwc2_hregs_backup hr_backup;
56f5b1cf 714
941fcce4 715 struct dentry *debug_root;
563cf017 716 struct debugfs_regset32 *regset;
941fcce4
DN		 717
718 /* DWC OTG HW Release versions */
719#define DWC2_CORE_REV_2_71a 0x4f54271a
720#define DWC2_CORE_REV_2_90a 0x4f54290a
721#define DWC2_CORE_REV_2_92a 0x4f54292a
722#define DWC2_CORE_REV_2_94a 0x4f54294a
723#define DWC2_CORE_REV_3_00a 0x4f54300a
724
725#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 726 union dwc2_hcd_internal_flags {
727 u32 d32;
728 struct {
729 unsigned port_connect_status_change:1;
730 unsigned port_connect_status:1;
731 unsigned port_reset_change:1;
732 unsigned port_enable_change:1;
733 unsigned port_suspend_change:1;
734 unsigned port_over_current_change:1;
735 unsigned port_l1_change:1;
fd4850cf 736 unsigned reserved:25;
56f5b1cf
PZ		 737 } b;
738 } flags;
739
740 struct list_head non_periodic_sched_inactive;
741 struct list_head non_periodic_sched_active;
742 struct list_head *non_periodic_qh_ptr;
743 struct list_head periodic_sched_inactive;
744 struct list_head periodic_sched_ready;
745 struct list_head periodic_sched_assigned;
746 struct list_head periodic_sched_queued;
747 u16 periodic_usecs;
20f2eb9c 748 u16 frame_usecs[8];
56f5b1cf
PZ		 749 u16 frame_number;
750 u16 periodic_qh_count;
751
752#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
753#define FRAME_NUM_ARRAY_SIZE 1000
754 u16 last_frame_num;
755 u16 *frame_num_array;
756 u16 *last_frame_num_array;
757 int frame_num_idx;
758 int dumped_frame_num_array;
759#endif
760
761 struct list_head free_hc_list;
762 int periodic_channels;
763 int non_periodic_channels;
20f2eb9c 764 int available_host_channels;
56f5b1cf
PZ		 765 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
766 u8 *status_buf;
767 dma_addr_t status_buf_dma;
768#define DWC2_HCD_STATUS_BUF_SIZE 64
769
770 struct delayed_work start_work;
771 struct delayed_work reset_work;
56f5b1cf
PZ		 772 u8 otg_port;
773 u32 *frame_list;
774 dma_addr_t frame_list_dma;
775
56f5b1cf
PZ		 776#ifdef DEBUG
777 u32 frrem_samples;
778 u64 frrem_accum;
779
780 u32 hfnum_7_samples_a;
781 u64 hfnum_7_frrem_accum_a;
782 u32 hfnum_0_samples_a;
783 u64 hfnum_0_frrem_accum_a;
784 u32 hfnum_other_samples_a;
785 u64 hfnum_other_frrem_accum_a;
786
787 u32 hfnum_7_samples_b;
788 u64 hfnum_7_frrem_accum_b;
789 u32 hfnum_0_samples_b;
790 u64 hfnum_0_frrem_accum_b;
791 u32 hfnum_other_samples_b;
792 u64 hfnum_other_frrem_accum_b;
793#endif
941fcce4
DN		 794#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
795
796#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
797 /* Gadget structures */
798 struct usb_gadget_driver *driver;
799 struct s3c_hsotg_plat *plat;
800
801 u32 phyif;
802 int fifo_mem;
803 unsigned int dedicated_fifos:1;
804 unsigned char num_of_eps;
805 u32 fifo_map;
806
807 struct usb_request *ep0_reply;
808 struct usb_request *ctrl_req;
3f95001d
MYK		 809 void *ep0_buff;
810 void *ctrl_buff;
fe0b94ab 811 enum dwc2_ep0_state ep0_state;
9e14d0a5 812 u8 test_mode;
941fcce4
DN		 813
814 struct usb_gadget gadget;
dc6e69e6 815 unsigned int enabled:1;
4ace06e8 816 unsigned int connected:1;
941fcce4 817 unsigned long last_rst;
c6f5c050
MYK		 818 struct s3c_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
819 struct s3c_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
edd74be8 820 u32 g_using_dma;
0a176279
GH		 821 u32 g_rx_fifo_sz;
822 u32 g_np_g_tx_fifo_sz;
823 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
941fcce4 824#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 825};
826
827/* Reasons for halting a host channel */
828enum dwc2_halt_status {
829 DWC2_HC_XFER_NO_HALT_STATUS,
830 DWC2_HC_XFER_COMPLETE,
831 DWC2_HC_XFER_URB_COMPLETE,
832 DWC2_HC_XFER_ACK,
833 DWC2_HC_XFER_NAK,
834 DWC2_HC_XFER_NYET,
835 DWC2_HC_XFER_STALL,
836 DWC2_HC_XFER_XACT_ERR,
837 DWC2_HC_XFER_FRAME_OVERRUN,
838 DWC2_HC_XFER_BABBLE_ERR,
839 DWC2_HC_XFER_DATA_TOGGLE_ERR,
840 DWC2_HC_XFER_AHB_ERR,
841 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
842 DWC2_HC_XFER_URB_DEQUEUE,
843};
844
845/*
846 * The following functions support initialization of the core driver component
847 * and the DWC_otg controller
848 */
849extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
d17ee77b
GH		 850extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
851extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
56f5b1cf
PZ		 852
853/*
854 * Host core Functions.
855 * The following functions support managing the DWC_otg controller in host
856 * mode.
857 */
858extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
859extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
860 enum dwc2_halt_status halt_status);
861extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
862 struct dwc2_host_chan *chan);
863extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
864 struct dwc2_host_chan *chan);
865extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
866 struct dwc2_host_chan *chan);
867extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
868 struct dwc2_host_chan *chan);
869extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
870 struct dwc2_host_chan *chan);
871extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
872extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
873
874extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
057715f2 875extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 876
877/*
878 * Common core Functions.
879 * The following functions support managing the DWC_otg controller in either
880 * device or host mode.
881 */
882extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
883extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
884extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
885
6706c721 886extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq);
56f5b1cf
PZ		 887extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
888extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
889
890/* This function should be called on every hardware interrupt. */
891extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
892
893/* OTG Core Parameters */
894
895/*
896 * Specifies the OTG capabilities. The driver will automatically
897 * detect the value for this parameter if none is specified.
898 * 0 - HNP and SRP capable (default)
899 * 1 - SRP Only capable
900 * 2 - No HNP/SRP capable
901 */
7218dae7 902extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 903#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
904#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
905#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
906
907/*
908 * Specifies whether to use slave or DMA mode for accessing the data
909 * FIFOs. The driver will automatically detect the value for this
910 * parameter if none is specified.
911 * 0 - Slave
912 * 1 - DMA (default, if available)
913 */
7218dae7 914extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 915
916/*
917 * When DMA mode is enabled specifies whether to use
918 * address DMA or DMA Descritor mode for accessing the data
919 * FIFOs in device mode. The driver will automatically detect
920 * the value for this parameter if none is specified.
921 * 0 - address DMA
922 * 1 - DMA Descriptor(default, if available)
923 */
7218dae7 924extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 925
926/*
927 * Specifies the maximum speed of operation in host and device mode.
928 * The actual speed depends on the speed of the attached device and
929 * the value of phy_type. The actual speed depends on the speed of the
930 * attached device.
931 * 0 - High Speed (default)
932 * 1 - Full Speed
933 */
7218dae7 934extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 935#define DWC2_SPEED_PARAM_HIGH 0
936#define DWC2_SPEED_PARAM_FULL 1
937
938/*
939 * Specifies whether low power mode is supported when attached
940 * to a Full Speed or Low Speed device in host mode.
941 *
942 * 0 - Don't support low power mode (default)
943 * 1 - Support low power mode
944 */
7218dae7
PZ		 945extern void dwc2_set_param_host_support_fs_ls_low_power(
946 struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 947
948/*
949 * Specifies the PHY clock rate in low power mode when connected to a
950 * Low Speed device in host mode. This parameter is applicable only if
951 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
952 * then defaults to 6 MHZ otherwise 48 MHZ.
953 *
954 * 0 - 48 MHz
955 * 1 - 6 MHz
956 */
7218dae7
PZ		 957extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
958 int val);
56f5b1cf
PZ		 959#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
960#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
961
962/*
963 * 0 - Use cC FIFO size parameters
964 * 1 - Allow dynamic FIFO sizing (default)
965 */
7218dae7
PZ		 966extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
967 int val);
56f5b1cf
PZ		 968
969/*
970 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
971 * FIFO sizing is enabled.
972 * 16 to 32768 (default 1024)
973 */
7218dae7 974extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 975
976/*
977 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
978 * when Dynamic FIFO sizing is enabled in the core.
979 * 16 to 32768 (default 256)
980 */
7218dae7
PZ		 981extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
982 int val);
56f5b1cf
PZ		 983
984/*
985 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
986 * FIFO sizing is enabled.
987 * 16 to 32768 (default 256)
988 */
7218dae7
PZ		 989extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
990 int val);
56f5b1cf
PZ		 991
992/*
993 * The maximum transfer size supported in bytes.
994 * 2047 to 65,535 (default 65,535)
995 */
7218dae7 996extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 997
998/*
999 * The maximum number of packets in a transfer.
1000 * 15 to 511 (default 511)
1001 */
7218dae7 1002extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1003
1004/*
1005 * The number of host channel registers to use.
1006 * 1 to 16 (default 11)
1007 * Note: The FPGA configuration supports a maximum of 11 host channels.
1008 */
7218dae7 1009extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1010
1011/*
1012 * Specifies the type of PHY interface to use. By default, the driver
1013 * will automatically detect the phy_type.
1014 *
1015 * 0 - Full Speed PHY
1016 * 1 - UTMI+ (default)
1017 * 2 - ULPI
1018 */
7218dae7 1019extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1020#define DWC2_PHY_TYPE_PARAM_FS 0
1021#define DWC2_PHY_TYPE_PARAM_UTMI 1
1022#define DWC2_PHY_TYPE_PARAM_ULPI 2
1023
1024/*
1025 * Specifies the UTMI+ Data Width. This parameter is
1026 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
1027 * PHY_TYPE, this parameter indicates the data width between
1028 * the MAC and the ULPI Wrapper.) Also, this parameter is
1029 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
1030 * to "8 and 16 bits", meaning that the core has been
1031 * configured to work at either data path width.
1032 *
1033 * 8 or 16 bits (default 16)
1034 */
7218dae7 1035extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1036
1037/*
1038 * Specifies whether the ULPI operates at double or single
1039 * data rate. This parameter is only applicable if PHY_TYPE is
1040 * ULPI.
1041 *
1042 * 0 - single data rate ULPI interface with 8 bit wide data
1043 * bus (default)
1044 * 1 - double data rate ULPI interface with 4 bit wide data
1045 * bus
1046 */
7218dae7 1047extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1048
1049/*
1050 * Specifies whether to use the internal or external supply to
1051 * drive the vbus with a ULPI phy.
1052 */
7218dae7 1053extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1054#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
1055#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
1056
1057/*
1058 * Specifies whether to use the I2Cinterface for full speed PHY. This
1059 * parameter is only applicable if PHY_TYPE is FS.
1060 * 0 - No (default)
1061 * 1 - Yes
1062 */
7218dae7 1063extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1064
7218dae7 1065extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1066
7218dae7 1067extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1068
1069/*
1070 * Specifies whether dedicated transmit FIFOs are
1071 * enabled for non periodic IN endpoints in device mode
1072 * 0 - No
1073 * 1 - Yes
1074 */
7218dae7
PZ		 1075extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
1076 int val);
56f5b1cf 1077
7218dae7 1078extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1079
7218dae7 1080extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1081
7218dae7 1082extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1083
ecb176c6
MYK		 1084extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1085 const struct dwc2_core_params *params);
1086
1087extern void dwc2_set_all_params(struct dwc2_core_params *params, int value);
1088
1089extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1090
1091
1092
56f5b1cf
PZ		 1093/*
1094 * Dump core registers and SPRAM
1095 */
1096extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1097extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1098extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1099
1100/*
1101 * Return OTG version - either 1.3 or 2.0
1102 */
1103extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1104
117777b2
DN		 1105/* Gadget defines */
1106#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1107extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg);
1108extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2);
1109extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2);
1110extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
643cc4de
GH		 1111extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1112 bool reset);
510ffaa4 1113extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg);
4ace06e8 1114extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2);
f91eea44 1115extern int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1116#define dwc2_is_device_connected(hsotg) (hsotg->connected)
117777b2
DN		 1117#else
1118static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2)
1119{ return 0; }
1120static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2)
1121{ return 0; }
1122static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2)
1123{ return 0; }
1124static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1125{ return 0; }
643cc4de
GH		 1126static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1127 bool reset) {}
510ffaa4 1128static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
4ace06e8 1129static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
f91eea44
MYK		 1130static inline int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1131 int testmode)
1132{ return 0; }
f81f46e1 1133#define dwc2_is_device_connected(hsotg) (0)
117777b2
DN		 1134#endif
1135
1136#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1137extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1138extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg);
1139extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1140#else
117777b2
DN		 1141static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1142{ return 0; }
1143static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {}
1144static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1145static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
ecb176c6 1146static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
117777b2
DN		 1147{ return 0; }
1148#endif
1149
56f5b1cf 1150#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)