Commit | Line | Data |
---|---|---|
57677be5 LJ |
1 | /* |
2 | * otg_fsm.c - ChipIdea USB IP core OTG FSM driver | |
3 | * | |
4 | * Copyright (C) 2014 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Author: Jun Li | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file mainly handles OTG fsm, it includes OTG fsm operations | |
15 | * for HNP and SRP. | |
4dcf720c LJ |
16 | * |
17 | * TODO List | |
18 | * - ADP | |
19 | * - OTG test device | |
57677be5 LJ |
20 | */ |
21 | ||
22 | #include <linux/usb/otg.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | #include <linux/usb/hcd.h> | |
25 | #include <linux/usb/chipidea.h> | |
826cfe75 | 26 | #include <linux/regulator/consumer.h> |
57677be5 LJ |
27 | |
28 | #include "ci.h" | |
29 | #include "bits.h" | |
30 | #include "otg.h" | |
31 | #include "otg_fsm.h" | |
32 | ||
e287b67b LJ |
33 | static struct ci_otg_fsm_timer *otg_timer_initializer |
34 | (struct ci_hdrc *ci, void (*function)(void *, unsigned long), | |
35 | unsigned long expires, unsigned long data) | |
36 | { | |
37 | struct ci_otg_fsm_timer *timer; | |
38 | ||
39 | timer = devm_kzalloc(ci->dev, sizeof(struct ci_otg_fsm_timer), | |
40 | GFP_KERNEL); | |
41 | if (!timer) | |
42 | return NULL; | |
43 | timer->function = function; | |
44 | timer->expires = expires; | |
45 | timer->data = data; | |
46 | return timer; | |
47 | } | |
48 | ||
15f75def LJ |
49 | /* Add for otg: interact with user space app */ |
50 | static ssize_t | |
51 | get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf) | |
52 | { | |
53 | char *next; | |
54 | unsigned size, t; | |
55 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
56 | ||
57 | next = buf; | |
58 | size = PAGE_SIZE; | |
59 | t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_req); | |
60 | size -= t; | |
61 | next += t; | |
62 | ||
63 | return PAGE_SIZE - size; | |
64 | } | |
65 | ||
66 | static ssize_t | |
67 | set_a_bus_req(struct device *dev, struct device_attribute *attr, | |
68 | const char *buf, size_t count) | |
69 | { | |
70 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
71 | ||
72 | if (count > 2) | |
73 | return -1; | |
74 | ||
75 | mutex_lock(&ci->fsm.lock); | |
76 | if (buf[0] == '0') { | |
77 | ci->fsm.a_bus_req = 0; | |
78 | } else if (buf[0] == '1') { | |
79 | /* If a_bus_drop is TRUE, a_bus_req can't be set */ | |
80 | if (ci->fsm.a_bus_drop) { | |
81 | mutex_unlock(&ci->fsm.lock); | |
82 | return count; | |
83 | } | |
84 | ci->fsm.a_bus_req = 1; | |
85 | } | |
86 | ||
be6b0c1b | 87 | ci_otg_queue_work(ci); |
15f75def LJ |
88 | mutex_unlock(&ci->fsm.lock); |
89 | ||
90 | return count; | |
91 | } | |
92 | static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req, set_a_bus_req); | |
93 | ||
94 | static ssize_t | |
95 | get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf) | |
96 | { | |
97 | char *next; | |
98 | unsigned size, t; | |
99 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
100 | ||
101 | next = buf; | |
102 | size = PAGE_SIZE; | |
103 | t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_drop); | |
104 | size -= t; | |
105 | next += t; | |
106 | ||
107 | return PAGE_SIZE - size; | |
108 | } | |
109 | ||
110 | static ssize_t | |
111 | set_a_bus_drop(struct device *dev, struct device_attribute *attr, | |
112 | const char *buf, size_t count) | |
113 | { | |
114 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
115 | ||
116 | if (count > 2) | |
117 | return -1; | |
118 | ||
119 | mutex_lock(&ci->fsm.lock); | |
120 | if (buf[0] == '0') { | |
121 | ci->fsm.a_bus_drop = 0; | |
122 | } else if (buf[0] == '1') { | |
123 | ci->fsm.a_bus_drop = 1; | |
124 | ci->fsm.a_bus_req = 0; | |
125 | } | |
126 | ||
be6b0c1b | 127 | ci_otg_queue_work(ci); |
15f75def LJ |
128 | mutex_unlock(&ci->fsm.lock); |
129 | ||
130 | return count; | |
131 | } | |
132 | static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR, get_a_bus_drop, | |
133 | set_a_bus_drop); | |
134 | ||
135 | static ssize_t | |
136 | get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf) | |
137 | { | |
138 | char *next; | |
139 | unsigned size, t; | |
140 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
141 | ||
142 | next = buf; | |
143 | size = PAGE_SIZE; | |
144 | t = scnprintf(next, size, "%d\n", ci->fsm.b_bus_req); | |
145 | size -= t; | |
146 | next += t; | |
147 | ||
148 | return PAGE_SIZE - size; | |
149 | } | |
150 | ||
151 | static ssize_t | |
152 | set_b_bus_req(struct device *dev, struct device_attribute *attr, | |
153 | const char *buf, size_t count) | |
154 | { | |
155 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
156 | ||
157 | if (count > 2) | |
158 | return -1; | |
159 | ||
160 | mutex_lock(&ci->fsm.lock); | |
161 | if (buf[0] == '0') | |
162 | ci->fsm.b_bus_req = 0; | |
163 | else if (buf[0] == '1') | |
164 | ci->fsm.b_bus_req = 1; | |
165 | ||
be6b0c1b | 166 | ci_otg_queue_work(ci); |
15f75def LJ |
167 | mutex_unlock(&ci->fsm.lock); |
168 | ||
169 | return count; | |
170 | } | |
171 | static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUSR, get_b_bus_req, set_b_bus_req); | |
172 | ||
173 | static ssize_t | |
174 | set_a_clr_err(struct device *dev, struct device_attribute *attr, | |
175 | const char *buf, size_t count) | |
176 | { | |
177 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
178 | ||
179 | if (count > 2) | |
180 | return -1; | |
181 | ||
182 | mutex_lock(&ci->fsm.lock); | |
183 | if (buf[0] == '1') | |
184 | ci->fsm.a_clr_err = 1; | |
185 | ||
be6b0c1b | 186 | ci_otg_queue_work(ci); |
15f75def LJ |
187 | mutex_unlock(&ci->fsm.lock); |
188 | ||
189 | return count; | |
190 | } | |
191 | static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err); | |
192 | ||
193 | static struct attribute *inputs_attrs[] = { | |
194 | &dev_attr_a_bus_req.attr, | |
195 | &dev_attr_a_bus_drop.attr, | |
196 | &dev_attr_b_bus_req.attr, | |
197 | &dev_attr_a_clr_err.attr, | |
198 | NULL, | |
199 | }; | |
200 | ||
201 | static struct attribute_group inputs_attr_group = { | |
202 | .name = "inputs", | |
203 | .attrs = inputs_attrs, | |
204 | }; | |
205 | ||
826cfe75 LJ |
206 | /* |
207 | * Add timer to active timer list | |
208 | */ | |
209 | static void ci_otg_add_timer(struct ci_hdrc *ci, enum ci_otg_fsm_timer_index t) | |
210 | { | |
211 | struct ci_otg_fsm_timer *tmp_timer; | |
212 | struct ci_otg_fsm_timer *timer = ci->fsm_timer->timer_list[t]; | |
213 | struct list_head *active_timers = &ci->fsm_timer->active_timers; | |
214 | ||
215 | if (t >= NUM_CI_OTG_FSM_TIMERS) | |
216 | return; | |
217 | ||
218 | /* | |
219 | * Check if the timer is already in the active list, | |
220 | * if so update timer count | |
221 | */ | |
222 | list_for_each_entry(tmp_timer, active_timers, list) | |
223 | if (tmp_timer == timer) { | |
224 | timer->count = timer->expires; | |
225 | return; | |
226 | } | |
227 | ||
961ea496 LJ |
228 | if (list_empty(active_timers)) |
229 | pm_runtime_get(ci->dev); | |
230 | ||
826cfe75 LJ |
231 | timer->count = timer->expires; |
232 | list_add_tail(&timer->list, active_timers); | |
233 | ||
234 | /* Enable 1ms irq */ | |
235 | if (!(hw_read_otgsc(ci, OTGSC_1MSIE))) | |
236 | hw_write_otgsc(ci, OTGSC_1MSIE, OTGSC_1MSIE); | |
237 | } | |
238 | ||
239 | /* | |
240 | * Remove timer from active timer list | |
241 | */ | |
242 | static void ci_otg_del_timer(struct ci_hdrc *ci, enum ci_otg_fsm_timer_index t) | |
243 | { | |
244 | struct ci_otg_fsm_timer *tmp_timer, *del_tmp; | |
245 | struct ci_otg_fsm_timer *timer = ci->fsm_timer->timer_list[t]; | |
246 | struct list_head *active_timers = &ci->fsm_timer->active_timers; | |
961ea496 | 247 | int flag = 0; |
826cfe75 LJ |
248 | |
249 | if (t >= NUM_CI_OTG_FSM_TIMERS) | |
250 | return; | |
251 | ||
252 | list_for_each_entry_safe(tmp_timer, del_tmp, active_timers, list) | |
961ea496 | 253 | if (tmp_timer == timer) { |
826cfe75 | 254 | list_del(&timer->list); |
961ea496 LJ |
255 | flag = 1; |
256 | } | |
826cfe75 LJ |
257 | |
258 | /* Disable 1ms irq if there is no any active timer */ | |
961ea496 | 259 | if (list_empty(active_timers) && (flag == 1)) { |
826cfe75 | 260 | hw_write_otgsc(ci, OTGSC_1MSIE, 0); |
961ea496 LJ |
261 | pm_runtime_put(ci->dev); |
262 | } | |
826cfe75 LJ |
263 | } |
264 | ||
4dcf720c LJ |
265 | /* |
266 | * Reduce timer count by 1, and find timeout conditions. | |
267 | * Called by otg 1ms timer interrupt | |
268 | */ | |
269 | static inline int ci_otg_tick_timer(struct ci_hdrc *ci) | |
270 | { | |
271 | struct ci_otg_fsm_timer *tmp_timer, *del_tmp; | |
272 | struct list_head *active_timers = &ci->fsm_timer->active_timers; | |
273 | int expired = 0; | |
274 | ||
275 | list_for_each_entry_safe(tmp_timer, del_tmp, active_timers, list) { | |
276 | tmp_timer->count--; | |
277 | /* check if timer expires */ | |
278 | if (!tmp_timer->count) { | |
279 | list_del(&tmp_timer->list); | |
280 | tmp_timer->function(ci, tmp_timer->data); | |
281 | expired = 1; | |
282 | } | |
283 | } | |
284 | ||
285 | /* disable 1ms irq if there is no any timer active */ | |
961ea496 | 286 | if ((expired == 1) && list_empty(active_timers)) { |
4dcf720c | 287 | hw_write_otgsc(ci, OTGSC_1MSIE, 0); |
961ea496 LJ |
288 | pm_runtime_put(ci->dev); |
289 | } | |
4dcf720c LJ |
290 | |
291 | return expired; | |
292 | } | |
293 | ||
e287b67b LJ |
294 | /* The timeout callback function to set time out bit */ |
295 | static void set_tmout(void *ptr, unsigned long indicator) | |
296 | { | |
297 | *(int *)indicator = 1; | |
298 | } | |
299 | ||
300 | static void set_tmout_and_fsm(void *ptr, unsigned long indicator) | |
301 | { | |
302 | struct ci_hdrc *ci = (struct ci_hdrc *)ptr; | |
303 | ||
304 | set_tmout(ci, indicator); | |
305 | ||
be6b0c1b | 306 | ci_otg_queue_work(ci); |
e287b67b LJ |
307 | } |
308 | ||
309 | static void a_wait_vfall_tmout_func(void *ptr, unsigned long indicator) | |
310 | { | |
311 | struct ci_hdrc *ci = (struct ci_hdrc *)ptr; | |
312 | ||
313 | set_tmout(ci, indicator); | |
314 | /* Disable port power */ | |
315 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 0); | |
6629467b | 316 | /* Clear existing DP irq */ |
e287b67b LJ |
317 | hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS); |
318 | /* Enable data pulse irq */ | |
319 | hw_write_otgsc(ci, OTGSC_DPIE, OTGSC_DPIE); | |
be6b0c1b | 320 | ci_otg_queue_work(ci); |
e287b67b LJ |
321 | } |
322 | ||
e287b67b LJ |
323 | static void b_ssend_srp_tmout_func(void *ptr, unsigned long indicator) |
324 | { | |
325 | struct ci_hdrc *ci = (struct ci_hdrc *)ptr; | |
326 | ||
327 | set_tmout(ci, indicator); | |
328 | ||
329 | /* only vbus fall below B_sess_vld in b_idle state */ | |
e47d9254 | 330 | if (ci->fsm.otg->state == OTG_STATE_B_IDLE) |
be6b0c1b | 331 | ci_otg_queue_work(ci); |
e287b67b LJ |
332 | } |
333 | ||
e287b67b LJ |
334 | static void b_data_pulse_end(void *ptr, unsigned long indicator) |
335 | { | |
336 | struct ci_hdrc *ci = (struct ci_hdrc *)ptr; | |
337 | ||
338 | ci->fsm.b_srp_done = 1; | |
339 | ci->fsm.b_bus_req = 0; | |
340 | if (ci->fsm.power_up) | |
341 | ci->fsm.power_up = 0; | |
342 | ||
343 | hw_write_otgsc(ci, OTGSC_HABA, 0); | |
344 | ||
be6b0c1b | 345 | ci_otg_queue_work(ci); |
e287b67b LJ |
346 | } |
347 | ||
348 | /* Initialize timers */ | |
349 | static int ci_otg_init_timers(struct ci_hdrc *ci) | |
350 | { | |
351 | struct otg_fsm *fsm = &ci->fsm; | |
352 | ||
353 | /* FSM used timers */ | |
354 | ci->fsm_timer->timer_list[A_WAIT_VRISE] = | |
355 | otg_timer_initializer(ci, &set_tmout_and_fsm, TA_WAIT_VRISE, | |
356 | (unsigned long)&fsm->a_wait_vrise_tmout); | |
357 | if (ci->fsm_timer->timer_list[A_WAIT_VRISE] == NULL) | |
358 | return -ENOMEM; | |
359 | ||
360 | ci->fsm_timer->timer_list[A_WAIT_VFALL] = | |
361 | otg_timer_initializer(ci, &a_wait_vfall_tmout_func, | |
362 | TA_WAIT_VFALL, (unsigned long)&fsm->a_wait_vfall_tmout); | |
363 | if (ci->fsm_timer->timer_list[A_WAIT_VFALL] == NULL) | |
364 | return -ENOMEM; | |
365 | ||
366 | ci->fsm_timer->timer_list[A_WAIT_BCON] = | |
367 | otg_timer_initializer(ci, &set_tmout_and_fsm, TA_WAIT_BCON, | |
368 | (unsigned long)&fsm->a_wait_bcon_tmout); | |
369 | if (ci->fsm_timer->timer_list[A_WAIT_BCON] == NULL) | |
370 | return -ENOMEM; | |
371 | ||
372 | ci->fsm_timer->timer_list[A_AIDL_BDIS] = | |
373 | otg_timer_initializer(ci, &set_tmout_and_fsm, TA_AIDL_BDIS, | |
374 | (unsigned long)&fsm->a_aidl_bdis_tmout); | |
375 | if (ci->fsm_timer->timer_list[A_AIDL_BDIS] == NULL) | |
376 | return -ENOMEM; | |
377 | ||
378 | ci->fsm_timer->timer_list[A_BIDL_ADIS] = | |
379 | otg_timer_initializer(ci, &set_tmout_and_fsm, TA_BIDL_ADIS, | |
380 | (unsigned long)&fsm->a_bidl_adis_tmout); | |
381 | if (ci->fsm_timer->timer_list[A_BIDL_ADIS] == NULL) | |
382 | return -ENOMEM; | |
383 | ||
384 | ci->fsm_timer->timer_list[B_ASE0_BRST] = | |
01ecd156 | 385 | otg_timer_initializer(ci, &set_tmout_and_fsm, TB_ASE0_BRST, |
e287b67b LJ |
386 | (unsigned long)&fsm->b_ase0_brst_tmout); |
387 | if (ci->fsm_timer->timer_list[B_ASE0_BRST] == NULL) | |
388 | return -ENOMEM; | |
389 | ||
390 | ci->fsm_timer->timer_list[B_SE0_SRP] = | |
391 | otg_timer_initializer(ci, &set_tmout_and_fsm, TB_SE0_SRP, | |
392 | (unsigned long)&fsm->b_se0_srp); | |
393 | if (ci->fsm_timer->timer_list[B_SE0_SRP] == NULL) | |
394 | return -ENOMEM; | |
395 | ||
396 | ci->fsm_timer->timer_list[B_SSEND_SRP] = | |
397 | otg_timer_initializer(ci, &b_ssend_srp_tmout_func, TB_SSEND_SRP, | |
398 | (unsigned long)&fsm->b_ssend_srp); | |
399 | if (ci->fsm_timer->timer_list[B_SSEND_SRP] == NULL) | |
400 | return -ENOMEM; | |
401 | ||
402 | ci->fsm_timer->timer_list[B_SRP_FAIL] = | |
403 | otg_timer_initializer(ci, &set_tmout, TB_SRP_FAIL, | |
404 | (unsigned long)&fsm->b_srp_done); | |
405 | if (ci->fsm_timer->timer_list[B_SRP_FAIL] == NULL) | |
406 | return -ENOMEM; | |
407 | ||
408 | ci->fsm_timer->timer_list[B_DATA_PLS] = | |
409 | otg_timer_initializer(ci, &b_data_pulse_end, TB_DATA_PLS, 0); | |
410 | if (ci->fsm_timer->timer_list[B_DATA_PLS] == NULL) | |
411 | return -ENOMEM; | |
412 | ||
e287b67b LJ |
413 | return 0; |
414 | } | |
415 | ||
826cfe75 LJ |
416 | /* -------------------------------------------------------------*/ |
417 | /* Operations that will be called from OTG Finite State Machine */ | |
418 | /* -------------------------------------------------------------*/ | |
419 | static void ci_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t) | |
420 | { | |
421 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
422 | ||
423 | if (t < NUM_OTG_FSM_TIMERS) | |
424 | ci_otg_add_timer(ci, t); | |
425 | return; | |
426 | } | |
427 | ||
428 | static void ci_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t) | |
429 | { | |
430 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
431 | ||
432 | if (t < NUM_OTG_FSM_TIMERS) | |
433 | ci_otg_del_timer(ci, t); | |
434 | return; | |
435 | } | |
436 | ||
437 | /* | |
438 | * A-device drive vbus: turn on vbus regulator and enable port power | |
439 | * Data pulse irq should be disabled while vbus is on. | |
440 | */ | |
441 | static void ci_otg_drv_vbus(struct otg_fsm *fsm, int on) | |
442 | { | |
443 | int ret; | |
444 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
445 | ||
446 | if (on) { | |
447 | /* Enable power power */ | |
448 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, | |
449 | PORTSC_PP); | |
450 | if (ci->platdata->reg_vbus) { | |
451 | ret = regulator_enable(ci->platdata->reg_vbus); | |
452 | if (ret) { | |
453 | dev_err(ci->dev, | |
454 | "Failed to enable vbus regulator, ret=%d\n", | |
455 | ret); | |
456 | return; | |
457 | } | |
458 | } | |
459 | /* Disable data pulse irq */ | |
460 | hw_write_otgsc(ci, OTGSC_DPIE, 0); | |
461 | ||
462 | fsm->a_srp_det = 0; | |
463 | fsm->power_up = 0; | |
464 | } else { | |
465 | if (ci->platdata->reg_vbus) | |
466 | regulator_disable(ci->platdata->reg_vbus); | |
467 | ||
468 | fsm->a_bus_drop = 1; | |
469 | fsm->a_bus_req = 0; | |
470 | } | |
471 | } | |
472 | ||
473 | /* | |
474 | * Control data line by Run Stop bit. | |
475 | */ | |
476 | static void ci_otg_loc_conn(struct otg_fsm *fsm, int on) | |
477 | { | |
478 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
479 | ||
480 | if (on) | |
481 | hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS); | |
482 | else | |
483 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); | |
484 | } | |
485 | ||
486 | /* | |
487 | * Generate SOF by host. | |
488 | * This is controlled through suspend/resume the port. | |
489 | * In host mode, controller will automatically send SOF. | |
490 | * Suspend will block the data on the port. | |
491 | */ | |
492 | static void ci_otg_loc_sof(struct otg_fsm *fsm, int on) | |
493 | { | |
494 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
495 | ||
496 | if (on) | |
497 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_FPR, | |
498 | PORTSC_FPR); | |
499 | else | |
500 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_SUSP, | |
501 | PORTSC_SUSP); | |
502 | } | |
503 | ||
504 | /* | |
505 | * Start SRP pulsing by data-line pulsing, | |
506 | * no v-bus pulsing followed | |
507 | */ | |
508 | static void ci_otg_start_pulse(struct otg_fsm *fsm) | |
509 | { | |
510 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
511 | ||
512 | /* Hardware Assistant Data pulse */ | |
513 | hw_write_otgsc(ci, OTGSC_HADP, OTGSC_HADP); | |
514 | ||
515 | ci_otg_add_timer(ci, B_DATA_PLS); | |
516 | } | |
517 | ||
518 | static int ci_otg_start_host(struct otg_fsm *fsm, int on) | |
519 | { | |
520 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
521 | ||
522 | mutex_unlock(&fsm->lock); | |
523 | if (on) { | |
524 | ci_role_stop(ci); | |
525 | ci_role_start(ci, CI_ROLE_HOST); | |
526 | } else { | |
527 | ci_role_stop(ci); | |
5b157300 | 528 | hw_device_reset(ci); |
826cfe75 LJ |
529 | ci_role_start(ci, CI_ROLE_GADGET); |
530 | } | |
531 | mutex_lock(&fsm->lock); | |
532 | return 0; | |
533 | } | |
534 | ||
535 | static int ci_otg_start_gadget(struct otg_fsm *fsm, int on) | |
536 | { | |
537 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
538 | ||
539 | mutex_unlock(&fsm->lock); | |
540 | if (on) | |
541 | usb_gadget_vbus_connect(&ci->gadget); | |
542 | else | |
543 | usb_gadget_vbus_disconnect(&ci->gadget); | |
544 | mutex_lock(&fsm->lock); | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
549 | static struct otg_fsm_ops ci_otg_ops = { | |
550 | .drv_vbus = ci_otg_drv_vbus, | |
551 | .loc_conn = ci_otg_loc_conn, | |
552 | .loc_sof = ci_otg_loc_sof, | |
553 | .start_pulse = ci_otg_start_pulse, | |
554 | .add_timer = ci_otg_fsm_add_timer, | |
555 | .del_timer = ci_otg_fsm_del_timer, | |
556 | .start_host = ci_otg_start_host, | |
557 | .start_gadget = ci_otg_start_gadget, | |
558 | }; | |
559 | ||
4dcf720c LJ |
560 | int ci_otg_fsm_work(struct ci_hdrc *ci) |
561 | { | |
562 | /* | |
563 | * Don't do fsm transition for B device | |
564 | * when there is no gadget class driver | |
565 | */ | |
566 | if (ci->fsm.id && !(ci->driver) && | |
e47d9254 | 567 | ci->fsm.otg->state < OTG_STATE_A_IDLE) |
4dcf720c LJ |
568 | return 0; |
569 | ||
961ea496 | 570 | pm_runtime_get_sync(ci->dev); |
4dcf720c | 571 | if (otg_statemachine(&ci->fsm)) { |
e47d9254 | 572 | if (ci->fsm.otg->state == OTG_STATE_A_IDLE) { |
4dcf720c LJ |
573 | /* |
574 | * Further state change for cases: | |
575 | * a_idle to b_idle; or | |
576 | * a_idle to a_wait_vrise due to ID change(1->0), so | |
577 | * B-dev becomes A-dev can try to start new session | |
578 | * consequently; or | |
579 | * a_idle to a_wait_vrise when power up | |
580 | */ | |
581 | if ((ci->fsm.id) || (ci->id_event) || | |
be6b0c1b PC |
582 | (ci->fsm.power_up)) |
583 | ci_otg_queue_work(ci); | |
4dcf720c LJ |
584 | if (ci->id_event) |
585 | ci->id_event = false; | |
e47d9254 | 586 | } else if (ci->fsm.otg->state == OTG_STATE_B_IDLE) { |
4dcf720c LJ |
587 | if (ci->fsm.b_sess_vld) { |
588 | ci->fsm.power_up = 0; | |
589 | /* | |
590 | * Further transite to b_periphearl state | |
591 | * when register gadget driver with vbus on | |
592 | */ | |
be6b0c1b | 593 | ci_otg_queue_work(ci); |
4dcf720c | 594 | } |
961ea496 LJ |
595 | } else if (ci->fsm.otg->state == OTG_STATE_A_HOST) { |
596 | pm_runtime_mark_last_busy(ci->dev); | |
597 | pm_runtime_put_autosuspend(ci->dev); | |
598 | return 0; | |
4dcf720c LJ |
599 | } |
600 | } | |
961ea496 | 601 | pm_runtime_put_sync(ci->dev); |
4dcf720c LJ |
602 | return 0; |
603 | } | |
604 | ||
605 | /* | |
606 | * Update fsm variables in each state if catching expected interrupts, | |
607 | * called by otg fsm isr. | |
608 | */ | |
609 | static void ci_otg_fsm_event(struct ci_hdrc *ci) | |
610 | { | |
611 | u32 intr_sts, otg_bsess_vld, port_conn; | |
612 | struct otg_fsm *fsm = &ci->fsm; | |
613 | ||
614 | intr_sts = hw_read_intr_status(ci); | |
615 | otg_bsess_vld = hw_read_otgsc(ci, OTGSC_BSV); | |
616 | port_conn = hw_read(ci, OP_PORTSC, PORTSC_CCS); | |
617 | ||
e47d9254 | 618 | switch (ci->fsm.otg->state) { |
4dcf720c LJ |
619 | case OTG_STATE_A_WAIT_BCON: |
620 | if (port_conn) { | |
621 | fsm->b_conn = 1; | |
622 | fsm->a_bus_req = 1; | |
be6b0c1b | 623 | ci_otg_queue_work(ci); |
4dcf720c LJ |
624 | } |
625 | break; | |
626 | case OTG_STATE_B_IDLE: | |
627 | if (otg_bsess_vld && (intr_sts & USBi_PCI) && port_conn) { | |
628 | fsm->b_sess_vld = 1; | |
be6b0c1b | 629 | ci_otg_queue_work(ci); |
4dcf720c LJ |
630 | } |
631 | break; | |
632 | case OTG_STATE_B_PERIPHERAL: | |
633 | if ((intr_sts & USBi_SLI) && port_conn && otg_bsess_vld) { | |
634 | fsm->a_bus_suspend = 1; | |
be6b0c1b | 635 | ci_otg_queue_work(ci); |
4dcf720c LJ |
636 | } else if (intr_sts & USBi_PCI) { |
637 | if (fsm->a_bus_suspend == 1) | |
638 | fsm->a_bus_suspend = 0; | |
639 | } | |
640 | break; | |
641 | case OTG_STATE_B_HOST: | |
642 | if ((intr_sts & USBi_PCI) && !port_conn) { | |
643 | fsm->a_conn = 0; | |
644 | fsm->b_bus_req = 0; | |
be6b0c1b | 645 | ci_otg_queue_work(ci); |
4dcf720c LJ |
646 | } |
647 | break; | |
648 | case OTG_STATE_A_PERIPHERAL: | |
649 | if (intr_sts & USBi_SLI) { | |
650 | fsm->b_bus_suspend = 1; | |
651 | /* | |
652 | * Init a timer to know how long this suspend | |
6629467b | 653 | * will continue, if time out, indicates B no longer |
4dcf720c LJ |
654 | * wants to be host role |
655 | */ | |
656 | ci_otg_add_timer(ci, A_BIDL_ADIS); | |
657 | } | |
658 | ||
659 | if (intr_sts & USBi_URI) | |
660 | ci_otg_del_timer(ci, A_BIDL_ADIS); | |
661 | ||
662 | if (intr_sts & USBi_PCI) { | |
663 | if (fsm->b_bus_suspend == 1) { | |
664 | ci_otg_del_timer(ci, A_BIDL_ADIS); | |
665 | fsm->b_bus_suspend = 0; | |
666 | } | |
667 | } | |
668 | break; | |
669 | case OTG_STATE_A_SUSPEND: | |
670 | if ((intr_sts & USBi_PCI) && !port_conn) { | |
671 | fsm->b_conn = 0; | |
672 | ||
673 | /* if gadget driver is binded */ | |
674 | if (ci->driver) { | |
675 | /* A device to be peripheral mode */ | |
676 | ci->gadget.is_a_peripheral = 1; | |
677 | } | |
be6b0c1b | 678 | ci_otg_queue_work(ci); |
4dcf720c LJ |
679 | } |
680 | break; | |
681 | case OTG_STATE_A_HOST: | |
682 | if ((intr_sts & USBi_PCI) && !port_conn) { | |
683 | fsm->b_conn = 0; | |
be6b0c1b | 684 | ci_otg_queue_work(ci); |
4dcf720c LJ |
685 | } |
686 | break; | |
687 | case OTG_STATE_B_WAIT_ACON: | |
688 | if ((intr_sts & USBi_PCI) && port_conn) { | |
689 | fsm->a_conn = 1; | |
be6b0c1b | 690 | ci_otg_queue_work(ci); |
4dcf720c LJ |
691 | } |
692 | break; | |
693 | default: | |
694 | break; | |
695 | } | |
696 | } | |
697 | ||
698 | /* | |
699 | * ci_otg_irq - otg fsm related irq handling | |
700 | * and also update otg fsm variable by monitoring usb host and udc | |
701 | * state change interrupts. | |
702 | * @ci: ci_hdrc | |
703 | */ | |
704 | irqreturn_t ci_otg_fsm_irq(struct ci_hdrc *ci) | |
705 | { | |
706 | irqreturn_t retval = IRQ_NONE; | |
707 | u32 otgsc, otg_int_src = 0; | |
708 | struct otg_fsm *fsm = &ci->fsm; | |
709 | ||
710 | otgsc = hw_read_otgsc(ci, ~0); | |
711 | otg_int_src = otgsc & OTGSC_INT_STATUS_BITS & (otgsc >> 8); | |
712 | fsm->id = (otgsc & OTGSC_ID) ? 1 : 0; | |
713 | ||
714 | if (otg_int_src) { | |
715 | if (otg_int_src & OTGSC_1MSIS) { | |
716 | hw_write_otgsc(ci, OTGSC_1MSIS, OTGSC_1MSIS); | |
717 | retval = ci_otg_tick_timer(ci); | |
718 | return IRQ_HANDLED; | |
719 | } else if (otg_int_src & OTGSC_DPIS) { | |
720 | hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS); | |
721 | fsm->a_srp_det = 1; | |
722 | fsm->a_bus_drop = 0; | |
723 | } else if (otg_int_src & OTGSC_IDIS) { | |
724 | hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); | |
725 | if (fsm->id == 0) { | |
726 | fsm->a_bus_drop = 0; | |
727 | fsm->a_bus_req = 1; | |
728 | ci->id_event = true; | |
729 | } | |
730 | } else if (otg_int_src & OTGSC_BSVIS) { | |
731 | hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); | |
732 | if (otgsc & OTGSC_BSV) { | |
733 | fsm->b_sess_vld = 1; | |
734 | ci_otg_del_timer(ci, B_SSEND_SRP); | |
735 | ci_otg_del_timer(ci, B_SRP_FAIL); | |
736 | fsm->b_ssend_srp = 0; | |
737 | } else { | |
738 | fsm->b_sess_vld = 0; | |
739 | if (fsm->id) | |
740 | ci_otg_add_timer(ci, B_SSEND_SRP); | |
741 | } | |
742 | } else if (otg_int_src & OTGSC_AVVIS) { | |
743 | hw_write_otgsc(ci, OTGSC_AVVIS, OTGSC_AVVIS); | |
744 | if (otgsc & OTGSC_AVV) { | |
745 | fsm->a_vbus_vld = 1; | |
746 | } else { | |
747 | fsm->a_vbus_vld = 0; | |
748 | fsm->b_conn = 0; | |
749 | } | |
750 | } | |
be6b0c1b | 751 | ci_otg_queue_work(ci); |
4dcf720c LJ |
752 | return IRQ_HANDLED; |
753 | } | |
754 | ||
755 | ci_otg_fsm_event(ci); | |
756 | ||
757 | return retval; | |
758 | } | |
759 | ||
760 | void ci_hdrc_otg_fsm_start(struct ci_hdrc *ci) | |
761 | { | |
be6b0c1b | 762 | ci_otg_queue_work(ci); |
4dcf720c LJ |
763 | } |
764 | ||
57677be5 LJ |
765 | int ci_hdrc_otg_fsm_init(struct ci_hdrc *ci) |
766 | { | |
e287b67b | 767 | int retval = 0; |
57677be5 | 768 | |
1e5e2d3d AT |
769 | if (ci->phy) |
770 | ci->otg.phy = ci->phy; | |
771 | else | |
772 | ci->otg.usb_phy = ci->usb_phy; | |
57677be5 | 773 | |
ef44cb42 AT |
774 | ci->otg.gadget = &ci->gadget; |
775 | ci->fsm.otg = &ci->otg; | |
57677be5 LJ |
776 | ci->fsm.power_up = 1; |
777 | ci->fsm.id = hw_read_otgsc(ci, OTGSC_ID) ? 1 : 0; | |
e47d9254 | 778 | ci->fsm.otg->state = OTG_STATE_UNDEFINED; |
826cfe75 | 779 | ci->fsm.ops = &ci_otg_ops; |
57677be5 LJ |
780 | |
781 | mutex_init(&ci->fsm.lock); | |
782 | ||
e287b67b LJ |
783 | ci->fsm_timer = devm_kzalloc(ci->dev, |
784 | sizeof(struct ci_otg_fsm_timer_list), GFP_KERNEL); | |
51f1741f | 785 | if (!ci->fsm_timer) |
e287b67b | 786 | return -ENOMEM; |
e287b67b LJ |
787 | |
788 | INIT_LIST_HEAD(&ci->fsm_timer->active_timers); | |
789 | retval = ci_otg_init_timers(ci); | |
790 | if (retval) { | |
791 | dev_err(ci->dev, "Couldn't init OTG timers\n"); | |
792 | return retval; | |
793 | } | |
794 | ||
15f75def LJ |
795 | retval = sysfs_create_group(&ci->dev->kobj, &inputs_attr_group); |
796 | if (retval < 0) { | |
797 | dev_dbg(ci->dev, | |
798 | "Can't register sysfs attr group: %d\n", retval); | |
799 | return retval; | |
800 | } | |
801 | ||
57677be5 LJ |
802 | /* Enable A vbus valid irq */ |
803 | hw_write_otgsc(ci, OTGSC_AVVIE, OTGSC_AVVIE); | |
804 | ||
805 | if (ci->fsm.id) { | |
806 | ci->fsm.b_ssend_srp = | |
807 | hw_read_otgsc(ci, OTGSC_BSV) ? 0 : 1; | |
808 | ci->fsm.b_sess_vld = | |
809 | hw_read_otgsc(ci, OTGSC_BSV) ? 1 : 0; | |
810 | /* Enable BSV irq */ | |
811 | hw_write_otgsc(ci, OTGSC_BSVIE, OTGSC_BSVIE); | |
812 | } | |
813 | ||
814 | return 0; | |
815 | } | |
15f75def LJ |
816 | |
817 | void ci_hdrc_otg_fsm_remove(struct ci_hdrc *ci) | |
818 | { | |
819 | sysfs_remove_group(&ci->dev->kobj, &inputs_attr_group); | |
820 | } |