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bluetooth: add module.h to drivers/bluetooth files as required.
[linux-2.6-block.git] / drivers / tty / serial / xilinx_uartps.c
CommitLineData
61ec9016
JL		 1/*
2 * Xilinx PS UART driver
3 *
4 * 2011 (c) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 */
13
14#include <linux/platform_device.h>
ee160a38 15#include <linux/serial.h>
61ec9016 16#include <linux/serial_core.h>
ee160a38
JS		 17#include <linux/tty.h>
18#include <linux/tty_flip.h>
61ec9016 19#include <linux/console.h>
61ec9016
JL		 20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
23
24#define XUARTPS_TTY_NAME "ttyPS"
25#define XUARTPS_NAME "xuartps"
26#define XUARTPS_MAJOR 0 /* use dynamic node allocation */
27#define XUARTPS_MINOR 0 /* works best with devtmpfs */
28#define XUARTPS_NR_PORTS 2
29#define XUARTPS_FIFO_SIZE 16 /* FIFO size */
30#define XUARTPS_REGISTER_SPACE 0xFFF
31
32#define xuartps_readl(offset) ioread32(port->membase + offset)
33#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
34
35/********************************Register Map********************************/
36/** UART
37 *
38 * Register offsets for the UART.
39 *
40 */
41#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
42#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
43#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
44#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
45#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
46#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
47#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
48#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
49#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
50#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
51#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
52#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
53#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
54#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
55#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
56#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
57 Width [15:0] */
58#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
59 Width [7:0] */
60#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
61
62/** Control Register
63 *
64 * The Control register (CR) controls the major functions of the device.
65 *
66 * Control Register Bit Definitions
67 */
68#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
69#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
70#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
71#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
72#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
73#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
74#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
75#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
76#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
77
78/** Mode Register
79 *
80 * The mode register (MR) defines the mode of transfer as well as the data
81 * format. If this register is modified during transmission or reception,
82 * data validity cannot be guaranteed.
83 *
84 * Mode Register Bit Definitions
85 *
86 */
87#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
88#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
89#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
90
91#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
92#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
93
94#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
95#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
96#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
97#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
98#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
99
100#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
101#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
102#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
103
104/** Interrupt Registers
105 *
106 * Interrupt control logic uses the interrupt enable register (IER) and the
107 * interrupt disable register (IDR) to set the value of the bits in the
108 * interrupt mask register (IMR). The IMR determines whether to pass an
109 * interrupt to the interrupt status register (ISR).
110 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
111 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
112 * Reading either IER or IDR returns 0x00.
113 *
114 * All four registers have the same bit definitions.
115 */
116#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
117#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
118#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
119#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
120#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
121#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
122#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
123#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
124#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
125#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
126#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
127
128/** Channel Status Register
129 *
130 * The channel status register (CSR) is provided to enable the control logic
131 * to monitor the status of bits in the channel interrupt status register,
132 * even if these are masked out by the interrupt mask register.
133 */
134#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
135#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
136#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
137#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
138
139/**
140 * xuartps_isr - Interrupt handler
141 * @irq: Irq number
142 * @dev_id: Id of the port
143 *
144 * Returns IRQHANDLED
145 **/
146static irqreturn_t xuartps_isr(int irq, void *dev_id)
147{
148 struct uart_port *port = (struct uart_port *)dev_id;
149 struct tty_struct *tty;
150 unsigned long flags;
151 unsigned int isrstatus, numbytes;
152 unsigned int data;
153 char status = TTY_NORMAL;
154
155 /* Get the tty which could be NULL so don't assume it's valid */
156 tty = tty_port_tty_get(&port->state->port);
157
158 spin_lock_irqsave(&port->lock, flags);
159
160 /* Read the interrupt status register to determine which
161 * interrupt(s) is/are active.
162 */
163 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
164
165 /* drop byte with parity error if IGNPAR specified */
166 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
167 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
168
169 isrstatus &= port->read_status_mask;
170 isrstatus &= ~port->ignore_status_mask;
171
172 if ((isrstatus & XUARTPS_IXR_TOUT) ||
173 (isrstatus & XUARTPS_IXR_RXTRIG)) {
174 /* Receive Timeout Interrupt */
175 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
176 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
177 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
178 port->icount.rx++;
179
180 if (isrstatus & XUARTPS_IXR_PARITY) {
181 port->icount.parity++;
182 status = TTY_PARITY;
183 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
184 port->icount.frame++;
185 status = TTY_FRAME;
186 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
187 port->icount.overrun++;
188
189 if (tty)
190 uart_insert_char(port, isrstatus,
191 XUARTPS_IXR_OVERRUN, data,
192 status);
193 }
194 spin_unlock(&port->lock);
195 if (tty)
196 tty_flip_buffer_push(tty);
197 spin_lock(&port->lock);
198 }
199
200 /* Dispatch an appropriate handler */
201 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
202 if (uart_circ_empty(&port->state->xmit)) {
203 xuartps_writel(XUARTPS_IXR_TXEMPTY,
204 XUARTPS_IDR_OFFSET);
205 } else {
206 numbytes = port->fifosize;
207 /* Break if no more data available in the UART buffer */
208 while (numbytes--) {
209 if (uart_circ_empty(&port->state->xmit))
210 break;
211 /* Get the data from the UART circular buffer
212 * and write it to the xuartps's TX_FIFO
213 * register.
214 */
215 xuartps_writel(
216 port->state->xmit.buf[port->state->xmit.
217 tail], XUARTPS_FIFO_OFFSET);
218
219 port->icount.tx++;
220
221 /* Adjust the tail of the UART buffer and wrap
222 * the buffer if it reaches limit.
223 */
224 port->state->xmit.tail =
225 (port->state->xmit.tail + 1) & \
226 (UART_XMIT_SIZE - 1);
227 }
228
229 if (uart_circ_chars_pending(
230 &port->state->xmit) < WAKEUP_CHARS)
231 uart_write_wakeup(port);
232 }
233 }
234
235 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
236
237 /* be sure to release the lock and tty before leaving */
238 spin_unlock_irqrestore(&port->lock, flags);
239 tty_kref_put(tty);
240
241 return IRQ_HANDLED;
242}
243
244/**
245 * xuartps_set_baud_rate - Calculate and set the baud rate
246 * @port: Handle to the uart port structure
247 * @baud: Baud rate to set
248 *
249 * Returns baud rate, requested baud when possible, or actual baud when there
250 * was too much error
251 **/
252static unsigned int xuartps_set_baud_rate(struct uart_port *port,
253 unsigned int baud)
254{
255 unsigned int sel_clk;
256 unsigned int calc_baud = 0;
257 unsigned int brgr_val, brdiv_val;
258 unsigned int bauderror;
259
260 /* Formula to obtain baud rate is
261 * baud_tx/rx rate = sel_clk/CD * (BDIV + 1)
262 * input_clk = (Uart User Defined Clock or Apb Clock)
263 * depends on UCLKEN in MR Reg
264 * sel_clk = input_clk or input_clk/8;
265 * depends on CLKS in MR reg
266 * CD and BDIV depends on values in
267 * baud rate generate register
268 * baud rate clock divisor register
269 */
270 sel_clk = port->uartclk;
271 if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL)
272 sel_clk = sel_clk / 8;
273
274 /* Find the best values for baud generation */
275 for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) {
276
277 brgr_val = sel_clk / (baud * (brdiv_val + 1));
278 if (brgr_val < 2 || brgr_val > 65535)
279 continue;
280
281 calc_baud = sel_clk / (brgr_val * (brdiv_val + 1));
282
283 if (baud > calc_baud)
284 bauderror = baud - calc_baud;
285 else
286 bauderror = calc_baud - baud;
287
288 /* use the values when percent error is acceptable */
289 if (((bauderror * 100) / baud) < 3) {
290 calc_baud = baud;
291 break;
292 }
293 }
294
295 /* Set the values for the new baud rate */
296 xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET);
297 xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET);
298
299 return calc_baud;
300}
301
302/*----------------------Uart Operations---------------------------*/
303
304/**
305 * xuartps_start_tx - Start transmitting bytes
306 * @port: Handle to the uart port structure
307 *
308 **/
309static void xuartps_start_tx(struct uart_port *port)
310{
311 unsigned int status, numbytes = port->fifosize;
312
313 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
314 return;
315
316 status = xuartps_readl(XUARTPS_CR_OFFSET);
317 /* Set the TX enable bit and clear the TX disable bit to enable the
318 * transmitter.
319 */
320 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
321 XUARTPS_CR_OFFSET);
322
323 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
324 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
325
326 /* Break if no more data available in the UART buffer */
327 if (uart_circ_empty(&port->state->xmit))
328 break;
329
330 /* Get the data from the UART circular buffer and
331 * write it to the xuartps's TX_FIFO register.
332 */
333 xuartps_writel(
334 port->state->xmit.buf[port->state->xmit.tail],
335 XUARTPS_FIFO_OFFSET);
336 port->icount.tx++;
337
338 /* Adjust the tail of the UART buffer and wrap
339 * the buffer if it reaches limit.
340 */
341 port->state->xmit.tail = (port->state->xmit.tail + 1) &
342 (UART_XMIT_SIZE - 1);
343 }
344
345 /* Enable the TX Empty interrupt */
346 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
347
348 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
349 uart_write_wakeup(port);
350}
351
352/**
353 * xuartps_stop_tx - Stop TX
354 * @port: Handle to the uart port structure
355 *
356 **/
357static void xuartps_stop_tx(struct uart_port *port)
358{
359 unsigned int regval;
360
361 regval = xuartps_readl(XUARTPS_CR_OFFSET);
362 regval |= XUARTPS_CR_TX_DIS;
363 /* Disable the transmitter */
364 xuartps_writel(regval, XUARTPS_CR_OFFSET);
365}
366
367/**
368 * xuartps_stop_rx - Stop RX
369 * @port: Handle to the uart port structure
370 *
371 **/
372static void xuartps_stop_rx(struct uart_port *port)
373{
374 unsigned int regval;
375
376 regval = xuartps_readl(XUARTPS_CR_OFFSET);
377 regval |= XUARTPS_CR_RX_DIS;
378 /* Disable the receiver */
379 xuartps_writel(regval, XUARTPS_CR_OFFSET);
380}
381
382/**
383 * xuartps_tx_empty - Check whether TX is empty
384 * @port: Handle to the uart port structure
385 *
386 * Returns TIOCSER_TEMT on success, 0 otherwise
387 **/
388static unsigned int xuartps_tx_empty(struct uart_port *port)
389{
390 unsigned int status;
391
392 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
393 return status ? TIOCSER_TEMT : 0;
394}
395
396/**
397 * xuartps_break_ctl - Based on the input ctl we have to start or stop
398 * transmitting char breaks
399 * @port: Handle to the uart port structure
400 * @ctl: Value based on which start or stop decision is taken
401 *
402 **/
403static void xuartps_break_ctl(struct uart_port *port, int ctl)
404{
405 unsigned int status;
406 unsigned long flags;
407
408 spin_lock_irqsave(&port->lock, flags);
409
410 status = xuartps_readl(XUARTPS_CR_OFFSET);
411
412 if (ctl == -1)
413 xuartps_writel(XUARTPS_CR_STARTBRK | status,
414 XUARTPS_CR_OFFSET);
415 else {
416 if ((status & XUARTPS_CR_STOPBRK) == 0)
417 xuartps_writel(XUARTPS_CR_STOPBRK | status,
418 XUARTPS_CR_OFFSET);
419 }
420 spin_unlock_irqrestore(&port->lock, flags);
421}
422
423/**
424 * xuartps_set_termios - termios operations, handling data length, parity,
425 * stop bits, flow control, baud rate
426 * @port: Handle to the uart port structure
427 * @termios: Handle to the input termios structure
428 * @old: Values of the previously saved termios structure
429 *
430 **/
431static void xuartps_set_termios(struct uart_port *port,
432 struct ktermios *termios, struct ktermios *old)
433{
434 unsigned int cval = 0;
435 unsigned int baud;
436 unsigned long flags;
437 unsigned int ctrl_reg, mode_reg;
438
439 spin_lock_irqsave(&port->lock, flags);
440
441 /* Empty the receive FIFO 1st before making changes */
442 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
443 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
444 xuartps_readl(XUARTPS_FIFO_OFFSET);
445 }
446
447 /* Disable the TX and RX to set baud rate */
448 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
449 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
450 XUARTPS_CR_OFFSET);
451
452 /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */
453 baud = uart_get_baud_rate(port, termios, old, 0, 10000000);
454 baud = xuartps_set_baud_rate(port, baud);
455 if (tty_termios_baud_rate(termios))
456 tty_termios_encode_baud_rate(termios, baud, baud);
457
458 /*
459 * Update the per-port timeout.
460 */
461 uart_update_timeout(port, termios->c_cflag, baud);
462
463 /* Set TX/RX Reset */
464 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
465 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
466 XUARTPS_CR_OFFSET);
467
468 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
469
470 /* Clear the RX disable and TX disable bits and then set the TX enable
471 * bit and RX enable bit to enable the transmitter and receiver.
472 */
473 xuartps_writel(
474 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
475 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
476 XUARTPS_CR_OFFSET);
477
478 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
479
480 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
481 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
482 port->ignore_status_mask = 0;
483
484 if (termios->c_iflag & INPCK)
485 port->read_status_mask |= XUARTPS_IXR_PARITY |
486 XUARTPS_IXR_FRAMING;
487
488 if (termios->c_iflag & IGNPAR)
489 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
490 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
491
492 /* ignore all characters if CREAD is not set */
493 if ((termios->c_cflag & CREAD) == 0)
494 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
495 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
496 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
497
498 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
499
500 /* Handling Data Size */
501 switch (termios->c_cflag & CSIZE) {
502 case CS6:
503 cval |= XUARTPS_MR_CHARLEN_6_BIT;
504 break;
505 case CS7:
506 cval |= XUARTPS_MR_CHARLEN_7_BIT;
507 break;
508 default:
509 case CS8:
510 cval |= XUARTPS_MR_CHARLEN_8_BIT;
511 termios->c_cflag &= ~CSIZE;
512 termios->c_cflag |= CS8;
513 break;
514 }
515
516 /* Handling Parity and Stop Bits length */
517 if (termios->c_cflag & CSTOPB)
518 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
519 else
520 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
521
522 if (termios->c_cflag & PARENB) {
523 /* Mark or Space parity */
524 if (termios->c_cflag & CMSPAR) {
525 if (termios->c_cflag & PARODD)
526 cval |= XUARTPS_MR_PARITY_MARK;
527 else
528 cval |= XUARTPS_MR_PARITY_SPACE;
529 } else if (termios->c_cflag & PARODD)
530 cval |= XUARTPS_MR_PARITY_ODD;
531 else
532 cval |= XUARTPS_MR_PARITY_EVEN;
533 } else
534 cval |= XUARTPS_MR_PARITY_NONE;
535 xuartps_writel(cval , XUARTPS_MR_OFFSET);
536
537 spin_unlock_irqrestore(&port->lock, flags);
538}
539
540/**
541 * xuartps_startup - Called when an application opens a xuartps port
542 * @port: Handle to the uart port structure
543 *
544 * Returns 0 on success, negative error otherwise
545 **/
546static int xuartps_startup(struct uart_port *port)
547{
548 unsigned int retval = 0, status = 0;
549
550 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
551 (void *)port);
552 if (retval)
553 return retval;
554
555 /* Disable the TX and RX */
556 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
557 XUARTPS_CR_OFFSET);
558
559 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
560 * no break chars.
561 */
562 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
563 XUARTPS_CR_OFFSET);
564
565 status = xuartps_readl(XUARTPS_CR_OFFSET);
566
567 /* Clear the RX disable and TX disable bits and then set the TX enable
568 * bit and RX enable bit to enable the transmitter and receiver.
569 */
570 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
571 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
572 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
573
574 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
575 * no parity.
576 */
577 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
578 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
579 XUARTPS_MR_OFFSET);
580
581 /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */
582 xuartps_writel(14, XUARTPS_RXWM_OFFSET);
583
584 /* Receive Timeout register is enabled with value of 10 */
585 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
586
587
588 /* Set the Interrupt Registers with desired interrupts */
589 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
590 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
591 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
592 xuartps_writel(~(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
593 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
594 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT), XUARTPS_IDR_OFFSET);
595
596 return retval;
597}
598
599/**
600 * xuartps_shutdown - Called when an application closes a xuartps port
601 * @port: Handle to the uart port structure
602 *
603 **/
604static void xuartps_shutdown(struct uart_port *port)
605{
606 int status;
607
608 /* Disable interrupts */
609 status = xuartps_readl(XUARTPS_IMR_OFFSET);
610 xuartps_writel(status, XUARTPS_IDR_OFFSET);
611
612 /* Disable the TX and RX */
613 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
614 XUARTPS_CR_OFFSET);
615 free_irq(port->irq, port);
616}
617
618/**
619 * xuartps_type - Set UART type to xuartps port
620 * @port: Handle to the uart port structure
621 *
622 * Returns string on success, NULL otherwise
623 **/
624static const char *xuartps_type(struct uart_port *port)
625{
626 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
627}
628
629/**
630 * xuartps_verify_port - Verify the port params
631 * @port: Handle to the uart port structure
632 * @ser: Handle to the structure whose members are compared
633 *
634 * Returns 0 if success otherwise -EINVAL
635 **/
636static int xuartps_verify_port(struct uart_port *port,
637 struct serial_struct *ser)
638{
639 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
640 return -EINVAL;
641 if (port->irq != ser->irq)
642 return -EINVAL;
643 if (ser->io_type != UPIO_MEM)
644 return -EINVAL;
645 if (port->iobase != ser->port)
646 return -EINVAL;
647 if (ser->hub6 != 0)
648 return -EINVAL;
649 return 0;
650}
651
652/**
653 * xuartps_request_port - Claim the memory region attached to xuartps port,
654 * called when the driver adds a xuartps port via
655 * uart_add_one_port()
656 * @port: Handle to the uart port structure
657 *
658 * Returns 0, -ENOMEM if request fails
659 **/
660static int xuartps_request_port(struct uart_port *port)
661{
662 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
663 XUARTPS_NAME)) {
664 return -ENOMEM;
665 }
666
667 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
668 if (!port->membase) {
669 dev_err(port->dev, "Unable to map registers\n");
670 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
671 return -ENOMEM;
672 }
673 return 0;
674}
675
676/**
677 * xuartps_release_port - Release the memory region attached to a xuartps
678 * port, called when the driver removes a xuartps
679 * port via uart_remove_one_port().
680 * @port: Handle to the uart port structure
681 *
682 **/
683static void xuartps_release_port(struct uart_port *port)
684{
685 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
686 iounmap(port->membase);
687 port->membase = NULL;
688}
689
690/**
691 * xuartps_config_port - Configure xuartps, called when the driver adds a
692 * xuartps port
693 * @port: Handle to the uart port structure
694 * @flags: If any
695 *
696 **/
697static void xuartps_config_port(struct uart_port *port, int flags)
698{
699 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
700 port->type = PORT_XUARTPS;
701}
702
703/**
704 * xuartps_get_mctrl - Get the modem control state
705 *
706 * @port: Handle to the uart port structure
707 *
708 * Returns the modem control state
709 *
710 **/
711static unsigned int xuartps_get_mctrl(struct uart_port *port)
712{
713 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
714}
715
716static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
717{
718 /* N/A */
719}
720
721static void xuartps_enable_ms(struct uart_port *port)
722{
723 /* N/A */
724}
725
726/** The UART operations structure
727 */
728static struct uart_ops xuartps_ops = {
729 .set_mctrl = xuartps_set_mctrl,
730 .get_mctrl = xuartps_get_mctrl,
731 .enable_ms = xuartps_enable_ms,
732
733 .start_tx = xuartps_start_tx, /* Start transmitting */
734 .stop_tx = xuartps_stop_tx, /* Stop transmission */
735 .stop_rx = xuartps_stop_rx, /* Stop reception */
736 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
737 .break_ctl = xuartps_break_ctl, /* Start/stop
738 * transmitting break
739 */
740 .set_termios = xuartps_set_termios, /* Set termios */
741 .startup = xuartps_startup, /* App opens xuartps */
742 .shutdown = xuartps_shutdown, /* App closes xuartps */
743 .type = xuartps_type, /* Set UART type */
744 .verify_port = xuartps_verify_port, /* Verification of port
745 * params
746 */
747 .request_port = xuartps_request_port, /* Claim resources
748 * associated with a
749 * xuartps port
750 */
751 .release_port = xuartps_release_port, /* Release resources
752 * associated with a
753 * xuartps port
754 */
755 .config_port = xuartps_config_port, /* Configure when driver
756 * adds a xuartps port
757 */
758};
759
760static struct uart_port xuartps_port[2];
761
762/**
763 * xuartps_get_port - Configure the port from the platform device resource
764 * info
765 *
766 * Returns a pointer to a uart_port or NULL for failure
767 **/
768static struct uart_port *xuartps_get_port(void)
769{
770 struct uart_port *port;
771 int id;
772
773 /* Find the next unused port */
774 for (id = 0; id < XUARTPS_NR_PORTS; id++)
775 if (xuartps_port[id].mapbase == 0)
776 break;
777
778 if (id >= XUARTPS_NR_PORTS)
779 return NULL;
780
781 port = &xuartps_port[id];
782
783 /* At this point, we've got an empty uart_port struct, initialize it */
784 spin_lock_init(&port->lock);
785 port->membase = NULL;
786 port->iobase = 1; /* mark port in use */
787 port->irq = 0;
788 port->type = PORT_UNKNOWN;
789 port->iotype = UPIO_MEM32;
790 port->flags = UPF_BOOT_AUTOCONF;
791 port->ops = &xuartps_ops;
792 port->fifosize = XUARTPS_FIFO_SIZE;
793 port->line = id;
794 port->dev = NULL;
795 return port;
796}
797
798/*-----------------------Console driver operations--------------------------*/
799
800#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
801/**
802 * xuartps_console_wait_tx - Wait for the TX to be full
803 * @port: Handle to the uart port structure
804 *
805 **/
806static void xuartps_console_wait_tx(struct uart_port *port)
807{
808 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
809 != XUARTPS_SR_TXEMPTY)
810 barrier();
811}
812
813/**
814 * xuartps_console_putchar - write the character to the FIFO buffer
815 * @port: Handle to the uart port structure
816 * @ch: Character to be written
817 *
818 **/
819static void xuartps_console_putchar(struct uart_port *port, int ch)
820{
821 xuartps_console_wait_tx(port);
822 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
823}
824
825/**
826 * xuartps_console_write - perform write operation
827 * @port: Handle to the uart port structure
828 * @s: Pointer to character array
829 * @count: No of characters
830 **/
831static void xuartps_console_write(struct console *co, const char *s,
832 unsigned int count)
833{
834 struct uart_port *port = &xuartps_port[co->index];
835 unsigned long flags;
836 unsigned int imr;
837 int locked = 1;
838
839 if (oops_in_progress)
840 locked = spin_trylock_irqsave(&port->lock, flags);
841 else
842 spin_lock_irqsave(&port->lock, flags);
843
844 /* save and disable interrupt */
845 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
846 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
847
848 uart_console_write(port, s, count, xuartps_console_putchar);
849 xuartps_console_wait_tx(port);
850
851 /* restore interrupt state, it seems like there may be a h/w bug
852 * in that the interrupt enable register should not need to be
853 * written based on the data sheet
854 */
855 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
856 xuartps_writel(imr, XUARTPS_IER_OFFSET);
857
858 if (locked)
859 spin_unlock_irqrestore(&port->lock, flags);
860}
861
862/**
863 * xuartps_console_setup - Initialize the uart to default config
864 * @co: Console handle
865 * @options: Initial settings of uart
866 *
867 * Returns 0, -ENODEV if no device
868 **/
869static int __init xuartps_console_setup(struct console *co, char *options)
870{
871 struct uart_port *port = &xuartps_port[co->index];
872 int baud = 9600;
873 int bits = 8;
874 int parity = 'n';
875 int flow = 'n';
876
877 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
878 return -EINVAL;
879
880 if (!port->mapbase) {
881 pr_debug("console on ttyPS%i not present\n", co->index);
882 return -ENODEV;
883 }
884
885 if (options)
886 uart_parse_options(options, &baud, &parity, &bits, &flow);
887
888 return uart_set_options(port, co, baud, parity, bits, flow);
889}
890
891static struct uart_driver xuartps_uart_driver;
892
893static struct console xuartps_console = {
894 .name = XUARTPS_TTY_NAME,
895 .write = xuartps_console_write,
896 .device = uart_console_device,
897 .setup = xuartps_console_setup,
898 .flags = CON_PRINTBUFFER,
899 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
900 .data = &xuartps_uart_driver,
901};
902
903/**
904 * xuartps_console_init - Initialization call
905 *
906 * Returns 0 on success, negative error otherwise
907 **/
908static int __init xuartps_console_init(void)
909{
910 register_console(&xuartps_console);
911 return 0;
912}
913
914console_initcall(xuartps_console_init);
915
916#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
917
918/** Structure Definitions
919 */
920static struct uart_driver xuartps_uart_driver = {
921 .owner = THIS_MODULE, /* Owner */
922 .driver_name = XUARTPS_NAME, /* Driver name */
923 .dev_name = XUARTPS_TTY_NAME, /* Node name */
924 .major = XUARTPS_MAJOR, /* Major number */
925 .minor = XUARTPS_MINOR, /* Minor number */
926 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
927#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
928 .cons = &xuartps_console, /* Console */
929#endif
930};
931
932/* ---------------------------------------------------------------------
933 * Platform bus binding
934 */
935/**
936 * xuartps_probe - Platform driver probe
937 * @pdev: Pointer to the platform device structure
938 *
939 * Returns 0 on success, negative error otherwise
940 **/
941static int __devinit xuartps_probe(struct platform_device *pdev)
942{
943 int rc;
944 struct uart_port *port;
945 struct resource *res, *res2;
946 int clk = 0;
947
948#ifdef CONFIG_OF
949 const unsigned int *prop;
950
951 prop = of_get_property(pdev->dev.of_node, "clock", NULL);
952 if (prop)
953 clk = be32_to_cpup(prop);
954#else
955 clk = *((unsigned int *)(pdev->dev.platform_data));
956#endif
957 if (!clk) {
958 dev_err(&pdev->dev, "no clock specified\n");
959 return -ENODEV;
960 }
961
962 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
963 if (!res)
964 return -ENODEV;
965
966 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
967 if (!res2)
968 return -ENODEV;
969
970 /* Initialize the port structure */
971 port = xuartps_get_port();
972
973 if (!port) {
974 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
975 return -ENODEV;
976 } else {
977 /* Register the port.
978 * This function also registers this device with the tty layer
979 * and triggers invocation of the config_port() entry point.
980 */
981 port->mapbase = res->start;
982 port->irq = res2->start;
983 port->dev = &pdev->dev;
984 port->uartclk = clk;
985 dev_set_drvdata(&pdev->dev, port);
986 rc = uart_add_one_port(&xuartps_uart_driver, port);
987 if (rc) {
988 dev_err(&pdev->dev,
989 "uart_add_one_port() failed; err=%i\n", rc);
990 dev_set_drvdata(&pdev->dev, NULL);
991 return rc;
992 }
993 return 0;
994 }
995}
996
997/**
998 * xuartps_remove - called when the platform driver is unregistered
999 * @pdev: Pointer to the platform device structure
1000 *
1001 * Returns 0 on success, negative error otherwise
1002 **/
1003static int __devexit xuartps_remove(struct platform_device *pdev)
1004{
1005 struct uart_port *port = dev_get_drvdata(&pdev->dev);
1006 int rc = 0;
1007
1008 /* Remove the xuartps port from the serial core */
1009 if (port) {
1010 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1011 dev_set_drvdata(&pdev->dev, NULL);
1012 port->mapbase = 0;
1013 }
1014 return rc;
1015}
1016
1017/**
1018 * xuartps_suspend - suspend event
1019 * @pdev: Pointer to the platform device structure
1020 * @state: State of the device
1021 *
1022 * Returns 0
1023 **/
1024static int xuartps_suspend(struct platform_device *pdev, pm_message_t state)
1025{
1026 /* Call the API provided in serial_core.c file which handles
1027 * the suspend.
1028 */
1029 uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
1030 return 0;
1031}
1032
1033/**
1034 * xuartps_resume - Resume after a previous suspend
1035 * @pdev: Pointer to the platform device structure
1036 *
1037 * Returns 0
1038 **/
1039static int xuartps_resume(struct platform_device *pdev)
1040{
1041 uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
1042 return 0;
1043}
1044
1045/* Match table for of_platform binding */
1046
1047#ifdef CONFIG_OF
1048static struct of_device_id xuartps_of_match[] __devinitdata = {
1049 { .compatible = "xlnx,xuartps", },
1050 {}
1051};
1052MODULE_DEVICE_TABLE(of, xuartps_of_match);
1053#else
1054#define xuartps_of_match NULL
1055#endif
1056
1057static struct platform_driver xuartps_platform_driver = {
1058 .probe = xuartps_probe, /* Probe method */
1059 .remove = __exit_p(xuartps_remove), /* Detach method */
1060 .suspend = xuartps_suspend, /* Suspend */
1061 .resume = xuartps_resume, /* Resume after a suspend */
1062 .driver = {
1063 .owner = THIS_MODULE,
1064 .name = XUARTPS_NAME, /* Driver name */
1065 .of_match_table = xuartps_of_match,
1066 },
1067};
1068
1069/* ---------------------------------------------------------------------
1070 * Module Init and Exit
1071 */
1072/**
1073 * xuartps_init - Initial driver registration call
1074 *
1075 * Returns whether the registration was successful or not
1076 **/
1077static int __init xuartps_init(void)
1078{
1079 int retval = 0;
1080
1081 /* Register the xuartps driver with the serial core */
1082 retval = uart_register_driver(&xuartps_uart_driver);
1083 if (retval)
1084 return retval;
1085
1086 /* Register the platform driver */
1087 retval = platform_driver_register(&xuartps_platform_driver);
1088 if (retval)
1089 uart_unregister_driver(&xuartps_uart_driver);
1090
1091 return retval;
1092}
1093
1094/**
1095 * xuartps_exit - Driver unregistration call
1096 **/
1097static void __exit xuartps_exit(void)
1098{
1099 /* The order of unregistration is important. Unregister the
1100 * UART driver before the platform driver crashes the system.
1101 */
1102
1103 /* Unregister the platform driver */
1104 platform_driver_unregister(&xuartps_platform_driver);
1105
1106 /* Unregister the xuartps driver */
1107 uart_unregister_driver(&xuartps_uart_driver);
1108}
1109
1110module_init(xuartps_init);
1111module_exit(xuartps_exit);
1112
1113MODULE_DESCRIPTION("Driver for PS UART");
1114MODULE_AUTHOR("Xilinx Inc.");
1115MODULE_LICENSE("GPL");
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