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61ec9016 JL |
1 | /* |
2 | * Xilinx PS UART driver | |
3 | * | |
4 | * 2011 (c) Xilinx Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it | |
7 | * and/or modify it under the terms of the GNU General Public | |
8 | * License as published by the Free Software Foundation; | |
9 | * either version 2 of the License, or (at your option) any | |
10 | * later version. | |
11 | * | |
12 | */ | |
13 | ||
0c0c47bc VL |
14 | #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
15 | #define SUPPORT_SYSRQ | |
16 | #endif | |
17 | ||
61ec9016 | 18 | #include <linux/platform_device.h> |
ee160a38 | 19 | #include <linux/serial.h> |
0c0c47bc | 20 | #include <linux/console.h> |
61ec9016 | 21 | #include <linux/serial_core.h> |
30e1e285 | 22 | #include <linux/slab.h> |
ee160a38 JS |
23 | #include <linux/tty.h> |
24 | #include <linux/tty_flip.h> | |
2326669c | 25 | #include <linux/clk.h> |
61ec9016 JL |
26 | #include <linux/irq.h> |
27 | #include <linux/io.h> | |
28 | #include <linux/of.h> | |
578b9ce0 | 29 | #include <linux/module.h> |
61ec9016 JL |
30 | |
31 | #define XUARTPS_TTY_NAME "ttyPS" | |
32 | #define XUARTPS_NAME "xuartps" | |
33 | #define XUARTPS_MAJOR 0 /* use dynamic node allocation */ | |
34 | #define XUARTPS_MINOR 0 /* works best with devtmpfs */ | |
35 | #define XUARTPS_NR_PORTS 2 | |
85baf542 | 36 | #define XUARTPS_FIFO_SIZE 64 /* FIFO size */ |
61ec9016 JL |
37 | #define XUARTPS_REGISTER_SPACE 0xFFF |
38 | ||
39 | #define xuartps_readl(offset) ioread32(port->membase + offset) | |
40 | #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset) | |
41 | ||
85baf542 S |
42 | /* Rx Trigger level */ |
43 | static int rx_trigger_level = 56; | |
44 | module_param(rx_trigger_level, uint, S_IRUGO); | |
45 | MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); | |
46 | ||
47 | /* Rx Timeout */ | |
48 | static int rx_timeout = 10; | |
49 | module_param(rx_timeout, uint, S_IRUGO); | |
50 | MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); | |
51 | ||
61ec9016 JL |
52 | /********************************Register Map********************************/ |
53 | /** UART | |
54 | * | |
55 | * Register offsets for the UART. | |
56 | * | |
57 | */ | |
58 | #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */ | |
59 | #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */ | |
60 | #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ | |
61 | #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ | |
62 | #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ | |
63 | #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ | |
64 | #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ | |
65 | #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ | |
66 | #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ | |
67 | #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ | |
68 | #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ | |
69 | #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */ | |
70 | #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ | |
71 | #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ | |
72 | #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ | |
73 | #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse | |
74 | Width [15:0] */ | |
75 | #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse | |
76 | Width [7:0] */ | |
77 | #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */ | |
78 | ||
79 | /** Control Register | |
80 | * | |
81 | * The Control register (CR) controls the major functions of the device. | |
82 | * | |
83 | * Control Register Bit Definitions | |
84 | */ | |
85 | #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */ | |
86 | #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */ | |
87 | #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */ | |
88 | #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */ | |
89 | #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */ | |
90 | #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */ | |
91 | #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */ | |
92 | #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */ | |
93 | #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ | |
94 | ||
95 | /** Mode Register | |
96 | * | |
97 | * The mode register (MR) defines the mode of transfer as well as the data | |
98 | * format. If this register is modified during transmission or reception, | |
99 | * data validity cannot be guaranteed. | |
100 | * | |
101 | * Mode Register Bit Definitions | |
102 | * | |
103 | */ | |
104 | #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ | |
105 | #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ | |
106 | #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */ | |
107 | ||
108 | #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ | |
109 | #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ | |
110 | ||
111 | #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */ | |
112 | #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ | |
113 | #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ | |
114 | #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ | |
115 | #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ | |
116 | ||
117 | #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ | |
118 | #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ | |
119 | #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ | |
120 | ||
121 | /** Interrupt Registers | |
122 | * | |
123 | * Interrupt control logic uses the interrupt enable register (IER) and the | |
124 | * interrupt disable register (IDR) to set the value of the bits in the | |
125 | * interrupt mask register (IMR). The IMR determines whether to pass an | |
126 | * interrupt to the interrupt status register (ISR). | |
127 | * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an | |
128 | * interrupt. IMR and ISR are read only, and IER and IDR are write only. | |
129 | * Reading either IER or IDR returns 0x00. | |
130 | * | |
131 | * All four registers have the same bit definitions. | |
132 | */ | |
133 | #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ | |
134 | #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */ | |
135 | #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */ | |
136 | #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ | |
137 | #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ | |
138 | #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ | |
139 | #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ | |
140 | #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ | |
141 | #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ | |
142 | #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ | |
143 | #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */ | |
144 | ||
0c0c47bc VL |
145 | /* Goes in read_status_mask for break detection as the HW doesn't do it*/ |
146 | #define XUARTPS_IXR_BRK 0x80000000 | |
147 | ||
61ec9016 JL |
148 | /** Channel Status Register |
149 | * | |
150 | * The channel status register (CSR) is provided to enable the control logic | |
151 | * to monitor the status of bits in the channel interrupt status register, | |
152 | * even if these are masked out by the interrupt mask register. | |
153 | */ | |
154 | #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ | |
155 | #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ | |
156 | #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */ | |
157 | #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */ | |
158 | ||
30e1e285 SB |
159 | /** |
160 | * struct xuartps - device data | |
161 | * @refclk Reference clock | |
162 | * @aperclk APB clock | |
163 | */ | |
164 | struct xuartps { | |
165 | struct clk *refclk; | |
166 | struct clk *aperclk; | |
167 | }; | |
168 | ||
61ec9016 JL |
169 | /** |
170 | * xuartps_isr - Interrupt handler | |
171 | * @irq: Irq number | |
172 | * @dev_id: Id of the port | |
173 | * | |
174 | * Returns IRQHANDLED | |
175 | **/ | |
176 | static irqreturn_t xuartps_isr(int irq, void *dev_id) | |
177 | { | |
178 | struct uart_port *port = (struct uart_port *)dev_id; | |
61ec9016 JL |
179 | unsigned long flags; |
180 | unsigned int isrstatus, numbytes; | |
181 | unsigned int data; | |
182 | char status = TTY_NORMAL; | |
183 | ||
61ec9016 JL |
184 | spin_lock_irqsave(&port->lock, flags); |
185 | ||
186 | /* Read the interrupt status register to determine which | |
187 | * interrupt(s) is/are active. | |
188 | */ | |
189 | isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET); | |
190 | ||
0c0c47bc VL |
191 | /* |
192 | * There is no hardware break detection, so we interpret framing | |
193 | * error with all-zeros data as a break sequence. Most of the time, | |
194 | * there's another non-zero byte at the end of the sequence. | |
195 | */ | |
196 | ||
197 | if (isrstatus & XUARTPS_IXR_FRAMING) { | |
198 | while (!(xuartps_readl(XUARTPS_SR_OFFSET) & | |
199 | XUARTPS_SR_RXEMPTY)) { | |
200 | if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) { | |
201 | port->read_status_mask |= XUARTPS_IXR_BRK; | |
202 | isrstatus &= ~XUARTPS_IXR_FRAMING; | |
203 | } | |
204 | } | |
205 | xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET); | |
206 | } | |
207 | ||
61ec9016 JL |
208 | /* drop byte with parity error if IGNPAR specified */ |
209 | if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY) | |
210 | isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT); | |
211 | ||
212 | isrstatus &= port->read_status_mask; | |
213 | isrstatus &= ~port->ignore_status_mask; | |
214 | ||
215 | if ((isrstatus & XUARTPS_IXR_TOUT) || | |
216 | (isrstatus & XUARTPS_IXR_RXTRIG)) { | |
217 | /* Receive Timeout Interrupt */ | |
218 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & | |
219 | XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { | |
220 | data = xuartps_readl(XUARTPS_FIFO_OFFSET); | |
0c0c47bc VL |
221 | |
222 | /* Non-NULL byte after BREAK is garbage (99%) */ | |
223 | if (data && (port->read_status_mask & | |
224 | XUARTPS_IXR_BRK)) { | |
225 | port->read_status_mask &= ~XUARTPS_IXR_BRK; | |
226 | port->icount.brk++; | |
227 | if (uart_handle_break(port)) | |
228 | continue; | |
229 | } | |
230 | ||
231 | /* | |
232 | * uart_handle_sysrq_char() doesn't work if | |
233 | * spinlocked, for some reason | |
234 | */ | |
235 | if (port->sysrq) { | |
236 | spin_unlock(&port->lock); | |
237 | if (uart_handle_sysrq_char(port, | |
238 | (unsigned char)data)) { | |
239 | spin_lock(&port->lock); | |
240 | continue; | |
241 | } | |
242 | spin_lock(&port->lock); | |
243 | } | |
244 | ||
61ec9016 JL |
245 | port->icount.rx++; |
246 | ||
247 | if (isrstatus & XUARTPS_IXR_PARITY) { | |
248 | port->icount.parity++; | |
249 | status = TTY_PARITY; | |
250 | } else if (isrstatus & XUARTPS_IXR_FRAMING) { | |
251 | port->icount.frame++; | |
252 | status = TTY_FRAME; | |
253 | } else if (isrstatus & XUARTPS_IXR_OVERRUN) | |
254 | port->icount.overrun++; | |
255 | ||
2e124b4a JS |
256 | uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN, |
257 | data, status); | |
61ec9016 JL |
258 | } |
259 | spin_unlock(&port->lock); | |
2e124b4a | 260 | tty_flip_buffer_push(&port->state->port); |
61ec9016 JL |
261 | spin_lock(&port->lock); |
262 | } | |
263 | ||
264 | /* Dispatch an appropriate handler */ | |
265 | if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) { | |
266 | if (uart_circ_empty(&port->state->xmit)) { | |
267 | xuartps_writel(XUARTPS_IXR_TXEMPTY, | |
268 | XUARTPS_IDR_OFFSET); | |
269 | } else { | |
270 | numbytes = port->fifosize; | |
271 | /* Break if no more data available in the UART buffer */ | |
272 | while (numbytes--) { | |
273 | if (uart_circ_empty(&port->state->xmit)) | |
274 | break; | |
275 | /* Get the data from the UART circular buffer | |
276 | * and write it to the xuartps's TX_FIFO | |
277 | * register. | |
278 | */ | |
279 | xuartps_writel( | |
280 | port->state->xmit.buf[port->state->xmit. | |
281 | tail], XUARTPS_FIFO_OFFSET); | |
282 | ||
283 | port->icount.tx++; | |
284 | ||
285 | /* Adjust the tail of the UART buffer and wrap | |
286 | * the buffer if it reaches limit. | |
287 | */ | |
288 | port->state->xmit.tail = | |
289 | (port->state->xmit.tail + 1) & \ | |
290 | (UART_XMIT_SIZE - 1); | |
291 | } | |
292 | ||
293 | if (uart_circ_chars_pending( | |
294 | &port->state->xmit) < WAKEUP_CHARS) | |
295 | uart_write_wakeup(port); | |
296 | } | |
297 | } | |
298 | ||
299 | xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET); | |
300 | ||
301 | /* be sure to release the lock and tty before leaving */ | |
302 | spin_unlock_irqrestore(&port->lock, flags); | |
61ec9016 JL |
303 | |
304 | return IRQ_HANDLED; | |
305 | } | |
306 | ||
307 | /** | |
308 | * xuartps_set_baud_rate - Calculate and set the baud rate | |
309 | * @port: Handle to the uart port structure | |
310 | * @baud: Baud rate to set | |
311 | * | |
312 | * Returns baud rate, requested baud when possible, or actual baud when there | |
313 | * was too much error | |
314 | **/ | |
315 | static unsigned int xuartps_set_baud_rate(struct uart_port *port, | |
316 | unsigned int baud) | |
317 | { | |
318 | unsigned int sel_clk; | |
319 | unsigned int calc_baud = 0; | |
320 | unsigned int brgr_val, brdiv_val; | |
321 | unsigned int bauderror; | |
322 | ||
323 | /* Formula to obtain baud rate is | |
324 | * baud_tx/rx rate = sel_clk/CD * (BDIV + 1) | |
325 | * input_clk = (Uart User Defined Clock or Apb Clock) | |
326 | * depends on UCLKEN in MR Reg | |
327 | * sel_clk = input_clk or input_clk/8; | |
328 | * depends on CLKS in MR reg | |
329 | * CD and BDIV depends on values in | |
330 | * baud rate generate register | |
331 | * baud rate clock divisor register | |
332 | */ | |
333 | sel_clk = port->uartclk; | |
334 | if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL) | |
335 | sel_clk = sel_clk / 8; | |
336 | ||
337 | /* Find the best values for baud generation */ | |
338 | for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) { | |
339 | ||
340 | brgr_val = sel_clk / (baud * (brdiv_val + 1)); | |
341 | if (brgr_val < 2 || brgr_val > 65535) | |
342 | continue; | |
343 | ||
344 | calc_baud = sel_clk / (brgr_val * (brdiv_val + 1)); | |
345 | ||
346 | if (baud > calc_baud) | |
347 | bauderror = baud - calc_baud; | |
348 | else | |
349 | bauderror = calc_baud - baud; | |
350 | ||
351 | /* use the values when percent error is acceptable */ | |
352 | if (((bauderror * 100) / baud) < 3) { | |
353 | calc_baud = baud; | |
354 | break; | |
355 | } | |
356 | } | |
357 | ||
358 | /* Set the values for the new baud rate */ | |
359 | xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET); | |
360 | xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET); | |
361 | ||
362 | return calc_baud; | |
363 | } | |
364 | ||
365 | /*----------------------Uart Operations---------------------------*/ | |
366 | ||
367 | /** | |
368 | * xuartps_start_tx - Start transmitting bytes | |
369 | * @port: Handle to the uart port structure | |
370 | * | |
371 | **/ | |
372 | static void xuartps_start_tx(struct uart_port *port) | |
373 | { | |
374 | unsigned int status, numbytes = port->fifosize; | |
375 | ||
376 | if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) | |
377 | return; | |
378 | ||
379 | status = xuartps_readl(XUARTPS_CR_OFFSET); | |
380 | /* Set the TX enable bit and clear the TX disable bit to enable the | |
381 | * transmitter. | |
382 | */ | |
383 | xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, | |
384 | XUARTPS_CR_OFFSET); | |
385 | ||
386 | while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET) | |
387 | & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) { | |
388 | ||
389 | /* Break if no more data available in the UART buffer */ | |
390 | if (uart_circ_empty(&port->state->xmit)) | |
391 | break; | |
392 | ||
393 | /* Get the data from the UART circular buffer and | |
394 | * write it to the xuartps's TX_FIFO register. | |
395 | */ | |
396 | xuartps_writel( | |
397 | port->state->xmit.buf[port->state->xmit.tail], | |
398 | XUARTPS_FIFO_OFFSET); | |
399 | port->icount.tx++; | |
400 | ||
401 | /* Adjust the tail of the UART buffer and wrap | |
402 | * the buffer if it reaches limit. | |
403 | */ | |
404 | port->state->xmit.tail = (port->state->xmit.tail + 1) & | |
405 | (UART_XMIT_SIZE - 1); | |
406 | } | |
85baf542 | 407 | xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET); |
61ec9016 JL |
408 | /* Enable the TX Empty interrupt */ |
409 | xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET); | |
410 | ||
411 | if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) | |
412 | uart_write_wakeup(port); | |
413 | } | |
414 | ||
415 | /** | |
416 | * xuartps_stop_tx - Stop TX | |
417 | * @port: Handle to the uart port structure | |
418 | * | |
419 | **/ | |
420 | static void xuartps_stop_tx(struct uart_port *port) | |
421 | { | |
422 | unsigned int regval; | |
423 | ||
424 | regval = xuartps_readl(XUARTPS_CR_OFFSET); | |
425 | regval |= XUARTPS_CR_TX_DIS; | |
426 | /* Disable the transmitter */ | |
427 | xuartps_writel(regval, XUARTPS_CR_OFFSET); | |
428 | } | |
429 | ||
430 | /** | |
431 | * xuartps_stop_rx - Stop RX | |
432 | * @port: Handle to the uart port structure | |
433 | * | |
434 | **/ | |
435 | static void xuartps_stop_rx(struct uart_port *port) | |
436 | { | |
437 | unsigned int regval; | |
438 | ||
439 | regval = xuartps_readl(XUARTPS_CR_OFFSET); | |
440 | regval |= XUARTPS_CR_RX_DIS; | |
441 | /* Disable the receiver */ | |
442 | xuartps_writel(regval, XUARTPS_CR_OFFSET); | |
443 | } | |
444 | ||
445 | /** | |
446 | * xuartps_tx_empty - Check whether TX is empty | |
447 | * @port: Handle to the uart port structure | |
448 | * | |
449 | * Returns TIOCSER_TEMT on success, 0 otherwise | |
450 | **/ | |
451 | static unsigned int xuartps_tx_empty(struct uart_port *port) | |
452 | { | |
453 | unsigned int status; | |
454 | ||
455 | status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY; | |
456 | return status ? TIOCSER_TEMT : 0; | |
457 | } | |
458 | ||
459 | /** | |
460 | * xuartps_break_ctl - Based on the input ctl we have to start or stop | |
461 | * transmitting char breaks | |
462 | * @port: Handle to the uart port structure | |
463 | * @ctl: Value based on which start or stop decision is taken | |
464 | * | |
465 | **/ | |
466 | static void xuartps_break_ctl(struct uart_port *port, int ctl) | |
467 | { | |
468 | unsigned int status; | |
469 | unsigned long flags; | |
470 | ||
471 | spin_lock_irqsave(&port->lock, flags); | |
472 | ||
473 | status = xuartps_readl(XUARTPS_CR_OFFSET); | |
474 | ||
475 | if (ctl == -1) | |
476 | xuartps_writel(XUARTPS_CR_STARTBRK | status, | |
477 | XUARTPS_CR_OFFSET); | |
478 | else { | |
479 | if ((status & XUARTPS_CR_STOPBRK) == 0) | |
480 | xuartps_writel(XUARTPS_CR_STOPBRK | status, | |
481 | XUARTPS_CR_OFFSET); | |
482 | } | |
483 | spin_unlock_irqrestore(&port->lock, flags); | |
484 | } | |
485 | ||
486 | /** | |
487 | * xuartps_set_termios - termios operations, handling data length, parity, | |
488 | * stop bits, flow control, baud rate | |
489 | * @port: Handle to the uart port structure | |
490 | * @termios: Handle to the input termios structure | |
491 | * @old: Values of the previously saved termios structure | |
492 | * | |
493 | **/ | |
494 | static void xuartps_set_termios(struct uart_port *port, | |
495 | struct ktermios *termios, struct ktermios *old) | |
496 | { | |
497 | unsigned int cval = 0; | |
498 | unsigned int baud; | |
499 | unsigned long flags; | |
500 | unsigned int ctrl_reg, mode_reg; | |
501 | ||
502 | spin_lock_irqsave(&port->lock, flags); | |
503 | ||
504 | /* Empty the receive FIFO 1st before making changes */ | |
505 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & | |
506 | XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { | |
507 | xuartps_readl(XUARTPS_FIFO_OFFSET); | |
508 | } | |
509 | ||
510 | /* Disable the TX and RX to set baud rate */ | |
511 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | | |
512 | (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), | |
513 | XUARTPS_CR_OFFSET); | |
514 | ||
515 | /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */ | |
516 | baud = uart_get_baud_rate(port, termios, old, 0, 10000000); | |
517 | baud = xuartps_set_baud_rate(port, baud); | |
518 | if (tty_termios_baud_rate(termios)) | |
519 | tty_termios_encode_baud_rate(termios, baud, baud); | |
520 | ||
521 | /* | |
522 | * Update the per-port timeout. | |
523 | */ | |
524 | uart_update_timeout(port, termios->c_cflag, baud); | |
525 | ||
526 | /* Set TX/RX Reset */ | |
527 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | | |
528 | (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), | |
529 | XUARTPS_CR_OFFSET); | |
530 | ||
531 | ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); | |
532 | ||
533 | /* Clear the RX disable and TX disable bits and then set the TX enable | |
534 | * bit and RX enable bit to enable the transmitter and receiver. | |
535 | */ | |
536 | xuartps_writel( | |
537 | (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | |
538 | | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), | |
539 | XUARTPS_CR_OFFSET); | |
540 | ||
85baf542 | 541 | xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); |
61ec9016 JL |
542 | |
543 | port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG | | |
544 | XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT; | |
545 | port->ignore_status_mask = 0; | |
546 | ||
547 | if (termios->c_iflag & INPCK) | |
548 | port->read_status_mask |= XUARTPS_IXR_PARITY | | |
549 | XUARTPS_IXR_FRAMING; | |
550 | ||
551 | if (termios->c_iflag & IGNPAR) | |
552 | port->ignore_status_mask |= XUARTPS_IXR_PARITY | | |
553 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; | |
554 | ||
555 | /* ignore all characters if CREAD is not set */ | |
556 | if ((termios->c_cflag & CREAD) == 0) | |
557 | port->ignore_status_mask |= XUARTPS_IXR_RXTRIG | | |
558 | XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | | |
559 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; | |
560 | ||
561 | mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); | |
562 | ||
563 | /* Handling Data Size */ | |
564 | switch (termios->c_cflag & CSIZE) { | |
565 | case CS6: | |
566 | cval |= XUARTPS_MR_CHARLEN_6_BIT; | |
567 | break; | |
568 | case CS7: | |
569 | cval |= XUARTPS_MR_CHARLEN_7_BIT; | |
570 | break; | |
571 | default: | |
572 | case CS8: | |
573 | cval |= XUARTPS_MR_CHARLEN_8_BIT; | |
574 | termios->c_cflag &= ~CSIZE; | |
575 | termios->c_cflag |= CS8; | |
576 | break; | |
577 | } | |
578 | ||
579 | /* Handling Parity and Stop Bits length */ | |
580 | if (termios->c_cflag & CSTOPB) | |
581 | cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */ | |
582 | else | |
583 | cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */ | |
584 | ||
585 | if (termios->c_cflag & PARENB) { | |
586 | /* Mark or Space parity */ | |
587 | if (termios->c_cflag & CMSPAR) { | |
588 | if (termios->c_cflag & PARODD) | |
589 | cval |= XUARTPS_MR_PARITY_MARK; | |
590 | else | |
591 | cval |= XUARTPS_MR_PARITY_SPACE; | |
592 | } else if (termios->c_cflag & PARODD) | |
593 | cval |= XUARTPS_MR_PARITY_ODD; | |
594 | else | |
595 | cval |= XUARTPS_MR_PARITY_EVEN; | |
596 | } else | |
597 | cval |= XUARTPS_MR_PARITY_NONE; | |
598 | xuartps_writel(cval , XUARTPS_MR_OFFSET); | |
599 | ||
600 | spin_unlock_irqrestore(&port->lock, flags); | |
601 | } | |
602 | ||
603 | /** | |
604 | * xuartps_startup - Called when an application opens a xuartps port | |
605 | * @port: Handle to the uart port structure | |
606 | * | |
607 | * Returns 0 on success, negative error otherwise | |
608 | **/ | |
609 | static int xuartps_startup(struct uart_port *port) | |
610 | { | |
611 | unsigned int retval = 0, status = 0; | |
612 | ||
613 | retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME, | |
614 | (void *)port); | |
615 | if (retval) | |
616 | return retval; | |
617 | ||
618 | /* Disable the TX and RX */ | |
619 | xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, | |
620 | XUARTPS_CR_OFFSET); | |
621 | ||
622 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, | |
623 | * no break chars. | |
624 | */ | |
625 | xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, | |
626 | XUARTPS_CR_OFFSET); | |
627 | ||
628 | status = xuartps_readl(XUARTPS_CR_OFFSET); | |
629 | ||
630 | /* Clear the RX disable and TX disable bits and then set the TX enable | |
631 | * bit and RX enable bit to enable the transmitter and receiver. | |
632 | */ | |
633 | xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | |
634 | | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN | | |
635 | XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET); | |
636 | ||
637 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, | |
638 | * no parity. | |
639 | */ | |
640 | xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT | |
641 | | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT, | |
642 | XUARTPS_MR_OFFSET); | |
643 | ||
85baf542 S |
644 | /* |
645 | * Set the RX FIFO Trigger level to use most of the FIFO, but it | |
646 | * can be tuned with a module parameter | |
647 | */ | |
648 | xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); | |
61ec9016 | 649 | |
85baf542 S |
650 | /* |
651 | * Receive Timeout register is enabled but it | |
652 | * can be tuned with a module parameter | |
653 | */ | |
654 | xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); | |
61ec9016 | 655 | |
855f6fd9 JL |
656 | /* Clear out any pending interrupts before enabling them */ |
657 | xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET); | |
61ec9016 JL |
658 | |
659 | /* Set the Interrupt Registers with desired interrupts */ | |
660 | xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | | |
661 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | | |
662 | XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); | |
61ec9016 JL |
663 | |
664 | return retval; | |
665 | } | |
666 | ||
667 | /** | |
668 | * xuartps_shutdown - Called when an application closes a xuartps port | |
669 | * @port: Handle to the uart port structure | |
670 | * | |
671 | **/ | |
672 | static void xuartps_shutdown(struct uart_port *port) | |
673 | { | |
674 | int status; | |
675 | ||
676 | /* Disable interrupts */ | |
677 | status = xuartps_readl(XUARTPS_IMR_OFFSET); | |
678 | xuartps_writel(status, XUARTPS_IDR_OFFSET); | |
679 | ||
680 | /* Disable the TX and RX */ | |
681 | xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, | |
682 | XUARTPS_CR_OFFSET); | |
683 | free_irq(port->irq, port); | |
684 | } | |
685 | ||
686 | /** | |
687 | * xuartps_type - Set UART type to xuartps port | |
688 | * @port: Handle to the uart port structure | |
689 | * | |
690 | * Returns string on success, NULL otherwise | |
691 | **/ | |
692 | static const char *xuartps_type(struct uart_port *port) | |
693 | { | |
694 | return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL; | |
695 | } | |
696 | ||
697 | /** | |
698 | * xuartps_verify_port - Verify the port params | |
699 | * @port: Handle to the uart port structure | |
700 | * @ser: Handle to the structure whose members are compared | |
701 | * | |
702 | * Returns 0 if success otherwise -EINVAL | |
703 | **/ | |
704 | static int xuartps_verify_port(struct uart_port *port, | |
705 | struct serial_struct *ser) | |
706 | { | |
707 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) | |
708 | return -EINVAL; | |
709 | if (port->irq != ser->irq) | |
710 | return -EINVAL; | |
711 | if (ser->io_type != UPIO_MEM) | |
712 | return -EINVAL; | |
713 | if (port->iobase != ser->port) | |
714 | return -EINVAL; | |
715 | if (ser->hub6 != 0) | |
716 | return -EINVAL; | |
717 | return 0; | |
718 | } | |
719 | ||
720 | /** | |
721 | * xuartps_request_port - Claim the memory region attached to xuartps port, | |
722 | * called when the driver adds a xuartps port via | |
723 | * uart_add_one_port() | |
724 | * @port: Handle to the uart port structure | |
725 | * | |
726 | * Returns 0, -ENOMEM if request fails | |
727 | **/ | |
728 | static int xuartps_request_port(struct uart_port *port) | |
729 | { | |
730 | if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE, | |
731 | XUARTPS_NAME)) { | |
732 | return -ENOMEM; | |
733 | } | |
734 | ||
735 | port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE); | |
736 | if (!port->membase) { | |
737 | dev_err(port->dev, "Unable to map registers\n"); | |
738 | release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); | |
739 | return -ENOMEM; | |
740 | } | |
741 | return 0; | |
742 | } | |
743 | ||
744 | /** | |
745 | * xuartps_release_port - Release the memory region attached to a xuartps | |
746 | * port, called when the driver removes a xuartps | |
747 | * port via uart_remove_one_port(). | |
748 | * @port: Handle to the uart port structure | |
749 | * | |
750 | **/ | |
751 | static void xuartps_release_port(struct uart_port *port) | |
752 | { | |
753 | release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); | |
754 | iounmap(port->membase); | |
755 | port->membase = NULL; | |
756 | } | |
757 | ||
758 | /** | |
759 | * xuartps_config_port - Configure xuartps, called when the driver adds a | |
760 | * xuartps port | |
761 | * @port: Handle to the uart port structure | |
762 | * @flags: If any | |
763 | * | |
764 | **/ | |
765 | static void xuartps_config_port(struct uart_port *port, int flags) | |
766 | { | |
767 | if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0) | |
768 | port->type = PORT_XUARTPS; | |
769 | } | |
770 | ||
771 | /** | |
772 | * xuartps_get_mctrl - Get the modem control state | |
773 | * | |
774 | * @port: Handle to the uart port structure | |
775 | * | |
776 | * Returns the modem control state | |
777 | * | |
778 | **/ | |
779 | static unsigned int xuartps_get_mctrl(struct uart_port *port) | |
780 | { | |
781 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
782 | } | |
783 | ||
784 | static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
785 | { | |
786 | /* N/A */ | |
787 | } | |
788 | ||
789 | static void xuartps_enable_ms(struct uart_port *port) | |
790 | { | |
791 | /* N/A */ | |
792 | } | |
793 | ||
6ee04c6c VL |
794 | #ifdef CONFIG_CONSOLE_POLL |
795 | static int xuartps_poll_get_char(struct uart_port *port) | |
796 | { | |
797 | u32 imr; | |
798 | int c; | |
799 | ||
800 | /* Disable all interrupts */ | |
801 | imr = xuartps_readl(XUARTPS_IMR_OFFSET); | |
802 | xuartps_writel(imr, XUARTPS_IDR_OFFSET); | |
803 | ||
804 | /* Check if FIFO is empty */ | |
805 | if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) | |
806 | c = NO_POLL_CHAR; | |
807 | else /* Read a character */ | |
808 | c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET); | |
809 | ||
810 | /* Enable interrupts */ | |
811 | xuartps_writel(imr, XUARTPS_IER_OFFSET); | |
812 | ||
813 | return c; | |
814 | } | |
815 | ||
816 | static void xuartps_poll_put_char(struct uart_port *port, unsigned char c) | |
817 | { | |
818 | u32 imr; | |
819 | ||
820 | /* Disable all interrupts */ | |
821 | imr = xuartps_readl(XUARTPS_IMR_OFFSET); | |
822 | xuartps_writel(imr, XUARTPS_IDR_OFFSET); | |
823 | ||
824 | /* Wait until FIFO is empty */ | |
825 | while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) | |
826 | cpu_relax(); | |
827 | ||
828 | /* Write a character */ | |
829 | xuartps_writel(c, XUARTPS_FIFO_OFFSET); | |
830 | ||
831 | /* Wait until FIFO is empty */ | |
832 | while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) | |
833 | cpu_relax(); | |
834 | ||
835 | /* Enable interrupts */ | |
836 | xuartps_writel(imr, XUARTPS_IER_OFFSET); | |
837 | ||
838 | return; | |
839 | } | |
840 | #endif | |
841 | ||
61ec9016 JL |
842 | /** The UART operations structure |
843 | */ | |
844 | static struct uart_ops xuartps_ops = { | |
845 | .set_mctrl = xuartps_set_mctrl, | |
846 | .get_mctrl = xuartps_get_mctrl, | |
847 | .enable_ms = xuartps_enable_ms, | |
848 | ||
849 | .start_tx = xuartps_start_tx, /* Start transmitting */ | |
850 | .stop_tx = xuartps_stop_tx, /* Stop transmission */ | |
851 | .stop_rx = xuartps_stop_rx, /* Stop reception */ | |
852 | .tx_empty = xuartps_tx_empty, /* Transmitter busy? */ | |
853 | .break_ctl = xuartps_break_ctl, /* Start/stop | |
854 | * transmitting break | |
855 | */ | |
856 | .set_termios = xuartps_set_termios, /* Set termios */ | |
857 | .startup = xuartps_startup, /* App opens xuartps */ | |
858 | .shutdown = xuartps_shutdown, /* App closes xuartps */ | |
859 | .type = xuartps_type, /* Set UART type */ | |
860 | .verify_port = xuartps_verify_port, /* Verification of port | |
861 | * params | |
862 | */ | |
863 | .request_port = xuartps_request_port, /* Claim resources | |
864 | * associated with a | |
865 | * xuartps port | |
866 | */ | |
867 | .release_port = xuartps_release_port, /* Release resources | |
868 | * associated with a | |
869 | * xuartps port | |
870 | */ | |
871 | .config_port = xuartps_config_port, /* Configure when driver | |
872 | * adds a xuartps port | |
873 | */ | |
6ee04c6c VL |
874 | #ifdef CONFIG_CONSOLE_POLL |
875 | .poll_get_char = xuartps_poll_get_char, | |
876 | .poll_put_char = xuartps_poll_put_char, | |
877 | #endif | |
61ec9016 JL |
878 | }; |
879 | ||
880 | static struct uart_port xuartps_port[2]; | |
881 | ||
882 | /** | |
883 | * xuartps_get_port - Configure the port from the platform device resource | |
884 | * info | |
885 | * | |
886 | * Returns a pointer to a uart_port or NULL for failure | |
887 | **/ | |
888 | static struct uart_port *xuartps_get_port(void) | |
889 | { | |
890 | struct uart_port *port; | |
891 | int id; | |
892 | ||
893 | /* Find the next unused port */ | |
894 | for (id = 0; id < XUARTPS_NR_PORTS; id++) | |
895 | if (xuartps_port[id].mapbase == 0) | |
896 | break; | |
897 | ||
898 | if (id >= XUARTPS_NR_PORTS) | |
899 | return NULL; | |
900 | ||
901 | port = &xuartps_port[id]; | |
902 | ||
903 | /* At this point, we've got an empty uart_port struct, initialize it */ | |
904 | spin_lock_init(&port->lock); | |
905 | port->membase = NULL; | |
906 | port->iobase = 1; /* mark port in use */ | |
907 | port->irq = 0; | |
908 | port->type = PORT_UNKNOWN; | |
909 | port->iotype = UPIO_MEM32; | |
910 | port->flags = UPF_BOOT_AUTOCONF; | |
911 | port->ops = &xuartps_ops; | |
912 | port->fifosize = XUARTPS_FIFO_SIZE; | |
913 | port->line = id; | |
914 | port->dev = NULL; | |
915 | return port; | |
916 | } | |
917 | ||
918 | /*-----------------------Console driver operations--------------------------*/ | |
919 | ||
920 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE | |
921 | /** | |
922 | * xuartps_console_wait_tx - Wait for the TX to be full | |
923 | * @port: Handle to the uart port structure | |
924 | * | |
925 | **/ | |
926 | static void xuartps_console_wait_tx(struct uart_port *port) | |
927 | { | |
928 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) | |
929 | != XUARTPS_SR_TXEMPTY) | |
930 | barrier(); | |
931 | } | |
932 | ||
933 | /** | |
934 | * xuartps_console_putchar - write the character to the FIFO buffer | |
935 | * @port: Handle to the uart port structure | |
936 | * @ch: Character to be written | |
937 | * | |
938 | **/ | |
939 | static void xuartps_console_putchar(struct uart_port *port, int ch) | |
940 | { | |
941 | xuartps_console_wait_tx(port); | |
942 | xuartps_writel(ch, XUARTPS_FIFO_OFFSET); | |
943 | } | |
944 | ||
945 | /** | |
946 | * xuartps_console_write - perform write operation | |
947 | * @port: Handle to the uart port structure | |
948 | * @s: Pointer to character array | |
949 | * @count: No of characters | |
950 | **/ | |
951 | static void xuartps_console_write(struct console *co, const char *s, | |
952 | unsigned int count) | |
953 | { | |
954 | struct uart_port *port = &xuartps_port[co->index]; | |
955 | unsigned long flags; | |
956 | unsigned int imr; | |
957 | int locked = 1; | |
958 | ||
959 | if (oops_in_progress) | |
960 | locked = spin_trylock_irqsave(&port->lock, flags); | |
961 | else | |
962 | spin_lock_irqsave(&port->lock, flags); | |
963 | ||
964 | /* save and disable interrupt */ | |
965 | imr = xuartps_readl(XUARTPS_IMR_OFFSET); | |
966 | xuartps_writel(imr, XUARTPS_IDR_OFFSET); | |
967 | ||
968 | uart_console_write(port, s, count, xuartps_console_putchar); | |
969 | xuartps_console_wait_tx(port); | |
970 | ||
971 | /* restore interrupt state, it seems like there may be a h/w bug | |
972 | * in that the interrupt enable register should not need to be | |
973 | * written based on the data sheet | |
974 | */ | |
975 | xuartps_writel(~imr, XUARTPS_IDR_OFFSET); | |
976 | xuartps_writel(imr, XUARTPS_IER_OFFSET); | |
977 | ||
978 | if (locked) | |
979 | spin_unlock_irqrestore(&port->lock, flags); | |
980 | } | |
981 | ||
982 | /** | |
983 | * xuartps_console_setup - Initialize the uart to default config | |
984 | * @co: Console handle | |
985 | * @options: Initial settings of uart | |
986 | * | |
987 | * Returns 0, -ENODEV if no device | |
988 | **/ | |
989 | static int __init xuartps_console_setup(struct console *co, char *options) | |
990 | { | |
991 | struct uart_port *port = &xuartps_port[co->index]; | |
992 | int baud = 9600; | |
993 | int bits = 8; | |
994 | int parity = 'n'; | |
995 | int flow = 'n'; | |
996 | ||
997 | if (co->index < 0 || co->index >= XUARTPS_NR_PORTS) | |
998 | return -EINVAL; | |
999 | ||
1000 | if (!port->mapbase) { | |
1001 | pr_debug("console on ttyPS%i not present\n", co->index); | |
1002 | return -ENODEV; | |
1003 | } | |
1004 | ||
1005 | if (options) | |
1006 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1007 | ||
1008 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1009 | } | |
1010 | ||
1011 | static struct uart_driver xuartps_uart_driver; | |
1012 | ||
1013 | static struct console xuartps_console = { | |
1014 | .name = XUARTPS_TTY_NAME, | |
1015 | .write = xuartps_console_write, | |
1016 | .device = uart_console_device, | |
1017 | .setup = xuartps_console_setup, | |
1018 | .flags = CON_PRINTBUFFER, | |
1019 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ | |
1020 | .data = &xuartps_uart_driver, | |
1021 | }; | |
1022 | ||
1023 | /** | |
1024 | * xuartps_console_init - Initialization call | |
1025 | * | |
1026 | * Returns 0 on success, negative error otherwise | |
1027 | **/ | |
1028 | static int __init xuartps_console_init(void) | |
1029 | { | |
1030 | register_console(&xuartps_console); | |
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | console_initcall(xuartps_console_init); | |
1035 | ||
1036 | #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ | |
1037 | ||
1038 | /** Structure Definitions | |
1039 | */ | |
1040 | static struct uart_driver xuartps_uart_driver = { | |
1041 | .owner = THIS_MODULE, /* Owner */ | |
1042 | .driver_name = XUARTPS_NAME, /* Driver name */ | |
1043 | .dev_name = XUARTPS_TTY_NAME, /* Node name */ | |
1044 | .major = XUARTPS_MAJOR, /* Major number */ | |
1045 | .minor = XUARTPS_MINOR, /* Minor number */ | |
1046 | .nr = XUARTPS_NR_PORTS, /* Number of UART ports */ | |
1047 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE | |
1048 | .cons = &xuartps_console, /* Console */ | |
1049 | #endif | |
1050 | }; | |
1051 | ||
1052 | /* --------------------------------------------------------------------- | |
1053 | * Platform bus binding | |
1054 | */ | |
1055 | /** | |
1056 | * xuartps_probe - Platform driver probe | |
1057 | * @pdev: Pointer to the platform device structure | |
1058 | * | |
1059 | * Returns 0 on success, negative error otherwise | |
1060 | **/ | |
9671f099 | 1061 | static int xuartps_probe(struct platform_device *pdev) |
61ec9016 JL |
1062 | { |
1063 | int rc; | |
1064 | struct uart_port *port; | |
1065 | struct resource *res, *res2; | |
30e1e285 | 1066 | struct xuartps *xuartps_data; |
61ec9016 | 1067 | |
c03cae17 SB |
1068 | xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data), |
1069 | GFP_KERNEL); | |
30e1e285 SB |
1070 | if (!xuartps_data) |
1071 | return -ENOMEM; | |
1072 | ||
991fc259 | 1073 | xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk"); |
30e1e285 SB |
1074 | if (IS_ERR(xuartps_data->aperclk)) { |
1075 | dev_err(&pdev->dev, "aper_clk clock not found.\n"); | |
c03cae17 | 1076 | return PTR_ERR(xuartps_data->aperclk); |
30e1e285 | 1077 | } |
991fc259 | 1078 | xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk"); |
30e1e285 SB |
1079 | if (IS_ERR(xuartps_data->refclk)) { |
1080 | dev_err(&pdev->dev, "ref_clk clock not found.\n"); | |
c03cae17 | 1081 | return PTR_ERR(xuartps_data->refclk); |
2326669c JC |
1082 | } |
1083 | ||
30e1e285 SB |
1084 | rc = clk_prepare_enable(xuartps_data->aperclk); |
1085 | if (rc) { | |
1086 | dev_err(&pdev->dev, "Unable to enable APER clock.\n"); | |
c03cae17 | 1087 | return rc; |
30e1e285 SB |
1088 | } |
1089 | rc = clk_prepare_enable(xuartps_data->refclk); | |
2326669c | 1090 | if (rc) { |
30e1e285 SB |
1091 | dev_err(&pdev->dev, "Unable to enable device clock.\n"); |
1092 | goto err_out_clk_dis_aper; | |
61ec9016 JL |
1093 | } |
1094 | ||
1095 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
30e1e285 SB |
1096 | if (!res) { |
1097 | rc = -ENODEV; | |
1098 | goto err_out_clk_disable; | |
1099 | } | |
61ec9016 JL |
1100 | |
1101 | res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
30e1e285 SB |
1102 | if (!res2) { |
1103 | rc = -ENODEV; | |
1104 | goto err_out_clk_disable; | |
1105 | } | |
61ec9016 JL |
1106 | |
1107 | /* Initialize the port structure */ | |
1108 | port = xuartps_get_port(); | |
1109 | ||
1110 | if (!port) { | |
1111 | dev_err(&pdev->dev, "Cannot get uart_port structure\n"); | |
30e1e285 SB |
1112 | rc = -ENODEV; |
1113 | goto err_out_clk_disable; | |
61ec9016 JL |
1114 | } else { |
1115 | /* Register the port. | |
1116 | * This function also registers this device with the tty layer | |
1117 | * and triggers invocation of the config_port() entry point. | |
1118 | */ | |
1119 | port->mapbase = res->start; | |
1120 | port->irq = res2->start; | |
1121 | port->dev = &pdev->dev; | |
30e1e285 SB |
1122 | port->uartclk = clk_get_rate(xuartps_data->refclk); |
1123 | port->private_data = xuartps_data; | |
696faedd | 1124 | platform_set_drvdata(pdev, port); |
61ec9016 JL |
1125 | rc = uart_add_one_port(&xuartps_uart_driver, port); |
1126 | if (rc) { | |
1127 | dev_err(&pdev->dev, | |
1128 | "uart_add_one_port() failed; err=%i\n", rc); | |
30e1e285 | 1129 | goto err_out_clk_disable; |
61ec9016 JL |
1130 | } |
1131 | return 0; | |
1132 | } | |
30e1e285 SB |
1133 | |
1134 | err_out_clk_disable: | |
1135 | clk_disable_unprepare(xuartps_data->refclk); | |
1136 | err_out_clk_dis_aper: | |
1137 | clk_disable_unprepare(xuartps_data->aperclk); | |
30e1e285 SB |
1138 | |
1139 | return rc; | |
61ec9016 JL |
1140 | } |
1141 | ||
1142 | /** | |
1143 | * xuartps_remove - called when the platform driver is unregistered | |
1144 | * @pdev: Pointer to the platform device structure | |
1145 | * | |
1146 | * Returns 0 on success, negative error otherwise | |
1147 | **/ | |
ae8d8a14 | 1148 | static int xuartps_remove(struct platform_device *pdev) |
61ec9016 | 1149 | { |
696faedd | 1150 | struct uart_port *port = platform_get_drvdata(pdev); |
30e1e285 | 1151 | struct xuartps *xuartps_data = port->private_data; |
2326669c | 1152 | int rc; |
61ec9016 JL |
1153 | |
1154 | /* Remove the xuartps port from the serial core */ | |
2326669c | 1155 | rc = uart_remove_one_port(&xuartps_uart_driver, port); |
2326669c | 1156 | port->mapbase = 0; |
30e1e285 SB |
1157 | clk_disable_unprepare(xuartps_data->refclk); |
1158 | clk_disable_unprepare(xuartps_data->aperclk); | |
61ec9016 JL |
1159 | return rc; |
1160 | } | |
1161 | ||
61ec9016 | 1162 | /* Match table for of_platform binding */ |
de88b340 | 1163 | static struct of_device_id xuartps_of_match[] = { |
61ec9016 JL |
1164 | { .compatible = "xlnx,xuartps", }, |
1165 | {} | |
1166 | }; | |
1167 | MODULE_DEVICE_TABLE(of, xuartps_of_match); | |
61ec9016 JL |
1168 | |
1169 | static struct platform_driver xuartps_platform_driver = { | |
1170 | .probe = xuartps_probe, /* Probe method */ | |
eb51d917 | 1171 | .remove = xuartps_remove, /* Detach method */ |
61ec9016 JL |
1172 | .driver = { |
1173 | .owner = THIS_MODULE, | |
1174 | .name = XUARTPS_NAME, /* Driver name */ | |
1175 | .of_match_table = xuartps_of_match, | |
1176 | }, | |
1177 | }; | |
1178 | ||
1179 | /* --------------------------------------------------------------------- | |
1180 | * Module Init and Exit | |
1181 | */ | |
1182 | /** | |
1183 | * xuartps_init - Initial driver registration call | |
1184 | * | |
1185 | * Returns whether the registration was successful or not | |
1186 | **/ | |
1187 | static int __init xuartps_init(void) | |
1188 | { | |
1189 | int retval = 0; | |
1190 | ||
1191 | /* Register the xuartps driver with the serial core */ | |
1192 | retval = uart_register_driver(&xuartps_uart_driver); | |
1193 | if (retval) | |
1194 | return retval; | |
1195 | ||
1196 | /* Register the platform driver */ | |
1197 | retval = platform_driver_register(&xuartps_platform_driver); | |
1198 | if (retval) | |
1199 | uart_unregister_driver(&xuartps_uart_driver); | |
1200 | ||
1201 | return retval; | |
1202 | } | |
1203 | ||
1204 | /** | |
1205 | * xuartps_exit - Driver unregistration call | |
1206 | **/ | |
1207 | static void __exit xuartps_exit(void) | |
1208 | { | |
1209 | /* The order of unregistration is important. Unregister the | |
1210 | * UART driver before the platform driver crashes the system. | |
1211 | */ | |
1212 | ||
1213 | /* Unregister the platform driver */ | |
1214 | platform_driver_unregister(&xuartps_platform_driver); | |
1215 | ||
1216 | /* Unregister the xuartps driver */ | |
1217 | uart_unregister_driver(&xuartps_uart_driver); | |
1218 | } | |
1219 | ||
1220 | module_init(xuartps_init); | |
1221 | module_exit(xuartps_exit); | |
1222 | ||
1223 | MODULE_DESCRIPTION("Driver for PS UART"); | |
1224 | MODULE_AUTHOR("Xilinx Inc."); | |
1225 | MODULE_LICENSE("GPL"); |