[linux-2.6-block.git] / drivers / tty / serial / uartlite.c

/*
 * uartlite.c: Serial driver for Xilinx uartlite serial controller
 *
 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
 * Copyright (C) 2007 Secret Lab Technologies Ltd.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/console.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <asm/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>

#define ULITE_NAME		"ttyUL"
#define ULITE_MAJOR		204
#define ULITE_MINOR		187
#define ULITE_NR_UARTS		4

/* ---------------------------------------------------------------------
 * Register definitions
 *
 * For register details see datasheet:
 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 
 */

#define ULITE_RX		0x00
#define ULITE_TX		0x04
#define ULITE_STATUS		0x08
#define ULITE_CONTROL		0x0c

#define ULITE_REGION		16

#define ULITE_STATUS_RXVALID	0x01
#define ULITE_STATUS_RXFULL	0x02
#define ULITE_STATUS_TXEMPTY	0x04
#define ULITE_STATUS_TXFULL	0x08
#define ULITE_STATUS_IE		0x10
#define ULITE_STATUS_OVERRUN	0x20
#define ULITE_STATUS_FRAME	0x40
#define ULITE_STATUS_PARITY	0x80

#define ULITE_CONTROL_RST_TX	0x01
#define ULITE_CONTROL_RST_RX	0x02
#define ULITE_CONTROL_IE	0x10


static struct uart_port ulite_ports[ULITE_NR_UARTS];

/* ---------------------------------------------------------------------
 * Core UART driver operations
 */

static int ulite_receive(struct uart_port *port, int stat)
{
	struct tty_struct *tty = port->state->port.tty;
	unsigned char ch = 0;
	char flag = TTY_NORMAL;

	if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		     | ULITE_STATUS_FRAME)) == 0)
		return 0;

	/* stats */
	if (stat & ULITE_STATUS_RXVALID) {
		port->icount.rx++;
		ch = ioread32be(port->membase + ULITE_RX);

		if (stat & ULITE_STATUS_PARITY)
			port->icount.parity++;
	}

	if (stat & ULITE_STATUS_OVERRUN)
		port->icount.overrun++;

	if (stat & ULITE_STATUS_FRAME)
		port->icount.frame++;


	/* drop byte with parity error if IGNPAR specificed */
	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
		stat &= ~ULITE_STATUS_RXVALID;

	stat &= port->read_status_mask;

	if (stat & ULITE_STATUS_PARITY)
		flag = TTY_PARITY;


	stat &= ~port->ignore_status_mask;

	if (stat & ULITE_STATUS_RXVALID)
		tty_insert_flip_char(tty, ch, flag);

	if (stat & ULITE_STATUS_FRAME)
		tty_insert_flip_char(tty, 0, TTY_FRAME);

	if (stat & ULITE_STATUS_OVERRUN)
		tty_insert_flip_char(tty, 0, TTY_OVERRUN);

	return 1;
}

static int ulite_transmit(struct uart_port *port, int stat)
{
	struct circ_buf *xmit  = &port->state->xmit;

	if (stat & ULITE_STATUS_TXFULL)
		return 0;

	if (port->x_char) {
		iowrite32be(port->x_char, port->membase + ULITE_TX);
		port->x_char = 0;
		port->icount.tx++;
		return 1;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
		return 0;

	iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	port->icount.tx++;

	/* wake up */
	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	return 1;
}

static irqreturn_t ulite_isr(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	int busy, n = 0;

	do {
		int stat = ioread32be(port->membase + ULITE_STATUS);
		busy  = ulite_receive(port, stat);
		busy |= ulite_transmit(port, stat);
		n++;
	} while (busy);

	/* work done? */
	if (n > 1) {
		tty_flip_buffer_push(port->state->port.tty);
		return IRQ_HANDLED;
	} else {
		return IRQ_NONE;
	}
}

static unsigned int ulite_tx_empty(struct uart_port *port)
{
	unsigned long flags;
	unsigned int ret;

	spin_lock_irqsave(&port->lock, flags);
	ret = ioread32be(port->membase + ULITE_STATUS);
	spin_unlock_irqrestore(&port->lock, flags);

	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
}

static unsigned int ulite_get_mctrl(struct uart_port *port)
{
	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
}

static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	/* N/A */
}

static void ulite_stop_tx(struct uart_port *port)
{
	/* N/A */
}

static void ulite_start_tx(struct uart_port *port)
{
	ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
}

static void ulite_stop_rx(struct uart_port *port)
{
	/* don't forward any more data (like !CREAD) */
	port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
		| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
}

static void ulite_enable_ms(struct uart_port *port)
{
	/* N/A */
}

static void ulite_break_ctl(struct uart_port *port, int ctl)
{
	/* N/A */
}

static int ulite_startup(struct uart_port *port)
{
	int ret;

	ret = request_irq(port->irq, ulite_isr,
			  IRQF_SHARED | IRQF_SAMPLE_RANDOM, "uartlite", port);
	if (ret)
		return ret;

	iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
	       port->membase + ULITE_CONTROL);
	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);

	return 0;
}

static void ulite_shutdown(struct uart_port *port)
{
	iowrite32be(0, port->membase + ULITE_CONTROL);
	ioread32be(port->membase + ULITE_CONTROL); /* dummy */
	free_irq(port->irq, port);
}

static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
			      struct ktermios *old)
{
	unsigned long flags;
	unsigned int baud;

	spin_lock_irqsave(&port->lock, flags);

	port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		| ULITE_STATUS_TXFULL;

	if (termios->c_iflag & INPCK)
		port->read_status_mask |=
			ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;

	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* ignore all characters if CREAD is not set */
	if ((termios->c_cflag & CREAD) == 0)
		port->ignore_status_mask |=
			ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* update timeout */
	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	uart_update_timeout(port, termios->c_cflag, baud);

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *ulite_type(struct uart_port *port)
{
	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
}

static void ulite_release_port(struct uart_port *port)
{
	release_mem_region(port->mapbase, ULITE_REGION);
	iounmap(port->membase);
	port->membase = NULL;
}

static int ulite_request_port(struct uart_port *port)
{
	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
		 port, (unsigned long long) port->mapbase);

	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
		dev_err(port->dev, "Memory region busy\n");
		return -EBUSY;
	}

	port->membase = ioremap(port->mapbase, ULITE_REGION);
	if (!port->membase) {
		dev_err(port->dev, "Unable to map registers\n");
		release_mem_region(port->mapbase, ULITE_REGION);
		return -EBUSY;
	}

	return 0;
}

static void ulite_config_port(struct uart_port *port, int flags)
{
	if (!ulite_request_port(port))
		port->type = PORT_UARTLITE;
}

static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	/* we don't want the core code to modify any port params */
	return -EINVAL;
}

#ifdef CONFIG_CONSOLE_POLL
static int ulite_get_poll_char(struct uart_port *port)
{
	if (!(ioread32be(port->membase + ULITE_STATUS)
						& ULITE_STATUS_RXVALID))
		return NO_POLL_CHAR;

	return ioread32be(port->membase + ULITE_RX);
}

static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
{
	while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)
		cpu_relax();

	/* write char to device */
	iowrite32be(ch, port->membase + ULITE_TX);
}
#endif

static struct uart_ops ulite_ops = {
	.tx_empty	= ulite_tx_empty,
	.set_mctrl	= ulite_set_mctrl,
	.get_mctrl	= ulite_get_mctrl,
	.stop_tx	= ulite_stop_tx,
	.start_tx	= ulite_start_tx,
	.stop_rx	= ulite_stop_rx,
	.enable_ms	= ulite_enable_ms,
	.break_ctl	= ulite_break_ctl,
	.startup	= ulite_startup,
	.shutdown	= ulite_shutdown,
	.set_termios	= ulite_set_termios,
	.type		= ulite_type,
	.release_port	= ulite_release_port,
	.request_port	= ulite_request_port,
	.config_port	= ulite_config_port,
	.verify_port	= ulite_verify_port,
#ifdef CONFIG_CONSOLE_POLL
	.poll_get_char	= ulite_get_poll_char,
	.poll_put_char	= ulite_put_poll_char,
#endif
};

/* ---------------------------------------------------------------------
 * Console driver operations
 */

#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
static void ulite_console_wait_tx(struct uart_port *port)
{
	int i;
	u8 val;

	/* Spin waiting for TX fifo to have space available */
	for (i = 0; i < 100000; i++) {
		val = ioread32be(port->membase + ULITE_STATUS);
		if ((val & ULITE_STATUS_TXFULL) == 0)
			break;
		cpu_relax();
	}
}

static void ulite_console_putchar(struct uart_port *port, int ch)
{
	ulite_console_wait_tx(port);
	iowrite32be(ch, port->membase + ULITE_TX);
}

static void ulite_console_write(struct console *co, const char *s,
				unsigned int count)
{
	struct uart_port *port = &ulite_ports[co->index];
	unsigned long flags;
	unsigned int ier;
	int locked = 1;

	if (oops_in_progress) {
		locked = spin_trylock_irqsave(&port->lock, flags);
	} else
		spin_lock_irqsave(&port->lock, flags);

	/* save and disable interrupt */
	ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
	iowrite32be(0, port->membase + ULITE_CONTROL);

	uart_console_write(port, s, count, ulite_console_putchar);

	ulite_console_wait_tx(port);

	/* restore interrupt state */
	if (ier)
		iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);

	if (locked)
		spin_unlock_irqrestore(&port->lock, flags);
}

static int __devinit ulite_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	if (co->index < 0 || co->index >= ULITE_NR_UARTS)
		return -EINVAL;

	port = &ulite_ports[co->index];

	/* Has the device been initialized yet? */
	if (!port->mapbase) {
		pr_debug("console on ttyUL%i not present\n", co->index);
		return -ENODEV;
	}

	/* not initialized yet? */
	if (!port->membase) {
		if (ulite_request_port(port))
			return -ENODEV;
	}

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver ulite_uart_driver;

static struct console ulite_console = {
	.name	= ULITE_NAME,
	.write	= ulite_console_write,
	.device	= uart_console_device,
	.setup	= ulite_console_setup,
	.flags	= CON_PRINTBUFFER,
	.index	= -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	.data	= &ulite_uart_driver,
};

static int __init ulite_console_init(void)
{
	register_console(&ulite_console);
	return 0;
}

console_initcall(ulite_console_init);

#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */

static struct uart_driver ulite_uart_driver = {
	.owner		= THIS_MODULE,
	.driver_name	= "uartlite",
	.dev_name	= ULITE_NAME,
	.major		= ULITE_MAJOR,
	.minor		= ULITE_MINOR,
	.nr		= ULITE_NR_UARTS,
#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	.cons		= &ulite_console,
#endif
};

/* ---------------------------------------------------------------------
 * Port assignment functions (mapping devices to uart_port structures)
 */

/** ulite_assign: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 * @id: requested id number.  Pass -1 for automatic port assignment
 * @base: base address of uartlite registers
 * @irq: irq number for uartlite
 *
 * Returns: 0 on success, <0 otherwise
 */
static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
{
	struct uart_port *port;
	int rc;

	/* if id = -1; then scan for a free id and use that */
	if (id < 0) {
		for (id = 0; id < ULITE_NR_UARTS; id++)
			if (ulite_ports[id].mapbase == 0)
				break;
	}
	if (id < 0 || id >= ULITE_NR_UARTS) {
		dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
		return -EINVAL;
	}

	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
		dev_err(dev, "cannot assign to %s%i; it is already in use\n",
			ULITE_NAME, id);
		return -EBUSY;
	}

	port = &ulite_ports[id];

	spin_lock_init(&port->lock);
	port->fifosize = 16;
	port->regshift = 2;
	port->iotype = UPIO_MEM;
	port->iobase = 1; /* mark port in use */
	port->mapbase = base;
	port->membase = NULL;
	port->ops = &ulite_ops;
	port->irq = irq;
	port->flags = UPF_BOOT_AUTOCONF;
	port->dev = dev;
	port->type = PORT_UNKNOWN;
	port->line = id;

	dev_set_drvdata(dev, port);

	/* Register the port */
	rc = uart_add_one_port(&ulite_uart_driver, port);
	if (rc) {
		dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
		port->mapbase = 0;
		dev_set_drvdata(dev, NULL);
		return rc;
	}

	return 0;
}

/** ulite_release: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 */
static int __devexit ulite_release(struct device *dev)
{
	struct uart_port *port = dev_get_drvdata(dev);
	int rc = 0;

	if (port) {
		rc = uart_remove_one_port(&ulite_uart_driver, port);
		dev_set_drvdata(dev, NULL);
		port->mapbase = 0;
	}

	return rc;
}

/* ---------------------------------------------------------------------
 * Platform bus binding
 */

#if defined(CONFIG_OF)
/* Match table for of_platform binding */
static struct of_device_id ulite_of_match[] __devinitdata = {
	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	{}
};
MODULE_DEVICE_TABLE(of, ulite_of_match);
#endif /* CONFIG_OF */

static int __devinit ulite_probe(struct platform_device *pdev)
{
	struct resource *res, *res2;
	int id = pdev->id;
#ifdef CONFIG_OF
	const __be32 *prop;

	prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
	if (prop)
		id = be32_to_cpup(prop);
#endif

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res2)
		return -ENODEV;

	return ulite_assign(&pdev->dev, id, res->start, res2->start);
}

static int __devexit ulite_remove(struct platform_device *pdev)
{
	return ulite_release(&pdev->dev);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:uartlite");

static struct platform_driver ulite_platform_driver = {
	.probe = ulite_probe,
	.remove = __devexit_p(ulite_remove),
	.driver = {
		.owner = THIS_MODULE,
		.name  = "uartlite",
		.of_match_table = of_match_ptr(ulite_of_match),
	},
};

/* ---------------------------------------------------------------------
 * Module setup/teardown
 */

int __init ulite_init(void)
{
	int ret;

	pr_debug("uartlite: calling uart_register_driver()\n");
	ret = uart_register_driver(&ulite_uart_driver);
	if (ret)
		goto err_uart;

	pr_debug("uartlite: calling platform_driver_register()\n");
	ret = platform_driver_register(&ulite_platform_driver);
	if (ret)
		goto err_plat;

	return 0;

err_plat:
	uart_unregister_driver(&ulite_uart_driver);
err_uart:
	printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
	return ret;
}

void __exit ulite_exit(void)
{
	platform_driver_unregister(&ulite_platform_driver);
	uart_unregister_driver(&ulite_uart_driver);
}

module_init(ulite_init);
module_exit(ulite_exit);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("Xilinx uartlite serial driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
238b8721 PK	1	/*
	2	* uartlite.c: Serial driver for Xilinx uartlite serial controller
	3	*
852e1ea7 GL	4	* Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
852e1ea7 GL	5	* Copyright (C) 2007 Secret Lab Technologies Ltd.
238b8721 PK	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	#include <linux/platform_device.h>
	13	#include <linux/module.h>
	14	#include <linux/console.h>
	15	#include <linux/serial.h>
	16	#include <linux/serial_core.h>
	17	#include <linux/tty.h>
ee160a38	18	#include <linux/tty_flip.h>
238b8721 PK	19	#include <linux/delay.h>
238b8721 PK	20	#include <linux/interrupt.h>
0e349b0e	21	#include <linux/init.h>
238b8721	22	#include <asm/io.h>
0e349b0e	23	#include <linux/of.h>
22ae782f	24	#include <linux/of_address.h>
852e1ea7 GL	25	#include <linux/of_device.h>
852e1ea7 GL	26	#include <linux/of_platform.h>
0e349b0e	27
00775828	28	#define ULITE_NAME "ttyUL"
238b8721 PK	29	#define ULITE_MAJOR 204
	30	#define ULITE_MINOR 187
	31	#define ULITE_NR_UARTS 4
	32
435706b3 GL	33	/* ---------------------------------------------------------------------
	34	* Register definitions
	35	*
	36	* For register details see datasheet:
631dd1a8	37	* http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
435706b3 GL	38	*/
435706b3 GL	39
238b8721 PK	40	#define ULITE_RX 0x00
	41	#define ULITE_TX 0x04
	42	#define ULITE_STATUS 0x08
	43	#define ULITE_CONTROL 0x0c
	44
	45	#define ULITE_REGION 16
	46
	47	#define ULITE_STATUS_RXVALID 0x01
	48	#define ULITE_STATUS_RXFULL 0x02
	49	#define ULITE_STATUS_TXEMPTY 0x04
	50	#define ULITE_STATUS_TXFULL 0x08
	51	#define ULITE_STATUS_IE 0x10
	52	#define ULITE_STATUS_OVERRUN 0x20
	53	#define ULITE_STATUS_FRAME 0x40
	54	#define ULITE_STATUS_PARITY 0x80
	55
	56	#define ULITE_CONTROL_RST_TX 0x01
	57	#define ULITE_CONTROL_RST_RX 0x02
	58	#define ULITE_CONTROL_IE 0x10
	59
	60
483c79db	61	static struct uart_port ulite_ports[ULITE_NR_UARTS];
238b8721	62
435706b3 GL	63	/* ---------------------------------------------------------------------
	64	* Core UART driver operations
	65	*/
	66
238b8721 PK	67	static int ulite_receive(struct uart_port *port, int stat)
238b8721 PK	68	{
ebd2c8f6	69	struct tty_struct *tty = port->state->port.tty;
238b8721 PK	70	unsigned char ch = 0;
	71	char flag = TTY_NORMAL;
	72
	73	if ((stat & (ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	74	\| ULITE_STATUS_FRAME)) == 0)
	75	return 0;
	76
	77	/* stats */
	78	if (stat & ULITE_STATUS_RXVALID) {
	79	port->icount.rx++;
e5bbbb18	80	ch = ioread32be(port->membase + ULITE_RX);
238b8721 PK	81
	82	if (stat & ULITE_STATUS_PARITY)
	83	port->icount.parity++;
	84	}
	85
	86	if (stat & ULITE_STATUS_OVERRUN)
	87	port->icount.overrun++;
	88
	89	if (stat & ULITE_STATUS_FRAME)
	90	port->icount.frame++;
	91
	92
	93	/* drop byte with parity error if IGNPAR specificed */
	94	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
	95	stat &= ~ULITE_STATUS_RXVALID;
	96
	97	stat &= port->read_status_mask;
	98
	99	if (stat & ULITE_STATUS_PARITY)
	100	flag = TTY_PARITY;
	101
	102
	103	stat &= ~port->ignore_status_mask;
	104
	105	if (stat & ULITE_STATUS_RXVALID)
	106	tty_insert_flip_char(tty, ch, flag);
	107
	108	if (stat & ULITE_STATUS_FRAME)
	109	tty_insert_flip_char(tty, 0, TTY_FRAME);
	110
	111	if (stat & ULITE_STATUS_OVERRUN)
	112	tty_insert_flip_char(tty, 0, TTY_OVERRUN);
	113
	114	return 1;
	115	}
	116
	117	static int ulite_transmit(struct uart_port *port, int stat)
	118	{
ebd2c8f6	119	struct circ_buf *xmit = &port->state->xmit;
238b8721 PK	120
	121	if (stat & ULITE_STATUS_TXFULL)
	122	return 0;
	123
	124	if (port->x_char) {
e5bbbb18	125	iowrite32be(port->x_char, port->membase + ULITE_TX);
238b8721 PK	126	port->x_char = 0;
	127	port->icount.tx++;
	128	return 1;
	129	}
	130
	131	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port))
	132	return 0;
	133
e5bbbb18	134	iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
238b8721 PK	135	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	136	port->icount.tx++;
	137
	138	/* wake up */
	139	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	140	uart_write_wakeup(port);
	141
	142	return 1;
	143	}
	144
	145	static irqreturn_t ulite_isr(int irq, void *dev_id)
	146	{
15aafa2f	147	struct uart_port *port = dev_id;
d2cfe962	148	int busy, n = 0;
238b8721 PK	149
238b8721 PK	150	do {
e5bbbb18	151	int stat = ioread32be(port->membase + ULITE_STATUS);
238b8721 PK	152	busy = ulite_receive(port, stat);
238b8721 PK	153	busy \|= ulite_transmit(port, stat);
d2cfe962	154	n++;
238b8721 PK	155	} while (busy);
238b8721 PK	156
d2cfe962 PK	157	/* work done? */
	158	if (n > 1) {
	159	tty_flip_buffer_push(port->state->port.tty);
	160	return IRQ_HANDLED;
	161	} else {
	162	return IRQ_NONE;
	163	}
238b8721 PK	164	}
	165
	166	static unsigned int ulite_tx_empty(struct uart_port *port)
	167	{
	168	unsigned long flags;
	169	unsigned int ret;
	170
	171	spin_lock_irqsave(&port->lock, flags);
e5bbbb18	172	ret = ioread32be(port->membase + ULITE_STATUS);
238b8721 PK	173	spin_unlock_irqrestore(&port->lock, flags);
	174
	175	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
	176	}
	177
	178	static unsigned int ulite_get_mctrl(struct uart_port *port)
	179	{
	180	return TIOCM_CTS \| TIOCM_DSR \| TIOCM_CAR;
	181	}
	182
	183	static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
	184	{
	185	/* N/A */
	186	}
	187
	188	static void ulite_stop_tx(struct uart_port *port)
	189	{
	190	/* N/A */
	191	}
	192
	193	static void ulite_start_tx(struct uart_port *port)
	194	{
e5bbbb18	195	ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
238b8721 PK	196	}
	197
	198	static void ulite_stop_rx(struct uart_port *port)
	199	{
	200	/* don't forward any more data (like !CREAD) */
	201	port->ignore_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	202	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	203	}
	204
	205	static void ulite_enable_ms(struct uart_port *port)
	206	{
	207	/* N/A */
	208	}
	209
	210	static void ulite_break_ctl(struct uart_port *port, int ctl)
	211	{
	212	/* N/A */
	213	}
	214
	215	static int ulite_startup(struct uart_port *port)
	216	{
	217	int ret;
	218
	219	ret = request_irq(port->irq, ulite_isr,
d2cfe962	220	IRQF_SHARED \| IRQF_SAMPLE_RANDOM, "uartlite", port);
238b8721 PK	221	if (ret)
	222	return ret;
	223
e5bbbb18	224	iowrite32be(ULITE_CONTROL_RST_RX \| ULITE_CONTROL_RST_TX,
e077b50c	225	port->membase + ULITE_CONTROL);
e5bbbb18	226	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
238b8721 PK	227
	228	return 0;
	229	}
	230
	231	static void ulite_shutdown(struct uart_port *port)
	232	{
e5bbbb18 JL	233	iowrite32be(0, port->membase + ULITE_CONTROL);
e5bbbb18 JL	234	ioread32be(port->membase + ULITE_CONTROL); /* dummy */
238b8721 PK	235	free_irq(port->irq, port);
	236	}
	237
606d099c AC	238	static void ulite_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	239	struct ktermios *old)
238b8721 PK	240	{
	241	unsigned long flags;
	242	unsigned int baud;
	243
	244	spin_lock_irqsave(&port->lock, flags);
	245
	246	port->read_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	247	\| ULITE_STATUS_TXFULL;
	248
	249	if (termios->c_iflag & INPCK)
	250	port->read_status_mask \|=
	251	ULITE_STATUS_PARITY \| ULITE_STATUS_FRAME;
	252
	253	port->ignore_status_mask = 0;
	254	if (termios->c_iflag & IGNPAR)
	255	port->ignore_status_mask \|= ULITE_STATUS_PARITY
	256	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	257
	258	/* ignore all characters if CREAD is not set */
	259	if ((termios->c_cflag & CREAD) == 0)
	260	port->ignore_status_mask \|=
	261	ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	262	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	263
	264	/* update timeout */
	265	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	266	uart_update_timeout(port, termios->c_cflag, baud);
	267
	268	spin_unlock_irqrestore(&port->lock, flags);
	269	}
	270
	271	static const char ulite_type(struct uart_port port)
	272	{
	273	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
	274	}
	275
	276	static void ulite_release_port(struct uart_port *port)
	277	{
	278	release_mem_region(port->mapbase, ULITE_REGION);
	279	iounmap(port->membase);
b81831c6	280	port->membase = NULL;
238b8721 PK	281	}
	282
	283	static int ulite_request_port(struct uart_port *port)
	284	{
a1080968 GL	285	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
a1080968 GL	286	port, (unsigned long long) port->mapbase);
0e349b0e	287
238b8721 PK	288	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
	289	dev_err(port->dev, "Memory region busy\n");
	290	return -EBUSY;
	291	}
	292
	293	port->membase = ioremap(port->mapbase, ULITE_REGION);
	294	if (!port->membase) {
	295	dev_err(port->dev, "Unable to map registers\n");
	296	release_mem_region(port->mapbase, ULITE_REGION);
	297	return -EBUSY;
	298	}
	299
	300	return 0;
	301	}
	302
	303	static void ulite_config_port(struct uart_port *port, int flags)
	304	{
e21654a7 PK	305	if (!ulite_request_port(port))
e21654a7 PK	306	port->type = PORT_UARTLITE;
238b8721 PK	307	}
	308
	309	static int ulite_verify_port(struct uart_port port, struct serial_struct ser)
	310	{
	311	/* we don't want the core code to modify any port params */
	312	return -EINVAL;
	313	}
	314
8a28af7f MS	315	#ifdef CONFIG_CONSOLE_POLL
	316	static int ulite_get_poll_char(struct uart_port *port)
	317	{
	318	if (!(ioread32be(port->membase + ULITE_STATUS)
	319	& ULITE_STATUS_RXVALID))
	320	return NO_POLL_CHAR;
	321
	322	return ioread32be(port->membase + ULITE_RX);
	323	}
	324
	325	static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
	326	{
	327	while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)
	328	cpu_relax();
	329
	330	/* write char to device */
	331	iowrite32be(ch, port->membase + ULITE_TX);
	332	}
	333	#endif
	334
238b8721 PK	335	static struct uart_ops ulite_ops = {
	336	.tx_empty = ulite_tx_empty,
	337	.set_mctrl = ulite_set_mctrl,
	338	.get_mctrl = ulite_get_mctrl,
	339	.stop_tx = ulite_stop_tx,
	340	.start_tx = ulite_start_tx,
	341	.stop_rx = ulite_stop_rx,
	342	.enable_ms = ulite_enable_ms,
	343	.break_ctl = ulite_break_ctl,
	344	.startup = ulite_startup,
	345	.shutdown = ulite_shutdown,
	346	.set_termios = ulite_set_termios,
	347	.type = ulite_type,
	348	.release_port = ulite_release_port,
	349	.request_port = ulite_request_port,
	350	.config_port = ulite_config_port,
8a28af7f MS	351	.verify_port = ulite_verify_port,
	352	#ifdef CONFIG_CONSOLE_POLL
	353	.poll_get_char = ulite_get_poll_char,
	354	.poll_put_char = ulite_put_poll_char,
	355	#endif
238b8721 PK	356	};
238b8721 PK	357
435706b3 GL	358	/* ---------------------------------------------------------------------
	359	* Console driver operations
	360	*/
	361
238b8721 PK	362	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	363	static void ulite_console_wait_tx(struct uart_port *port)
	364	{
	365	int i;
1d6b6987	366	u8 val;
238b8721	367
1d6b6987 GL	368	/* Spin waiting for TX fifo to have space available */
1d6b6987 GL	369	for (i = 0; i < 100000; i++) {
e5bbbb18	370	val = ioread32be(port->membase + ULITE_STATUS);
1d6b6987	371	if ((val & ULITE_STATUS_TXFULL) == 0)
238b8721	372	break;
1d6b6987	373	cpu_relax();
238b8721 PK	374	}
	375	}
	376
	377	static void ulite_console_putchar(struct uart_port *port, int ch)
	378	{
	379	ulite_console_wait_tx(port);
e5bbbb18	380	iowrite32be(ch, port->membase + ULITE_TX);
238b8721 PK	381	}
	382
	383	static void ulite_console_write(struct console co, const char s,
	384	unsigned int count)
	385	{
483c79db	386	struct uart_port *port = &ulite_ports[co->index];
238b8721 PK	387	unsigned long flags;
	388	unsigned int ier;
	389	int locked = 1;
	390
	391	if (oops_in_progress) {
	392	locked = spin_trylock_irqsave(&port->lock, flags);
	393	} else
	394	spin_lock_irqsave(&port->lock, flags);
	395
	396	/* save and disable interrupt */
e5bbbb18 JL	397	ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
e5bbbb18 JL	398	iowrite32be(0, port->membase + ULITE_CONTROL);
238b8721 PK	399
	400	uart_console_write(port, s, count, ulite_console_putchar);
	401
	402	ulite_console_wait_tx(port);
	403
	404	/* restore interrupt state */
	405	if (ier)
e5bbbb18	406	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
238b8721 PK	407
	408	if (locked)
	409	spin_unlock_irqrestore(&port->lock, flags);
	410	}
	411
03eac7bb	412	static int __devinit ulite_console_setup(struct console co, char options)
238b8721 PK	413	{
	414	struct uart_port *port;
	415	int baud = 9600;
	416	int bits = 8;
	417	int parity = 'n';
	418	int flow = 'n';
	419
	420	if (co->index < 0 \|\| co->index >= ULITE_NR_UARTS)
	421	return -EINVAL;
	422
483c79db	423	port = &ulite_ports[co->index];
238b8721	424
3de66a17	425	/* Has the device been initialized yet? */
fb4e6e66 GL	426	if (!port->mapbase) {
	427	pr_debug("console on ttyUL%i not present\n", co->index);
	428	return -ENODEV;
	429	}
	430
238b8721	431	/* not initialized yet? */
852e1ea7	432	if (!port->membase) {
fb4e6e66 GL	433	if (ulite_request_port(port))
fb4e6e66 GL	434	return -ENODEV;
852e1ea7	435	}
238b8721 PK	436
	437	if (options)
	438	uart_parse_options(options, &baud, &parity, &bits, &flow);
	439
	440	return uart_set_options(port, co, baud, parity, bits, flow);
	441	}
	442
	443	static struct uart_driver ulite_uart_driver;
	444
	445	static struct console ulite_console = {
00775828	446	.name = ULITE_NAME,
238b8721 PK	447	.write = ulite_console_write,
	448	.device = uart_console_device,
	449	.setup = ulite_console_setup,
	450	.flags = CON_PRINTBUFFER,
	451	.index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	452	.data = &ulite_uart_driver,
	453	};
	454
	455	static int __init ulite_console_init(void)
	456	{
	457	register_console(&ulite_console);
	458	return 0;
	459	}
	460
	461	console_initcall(ulite_console_init);
	462
	463	#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
	464
	465	static struct uart_driver ulite_uart_driver = {
	466	.owner = THIS_MODULE,
	467	.driver_name = "uartlite",
00775828	468	.dev_name = ULITE_NAME,
238b8721 PK	469	.major = ULITE_MAJOR,
	470	.minor = ULITE_MINOR,
	471	.nr = ULITE_NR_UARTS,
	472	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	473	.cons = &ulite_console,
	474	#endif
	475	};
	476
435706b3 GL	477	/* ---------------------------------------------------------------------
	478	* Port assignment functions (mapping devices to uart_port structures)
	479	*/
	480
	481	/** ulite_assign: register a uartlite device with the driver
	482	*
	483	* @dev: pointer to device structure
	484	* @id: requested id number. Pass -1 for automatic port assignment
	485	* @base: base address of uartlite registers
	486	* @irq: irq number for uartlite
	487	*
	488	* Returns: 0 on success, <0 otherwise
	489	*/
8fa7b610	490	static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
238b8721	491	{
238b8721	492	struct uart_port *port;
8fa7b610	493	int rc;
238b8721	494
8fa7b610 GL	495	/* if id = -1; then scan for a free id and use that */
	496	if (id < 0) {
	497	for (id = 0; id < ULITE_NR_UARTS; id++)
	498	if (ulite_ports[id].mapbase == 0)
	499	break;
	500	}
	501	if (id < 0 \|\| id >= ULITE_NR_UARTS) {
	502	dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
238b8721	503	return -EINVAL;
8fa7b610	504	}
238b8721	505
fb4e6e66	506	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
8fa7b610 GL	507	dev_err(dev, "cannot assign to %s%i; it is already in use\n",
8fa7b610 GL	508	ULITE_NAME, id);
238b8721	509	return -EBUSY;
8fa7b610	510	}
238b8721	511
8fa7b610	512	port = &ulite_ports[id];
238b8721	513
8fa7b610 GL	514	spin_lock_init(&port->lock);
	515	port->fifosize = 16;
	516	port->regshift = 2;
	517	port->iotype = UPIO_MEM;
	518	port->iobase = 1; /* mark port in use */
	519	port->mapbase = base;
	520	port->membase = NULL;
	521	port->ops = &ulite_ops;
	522	port->irq = irq;
	523	port->flags = UPF_BOOT_AUTOCONF;
	524	port->dev = dev;
	525	port->type = PORT_UNKNOWN;
	526	port->line = id;
	527
	528	dev_set_drvdata(dev, port);
	529
	530	/* Register the port */
	531	rc = uart_add_one_port(&ulite_uart_driver, port);
	532	if (rc) {
	533	dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
	534	port->mapbase = 0;
	535	dev_set_drvdata(dev, NULL);
	536	return rc;
	537	}
238b8721	538
8fa7b610 GL	539	return 0;
8fa7b610 GL	540	}
238b8721	541
435706b3 GL	542	/** ulite_release: register a uartlite device with the driver
	543	*
	544	* @dev: pointer to device structure
	545	*/
f67702a3	546	static int __devexit ulite_release(struct device *dev)
8fa7b610 GL	547	{
	548	struct uart_port *port = dev_get_drvdata(dev);
	549	int rc = 0;
238b8721	550
8fa7b610 GL	551	if (port) {
	552	rc = uart_remove_one_port(&ulite_uart_driver, port);
	553	dev_set_drvdata(dev, NULL);
	554	port->mapbase = 0;
	555	}
238b8721	556
8fa7b610	557	return rc;
238b8721 PK	558	}
238b8721 PK	559
435706b3 GL	560	/* ---------------------------------------------------------------------
	561	* Platform bus binding
	562	*/
	563
e5263a51 GL	564	#if defined(CONFIG_OF)
	565	/* Match table for of_platform binding */
	566	static struct of_device_id ulite_of_match[] __devinitdata = {
	567	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	568	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	569	{}
	570	};
	571	MODULE_DEVICE_TABLE(of, ulite_of_match);
e5263a51 GL	572	#endif /* CONFIG_OF */
e5263a51 GL	573
8fa7b610	574	static int __devinit ulite_probe(struct platform_device *pdev)
238b8721	575	{
8fa7b610	576	struct resource res, res2;
e5263a51 GL	577	int id = pdev->id;
	578	#ifdef CONFIG_OF
	579	const __be32 *prop;
	580
	581	prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
	582	if (prop)
	583	id = be32_to_cpup(prop);
	584	#endif
238b8721	585
8fa7b610 GL	586	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	587	if (!res)
	588	return -ENODEV;
238b8721	589
8fa7b610 GL	590	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	591	if (!res2)
	592	return -ENODEV;
238b8721	593
e5263a51	594	return ulite_assign(&pdev->dev, id, res->start, res2->start);
8fa7b610	595	}
238b8721	596
f67702a3	597	static int __devexit ulite_remove(struct platform_device *pdev)
8fa7b610 GL	598	{
8fa7b610 GL	599	return ulite_release(&pdev->dev);
238b8721 PK	600	}
238b8721 PK	601
e169c139 KS	602	/* work with hotplug and coldplug */
	603	MODULE_ALIAS("platform:uartlite");
	604
238b8721	605	static struct platform_driver ulite_platform_driver = {
e5263a51 GL	606	.probe = ulite_probe,
e5263a51 GL	607	.remove = __devexit_p(ulite_remove),
852e1ea7	608	.driver = {
4018294b	609	.owner = THIS_MODULE,
e5263a51	610	.name = "uartlite",
85888069	611	.of_match_table = of_match_ptr(ulite_of_match),
852e1ea7 GL	612	},
	613	};
	614
435706b3 GL	615	/* ---------------------------------------------------------------------
	616	* Module setup/teardown
	617	*/
	618
238b8721 PK	619	int __init ulite_init(void)
	620	{
	621	int ret;
	622
852e1ea7	623	pr_debug("uartlite: calling uart_register_driver()\n");
238b8721 PK	624	ret = uart_register_driver(&ulite_uart_driver);
238b8721 PK	625	if (ret)
852e1ea7 GL	626	goto err_uart;
852e1ea7 GL	627
852e1ea7	628	pr_debug("uartlite: calling platform_driver_register()\n");
238b8721 PK	629	ret = platform_driver_register(&ulite_platform_driver);
238b8721 PK	630	if (ret)
852e1ea7 GL	631	goto err_plat;
	632
	633	return 0;
238b8721	634
852e1ea7	635	err_plat:
852e1ea7 GL	636	uart_unregister_driver(&ulite_uart_driver);
	637	err_uart:
	638	printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
238b8721 PK	639	return ret;
	640	}
	641
	642	void __exit ulite_exit(void)
	643	{
	644	platform_driver_unregister(&ulite_platform_driver);
	645	uart_unregister_driver(&ulite_uart_driver);
	646	}
	647
	648	module_init(ulite_init);
	649	module_exit(ulite_exit);
	650
	651	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	652	MODULE_DESCRIPTION("Xilinx uartlite serial driver");
	653	MODULE_LICENSE("GPL");