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tty: serial/samsung: prepare for common clock API
[linux-2.6-block.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/delay.h>
43#include <linux/clk.h>
30555476 44#include <linux/cpufreq.h>
26c919e1 45#include <linux/of.h>
b497549a
BD		 46
47#include <asm/irq.h>
48
a09e64fb 49#include <mach/hardware.h>
b497549a 50
a2b7ba9c 51#include <plat/regs-serial.h>
5f5a7a55 52#include <plat/clock.h>
b497549a
BD		 53
54#include "samsung.h"
55
56/* UART name and device definitions */
57
58#define S3C24XX_SERIAL_NAME "ttySAC"
59#define S3C24XX_SERIAL_MAJOR 204
60#define S3C24XX_SERIAL_MINOR 64
61
b497549a
BD		 62/* macros to change one thing to another */
63
64#define tx_enabled(port) ((port)->unused[0])
65#define rx_enabled(port) ((port)->unused[1])
66
25985edc 67/* flag to ignore all characters coming in */
b497549a
BD		 68#define RXSTAT_DUMMY_READ (0x10000000)
69
70static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71{
72 return container_of(port, struct s3c24xx_uart_port, port);
73}
74
75/* translate a port to the device name */
76
77static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78{
79 return to_platform_device(port->dev)->name;
80}
81
82static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83{
9303ac15 84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 85}
86
88bb4ea1
TA		 87/*
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
91 */
92static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93{
94 return to_ourport(port)->info->type == PORT_S3C6400;
95}
96
b497549a
BD		 97static void s3c24xx_serial_rx_enable(struct uart_port *port)
98{
99 unsigned long flags;
100 unsigned int ucon, ufcon;
101 int count = 10000;
102
103 spin_lock_irqsave(&port->lock, flags);
104
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
106 udelay(100);
107
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
111
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
115
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
118}
119
120static void s3c24xx_serial_rx_disable(struct uart_port *port)
121{
122 unsigned long flags;
123 unsigned int ucon;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
130
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
133}
134
135static void s3c24xx_serial_stop_tx(struct uart_port *port)
136{
b73c289c
BD		 137 struct s3c24xx_uart_port *ourport = to_ourport(port);
138
b497549a 139 if (tx_enabled(port)) {
88bb4ea1
TA		 140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
143 else
144 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
148 }
149}
150
151static void s3c24xx_serial_start_tx(struct uart_port *port)
152{
b73c289c
BD		 153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
b497549a
BD		 155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
158
88bb4ea1
TA		 159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 enable_irq(ourport->tx_irq);
b497549a
BD		 164 tx_enabled(port) = 1;
165 }
166}
167
b497549a
BD		 168static void s3c24xx_serial_stop_rx(struct uart_port *port)
169{
b73c289c
BD		 170 struct s3c24xx_uart_port *ourport = to_ourport(port);
171
b497549a
BD		 172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
177 else
178 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 179 rx_enabled(port) = 0;
180 }
181}
182
183static void s3c24xx_serial_enable_ms(struct uart_port *port)
184{
185}
186
187static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188{
189 return to_ourport(port)->info;
190}
191
192static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193{
4d84e970
TA		 194 struct s3c24xx_uart_port *ourport;
195
b497549a
BD		 196 if (port->dev == NULL)
197 return NULL;
198
4d84e970
TA		 199 ourport = container_of(port, struct s3c24xx_uart_port, port);
200 return ourport->cfg;
b497549a
BD		 201}
202
203static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
205{
206 struct s3c24xx_uart_info *info = ourport->info;
207
208 if (ufstat & info->rx_fifofull)
da121506 209 return ourport->port.fifosize;
b497549a
BD		 210
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212}
213
214
215/* ? - where has parity gone?? */
216#define S3C2410_UERSTAT_PARITY (0x1000)
217
218static irqreturn_t
219s3c24xx_serial_rx_chars(int irq, void *dev_id)
220{
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
b497549a 223 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 224 unsigned long flags;
b497549a
BD		 225 int max_count = 64;
226
c15c3747
TA		 227 spin_lock_irqsave(&port->lock, flags);
228
b497549a
BD		 229 while (max_count-- > 0) {
230 ufcon = rd_regl(port, S3C2410_UFCON);
231 ufstat = rd_regl(port, S3C2410_UFSTAT);
232
233 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
234 break;
235
236 uerstat = rd_regl(port, S3C2410_UERSTAT);
237 ch = rd_regb(port, S3C2410_URXH);
238
239 if (port->flags & UPF_CONS_FLOW) {
240 int txe = s3c24xx_serial_txempty_nofifo(port);
241
242 if (rx_enabled(port)) {
243 if (!txe) {
244 rx_enabled(port) = 0;
245 continue;
246 }
247 } else {
248 if (txe) {
249 ufcon |= S3C2410_UFCON_RESETRX;
250 wr_regl(port, S3C2410_UFCON, ufcon);
251 rx_enabled(port) = 1;
252 goto out;
253 }
254 continue;
255 }
256 }
257
258 /* insert the character into the buffer */
259
260 flag = TTY_NORMAL;
261 port->icount.rx++;
262
263 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
264 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
265 ch, uerstat);
266
267 /* check for break */
268 if (uerstat & S3C2410_UERSTAT_BREAK) {
269 dbg("break!\n");
270 port->icount.brk++;
271 if (uart_handle_break(port))
9303ac15 272 goto ignore_char;
b497549a
BD		 273 }
274
275 if (uerstat & S3C2410_UERSTAT_FRAME)
276 port->icount.frame++;
277 if (uerstat & S3C2410_UERSTAT_OVERRUN)
278 port->icount.overrun++;
279
280 uerstat &= port->read_status_mask;
281
282 if (uerstat & S3C2410_UERSTAT_BREAK)
283 flag = TTY_BREAK;
284 else if (uerstat & S3C2410_UERSTAT_PARITY)
285 flag = TTY_PARITY;
286 else if (uerstat & (S3C2410_UERSTAT_FRAME |
287 S3C2410_UERSTAT_OVERRUN))
288 flag = TTY_FRAME;
289 }
290
291 if (uart_handle_sysrq_char(port, ch))
292 goto ignore_char;
293
294 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
295 ch, flag);
296
297 ignore_char:
298 continue;
299 }
2e124b4a 300 tty_flip_buffer_push(&port->state->port);
b497549a
BD		 301
302 out:
c15c3747 303 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 304 return IRQ_HANDLED;
305}
306
307static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
308{
309 struct s3c24xx_uart_port *ourport = id;
310 struct uart_port *port = &ourport->port;
ebd2c8f6 311 struct circ_buf *xmit = &port->state->xmit;
c15c3747 312 unsigned long flags;
b497549a
BD		 313 int count = 256;
314
c15c3747
TA		 315 spin_lock_irqsave(&port->lock, flags);
316
b497549a
BD		 317 if (port->x_char) {
318 wr_regb(port, S3C2410_UTXH, port->x_char);
319 port->icount.tx++;
320 port->x_char = 0;
321 goto out;
322 }
323
25985edc 324 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 325 * stopped, disable the uart and exit
326 */
327
328 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
329 s3c24xx_serial_stop_tx(port);
330 goto out;
331 }
332
333 /* try and drain the buffer... */
334
335 while (!uart_circ_empty(xmit) && count-- > 0) {
336 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
337 break;
338
339 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
340 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
341 port->icount.tx++;
342 }
343
c15c3747
TA		 344 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
345 spin_unlock(&port->lock);
b497549a 346 uart_write_wakeup(port);
c15c3747
TA		 347 spin_lock(&port->lock);
348 }
b497549a
BD		 349
350 if (uart_circ_empty(xmit))
351 s3c24xx_serial_stop_tx(port);
352
353 out:
c15c3747 354 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 355 return IRQ_HANDLED;
356}
357
88bb4ea1
TA		 358/* interrupt handler for s3c64xx and later SoC's.*/
359static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
360{
361 struct s3c24xx_uart_port *ourport = id;
362 struct uart_port *port = &ourport->port;
363 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 364 irqreturn_t ret = IRQ_HANDLED;
365
88bb4ea1
TA		 366 if (pend & S3C64XX_UINTM_RXD_MSK) {
367 ret = s3c24xx_serial_rx_chars(irq, id);
368 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
369 }
370 if (pend & S3C64XX_UINTM_TXD_MSK) {
371 ret = s3c24xx_serial_tx_chars(irq, id);
372 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
373 }
88bb4ea1
TA		 374 return ret;
375}
376
b497549a
BD		 377static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
378{
379 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
380 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
381 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
382
383 if (ufcon & S3C2410_UFCON_FIFOMODE) {
384 if ((ufstat & info->tx_fifomask) != 0 ||
385 (ufstat & info->tx_fifofull))
386 return 0;
387
388 return 1;
389 }
390
391 return s3c24xx_serial_txempty_nofifo(port);
392}
393
394/* no modem control lines */
395static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
396{
397 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
398
399 if (umstat & S3C2410_UMSTAT_CTS)
400 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
401 else
402 return TIOCM_CAR | TIOCM_DSR;
403}
404
405static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
406{
407 /* todo - possibly remove AFC and do manual CTS */
408}
409
410static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
411{
412 unsigned long flags;
413 unsigned int ucon;
414
415 spin_lock_irqsave(&port->lock, flags);
416
417 ucon = rd_regl(port, S3C2410_UCON);
418
419 if (break_state)
420 ucon |= S3C2410_UCON_SBREAK;
421 else
422 ucon &= ~S3C2410_UCON_SBREAK;
423
424 wr_regl(port, S3C2410_UCON, ucon);
425
426 spin_unlock_irqrestore(&port->lock, flags);
427}
428
429static void s3c24xx_serial_shutdown(struct uart_port *port)
430{
431 struct s3c24xx_uart_port *ourport = to_ourport(port);
432
433 if (ourport->tx_claimed) {
88bb4ea1
TA		 434 if (!s3c24xx_serial_has_interrupt_mask(port))
435 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 436 tx_enabled(port) = 0;
437 ourport->tx_claimed = 0;
438 }
439
440 if (ourport->rx_claimed) {
88bb4ea1
TA		 441 if (!s3c24xx_serial_has_interrupt_mask(port))
442 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 443 ourport->rx_claimed = 0;
444 rx_enabled(port) = 0;
445 }
b497549a 446
88bb4ea1
TA		 447 /* Clear pending interrupts and mask all interrupts */
448 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 449 free_irq(port->irq, ourport);
450
88bb4ea1
TA		 451 wr_regl(port, S3C64XX_UINTP, 0xf);
452 wr_regl(port, S3C64XX_UINTM, 0xf);
453 }
454}
b497549a
BD		 455
456static int s3c24xx_serial_startup(struct uart_port *port)
457{
458 struct s3c24xx_uart_port *ourport = to_ourport(port);
459 int ret;
460
461 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
462 port->mapbase, port->membase);
463
464 rx_enabled(port) = 1;
465
b73c289c 466 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 467 s3c24xx_serial_portname(port), ourport);
468
469 if (ret != 0) {
d20925e1 470 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 471 return ret;
472 }
473
474 ourport->rx_claimed = 1;
475
476 dbg("requesting tx irq...\n");
477
478 tx_enabled(port) = 1;
479
b73c289c 480 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 481 s3c24xx_serial_portname(port), ourport);
482
483 if (ret) {
d20925e1 484 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 485 goto err;
486 }
487
488 ourport->tx_claimed = 1;
489
490 dbg("s3c24xx_serial_startup ok\n");
491
492 /* the port reset code should have done the correct
493 * register setup for the port controls */
494
495 return ret;
496
497 err:
498 s3c24xx_serial_shutdown(port);
499 return ret;
500}
501
88bb4ea1
TA		 502static int s3c64xx_serial_startup(struct uart_port *port)
503{
504 struct s3c24xx_uart_port *ourport = to_ourport(port);
505 int ret;
506
507 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
508 port->mapbase, port->membase);
509
b6ad2935
TF		 510 wr_regl(port, S3C64XX_UINTM, 0xf);
511
88bb4ea1
TA		 512 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
513 s3c24xx_serial_portname(port), ourport);
514 if (ret) {
d20925e1 515 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 516 return ret;
517 }
518
519 /* For compatibility with s3c24xx Soc's */
520 rx_enabled(port) = 1;
521 ourport->rx_claimed = 1;
522 tx_enabled(port) = 0;
523 ourport->tx_claimed = 1;
524
525 /* Enable Rx Interrupt */
526 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
527 dbg("s3c64xx_serial_startup ok\n");
528 return ret;
529}
530
b497549a
BD		 531/* power power management control */
532
533static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
534 unsigned int old)
535{
536 struct s3c24xx_uart_port *ourport = to_ourport(port);
537
30555476
BD		 538 ourport->pm_level = level;
539
b497549a
BD		 540 switch (level) {
541 case 3:
7cd88831 542 if (!IS_ERR(ourport->baudclk))
9484b009 543 clk_disable_unprepare(ourport->baudclk);
b497549a 544
9484b009 545 clk_disable_unprepare(ourport->clk);
b497549a
BD		 546 break;
547
548 case 0:
9484b009 549 clk_prepare_enable(ourport->clk);
b497549a 550
7cd88831 551 if (!IS_ERR(ourport->baudclk))
9484b009 552 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 553
554 break;
555 default:
d20925e1 556 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 557 }
558}
559
560/* baud rate calculation
561 *
562 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
563 * of different sources, including the peripheral clock ("pclk") and an
564 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
565 * with a programmable extra divisor.
566 *
567 * The following code goes through the clock sources, and calculates the
568 * baud clocks (and the resultant actual baud rates) and then tries to
569 * pick the closest one and select that.
570 *
571*/
572
5f5a7a55 573#define MAX_CLK_NAME_LENGTH 15
b497549a 574
5f5a7a55 575static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 576{
577 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 578 unsigned int ucon;
b497549a 579
5f5a7a55
TA		 580 if (info->num_clks == 1)
581 return 0;
b497549a 582
5f5a7a55
TA		 583 ucon = rd_regl(port, S3C2410_UCON);
584 ucon &= info->clksel_mask;
585 return ucon >> info->clksel_shift;
b497549a
BD		 586}
587
5f5a7a55
TA		 588static void s3c24xx_serial_setsource(struct uart_port *port,
589 unsigned int clk_sel)
b497549a 590{
5f5a7a55
TA		 591 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
592 unsigned int ucon;
b497549a 593
5f5a7a55
TA		 594 if (info->num_clks == 1)
595 return;
090f848d 596
5f5a7a55
TA		 597 ucon = rd_regl(port, S3C2410_UCON);
598 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
599 return;
b497549a 600
5f5a7a55
TA		 601 ucon &= ~info->clksel_mask;
602 ucon |= clk_sel << info->clksel_shift;
603 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 604}
605
5f5a7a55
TA		 606static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
607 unsigned int req_baud, struct clk **best_clk,
608 unsigned int *clk_num)
b497549a 609{
5f5a7a55
TA		 610 struct s3c24xx_uart_info *info = ourport->info;
611 struct clk *clk;
612 unsigned long rate;
613 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
614 char clkname[MAX_CLK_NAME_LENGTH];
615 int calc_deviation, deviation = (1 << 30) - 1;
616
5f5a7a55
TA		 617 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
618 ourport->info->def_clk_sel;
619 for (cnt = 0; cnt < info->num_clks; cnt++) {
620 if (!(clk_sel & (1 << cnt)))
621 continue;
622
623 sprintf(clkname, "clk_uart_baud%d", cnt);
624 clk = clk_get(ourport->port.dev, clkname);
7cd88831 625 if (IS_ERR(clk))
5f5a7a55
TA		 626 continue;
627
628 rate = clk_get_rate(clk);
629 if (!rate)
630 continue;
631
632 if (ourport->info->has_divslot) {
633 unsigned long div = rate / req_baud;
634
635 /* The UDIVSLOT register on the newer UARTs allows us to
636 * get a divisor adjustment of 1/16th on the baud clock.
637 *
638 * We don't keep the UDIVSLOT value (the 16ths we
639 * calculated by not multiplying the baud by 16) as it
640 * is easy enough to recalculate.
641 */
642
643 quot = div / 16;
644 baud = rate / div;
645 } else {
646 quot = (rate + (8 * req_baud)) / (16 * req_baud);
647 baud = rate / (quot * 16);
b497549a 648 }
5f5a7a55 649 quot--;
b497549a 650
5f5a7a55
TA		 651 calc_deviation = req_baud - baud;
652 if (calc_deviation < 0)
653 calc_deviation = -calc_deviation;
b497549a 654
5f5a7a55
TA		 655 if (calc_deviation < deviation) {
656 *best_clk = clk;
657 best_quot = quot;
658 *clk_num = cnt;
659 deviation = calc_deviation;
b497549a
BD		 660 }
661 }
662
5f5a7a55 663 return best_quot;
b497549a
BD		 664}
665
090f848d
BD		 666/* udivslot_table[]
667 *
668 * This table takes the fractional value of the baud divisor and gives
669 * the recommended setting for the UDIVSLOT register.
670 */
671static u16 udivslot_table[16] = {
672 [0] = 0x0000,
673 [1] = 0x0080,
674 [2] = 0x0808,
675 [3] = 0x0888,
676 [4] = 0x2222,
677 [5] = 0x4924,
678 [6] = 0x4A52,
679 [7] = 0x54AA,
680 [8] = 0x5555,
681 [9] = 0xD555,
682 [10] = 0xD5D5,
683 [11] = 0xDDD5,
684 [12] = 0xDDDD,
685 [13] = 0xDFDD,
686 [14] = 0xDFDF,
687 [15] = 0xFFDF,
688};
689
b497549a
BD		 690static void s3c24xx_serial_set_termios(struct uart_port *port,
691 struct ktermios *termios,
692 struct ktermios *old)
693{
694 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
695 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 696 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 697 unsigned long flags;
5f5a7a55 698 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 699 unsigned int ulcon;
700 unsigned int umcon;
090f848d 701 unsigned int udivslot = 0;
b497549a
BD		 702
703 /*
704 * We don't support modem control lines.
705 */
706 termios->c_cflag &= ~(HUPCL | CMSPAR);
707 termios->c_cflag |= CLOCAL;
708
709 /*
710 * Ask the core to calculate the divisor for us.
711 */
712
713 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 714 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 715 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
716 quot = port->custom_divisor;
7cd88831 717 if (IS_ERR(clk))
5f5a7a55 718 return;
b497549a
BD		 719
720 /* check to see if we need to change clock source */
721
5f5a7a55
TA		 722 if (ourport->baudclk != clk) {
723 s3c24xx_serial_setsource(port, clk_sel);
b497549a 724
7cd88831 725 if (!IS_ERR(ourport->baudclk)) {
9484b009 726 clk_disable_unprepare(ourport->baudclk);
7cd88831 727 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 728 }
729
9484b009 730 clk_prepare_enable(clk);
b497549a 731
b497549a 732 ourport->baudclk = clk;
30555476 733 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 734 }
735
090f848d
BD		 736 if (ourport->info->has_divslot) {
737 unsigned int div = ourport->baudclk_rate / baud;
738
8b526ae4
JL		 739 if (cfg->has_fracval) {
740 udivslot = (div & 15);
741 dbg("fracval = %04x\n", udivslot);
742 } else {
743 udivslot = udivslot_table[div & 15];
744 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
745 }
090f848d
BD		 746 }
747
b497549a
BD		 748 switch (termios->c_cflag & CSIZE) {
749 case CS5:
750 dbg("config: 5bits/char\n");
751 ulcon = S3C2410_LCON_CS5;
752 break;
753 case CS6:
754 dbg("config: 6bits/char\n");
755 ulcon = S3C2410_LCON_CS6;
756 break;
757 case CS7:
758 dbg("config: 7bits/char\n");
759 ulcon = S3C2410_LCON_CS7;
760 break;
761 case CS8:
762 default:
763 dbg("config: 8bits/char\n");
764 ulcon = S3C2410_LCON_CS8;
765 break;
766 }
767
768 /* preserve original lcon IR settings */
769 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
770
771 if (termios->c_cflag & CSTOPB)
772 ulcon |= S3C2410_LCON_STOPB;
773
774 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
775
776 if (termios->c_cflag & PARENB) {
777 if (termios->c_cflag & PARODD)
778 ulcon |= S3C2410_LCON_PODD;
779 else
780 ulcon |= S3C2410_LCON_PEVEN;
781 } else {
782 ulcon |= S3C2410_LCON_PNONE;
783 }
784
785 spin_lock_irqsave(&port->lock, flags);
786
090f848d
BD		 787 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
788 ulcon, quot, udivslot);
b497549a
BD		 789
790 wr_regl(port, S3C2410_ULCON, ulcon);
791 wr_regl(port, S3C2410_UBRDIV, quot);
792 wr_regl(port, S3C2410_UMCON, umcon);
793
090f848d
BD		 794 if (ourport->info->has_divslot)
795 wr_regl(port, S3C2443_DIVSLOT, udivslot);
796
b497549a
BD		 797 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
798 rd_regl(port, S3C2410_ULCON),
799 rd_regl(port, S3C2410_UCON),
800 rd_regl(port, S3C2410_UFCON));
801
802 /*
803 * Update the per-port timeout.
804 */
805 uart_update_timeout(port, termios->c_cflag, baud);
806
807 /*
808 * Which character status flags are we interested in?
809 */
810 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
811 if (termios->c_iflag & INPCK)
812 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
813
814 /*
815 * Which character status flags should we ignore?
816 */
817 port->ignore_status_mask = 0;
818 if (termios->c_iflag & IGNPAR)
819 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
820 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
821 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
822
823 /*
824 * Ignore all characters if CREAD is not set.
825 */
826 if ((termios->c_cflag & CREAD) == 0)
827 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
828
829 spin_unlock_irqrestore(&port->lock, flags);
830}
831
832static const char *s3c24xx_serial_type(struct uart_port *port)
833{
834 switch (port->type) {
835 case PORT_S3C2410:
836 return "S3C2410";
837 case PORT_S3C2440:
838 return "S3C2440";
839 case PORT_S3C2412:
840 return "S3C2412";
b690ace5
BD		 841 case PORT_S3C6400:
842 return "S3C6400/10";
b497549a
BD		 843 default:
844 return NULL;
845 }
846}
847
848#define MAP_SIZE (0x100)
849
850static void s3c24xx_serial_release_port(struct uart_port *port)
851{
852 release_mem_region(port->mapbase, MAP_SIZE);
853}
854
855static int s3c24xx_serial_request_port(struct uart_port *port)
856{
857 const char *name = s3c24xx_serial_portname(port);
858 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
859}
860
861static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
862{
863 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
864
865 if (flags & UART_CONFIG_TYPE &&
866 s3c24xx_serial_request_port(port) == 0)
867 port->type = info->type;
868}
869
870/*
871 * verify the new serial_struct (for TIOCSSERIAL).
872 */
873static int
874s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
875{
876 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
877
878 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
879 return -EINVAL;
880
881 return 0;
882}
883
884
885#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
886
887static struct console s3c24xx_serial_console;
888
93b5c032
JP		 889static int __init s3c24xx_serial_console_init(void)
890{
891 register_console(&s3c24xx_serial_console);
892 return 0;
893}
894console_initcall(s3c24xx_serial_console_init);
895
b497549a
BD		 896#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
897#else
898#define S3C24XX_SERIAL_CONSOLE NULL
899#endif
900
93b5c032
JP		 901#ifdef CONFIG_CONSOLE_POLL
902static int s3c24xx_serial_get_poll_char(struct uart_port *port);
903static void s3c24xx_serial_put_poll_char(struct uart_port *port,
904 unsigned char c);
905#endif
906
b497549a
BD		 907static struct uart_ops s3c24xx_serial_ops = {
908 .pm = s3c24xx_serial_pm,
909 .tx_empty = s3c24xx_serial_tx_empty,
910 .get_mctrl = s3c24xx_serial_get_mctrl,
911 .set_mctrl = s3c24xx_serial_set_mctrl,
912 .stop_tx = s3c24xx_serial_stop_tx,
913 .start_tx = s3c24xx_serial_start_tx,
914 .stop_rx = s3c24xx_serial_stop_rx,
915 .enable_ms = s3c24xx_serial_enable_ms,
916 .break_ctl = s3c24xx_serial_break_ctl,
917 .startup = s3c24xx_serial_startup,
918 .shutdown = s3c24xx_serial_shutdown,
919 .set_termios = s3c24xx_serial_set_termios,
920 .type = s3c24xx_serial_type,
921 .release_port = s3c24xx_serial_release_port,
922 .request_port = s3c24xx_serial_request_port,
923 .config_port = s3c24xx_serial_config_port,
924 .verify_port = s3c24xx_serial_verify_port,
93b5c032
JP		 925#ifdef CONFIG_CONSOLE_POLL
926 .poll_get_char = s3c24xx_serial_get_poll_char,
927 .poll_put_char = s3c24xx_serial_put_poll_char,
928#endif
b497549a
BD		 929};
930
b497549a
BD		 931static struct uart_driver s3c24xx_uart_drv = {
932 .owner = THIS_MODULE,
2cf0c58e 933 .driver_name = "s3c2410_serial",
bdd4915a 934 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 935 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 936 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 937 .major = S3C24XX_SERIAL_MAJOR,
938 .minor = S3C24XX_SERIAL_MINOR,
939};
940
03d5e77b 941static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 942 [0] = {
943 .port = {
944 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
945 .iotype = UPIO_MEM,
b497549a
BD		 946 .uartclk = 0,
947 .fifosize = 16,
948 .ops = &s3c24xx_serial_ops,
949 .flags = UPF_BOOT_AUTOCONF,
950 .line = 0,
951 }
952 },
953 [1] = {
954 .port = {
955 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
956 .iotype = UPIO_MEM,
b497549a
BD		 957 .uartclk = 0,
958 .fifosize = 16,
959 .ops = &s3c24xx_serial_ops,
960 .flags = UPF_BOOT_AUTOCONF,
961 .line = 1,
962 }
963 },
03d5e77b 964#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 965
966 [2] = {
967 .port = {
968 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
969 .iotype = UPIO_MEM,
b497549a
BD		 970 .uartclk = 0,
971 .fifosize = 16,
972 .ops = &s3c24xx_serial_ops,
973 .flags = UPF_BOOT_AUTOCONF,
974 .line = 2,
975 }
03d5e77b
BD		 976 },
977#endif
978#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
979 [3] = {
980 .port = {
981 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
982 .iotype = UPIO_MEM,
03d5e77b
BD		 983 .uartclk = 0,
984 .fifosize = 16,
985 .ops = &s3c24xx_serial_ops,
986 .flags = UPF_BOOT_AUTOCONF,
987 .line = 3,
988 }
b497549a
BD		 989 }
990#endif
991};
992
993/* s3c24xx_serial_resetport
994 *
0dfb3b41 995 * reset the fifos and other the settings.
b497549a
BD		 996*/
997
0dfb3b41
TA		 998static void s3c24xx_serial_resetport(struct uart_port *port,
999 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1000{
1001 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1002 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1003 unsigned int ucon_mask;
b497549a 1004
0dfb3b41
TA		 1005 ucon_mask = info->clksel_mask;
1006 if (info->type == PORT_S3C2440)
1007 ucon_mask |= S3C2440_UCON0_DIVMASK;
1008
1009 ucon &= ucon_mask;
1010 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1011
1012 /* reset both fifos */
1013 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1014 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1015
1016 /* some delay is required after fifo reset */
1017 udelay(1);
b497549a
BD		 1018}
1019
30555476
BD		 1020
1021#ifdef CONFIG_CPU_FREQ
1022
1023static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1024 unsigned long val, void *data)
1025{
1026 struct s3c24xx_uart_port *port;
1027 struct uart_port *uport;
1028
1029 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1030 uport = &port->port;
1031
1032 /* check to see if port is enabled */
1033
1034 if (port->pm_level != 0)
1035 return 0;
1036
1037 /* try and work out if the baudrate is changing, we can detect
1038 * a change in rate, but we do not have support for detecting
1039 * a disturbance in the clock-rate over the change.
1040 */
1041
25f04ad4 1042 if (IS_ERR(port->baudclk))
30555476
BD		 1043 goto exit;
1044
25f04ad4 1045 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1046 goto exit;
1047
1048 if (val == CPUFREQ_PRECHANGE) {
1049 /* we should really shut the port down whilst the
1050 * frequency change is in progress. */
1051
1052 } else if (val == CPUFREQ_POSTCHANGE) {
1053 struct ktermios *termios;
1054 struct tty_struct *tty;
1055
ebd2c8f6 1056 if (uport->state == NULL)
30555476 1057 goto exit;
30555476 1058
ebd2c8f6 1059 tty = uport->state->port.tty;
30555476 1060
7de40c21 1061 if (tty == NULL)
30555476 1062 goto exit;
30555476 1063
adc8d746 1064 termios = &tty->termios;
30555476
BD		 1065
1066 if (termios == NULL) {
d20925e1 1067 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1068 goto exit;
1069 }
1070
1071 s3c24xx_serial_set_termios(uport, termios, NULL);
1072 }
1073
1074 exit:
1075 return 0;
1076}
1077
1078static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1079{
1080 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1081
1082 return cpufreq_register_notifier(&port->freq_transition,
1083 CPUFREQ_TRANSITION_NOTIFIER);
1084}
1085
1086static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1087{
1088 cpufreq_unregister_notifier(&port->freq_transition,
1089 CPUFREQ_TRANSITION_NOTIFIER);
1090}
1091
1092#else
1093static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1094{
1095 return 0;
1096}
1097
1098static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1099{
1100}
1101#endif
1102
b497549a
BD		 1103/* s3c24xx_serial_init_port
1104 *
1105 * initialise a single serial port from the platform device given
1106 */
1107
1108static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1109 struct platform_device *platdev)
1110{
1111 struct uart_port *port = &ourport->port;
da121506 1112 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1113 struct resource *res;
1114 int ret;
1115
1116 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1117
1118 if (platdev == NULL)
1119 return -ENODEV;
1120
b497549a
BD		 1121 if (port->mapbase != 0)
1122 return 0;
1123
b497549a
BD		 1124 /* setup info for port */
1125 port->dev = &platdev->dev;
b497549a 1126
88bb4ea1
TA		 1127 /* Startup sequence is different for s3c64xx and higher SoC's */
1128 if (s3c24xx_serial_has_interrupt_mask(port))
1129 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1130
b497549a
BD		 1131 port->uartclk = 1;
1132
1133 if (cfg->uart_flags & UPF_CONS_FLOW) {
1134 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1135 port->flags |= UPF_CONS_FLOW;
1136 }
1137
1138 /* sort our the physical and virtual addresses for each UART */
1139
1140 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1141 if (res == NULL) {
d20925e1 1142 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1143 return -EINVAL;
1144 }
1145
1146 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1147
41147bfd
TA		 1148 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1149 if (!port->membase) {
1150 dev_err(port->dev, "failed to remap controller address\n");
1151 return -EBUSY;
1152 }
1153
b690ace5 1154 port->mapbase = res->start;
b497549a
BD		 1155 ret = platform_get_irq(platdev, 0);
1156 if (ret < 0)
1157 port->irq = 0;
b73c289c 1158 else {
b497549a 1159 port->irq = ret;
b73c289c
BD		 1160 ourport->rx_irq = ret;
1161 ourport->tx_irq = ret + 1;
1162 }
9303ac15 1163
b73c289c
BD		 1164 ret = platform_get_irq(platdev, 1);
1165 if (ret > 0)
1166 ourport->tx_irq = ret;
b497549a
BD		 1167
1168 ourport->clk = clk_get(&platdev->dev, "uart");
1169
88bb4ea1
TA		 1170 /* Keep all interrupts masked and cleared */
1171 if (s3c24xx_serial_has_interrupt_mask(port)) {
1172 wr_regl(port, S3C64XX_UINTM, 0xf);
1173 wr_regl(port, S3C64XX_UINTP, 0xf);
1174 wr_regl(port, S3C64XX_UINTSP, 0xf);
1175 }
1176
b73c289c
BD		 1177 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1178 port->mapbase, port->membase, port->irq,
1179 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1180
1181 /* reset the fifos (and setup the uart) */
1182 s3c24xx_serial_resetport(port, cfg);
1183 return 0;
1184}
1185
17efd2b7 1186#ifdef CONFIG_SAMSUNG_CLOCK
b497549a
BD		 1187static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1188 struct device_attribute *attr,
1189 char *buf)
1190{
1191 struct uart_port *port = s3c24xx_dev_to_port(dev);
1192 struct s3c24xx_uart_port *ourport = to_ourport(port);
1193
7cd88831
KK		 1194 if (IS_ERR(ourport->baudclk))
1195 return -EINVAL;
1196
7b15e1d9
KP		 1197 return snprintf(buf, PAGE_SIZE, "* %s\n",
1198 ourport->baudclk->name ?: "(null)");
b497549a
BD		 1199}
1200
1201static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
17efd2b7 1202#endif
26c919e1 1203
b497549a
BD		 1204/* Device driver serial port probe */
1205
26c919e1 1206static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1207static int probe_index;
1208
26c919e1
TA		 1209static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1210 struct platform_device *pdev)
1211{
1212#ifdef CONFIG_OF
1213 if (pdev->dev.of_node) {
1214 const struct of_device_id *match;
1215 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1216 return (struct s3c24xx_serial_drv_data *)match->data;
1217 }
1218#endif
1219 return (struct s3c24xx_serial_drv_data *)
1220 platform_get_device_id(pdev)->driver_data;
1221}
1222
da121506 1223static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a
BD		 1224{
1225 struct s3c24xx_uart_port *ourport;
1226 int ret;
1227
da121506 1228 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
b497549a
BD		 1229
1230 ourport = &s3c24xx_serial_ports[probe_index];
da121506 1231
26c919e1
TA		 1232 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1233 if (!ourport->drv_data) {
1234 dev_err(&pdev->dev, "could not find driver data\n");
1235 return -ENODEV;
1236 }
da121506 1237
7cd88831 1238 ourport->baudclk = ERR_PTR(-EINVAL);
da121506
TA		 1239 ourport->info = ourport->drv_data->info;
1240 ourport->cfg = (pdev->dev.platform_data) ?
1241 (struct s3c2410_uartcfg *)pdev->dev.platform_data :
1242 ourport->drv_data->def_cfg;
1243
1244 ourport->port.fifosize = (ourport->info->fifosize) ?
1245 ourport->info->fifosize :
1246 ourport->drv_data->fifosize[probe_index];
1247
b497549a
BD		 1248 probe_index++;
1249
1250 dbg("%s: initialising port %p...\n", __func__, ourport);
1251
da121506 1252 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a
BD		 1253 if (ret < 0)
1254 goto probe_err;
1255
1256 dbg("%s: adding port\n", __func__);
1257 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1258 platform_set_drvdata(pdev, &ourport->port);
b497549a 1259
17efd2b7 1260#ifdef CONFIG_SAMSUNG_CLOCK
da121506 1261 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
b497549a 1262 if (ret < 0)
da121506 1263 dev_err(&pdev->dev, "failed to add clock source attr.\n");
17efd2b7 1264#endif
b497549a 1265
30555476
BD		 1266 ret = s3c24xx_serial_cpufreq_register(ourport);
1267 if (ret < 0)
da121506 1268 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1269
b497549a
BD		 1270 return 0;
1271
1272 probe_err:
1273 return ret;
1274}
1275
ae8d8a14 1276static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1277{
1278 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1279
1280 if (port) {
30555476 1281 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
17efd2b7 1282#ifdef CONFIG_SAMSUNG_CLOCK
b497549a 1283 device_remove_file(&dev->dev, &dev_attr_clock_source);
17efd2b7 1284#endif
b497549a
BD		 1285 uart_remove_one_port(&s3c24xx_uart_drv, port);
1286 }
1287
1288 return 0;
1289}
1290
b497549a 1291/* UART power management code */
aef7fe52
MH		 1292#ifdef CONFIG_PM_SLEEP
1293static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1294{
aef7fe52 1295 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1296
1297 if (port)
1298 uart_suspend_port(&s3c24xx_uart_drv, port);
1299
1300 return 0;
1301}
1302
aef7fe52 1303static int s3c24xx_serial_resume(struct device *dev)
b497549a 1304{
aef7fe52 1305 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1306 struct s3c24xx_uart_port *ourport = to_ourport(port);
1307
1308 if (port) {
9484b009 1309 clk_prepare_enable(ourport->clk);
b497549a 1310 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1311 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1312
1313 uart_resume_port(&s3c24xx_uart_drv, port);
1314 }
1315
1316 return 0;
1317}
aef7fe52 1318
d09a7308
MS		 1319static int s3c24xx_serial_resume_noirq(struct device *dev)
1320{
1321 struct uart_port *port = s3c24xx_dev_to_port(dev);
1322
1323 if (port) {
1324 /* restore IRQ mask */
1325 if (s3c24xx_serial_has_interrupt_mask(port)) {
1326 unsigned int uintm = 0xf;
1327 if (tx_enabled(port))
1328 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1329 if (rx_enabled(port))
1330 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1331 wr_regl(port, S3C64XX_UINTM, uintm);
1332 }
1333 }
1334
1335 return 0;
1336}
1337
aef7fe52
MH		 1338static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1339 .suspend = s3c24xx_serial_suspend,
1340 .resume = s3c24xx_serial_resume,
d09a7308 1341 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1342};
b882fc1b
KK		 1343#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1344
aef7fe52 1345#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1346
1347#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1348#endif /* CONFIG_PM_SLEEP */
b497549a 1349
b497549a
BD		 1350/* Console code */
1351
1352#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1353
1354static struct uart_port *cons_uart;
1355
1356static int
1357s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1358{
1359 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1360 unsigned long ufstat, utrstat;
1361
1362 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1363 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1364
1365 ufstat = rd_regl(port, S3C2410_UFSTAT);
1366 return (ufstat & info->tx_fifofull) ? 0 : 1;
1367 }
1368
1369 /* in non-fifo mode, we go and use the tx buffer empty */
1370
1371 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1372 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1373}
1374
38adbc54
MS		 1375static bool
1376s3c24xx_port_configured(unsigned int ucon)
1377{
1378 /* consider the serial port configured if the tx/rx mode set */
1379 return (ucon & 0xf) != 0;
1380}
1381
93b5c032
JP		 1382#ifdef CONFIG_CONSOLE_POLL
1383/*
1384 * Console polling routines for writing and reading from the uart while
1385 * in an interrupt or debug context.
1386 */
1387
1388static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1389{
1390 struct s3c24xx_uart_port *ourport = to_ourport(port);
1391 unsigned int ufstat;
1392
1393 ufstat = rd_regl(port, S3C2410_UFSTAT);
1394 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1395 return NO_POLL_CHAR;
1396
1397 return rd_regb(port, S3C2410_URXH);
1398}
1399
1400static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1401 unsigned char c)
1402{
1403 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
38adbc54
MS		 1404 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1405
1406 /* not possible to xmit on unconfigured port */
1407 if (!s3c24xx_port_configured(ucon))
1408 return;
93b5c032
JP		 1409
1410 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1411 cpu_relax();
1412 wr_regb(cons_uart, S3C2410_UTXH, c);
1413}
1414
1415#endif /* CONFIG_CONSOLE_POLL */
1416
b497549a
BD		 1417static void
1418s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1419{
1420 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
38adbc54
MS		 1421 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1422
1423 /* not possible to xmit on unconfigured port */
1424 if (!s3c24xx_port_configured(ucon))
1425 return;
1426
b497549a
BD		 1427 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1428 barrier();
1429 wr_regb(cons_uart, S3C2410_UTXH, ch);
1430}
1431
1432static void
1433s3c24xx_serial_console_write(struct console *co, const char *s,
1434 unsigned int count)
1435{
1436 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1437}
1438
1439static void __init
1440s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1441 int *parity, int *bits)
1442{
b497549a
BD		 1443 struct clk *clk;
1444 unsigned int ulcon;
1445 unsigned int ucon;
1446 unsigned int ubrdiv;
1447 unsigned long rate;
5f5a7a55
TA		 1448 unsigned int clk_sel;
1449 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1450
1451 ulcon = rd_regl(port, S3C2410_ULCON);
1452 ucon = rd_regl(port, S3C2410_UCON);
1453 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1454
1455 dbg("s3c24xx_serial_get_options: port=%p\n"
1456 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1457 port, ulcon, ucon, ubrdiv);
1458
38adbc54 1459 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 1460 switch (ulcon & S3C2410_LCON_CSMASK) {
1461 case S3C2410_LCON_CS5:
1462 *bits = 5;
1463 break;
1464 case S3C2410_LCON_CS6:
1465 *bits = 6;
1466 break;
1467 case S3C2410_LCON_CS7:
1468 *bits = 7;
1469 break;
1470 default:
1471 case S3C2410_LCON_CS8:
1472 *bits = 8;
1473 break;
1474 }
1475
1476 switch (ulcon & S3C2410_LCON_PMASK) {
1477 case S3C2410_LCON_PEVEN:
1478 *parity = 'e';
1479 break;
1480
1481 case S3C2410_LCON_PODD:
1482 *parity = 'o';
1483 break;
1484
1485 case S3C2410_LCON_PNONE:
1486 default:
1487 *parity = 'n';
1488 }
1489
1490 /* now calculate the baud rate */
1491
5f5a7a55
TA		 1492 clk_sel = s3c24xx_serial_getsource(port);
1493 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1494
5f5a7a55 1495 clk = clk_get(port->dev, clk_name);
7cd88831 1496 if (!IS_ERR(clk))
5f5a7a55 1497 rate = clk_get_rate(clk);
b497549a
BD		 1498 else
1499 rate = 1;
1500
b497549a
BD		 1501 *baud = rate / (16 * (ubrdiv + 1));
1502 dbg("calculated baud %d\n", *baud);
1503 }
1504
1505}
1506
b497549a
BD		 1507static int __init
1508s3c24xx_serial_console_setup(struct console *co, char *options)
1509{
1510 struct uart_port *port;
1511 int baud = 9600;
1512 int bits = 8;
1513 int parity = 'n';
1514 int flow = 'n';
1515
1516 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1517 co, co->index, options);
1518
1519 /* is this a valid port */
1520
03d5e77b 1521 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1522 co->index = 0;
1523
1524 port = &s3c24xx_serial_ports[co->index].port;
1525
1526 /* is the port configured? */
1527
ee430f16
TA		 1528 if (port->mapbase == 0x0)
1529 return -ENODEV;
b497549a
BD		 1530
1531 cons_uart = port;
1532
1533 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1534
1535 /*
1536 * Check whether an invalid uart number has been specified, and
1537 * if so, search for the first available port that does have
1538 * console support.
1539 */
1540 if (options)
1541 uart_parse_options(options, &baud, &parity, &bits, &flow);
1542 else
1543 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1544
1545 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1546
1547 return uart_set_options(port, co, baud, parity, bits, flow);
1548}
1549
b497549a
BD		 1550static struct console s3c24xx_serial_console = {
1551 .name = S3C24XX_SERIAL_NAME,
1552 .device = uart_console_device,
1553 .flags = CON_PRINTBUFFER,
1554 .index = -1,
1555 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1556 .setup = s3c24xx_serial_console_setup,
1557 .data = &s3c24xx_uart_drv,
b497549a 1558};
da121506
TA		 1559#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1560
1561#ifdef CONFIG_CPU_S3C2410
1562static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1563 .info = &(struct s3c24xx_uart_info) {
1564 .name = "Samsung S3C2410 UART",
1565 .type = PORT_S3C2410,
1566 .fifosize = 16,
1567 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1568 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1569 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1570 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1571 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1572 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1573 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1574 .num_clks = 2,
1575 .clksel_mask = S3C2410_UCON_CLKMASK,
1576 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1577 },
1578 .def_cfg = &(struct s3c2410_uartcfg) {
1579 .ucon = S3C2410_UCON_DEFAULT,
1580 .ufcon = S3C2410_UFCON_DEFAULT,
1581 },
1582};
1583#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1584#else
1585#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1586#endif
b497549a 1587
da121506
TA		 1588#ifdef CONFIG_CPU_S3C2412
1589static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1590 .info = &(struct s3c24xx_uart_info) {
1591 .name = "Samsung S3C2412 UART",
1592 .type = PORT_S3C2412,
1593 .fifosize = 64,
1594 .has_divslot = 1,
1595 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1596 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1597 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1598 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1599 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1600 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1601 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1602 .num_clks = 4,
1603 .clksel_mask = S3C2412_UCON_CLKMASK,
1604 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1605 },
1606 .def_cfg = &(struct s3c2410_uartcfg) {
1607 .ucon = S3C2410_UCON_DEFAULT,
1608 .ufcon = S3C2410_UFCON_DEFAULT,
1609 },
1610};
1611#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1612#else
1613#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1614#endif
b497549a 1615
da121506 1616#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 1617 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 1618static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1619 .info = &(struct s3c24xx_uart_info) {
1620 .name = "Samsung S3C2440 UART",
1621 .type = PORT_S3C2440,
1622 .fifosize = 64,
1623 .has_divslot = 1,
1624 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1625 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1626 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1627 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1628 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1629 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1630 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1631 .num_clks = 4,
1632 .clksel_mask = S3C2412_UCON_CLKMASK,
1633 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1634 },
1635 .def_cfg = &(struct s3c2410_uartcfg) {
1636 .ucon = S3C2410_UCON_DEFAULT,
1637 .ufcon = S3C2410_UFCON_DEFAULT,
1638 },
1639};
1640#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1641#else
1642#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1643#endif
b497549a 1644
da121506
TA		 1645#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1646 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1647 defined(CONFIG_CPU_S5PC100)
1648static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1649 .info = &(struct s3c24xx_uart_info) {
1650 .name = "Samsung S3C6400 UART",
1651 .type = PORT_S3C6400,
1652 .fifosize = 64,
1653 .has_divslot = 1,
1654 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1655 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1656 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1657 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1658 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1659 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1660 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1661 .num_clks = 4,
1662 .clksel_mask = S3C6400_UCON_CLKMASK,
1663 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1664 },
1665 .def_cfg = &(struct s3c2410_uartcfg) {
1666 .ucon = S3C2410_UCON_DEFAULT,
1667 .ufcon = S3C2410_UFCON_DEFAULT,
1668 },
1669};
1670#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1671#else
1672#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1673#endif
b497549a 1674
da121506
TA		 1675#ifdef CONFIG_CPU_S5PV210
1676static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1677 .info = &(struct s3c24xx_uart_info) {
1678 .name = "Samsung S5PV210 UART",
1679 .type = PORT_S3C6400,
1680 .has_divslot = 1,
1681 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1682 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1683 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1684 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1685 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1686 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1687 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1688 .num_clks = 2,
1689 .clksel_mask = S5PV210_UCON_CLKMASK,
1690 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1691 },
1692 .def_cfg = &(struct s3c2410_uartcfg) {
1693 .ucon = S5PV210_UCON_DEFAULT,
1694 .ufcon = S5PV210_UFCON_DEFAULT,
1695 },
1696 .fifosize = { 256, 64, 16, 16 },
1697};
1698#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1699#else
1700#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1701#endif
b497549a 1702
5f7b6d19 1703#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
2edb36c4
KK		 1704 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1705 defined(CONFIG_SOC_EXYNOS5440)
da121506
TA		 1706static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1707 .info = &(struct s3c24xx_uart_info) {
1708 .name = "Samsung Exynos4 UART",
1709 .type = PORT_S3C6400,
1710 .has_divslot = 1,
1711 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1712 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1713 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1714 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1715 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1716 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1717 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1718 .num_clks = 1,
1719 .clksel_mask = 0,
1720 .clksel_shift = 0,
1721 },
1722 .def_cfg = &(struct s3c2410_uartcfg) {
1723 .ucon = S5PV210_UCON_DEFAULT,
1724 .ufcon = S5PV210_UFCON_DEFAULT,
1725 .has_fracval = 1,
1726 },
1727 .fifosize = { 256, 64, 16, 16 },
1728};
1729#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1730#else
1731#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1732#endif
b497549a 1733
da121506
TA		 1734static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1735 {
1736 .name = "s3c2410-uart",
1737 .driver_data = S3C2410_SERIAL_DRV_DATA,
1738 }, {
1739 .name = "s3c2412-uart",
1740 .driver_data = S3C2412_SERIAL_DRV_DATA,
1741 }, {
1742 .name = "s3c2440-uart",
1743 .driver_data = S3C2440_SERIAL_DRV_DATA,
1744 }, {
1745 .name = "s3c6400-uart",
1746 .driver_data = S3C6400_SERIAL_DRV_DATA,
1747 }, {
1748 .name = "s5pv210-uart",
1749 .driver_data = S5PV210_SERIAL_DRV_DATA,
1750 }, {
1751 .name = "exynos4210-uart",
1752 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1753 },
1754 { },
1755};
1756MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1757
26c919e1
TA		 1758#ifdef CONFIG_OF
1759static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 1760 { .compatible = "samsung,s3c2410-uart",
1761 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1762 { .compatible = "samsung,s3c2412-uart",
1763 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1764 { .compatible = "samsung,s3c2440-uart",
1765 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1766 { .compatible = "samsung,s3c6400-uart",
1767 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1768 { .compatible = "samsung,s5pv210-uart",
1769 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 1770 { .compatible = "samsung,exynos4210-uart",
a169a888 1771 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
26c919e1
TA		 1772 {},
1773};
1774MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 1775#endif
1776
da121506
TA		 1777static struct platform_driver samsung_serial_driver = {
1778 .probe = s3c24xx_serial_probe,
2d47b716 1779 .remove = s3c24xx_serial_remove,
da121506
TA		 1780 .id_table = s3c24xx_serial_driver_ids,
1781 .driver = {
1782 .name = "samsung-uart",
1783 .owner = THIS_MODULE,
1784 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 1785 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 1786 },
1787};
b497549a 1788
da121506 1789/* module initialisation code */
b497549a 1790
da121506
TA		 1791static int __init s3c24xx_serial_modinit(void)
1792{
1793 int ret;
1794
1795 ret = uart_register_driver(&s3c24xx_uart_drv);
1796 if (ret < 0) {
d20925e1 1797 pr_err("Failed to register Samsung UART driver\n");
e740d8f1 1798 return ret;
da121506
TA		 1799 }
1800
1801 return platform_driver_register(&samsung_serial_driver);
b497549a
BD		 1802}
1803
da121506
TA		 1804static void __exit s3c24xx_serial_modexit(void)
1805{
1806 uart_unregister_driver(&s3c24xx_uart_drv);
1807}
1808
1809module_init(s3c24xx_serial_modinit);
1810module_exit(s3c24xx_serial_modexit);
b497549a 1811
da121506 1812MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1813MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1814MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1815MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)