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serial: samsung: no more support for S5P6440 and S5P6450 SoCs
[linux-2.6-block.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
9ee51f01 42#include <linux/serial_s3c.h>
b497549a
BD		 43#include <linux/delay.h>
44#include <linux/clk.h>
30555476 45#include <linux/cpufreq.h>
26c919e1 46#include <linux/of.h>
b497549a
BD		 47
48#include <asm/irq.h>
49
9ee51f01 50#ifdef CONFIG_SAMSUNG_CLOCK
5f5a7a55 51#include <plat/clock.h>
9ee51f01 52#endif
b497549a
BD		 53
54#include "samsung.h"
55
e4ac92df
JP		 56#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
57 defined(CONFIG_DEBUG_LL) && \
58 !defined(MODULE)
59
60extern void printascii(const char *);
61
62__printf(1, 2)
63static void dbg(const char *fmt, ...)
64{
65 va_list va;
66 char buff[256];
67
68 va_start(va, fmt);
a859c8b2 69 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 70 va_end(va);
71
72 printascii(buff);
73}
74
75#else
76#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
77#endif
78
b497549a
BD		 79/* UART name and device definitions */
80
81#define S3C24XX_SERIAL_NAME "ttySAC"
82#define S3C24XX_SERIAL_MAJOR 204
83#define S3C24XX_SERIAL_MINOR 64
84
b497549a
BD		 85/* macros to change one thing to another */
86
87#define tx_enabled(port) ((port)->unused[0])
88#define rx_enabled(port) ((port)->unused[1])
89
25985edc 90/* flag to ignore all characters coming in */
b497549a
BD		 91#define RXSTAT_DUMMY_READ (0x10000000)
92
93static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
94{
95 return container_of(port, struct s3c24xx_uart_port, port);
96}
97
98/* translate a port to the device name */
99
100static inline const char *s3c24xx_serial_portname(struct uart_port *port)
101{
102 return to_platform_device(port->dev)->name;
103}
104
105static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
106{
9303ac15 107 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 108}
109
88bb4ea1
TA		 110/*
111 * s3c64xx and later SoC's include the interrupt mask and status registers in
112 * the controller itself, unlike the s3c24xx SoC's which have these registers
113 * in the interrupt controller. Check if the port type is s3c64xx or higher.
114 */
115static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
116{
117 return to_ourport(port)->info->type == PORT_S3C6400;
118}
119
b497549a
BD		 120static void s3c24xx_serial_rx_enable(struct uart_port *port)
121{
122 unsigned long flags;
123 unsigned int ucon, ufcon;
124 int count = 10000;
125
126 spin_lock_irqsave(&port->lock, flags);
127
128 while (--count && !s3c24xx_serial_txempty_nofifo(port))
129 udelay(100);
130
131 ufcon = rd_regl(port, S3C2410_UFCON);
132 ufcon |= S3C2410_UFCON_RESETRX;
133 wr_regl(port, S3C2410_UFCON, ufcon);
134
135 ucon = rd_regl(port, S3C2410_UCON);
136 ucon |= S3C2410_UCON_RXIRQMODE;
137 wr_regl(port, S3C2410_UCON, ucon);
138
139 rx_enabled(port) = 1;
140 spin_unlock_irqrestore(&port->lock, flags);
141}
142
143static void s3c24xx_serial_rx_disable(struct uart_port *port)
144{
145 unsigned long flags;
146 unsigned int ucon;
147
148 spin_lock_irqsave(&port->lock, flags);
149
150 ucon = rd_regl(port, S3C2410_UCON);
151 ucon &= ~S3C2410_UCON_RXIRQMODE;
152 wr_regl(port, S3C2410_UCON, ucon);
153
154 rx_enabled(port) = 0;
155 spin_unlock_irqrestore(&port->lock, flags);
156}
157
158static void s3c24xx_serial_stop_tx(struct uart_port *port)
159{
b73c289c
BD		 160 struct s3c24xx_uart_port *ourport = to_ourport(port);
161
b497549a 162 if (tx_enabled(port)) {
88bb4ea1
TA		 163 if (s3c24xx_serial_has_interrupt_mask(port))
164 __set_bit(S3C64XX_UINTM_TXD,
165 portaddrl(port, S3C64XX_UINTM));
166 else
167 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 168 tx_enabled(port) = 0;
169 if (port->flags & UPF_CONS_FLOW)
170 s3c24xx_serial_rx_enable(port);
171 }
172}
173
174static void s3c24xx_serial_start_tx(struct uart_port *port)
175{
b73c289c
BD		 176 struct s3c24xx_uart_port *ourport = to_ourport(port);
177
b497549a
BD		 178 if (!tx_enabled(port)) {
179 if (port->flags & UPF_CONS_FLOW)
180 s3c24xx_serial_rx_disable(port);
181
88bb4ea1
TA		 182 if (s3c24xx_serial_has_interrupt_mask(port))
183 __clear_bit(S3C64XX_UINTM_TXD,
184 portaddrl(port, S3C64XX_UINTM));
185 else
186 enable_irq(ourport->tx_irq);
b497549a
BD		 187 tx_enabled(port) = 1;
188 }
189}
190
b497549a
BD		 191static void s3c24xx_serial_stop_rx(struct uart_port *port)
192{
b73c289c
BD		 193 struct s3c24xx_uart_port *ourport = to_ourport(port);
194
b497549a
BD		 195 if (rx_enabled(port)) {
196 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 197 if (s3c24xx_serial_has_interrupt_mask(port))
198 __set_bit(S3C64XX_UINTM_RXD,
199 portaddrl(port, S3C64XX_UINTM));
200 else
201 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 202 rx_enabled(port) = 0;
203 }
204}
205
206static void s3c24xx_serial_enable_ms(struct uart_port *port)
207{
208}
209
210static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
211{
212 return to_ourport(port)->info;
213}
214
215static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
216{
4d84e970
TA		 217 struct s3c24xx_uart_port *ourport;
218
b497549a
BD		 219 if (port->dev == NULL)
220 return NULL;
221
4d84e970
TA		 222 ourport = container_of(port, struct s3c24xx_uart_port, port);
223 return ourport->cfg;
b497549a
BD		 224}
225
226static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
227 unsigned long ufstat)
228{
229 struct s3c24xx_uart_info *info = ourport->info;
230
231 if (ufstat & info->rx_fifofull)
da121506 232 return ourport->port.fifosize;
b497549a
BD		 233
234 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
235}
236
237
238/* ? - where has parity gone?? */
239#define S3C2410_UERSTAT_PARITY (0x1000)
240
241static irqreturn_t
242s3c24xx_serial_rx_chars(int irq, void *dev_id)
243{
244 struct s3c24xx_uart_port *ourport = dev_id;
245 struct uart_port *port = &ourport->port;
b497549a 246 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 247 unsigned long flags;
b497549a
BD		 248 int max_count = 64;
249
c15c3747
TA		 250 spin_lock_irqsave(&port->lock, flags);
251
b497549a
BD		 252 while (max_count-- > 0) {
253 ufcon = rd_regl(port, S3C2410_UFCON);
254 ufstat = rd_regl(port, S3C2410_UFSTAT);
255
256 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
257 break;
258
259 uerstat = rd_regl(port, S3C2410_UERSTAT);
260 ch = rd_regb(port, S3C2410_URXH);
261
262 if (port->flags & UPF_CONS_FLOW) {
263 int txe = s3c24xx_serial_txempty_nofifo(port);
264
265 if (rx_enabled(port)) {
266 if (!txe) {
267 rx_enabled(port) = 0;
268 continue;
269 }
270 } else {
271 if (txe) {
272 ufcon |= S3C2410_UFCON_RESETRX;
273 wr_regl(port, S3C2410_UFCON, ufcon);
274 rx_enabled(port) = 1;
f5693ea2
VK		 275 spin_unlock_irqrestore(&port->lock,
276 flags);
b497549a
BD		 277 goto out;
278 }
279 continue;
280 }
281 }
282
283 /* insert the character into the buffer */
284
285 flag = TTY_NORMAL;
286 port->icount.rx++;
287
288 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
289 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
290 ch, uerstat);
291
292 /* check for break */
293 if (uerstat & S3C2410_UERSTAT_BREAK) {
294 dbg("break!\n");
295 port->icount.brk++;
296 if (uart_handle_break(port))
9303ac15 297 goto ignore_char;
b497549a
BD		 298 }
299
300 if (uerstat & S3C2410_UERSTAT_FRAME)
301 port->icount.frame++;
302 if (uerstat & S3C2410_UERSTAT_OVERRUN)
303 port->icount.overrun++;
304
305 uerstat &= port->read_status_mask;
306
307 if (uerstat & S3C2410_UERSTAT_BREAK)
308 flag = TTY_BREAK;
309 else if (uerstat & S3C2410_UERSTAT_PARITY)
310 flag = TTY_PARITY;
311 else if (uerstat & (S3C2410_UERSTAT_FRAME |
312 S3C2410_UERSTAT_OVERRUN))
313 flag = TTY_FRAME;
314 }
315
316 if (uart_handle_sysrq_char(port, ch))
317 goto ignore_char;
318
319 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
320 ch, flag);
321
322 ignore_char:
323 continue;
324 }
f5693ea2
VK		 325
326 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 327 tty_flip_buffer_push(&port->state->port);
b497549a
BD		 328
329 out:
330 return IRQ_HANDLED;
331}
332
333static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
334{
335 struct s3c24xx_uart_port *ourport = id;
336 struct uart_port *port = &ourport->port;
ebd2c8f6 337 struct circ_buf *xmit = &port->state->xmit;
c15c3747 338 unsigned long flags;
b497549a
BD		 339 int count = 256;
340
c15c3747
TA		 341 spin_lock_irqsave(&port->lock, flags);
342
b497549a
BD		 343 if (port->x_char) {
344 wr_regb(port, S3C2410_UTXH, port->x_char);
345 port->icount.tx++;
346 port->x_char = 0;
347 goto out;
348 }
349
25985edc 350 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 351 * stopped, disable the uart and exit
352 */
353
354 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
355 s3c24xx_serial_stop_tx(port);
356 goto out;
357 }
358
359 /* try and drain the buffer... */
360
361 while (!uart_circ_empty(xmit) && count-- > 0) {
362 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
363 break;
364
365 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
366 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
367 port->icount.tx++;
368 }
369
c15c3747
TA		 370 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
371 spin_unlock(&port->lock);
b497549a 372 uart_write_wakeup(port);
c15c3747
TA		 373 spin_lock(&port->lock);
374 }
b497549a
BD		 375
376 if (uart_circ_empty(xmit))
377 s3c24xx_serial_stop_tx(port);
378
379 out:
c15c3747 380 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 381 return IRQ_HANDLED;
382}
383
88bb4ea1
TA		 384/* interrupt handler for s3c64xx and later SoC's.*/
385static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
386{
387 struct s3c24xx_uart_port *ourport = id;
388 struct uart_port *port = &ourport->port;
389 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 390 irqreturn_t ret = IRQ_HANDLED;
391
88bb4ea1
TA		 392 if (pend & S3C64XX_UINTM_RXD_MSK) {
393 ret = s3c24xx_serial_rx_chars(irq, id);
394 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
395 }
396 if (pend & S3C64XX_UINTM_TXD_MSK) {
397 ret = s3c24xx_serial_tx_chars(irq, id);
398 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
399 }
88bb4ea1
TA		 400 return ret;
401}
402
b497549a
BD		 403static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
404{
405 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
406 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
407 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
408
409 if (ufcon & S3C2410_UFCON_FIFOMODE) {
410 if ((ufstat & info->tx_fifomask) != 0 ||
411 (ufstat & info->tx_fifofull))
412 return 0;
413
414 return 1;
415 }
416
417 return s3c24xx_serial_txempty_nofifo(port);
418}
419
420/* no modem control lines */
421static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
422{
423 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
424
425 if (umstat & S3C2410_UMSTAT_CTS)
426 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
427 else
428 return TIOCM_CAR | TIOCM_DSR;
429}
430
431static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
432{
2d1e5a48
JMG		 433 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
434
435 if (mctrl & TIOCM_RTS)
436 umcon |= S3C2410_UMCOM_RTS_LOW;
437 else
438 umcon &= ~S3C2410_UMCOM_RTS_LOW;
439
440 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 441}
442
443static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
444{
445 unsigned long flags;
446 unsigned int ucon;
447
448 spin_lock_irqsave(&port->lock, flags);
449
450 ucon = rd_regl(port, S3C2410_UCON);
451
452 if (break_state)
453 ucon |= S3C2410_UCON_SBREAK;
454 else
455 ucon &= ~S3C2410_UCON_SBREAK;
456
457 wr_regl(port, S3C2410_UCON, ucon);
458
459 spin_unlock_irqrestore(&port->lock, flags);
460}
461
462static void s3c24xx_serial_shutdown(struct uart_port *port)
463{
464 struct s3c24xx_uart_port *ourport = to_ourport(port);
465
466 if (ourport->tx_claimed) {
88bb4ea1
TA		 467 if (!s3c24xx_serial_has_interrupt_mask(port))
468 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 469 tx_enabled(port) = 0;
470 ourport->tx_claimed = 0;
471 }
472
473 if (ourport->rx_claimed) {
88bb4ea1
TA		 474 if (!s3c24xx_serial_has_interrupt_mask(port))
475 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 476 ourport->rx_claimed = 0;
477 rx_enabled(port) = 0;
478 }
b497549a 479
88bb4ea1
TA		 480 /* Clear pending interrupts and mask all interrupts */
481 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 482 free_irq(port->irq, ourport);
483
88bb4ea1
TA		 484 wr_regl(port, S3C64XX_UINTP, 0xf);
485 wr_regl(port, S3C64XX_UINTM, 0xf);
486 }
487}
b497549a
BD		 488
489static int s3c24xx_serial_startup(struct uart_port *port)
490{
491 struct s3c24xx_uart_port *ourport = to_ourport(port);
492 int ret;
493
e4ac92df
JP		 494 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
495 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 496
497 rx_enabled(port) = 1;
498
b73c289c 499 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 500 s3c24xx_serial_portname(port), ourport);
501
502 if (ret != 0) {
d20925e1 503 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 504 return ret;
505 }
506
507 ourport->rx_claimed = 1;
508
509 dbg("requesting tx irq...\n");
510
511 tx_enabled(port) = 1;
512
b73c289c 513 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 514 s3c24xx_serial_portname(port), ourport);
515
516 if (ret) {
d20925e1 517 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 518 goto err;
519 }
520
521 ourport->tx_claimed = 1;
522
523 dbg("s3c24xx_serial_startup ok\n");
524
525 /* the port reset code should have done the correct
526 * register setup for the port controls */
527
528 return ret;
529
530 err:
531 s3c24xx_serial_shutdown(port);
532 return ret;
533}
534
88bb4ea1
TA		 535static int s3c64xx_serial_startup(struct uart_port *port)
536{
537 struct s3c24xx_uart_port *ourport = to_ourport(port);
538 int ret;
539
e4ac92df
JP		 540 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
541 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 542
b6ad2935
TF		 543 wr_regl(port, S3C64XX_UINTM, 0xf);
544
88bb4ea1
TA		 545 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
546 s3c24xx_serial_portname(port), ourport);
547 if (ret) {
d20925e1 548 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 549 return ret;
550 }
551
552 /* For compatibility with s3c24xx Soc's */
553 rx_enabled(port) = 1;
554 ourport->rx_claimed = 1;
555 tx_enabled(port) = 0;
556 ourport->tx_claimed = 1;
557
558 /* Enable Rx Interrupt */
559 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
560 dbg("s3c64xx_serial_startup ok\n");
561 return ret;
562}
563
b497549a
BD		 564/* power power management control */
565
566static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
567 unsigned int old)
568{
569 struct s3c24xx_uart_port *ourport = to_ourport(port);
570
30555476
BD		 571 ourport->pm_level = level;
572
b497549a
BD		 573 switch (level) {
574 case 3:
7cd88831 575 if (!IS_ERR(ourport->baudclk))
9484b009 576 clk_disable_unprepare(ourport->baudclk);
b497549a 577
9484b009 578 clk_disable_unprepare(ourport->clk);
b497549a
BD		 579 break;
580
581 case 0:
9484b009 582 clk_prepare_enable(ourport->clk);
b497549a 583
7cd88831 584 if (!IS_ERR(ourport->baudclk))
9484b009 585 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 586
587 break;
588 default:
d20925e1 589 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 590 }
591}
592
593/* baud rate calculation
594 *
595 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
596 * of different sources, including the peripheral clock ("pclk") and an
597 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
598 * with a programmable extra divisor.
599 *
600 * The following code goes through the clock sources, and calculates the
601 * baud clocks (and the resultant actual baud rates) and then tries to
602 * pick the closest one and select that.
603 *
604*/
605
5f5a7a55 606#define MAX_CLK_NAME_LENGTH 15
b497549a 607
5f5a7a55 608static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 609{
610 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 611 unsigned int ucon;
b497549a 612
5f5a7a55
TA		 613 if (info->num_clks == 1)
614 return 0;
b497549a 615
5f5a7a55
TA		 616 ucon = rd_regl(port, S3C2410_UCON);
617 ucon &= info->clksel_mask;
618 return ucon >> info->clksel_shift;
b497549a
BD		 619}
620
5f5a7a55
TA		 621static void s3c24xx_serial_setsource(struct uart_port *port,
622 unsigned int clk_sel)
b497549a 623{
5f5a7a55
TA		 624 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
625 unsigned int ucon;
b497549a 626
5f5a7a55
TA		 627 if (info->num_clks == 1)
628 return;
090f848d 629
5f5a7a55
TA		 630 ucon = rd_regl(port, S3C2410_UCON);
631 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
632 return;
b497549a 633
5f5a7a55
TA		 634 ucon &= ~info->clksel_mask;
635 ucon |= clk_sel << info->clksel_shift;
636 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 637}
638
5f5a7a55
TA		 639static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
640 unsigned int req_baud, struct clk **best_clk,
641 unsigned int *clk_num)
b497549a 642{
5f5a7a55
TA		 643 struct s3c24xx_uart_info *info = ourport->info;
644 struct clk *clk;
645 unsigned long rate;
646 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
647 char clkname[MAX_CLK_NAME_LENGTH];
648 int calc_deviation, deviation = (1 << 30) - 1;
649
5f5a7a55
TA		 650 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
651 ourport->info->def_clk_sel;
652 for (cnt = 0; cnt < info->num_clks; cnt++) {
653 if (!(clk_sel & (1 << cnt)))
654 continue;
655
656 sprintf(clkname, "clk_uart_baud%d", cnt);
657 clk = clk_get(ourport->port.dev, clkname);
7cd88831 658 if (IS_ERR(clk))
5f5a7a55
TA		 659 continue;
660
661 rate = clk_get_rate(clk);
662 if (!rate)
663 continue;
664
665 if (ourport->info->has_divslot) {
666 unsigned long div = rate / req_baud;
667
668 /* The UDIVSLOT register on the newer UARTs allows us to
669 * get a divisor adjustment of 1/16th on the baud clock.
670 *
671 * We don't keep the UDIVSLOT value (the 16ths we
672 * calculated by not multiplying the baud by 16) as it
673 * is easy enough to recalculate.
674 */
675
676 quot = div / 16;
677 baud = rate / div;
678 } else {
679 quot = (rate + (8 * req_baud)) / (16 * req_baud);
680 baud = rate / (quot * 16);
b497549a 681 }
5f5a7a55 682 quot--;
b497549a 683
5f5a7a55
TA		 684 calc_deviation = req_baud - baud;
685 if (calc_deviation < 0)
686 calc_deviation = -calc_deviation;
b497549a 687
5f5a7a55
TA		 688 if (calc_deviation < deviation) {
689 *best_clk = clk;
690 best_quot = quot;
691 *clk_num = cnt;
692 deviation = calc_deviation;
b497549a
BD		 693 }
694 }
695
5f5a7a55 696 return best_quot;
b497549a
BD		 697}
698
090f848d
BD		 699/* udivslot_table[]
700 *
701 * This table takes the fractional value of the baud divisor and gives
702 * the recommended setting for the UDIVSLOT register.
703 */
704static u16 udivslot_table[16] = {
705 [0] = 0x0000,
706 [1] = 0x0080,
707 [2] = 0x0808,
708 [3] = 0x0888,
709 [4] = 0x2222,
710 [5] = 0x4924,
711 [6] = 0x4A52,
712 [7] = 0x54AA,
713 [8] = 0x5555,
714 [9] = 0xD555,
715 [10] = 0xD5D5,
716 [11] = 0xDDD5,
717 [12] = 0xDDDD,
718 [13] = 0xDFDD,
719 [14] = 0xDFDF,
720 [15] = 0xFFDF,
721};
722
b497549a
BD		 723static void s3c24xx_serial_set_termios(struct uart_port *port,
724 struct ktermios *termios,
725 struct ktermios *old)
726{
727 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
728 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 729 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 730 unsigned long flags;
5f5a7a55 731 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 732 unsigned int ulcon;
733 unsigned int umcon;
090f848d 734 unsigned int udivslot = 0;
b497549a
BD		 735
736 /*
737 * We don't support modem control lines.
738 */
739 termios->c_cflag &= ~(HUPCL | CMSPAR);
740 termios->c_cflag |= CLOCAL;
741
742 /*
743 * Ask the core to calculate the divisor for us.
744 */
745
746 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 747 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 748 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
749 quot = port->custom_divisor;
7cd88831 750 if (IS_ERR(clk))
5f5a7a55 751 return;
b497549a
BD		 752
753 /* check to see if we need to change clock source */
754
5f5a7a55
TA		 755 if (ourport->baudclk != clk) {
756 s3c24xx_serial_setsource(port, clk_sel);
b497549a 757
7cd88831 758 if (!IS_ERR(ourport->baudclk)) {
9484b009 759 clk_disable_unprepare(ourport->baudclk);
7cd88831 760 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 761 }
762
9484b009 763 clk_prepare_enable(clk);
b497549a 764
b497549a 765 ourport->baudclk = clk;
30555476 766 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 767 }
768
090f848d
BD		 769 if (ourport->info->has_divslot) {
770 unsigned int div = ourport->baudclk_rate / baud;
771
8b526ae4
JL		 772 if (cfg->has_fracval) {
773 udivslot = (div & 15);
774 dbg("fracval = %04x\n", udivslot);
775 } else {
776 udivslot = udivslot_table[div & 15];
777 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
778 }
090f848d
BD		 779 }
780
b497549a
BD		 781 switch (termios->c_cflag & CSIZE) {
782 case CS5:
783 dbg("config: 5bits/char\n");
784 ulcon = S3C2410_LCON_CS5;
785 break;
786 case CS6:
787 dbg("config: 6bits/char\n");
788 ulcon = S3C2410_LCON_CS6;
789 break;
790 case CS7:
791 dbg("config: 7bits/char\n");
792 ulcon = S3C2410_LCON_CS7;
793 break;
794 case CS8:
795 default:
796 dbg("config: 8bits/char\n");
797 ulcon = S3C2410_LCON_CS8;
798 break;
799 }
800
801 /* preserve original lcon IR settings */
802 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
803
804 if (termios->c_cflag & CSTOPB)
805 ulcon |= S3C2410_LCON_STOPB;
806
b497549a
BD		 807 if (termios->c_cflag & PARENB) {
808 if (termios->c_cflag & PARODD)
809 ulcon |= S3C2410_LCON_PODD;
810 else
811 ulcon |= S3C2410_LCON_PEVEN;
812 } else {
813 ulcon |= S3C2410_LCON_PNONE;
814 }
815
816 spin_lock_irqsave(&port->lock, flags);
817
090f848d
BD		 818 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
819 ulcon, quot, udivslot);
b497549a
BD		 820
821 wr_regl(port, S3C2410_ULCON, ulcon);
822 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 823
824 umcon = rd_regl(port, S3C2410_UMCON);
825 if (termios->c_cflag & CRTSCTS) {
826 umcon |= S3C2410_UMCOM_AFC;
827 /* Disable RTS when RX FIFO contains 63 bytes */
828 umcon &= ~S3C2412_UMCON_AFC_8;
829 } else {
830 umcon &= ~S3C2410_UMCOM_AFC;
831 }
b497549a
BD		 832 wr_regl(port, S3C2410_UMCON, umcon);
833
090f848d
BD		 834 if (ourport->info->has_divslot)
835 wr_regl(port, S3C2443_DIVSLOT, udivslot);
836
b497549a
BD		 837 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
838 rd_regl(port, S3C2410_ULCON),
839 rd_regl(port, S3C2410_UCON),
840 rd_regl(port, S3C2410_UFCON));
841
842 /*
843 * Update the per-port timeout.
844 */
845 uart_update_timeout(port, termios->c_cflag, baud);
846
847 /*
848 * Which character status flags are we interested in?
849 */
850 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
851 if (termios->c_iflag & INPCK)
852 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
853
854 /*
855 * Which character status flags should we ignore?
856 */
857 port->ignore_status_mask = 0;
858 if (termios->c_iflag & IGNPAR)
859 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
860 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
861 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
862
863 /*
864 * Ignore all characters if CREAD is not set.
865 */
866 if ((termios->c_cflag & CREAD) == 0)
867 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
868
869 spin_unlock_irqrestore(&port->lock, flags);
870}
871
872static const char *s3c24xx_serial_type(struct uart_port *port)
873{
874 switch (port->type) {
875 case PORT_S3C2410:
876 return "S3C2410";
877 case PORT_S3C2440:
878 return "S3C2440";
879 case PORT_S3C2412:
880 return "S3C2412";
b690ace5
BD		 881 case PORT_S3C6400:
882 return "S3C6400/10";
b497549a
BD		 883 default:
884 return NULL;
885 }
886}
887
888#define MAP_SIZE (0x100)
889
890static void s3c24xx_serial_release_port(struct uart_port *port)
891{
892 release_mem_region(port->mapbase, MAP_SIZE);
893}
894
895static int s3c24xx_serial_request_port(struct uart_port *port)
896{
897 const char *name = s3c24xx_serial_portname(port);
898 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
899}
900
901static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
902{
903 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
904
905 if (flags & UART_CONFIG_TYPE &&
906 s3c24xx_serial_request_port(port) == 0)
907 port->type = info->type;
908}
909
910/*
911 * verify the new serial_struct (for TIOCSSERIAL).
912 */
913static int
914s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
915{
916 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
917
918 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
919 return -EINVAL;
920
921 return 0;
922}
923
924
925#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
926
927static struct console s3c24xx_serial_console;
928
93b5c032
JP		 929static int __init s3c24xx_serial_console_init(void)
930{
931 register_console(&s3c24xx_serial_console);
932 return 0;
933}
934console_initcall(s3c24xx_serial_console_init);
935
b497549a
BD		 936#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
937#else
938#define S3C24XX_SERIAL_CONSOLE NULL
939#endif
940
84f57d9e 941#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 942static int s3c24xx_serial_get_poll_char(struct uart_port *port);
943static void s3c24xx_serial_put_poll_char(struct uart_port *port,
944 unsigned char c);
945#endif
946
b497549a
BD		 947static struct uart_ops s3c24xx_serial_ops = {
948 .pm = s3c24xx_serial_pm,
949 .tx_empty = s3c24xx_serial_tx_empty,
950 .get_mctrl = s3c24xx_serial_get_mctrl,
951 .set_mctrl = s3c24xx_serial_set_mctrl,
952 .stop_tx = s3c24xx_serial_stop_tx,
953 .start_tx = s3c24xx_serial_start_tx,
954 .stop_rx = s3c24xx_serial_stop_rx,
955 .enable_ms = s3c24xx_serial_enable_ms,
956 .break_ctl = s3c24xx_serial_break_ctl,
957 .startup = s3c24xx_serial_startup,
958 .shutdown = s3c24xx_serial_shutdown,
959 .set_termios = s3c24xx_serial_set_termios,
960 .type = s3c24xx_serial_type,
961 .release_port = s3c24xx_serial_release_port,
962 .request_port = s3c24xx_serial_request_port,
963 .config_port = s3c24xx_serial_config_port,
964 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 965#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 966 .poll_get_char = s3c24xx_serial_get_poll_char,
967 .poll_put_char = s3c24xx_serial_put_poll_char,
968#endif
b497549a
BD		 969};
970
b497549a
BD		 971static struct uart_driver s3c24xx_uart_drv = {
972 .owner = THIS_MODULE,
2cf0c58e 973 .driver_name = "s3c2410_serial",
bdd4915a 974 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 975 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 976 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 977 .major = S3C24XX_SERIAL_MAJOR,
978 .minor = S3C24XX_SERIAL_MINOR,
979};
980
03d5e77b 981static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 982 [0] = {
983 .port = {
984 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
985 .iotype = UPIO_MEM,
b497549a
BD		 986 .uartclk = 0,
987 .fifosize = 16,
988 .ops = &s3c24xx_serial_ops,
989 .flags = UPF_BOOT_AUTOCONF,
990 .line = 0,
991 }
992 },
993 [1] = {
994 .port = {
995 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
996 .iotype = UPIO_MEM,
b497549a
BD		 997 .uartclk = 0,
998 .fifosize = 16,
999 .ops = &s3c24xx_serial_ops,
1000 .flags = UPF_BOOT_AUTOCONF,
1001 .line = 1,
1002 }
1003 },
03d5e77b 1004#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1005
1006 [2] = {
1007 .port = {
1008 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
1009 .iotype = UPIO_MEM,
b497549a
BD		 1010 .uartclk = 0,
1011 .fifosize = 16,
1012 .ops = &s3c24xx_serial_ops,
1013 .flags = UPF_BOOT_AUTOCONF,
1014 .line = 2,
1015 }
03d5e77b
BD		 1016 },
1017#endif
1018#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1019 [3] = {
1020 .port = {
1021 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1022 .iotype = UPIO_MEM,
03d5e77b
BD		 1023 .uartclk = 0,
1024 .fifosize = 16,
1025 .ops = &s3c24xx_serial_ops,
1026 .flags = UPF_BOOT_AUTOCONF,
1027 .line = 3,
1028 }
b497549a
BD		 1029 }
1030#endif
1031};
1032
1033/* s3c24xx_serial_resetport
1034 *
0dfb3b41 1035 * reset the fifos and other the settings.
b497549a
BD		 1036*/
1037
0dfb3b41
TA		 1038static void s3c24xx_serial_resetport(struct uart_port *port,
1039 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1040{
1041 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1042 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1043 unsigned int ucon_mask;
b497549a 1044
0dfb3b41
TA		 1045 ucon_mask = info->clksel_mask;
1046 if (info->type == PORT_S3C2440)
1047 ucon_mask |= S3C2440_UCON0_DIVMASK;
1048
1049 ucon &= ucon_mask;
1050 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1051
1052 /* reset both fifos */
1053 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1054 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1055
1056 /* some delay is required after fifo reset */
1057 udelay(1);
b497549a
BD		 1058}
1059
30555476
BD		 1060
1061#ifdef CONFIG_CPU_FREQ
1062
1063static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1064 unsigned long val, void *data)
1065{
1066 struct s3c24xx_uart_port *port;
1067 struct uart_port *uport;
1068
1069 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1070 uport = &port->port;
1071
1072 /* check to see if port is enabled */
1073
1074 if (port->pm_level != 0)
1075 return 0;
1076
1077 /* try and work out if the baudrate is changing, we can detect
1078 * a change in rate, but we do not have support for detecting
1079 * a disturbance in the clock-rate over the change.
1080 */
1081
25f04ad4 1082 if (IS_ERR(port->baudclk))
30555476
BD		 1083 goto exit;
1084
25f04ad4 1085 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1086 goto exit;
1087
1088 if (val == CPUFREQ_PRECHANGE) {
1089 /* we should really shut the port down whilst the
1090 * frequency change is in progress. */
1091
1092 } else if (val == CPUFREQ_POSTCHANGE) {
1093 struct ktermios *termios;
1094 struct tty_struct *tty;
1095
ebd2c8f6 1096 if (uport->state == NULL)
30555476 1097 goto exit;
30555476 1098
ebd2c8f6 1099 tty = uport->state->port.tty;
30555476 1100
7de40c21 1101 if (tty == NULL)
30555476 1102 goto exit;
30555476 1103
adc8d746 1104 termios = &tty->termios;
30555476
BD		 1105
1106 if (termios == NULL) {
d20925e1 1107 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1108 goto exit;
1109 }
1110
1111 s3c24xx_serial_set_termios(uport, termios, NULL);
1112 }
1113
1114 exit:
1115 return 0;
1116}
1117
1118static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1119{
1120 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1121
1122 return cpufreq_register_notifier(&port->freq_transition,
1123 CPUFREQ_TRANSITION_NOTIFIER);
1124}
1125
1126static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1127{
1128 cpufreq_unregister_notifier(&port->freq_transition,
1129 CPUFREQ_TRANSITION_NOTIFIER);
1130}
1131
1132#else
1133static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1134{
1135 return 0;
1136}
1137
1138static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1139{
1140}
1141#endif
1142
b497549a
BD		 1143/* s3c24xx_serial_init_port
1144 *
1145 * initialise a single serial port from the platform device given
1146 */
1147
1148static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1149 struct platform_device *platdev)
1150{
1151 struct uart_port *port = &ourport->port;
da121506 1152 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1153 struct resource *res;
1154 int ret;
1155
1156 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1157
1158 if (platdev == NULL)
1159 return -ENODEV;
1160
b497549a
BD		 1161 if (port->mapbase != 0)
1162 return 0;
1163
b497549a
BD		 1164 /* setup info for port */
1165 port->dev = &platdev->dev;
b497549a 1166
88bb4ea1
TA		 1167 /* Startup sequence is different for s3c64xx and higher SoC's */
1168 if (s3c24xx_serial_has_interrupt_mask(port))
1169 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1170
b497549a
BD		 1171 port->uartclk = 1;
1172
1173 if (cfg->uart_flags & UPF_CONS_FLOW) {
1174 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1175 port->flags |= UPF_CONS_FLOW;
1176 }
1177
1178 /* sort our the physical and virtual addresses for each UART */
1179
1180 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1181 if (res == NULL) {
d20925e1 1182 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1183 return -EINVAL;
1184 }
1185
e4ac92df 1186 dbg("resource %pR)\n", res);
b497549a 1187
41147bfd
TA		 1188 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1189 if (!port->membase) {
1190 dev_err(port->dev, "failed to remap controller address\n");
1191 return -EBUSY;
1192 }
1193
b690ace5 1194 port->mapbase = res->start;
b497549a
BD		 1195 ret = platform_get_irq(platdev, 0);
1196 if (ret < 0)
1197 port->irq = 0;
b73c289c 1198 else {
b497549a 1199 port->irq = ret;
b73c289c
BD		 1200 ourport->rx_irq = ret;
1201 ourport->tx_irq = ret + 1;
1202 }
9303ac15 1203
b73c289c
BD		 1204 ret = platform_get_irq(platdev, 1);
1205 if (ret > 0)
1206 ourport->tx_irq = ret;
b497549a
BD		 1207
1208 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1209 if (IS_ERR(ourport->clk)) {
1210 pr_err("%s: Controller clock not found\n",
1211 dev_name(&platdev->dev));
1212 return PTR_ERR(ourport->clk);
1213 }
1214
1215 ret = clk_prepare_enable(ourport->clk);
1216 if (ret) {
1217 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1218 clk_put(ourport->clk);
1219 return ret;
1220 }
b497549a 1221
88bb4ea1
TA		 1222 /* Keep all interrupts masked and cleared */
1223 if (s3c24xx_serial_has_interrupt_mask(port)) {
1224 wr_regl(port, S3C64XX_UINTM, 0xf);
1225 wr_regl(port, S3C64XX_UINTP, 0xf);
1226 wr_regl(port, S3C64XX_UINTSP, 0xf);
1227 }
1228
e4ac92df 1229 dbg("port: map=%08x, mem=%p, irq=%d (%d,%d), clock=%u\n",
b73c289c
BD		 1230 port->mapbase, port->membase, port->irq,
1231 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1232
1233 /* reset the fifos (and setup the uart) */
1234 s3c24xx_serial_resetport(port, cfg);
1235 return 0;
1236}
1237
17efd2b7 1238#ifdef CONFIG_SAMSUNG_CLOCK
b497549a
BD		 1239static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1240 struct device_attribute *attr,
1241 char *buf)
1242{
1243 struct uart_port *port = s3c24xx_dev_to_port(dev);
1244 struct s3c24xx_uart_port *ourport = to_ourport(port);
1245
7cd88831
KK		 1246 if (IS_ERR(ourport->baudclk))
1247 return -EINVAL;
1248
7b15e1d9
KP		 1249 return snprintf(buf, PAGE_SIZE, "* %s\n",
1250 ourport->baudclk->name ?: "(null)");
b497549a
BD		 1251}
1252
1253static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
17efd2b7 1254#endif
26c919e1 1255
b497549a
BD		 1256/* Device driver serial port probe */
1257
26c919e1 1258static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1259static int probe_index;
1260
26c919e1
TA		 1261static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1262 struct platform_device *pdev)
1263{
1264#ifdef CONFIG_OF
1265 if (pdev->dev.of_node) {
1266 const struct of_device_id *match;
1267 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1268 return (struct s3c24xx_serial_drv_data *)match->data;
1269 }
1270#endif
1271 return (struct s3c24xx_serial_drv_data *)
1272 platform_get_device_id(pdev)->driver_data;
1273}
1274
da121506 1275static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a
BD		 1276{
1277 struct s3c24xx_uart_port *ourport;
13a9f6c6 1278 int index = probe_index;
b497549a
BD		 1279 int ret;
1280
13a9f6c6
TF		 1281 if (pdev->dev.of_node) {
1282 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1283 if (ret >= 0)
1284 index = ret;
1285 }
1286
1287 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1288
13a9f6c6 1289 ourport = &s3c24xx_serial_ports[index];
da121506 1290
26c919e1
TA		 1291 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1292 if (!ourport->drv_data) {
1293 dev_err(&pdev->dev, "could not find driver data\n");
1294 return -ENODEV;
1295 }
da121506 1296
7cd88831 1297 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1298 ourport->info = ourport->drv_data->info;
574de559 1299 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1300 dev_get_platdata(&pdev->dev) :
da121506
TA		 1301 ourport->drv_data->def_cfg;
1302
1303 ourport->port.fifosize = (ourport->info->fifosize) ?
1304 ourport->info->fifosize :
13a9f6c6 1305 ourport->drv_data->fifosize[index];
da121506 1306
b497549a
BD		 1307 probe_index++;
1308
1309 dbg("%s: initialising port %p...\n", __func__, ourport);
1310
da121506 1311 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1312 if (ret < 0)
8ad711a9 1313 return ret;
b497549a 1314
6f134c3c
TB		 1315 if (!s3c24xx_uart_drv.state) {
1316 ret = uart_register_driver(&s3c24xx_uart_drv);
1317 if (ret < 0) {
1318 pr_err("Failed to register Samsung UART driver\n");
1319 return ret;
1320 }
1321 }
1322
b497549a
BD		 1323 dbg("%s: adding port\n", __func__);
1324 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1325 platform_set_drvdata(pdev, &ourport->port);
b497549a 1326
0da3336f
HS		 1327 /*
1328 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1329 * so that a potential re-enablement through the pm-callback overlaps
1330 * and keeps the clock enabled in this case.
1331 */
1332 clk_disable_unprepare(ourport->clk);
1333
17efd2b7 1334#ifdef CONFIG_SAMSUNG_CLOCK
da121506 1335 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
b497549a 1336 if (ret < 0)
da121506 1337 dev_err(&pdev->dev, "failed to add clock source attr.\n");
17efd2b7 1338#endif
b497549a 1339
30555476
BD		 1340 ret = s3c24xx_serial_cpufreq_register(ourport);
1341 if (ret < 0)
da121506 1342 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1343
b497549a 1344 return 0;
b497549a
BD		 1345}
1346
ae8d8a14 1347static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1348{
1349 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1350
1351 if (port) {
30555476 1352 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
17efd2b7 1353#ifdef CONFIG_SAMSUNG_CLOCK
b497549a 1354 device_remove_file(&dev->dev, &dev_attr_clock_source);
17efd2b7 1355#endif
b497549a
BD		 1356 uart_remove_one_port(&s3c24xx_uart_drv, port);
1357 }
1358
6f134c3c
TB		 1359 uart_unregister_driver(&s3c24xx_uart_drv);
1360
b497549a
BD		 1361 return 0;
1362}
1363
b497549a 1364/* UART power management code */
aef7fe52
MH		 1365#ifdef CONFIG_PM_SLEEP
1366static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1367{
aef7fe52 1368 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1369
1370 if (port)
1371 uart_suspend_port(&s3c24xx_uart_drv, port);
1372
1373 return 0;
1374}
1375
aef7fe52 1376static int s3c24xx_serial_resume(struct device *dev)
b497549a 1377{
aef7fe52 1378 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1379 struct s3c24xx_uart_port *ourport = to_ourport(port);
1380
1381 if (port) {
9484b009 1382 clk_prepare_enable(ourport->clk);
b497549a 1383 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1384 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1385
1386 uart_resume_port(&s3c24xx_uart_drv, port);
1387 }
1388
1389 return 0;
1390}
aef7fe52 1391
d09a7308
MS		 1392static int s3c24xx_serial_resume_noirq(struct device *dev)
1393{
1394 struct uart_port *port = s3c24xx_dev_to_port(dev);
1395
1396 if (port) {
1397 /* restore IRQ mask */
1398 if (s3c24xx_serial_has_interrupt_mask(port)) {
1399 unsigned int uintm = 0xf;
1400 if (tx_enabled(port))
1401 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1402 if (rx_enabled(port))
1403 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1404 wr_regl(port, S3C64XX_UINTM, uintm);
1405 }
1406 }
1407
1408 return 0;
1409}
1410
aef7fe52
MH		 1411static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1412 .suspend = s3c24xx_serial_suspend,
1413 .resume = s3c24xx_serial_resume,
d09a7308 1414 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1415};
b882fc1b
KK		 1416#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1417
aef7fe52 1418#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1419
1420#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1421#endif /* CONFIG_PM_SLEEP */
b497549a 1422
b497549a
BD		 1423/* Console code */
1424
1425#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1426
1427static struct uart_port *cons_uart;
1428
1429static int
1430s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1431{
1432 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1433 unsigned long ufstat, utrstat;
1434
1435 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1436 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1437
1438 ufstat = rd_regl(port, S3C2410_UFSTAT);
1439 return (ufstat & info->tx_fifofull) ? 0 : 1;
1440 }
1441
1442 /* in non-fifo mode, we go and use the tx buffer empty */
1443
1444 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1445 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1446}
1447
38adbc54
MS		 1448static bool
1449s3c24xx_port_configured(unsigned int ucon)
1450{
1451 /* consider the serial port configured if the tx/rx mode set */
1452 return (ucon & 0xf) != 0;
1453}
1454
93b5c032
JP		 1455#ifdef CONFIG_CONSOLE_POLL
1456/*
1457 * Console polling routines for writing and reading from the uart while
1458 * in an interrupt or debug context.
1459 */
1460
1461static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1462{
1463 struct s3c24xx_uart_port *ourport = to_ourport(port);
1464 unsigned int ufstat;
1465
1466 ufstat = rd_regl(port, S3C2410_UFSTAT);
1467 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1468 return NO_POLL_CHAR;
1469
1470 return rd_regb(port, S3C2410_URXH);
1471}
1472
1473static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1474 unsigned char c)
1475{
bb7f09ba
DA		 1476 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1477 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 1478
1479 /* not possible to xmit on unconfigured port */
1480 if (!s3c24xx_port_configured(ucon))
1481 return;
93b5c032
JP		 1482
1483 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1484 cpu_relax();
bb7f09ba 1485 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 1486}
1487
1488#endif /* CONFIG_CONSOLE_POLL */
1489
b497549a
BD		 1490static void
1491s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1492{
bb7f09ba 1493 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 1494
b497549a 1495 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 1496 cpu_relax();
bb7f09ba 1497 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 1498}
1499
1500static void
1501s3c24xx_serial_console_write(struct console *co, const char *s,
1502 unsigned int count)
1503{
ab88c8dc
DA		 1504 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1505
1506 /* not possible to xmit on unconfigured port */
1507 if (!s3c24xx_port_configured(ucon))
1508 return;
1509
b497549a
BD		 1510 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1511}
1512
1513static void __init
1514s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1515 int *parity, int *bits)
1516{
b497549a
BD		 1517 struct clk *clk;
1518 unsigned int ulcon;
1519 unsigned int ucon;
1520 unsigned int ubrdiv;
1521 unsigned long rate;
5f5a7a55
TA		 1522 unsigned int clk_sel;
1523 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1524
1525 ulcon = rd_regl(port, S3C2410_ULCON);
1526 ucon = rd_regl(port, S3C2410_UCON);
1527 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1528
1529 dbg("s3c24xx_serial_get_options: port=%p\n"
1530 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1531 port, ulcon, ucon, ubrdiv);
1532
38adbc54 1533 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 1534 switch (ulcon & S3C2410_LCON_CSMASK) {
1535 case S3C2410_LCON_CS5:
1536 *bits = 5;
1537 break;
1538 case S3C2410_LCON_CS6:
1539 *bits = 6;
1540 break;
1541 case S3C2410_LCON_CS7:
1542 *bits = 7;
1543 break;
1544 default:
1545 case S3C2410_LCON_CS8:
1546 *bits = 8;
1547 break;
1548 }
1549
1550 switch (ulcon & S3C2410_LCON_PMASK) {
1551 case S3C2410_LCON_PEVEN:
1552 *parity = 'e';
1553 break;
1554
1555 case S3C2410_LCON_PODD:
1556 *parity = 'o';
1557 break;
1558
1559 case S3C2410_LCON_PNONE:
1560 default:
1561 *parity = 'n';
1562 }
1563
1564 /* now calculate the baud rate */
1565
5f5a7a55
TA		 1566 clk_sel = s3c24xx_serial_getsource(port);
1567 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1568
5f5a7a55 1569 clk = clk_get(port->dev, clk_name);
7cd88831 1570 if (!IS_ERR(clk))
5f5a7a55 1571 rate = clk_get_rate(clk);
b497549a
BD		 1572 else
1573 rate = 1;
1574
b497549a
BD		 1575 *baud = rate / (16 * (ubrdiv + 1));
1576 dbg("calculated baud %d\n", *baud);
1577 }
1578
1579}
1580
b497549a
BD		 1581static int __init
1582s3c24xx_serial_console_setup(struct console *co, char *options)
1583{
1584 struct uart_port *port;
1585 int baud = 9600;
1586 int bits = 8;
1587 int parity = 'n';
1588 int flow = 'n';
1589
1590 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1591 co, co->index, options);
1592
1593 /* is this a valid port */
1594
03d5e77b 1595 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1596 co->index = 0;
1597
1598 port = &s3c24xx_serial_ports[co->index].port;
1599
1600 /* is the port configured? */
1601
ee430f16
TA		 1602 if (port->mapbase == 0x0)
1603 return -ENODEV;
b497549a
BD		 1604
1605 cons_uart = port;
1606
1607 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1608
1609 /*
1610 * Check whether an invalid uart number has been specified, and
1611 * if so, search for the first available port that does have
1612 * console support.
1613 */
1614 if (options)
1615 uart_parse_options(options, &baud, &parity, &bits, &flow);
1616 else
1617 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1618
1619 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1620
1621 return uart_set_options(port, co, baud, parity, bits, flow);
1622}
1623
b497549a
BD		 1624static struct console s3c24xx_serial_console = {
1625 .name = S3C24XX_SERIAL_NAME,
1626 .device = uart_console_device,
1627 .flags = CON_PRINTBUFFER,
1628 .index = -1,
1629 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1630 .setup = s3c24xx_serial_console_setup,
1631 .data = &s3c24xx_uart_drv,
b497549a 1632};
da121506
TA		 1633#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1634
1635#ifdef CONFIG_CPU_S3C2410
1636static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1637 .info = &(struct s3c24xx_uart_info) {
1638 .name = "Samsung S3C2410 UART",
1639 .type = PORT_S3C2410,
1640 .fifosize = 16,
1641 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1642 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1643 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1644 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1645 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1646 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1647 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1648 .num_clks = 2,
1649 .clksel_mask = S3C2410_UCON_CLKMASK,
1650 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1651 },
1652 .def_cfg = &(struct s3c2410_uartcfg) {
1653 .ucon = S3C2410_UCON_DEFAULT,
1654 .ufcon = S3C2410_UFCON_DEFAULT,
1655 },
1656};
1657#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1658#else
1659#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1660#endif
b497549a 1661
da121506
TA		 1662#ifdef CONFIG_CPU_S3C2412
1663static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1664 .info = &(struct s3c24xx_uart_info) {
1665 .name = "Samsung S3C2412 UART",
1666 .type = PORT_S3C2412,
1667 .fifosize = 64,
1668 .has_divslot = 1,
1669 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1670 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1671 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1672 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1673 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1674 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1675 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1676 .num_clks = 4,
1677 .clksel_mask = S3C2412_UCON_CLKMASK,
1678 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1679 },
1680 .def_cfg = &(struct s3c2410_uartcfg) {
1681 .ucon = S3C2410_UCON_DEFAULT,
1682 .ufcon = S3C2410_UFCON_DEFAULT,
1683 },
1684};
1685#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1686#else
1687#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1688#endif
b497549a 1689
da121506 1690#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 1691 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 1692static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1693 .info = &(struct s3c24xx_uart_info) {
1694 .name = "Samsung S3C2440 UART",
1695 .type = PORT_S3C2440,
1696 .fifosize = 64,
1697 .has_divslot = 1,
1698 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1699 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1700 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1701 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1702 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1703 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1704 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1705 .num_clks = 4,
1706 .clksel_mask = S3C2412_UCON_CLKMASK,
1707 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1708 },
1709 .def_cfg = &(struct s3c2410_uartcfg) {
1710 .ucon = S3C2410_UCON_DEFAULT,
1711 .ufcon = S3C2410_UFCON_DEFAULT,
1712 },
1713};
1714#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1715#else
1716#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1717#endif
b497549a 1718
da121506 1719#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
da121506
TA		 1720 defined(CONFIG_CPU_S5PC100)
1721static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1722 .info = &(struct s3c24xx_uart_info) {
1723 .name = "Samsung S3C6400 UART",
1724 .type = PORT_S3C6400,
1725 .fifosize = 64,
1726 .has_divslot = 1,
1727 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1728 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1729 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1730 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1731 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1732 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1733 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1734 .num_clks = 4,
1735 .clksel_mask = S3C6400_UCON_CLKMASK,
1736 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1737 },
1738 .def_cfg = &(struct s3c2410_uartcfg) {
1739 .ucon = S3C2410_UCON_DEFAULT,
1740 .ufcon = S3C2410_UFCON_DEFAULT,
1741 },
1742};
1743#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1744#else
1745#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1746#endif
b497549a 1747
da121506
TA		 1748#ifdef CONFIG_CPU_S5PV210
1749static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1750 .info = &(struct s3c24xx_uart_info) {
1751 .name = "Samsung S5PV210 UART",
1752 .type = PORT_S3C6400,
1753 .has_divslot = 1,
1754 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1755 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1756 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1757 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1758 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1759 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1760 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1761 .num_clks = 2,
1762 .clksel_mask = S5PV210_UCON_CLKMASK,
1763 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1764 },
1765 .def_cfg = &(struct s3c2410_uartcfg) {
1766 .ucon = S5PV210_UCON_DEFAULT,
1767 .ufcon = S5PV210_UFCON_DEFAULT,
1768 },
1769 .fifosize = { 256, 64, 16, 16 },
1770};
1771#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1772#else
1773#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1774#endif
b497549a 1775
33f88136 1776#if defined(CONFIG_ARCH_EXYNOS)
da121506
TA		 1777static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1778 .info = &(struct s3c24xx_uart_info) {
1779 .name = "Samsung Exynos4 UART",
1780 .type = PORT_S3C6400,
1781 .has_divslot = 1,
1782 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1783 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1784 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1785 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1786 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1787 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1788 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1789 .num_clks = 1,
1790 .clksel_mask = 0,
1791 .clksel_shift = 0,
1792 },
1793 .def_cfg = &(struct s3c2410_uartcfg) {
1794 .ucon = S5PV210_UCON_DEFAULT,
1795 .ufcon = S5PV210_UFCON_DEFAULT,
1796 .has_fracval = 1,
1797 },
1798 .fifosize = { 256, 64, 16, 16 },
1799};
1800#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1801#else
1802#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1803#endif
b497549a 1804
da121506
TA		 1805static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1806 {
1807 .name = "s3c2410-uart",
1808 .driver_data = S3C2410_SERIAL_DRV_DATA,
1809 }, {
1810 .name = "s3c2412-uart",
1811 .driver_data = S3C2412_SERIAL_DRV_DATA,
1812 }, {
1813 .name = "s3c2440-uart",
1814 .driver_data = S3C2440_SERIAL_DRV_DATA,
1815 }, {
1816 .name = "s3c6400-uart",
1817 .driver_data = S3C6400_SERIAL_DRV_DATA,
1818 }, {
1819 .name = "s5pv210-uart",
1820 .driver_data = S5PV210_SERIAL_DRV_DATA,
1821 }, {
1822 .name = "exynos4210-uart",
1823 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1824 },
1825 { },
1826};
1827MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1828
26c919e1
TA		 1829#ifdef CONFIG_OF
1830static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 1831 { .compatible = "samsung,s3c2410-uart",
1832 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1833 { .compatible = "samsung,s3c2412-uart",
1834 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1835 { .compatible = "samsung,s3c2440-uart",
1836 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1837 { .compatible = "samsung,s3c6400-uart",
1838 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1839 { .compatible = "samsung,s5pv210-uart",
1840 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 1841 { .compatible = "samsung,exynos4210-uart",
a169a888 1842 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
26c919e1
TA		 1843 {},
1844};
1845MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 1846#endif
1847
da121506
TA		 1848static struct platform_driver samsung_serial_driver = {
1849 .probe = s3c24xx_serial_probe,
2d47b716 1850 .remove = s3c24xx_serial_remove,
da121506
TA		 1851 .id_table = s3c24xx_serial_driver_ids,
1852 .driver = {
1853 .name = "samsung-uart",
1854 .owner = THIS_MODULE,
1855 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 1856 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 1857 },
1858};
b497549a 1859
6f134c3c 1860module_platform_driver(samsung_serial_driver);
b497549a 1861
da121506 1862MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1863MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1864MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1865MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)