Commit | Line | Data |
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1e6c9c28 | 1 | /* |
7192f92c | 2 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
3 | * Copyright (C) 2003 Rick Bronson |
4 | * | |
5 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
a6670615 CC |
8 | * DMA support added by Chip Coldwell. |
9 | * | |
1e6c9c28 AV |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
5fbe46b6 NF |
36 | #include <linux/of.h> |
37 | #include <linux/of_device.h> | |
a6670615 | 38 | #include <linux/dma-mapping.h> |
93a3ddc2 | 39 | #include <linux/atmel_pdc.h> |
fa3218d8 | 40 | #include <linux/atmel_serial.h> |
e8faff73 | 41 | #include <linux/uaccess.h> |
bcd2360c | 42 | #include <linux/platform_data/atmel.h> |
1e6c9c28 AV |
43 | |
44 | #include <asm/io.h> | |
f7512e7c | 45 | #include <asm/ioctls.h> |
1e6c9c28 | 46 | |
acca9b83 | 47 | #ifdef CONFIG_ARM |
a09e64fb | 48 | #include <mach/cpu.h> |
60e8972d | 49 | #include <asm/gpio.h> |
acca9b83 | 50 | #endif |
1e6c9c28 | 51 | |
a6670615 CC |
52 | #define PDC_BUFFER_SIZE 512 |
53 | /* Revisit: We should calculate this based on the actual port settings */ | |
54 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
55 | ||
749c4e60 | 56 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
57 | #define SUPPORT_SYSRQ |
58 | #endif | |
59 | ||
60 | #include <linux/serial_core.h> | |
61 | ||
e8faff73 CS |
62 | static void atmel_start_rx(struct uart_port *port); |
63 | static void atmel_stop_rx(struct uart_port *port); | |
64 | ||
749c4e60 | 65 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
66 | |
67 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
68 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
69 | * UART. */ | |
7192f92c | 70 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 71 | #define MINOR_START 154 |
7192f92c | 72 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
73 | |
74 | #else | |
75 | ||
76 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
77 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 78 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 79 | #define MINOR_START 64 |
7192f92c | 80 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
81 | |
82 | #endif | |
83 | ||
7192f92c | 84 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 85 | |
b843aa21 | 86 | /* UART registers. CR is write-only, hence no GET macro */ |
544fc728 HS |
87 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
88 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
89 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
90 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
91 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
92 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
93 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
94 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
95 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
96 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
97 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
98 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
e8faff73 | 99 | #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) |
544fc728 | 100 | |
1e6c9c28 | 101 | /* PDC registers */ |
544fc728 HS |
102 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
103 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
104 | ||
105 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
106 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
107 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
108 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
109 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
110 | ||
111 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
112 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
39d4c922 | 113 | #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) |
1e6c9c28 | 114 | |
71f2e2b8 HS |
115 | static int (*atmel_open_hook)(struct uart_port *); |
116 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 117 | |
a6670615 CC |
118 | struct atmel_dma_buffer { |
119 | unsigned char *buf; | |
120 | dma_addr_t dma_addr; | |
121 | unsigned int dma_size; | |
122 | unsigned int ofs; | |
123 | }; | |
124 | ||
1ecc26bd RB |
125 | struct atmel_uart_char { |
126 | u16 status; | |
127 | u16 ch; | |
128 | }; | |
129 | ||
130 | #define ATMEL_SERIAL_RINGSIZE 1024 | |
131 | ||
afefc415 AV |
132 | /* |
133 | * We wrap our port structure around the generic uart_port. | |
134 | */ | |
7192f92c | 135 | struct atmel_uart_port { |
afefc415 AV |
136 | struct uart_port uart; /* uart */ |
137 | struct clk *clk; /* uart clock */ | |
f05596db AS |
138 | int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ |
139 | u32 backup_imr; /* IMR saved during suspend */ | |
9e6077bd | 140 | int break_active; /* break being received */ |
1ecc26bd | 141 | |
64e22ebe | 142 | bool use_pdc_rx; /* enable PDC receiver */ |
a6670615 CC |
143 | short pdc_rx_idx; /* current PDC RX buffer */ |
144 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
145 | ||
64e22ebe | 146 | bool use_pdc_tx; /* enable PDC transmitter */ |
a6670615 CC |
147 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ |
148 | ||
1ecc26bd RB |
149 | struct tasklet_struct tasklet; |
150 | unsigned int irq_status; | |
151 | unsigned int irq_status_prev; | |
152 | ||
153 | struct circ_buf rx_ring; | |
e8faff73 CS |
154 | |
155 | struct serial_rs485 rs485; /* rs485 settings */ | |
156 | unsigned int tx_done_mask; | |
a930e528 ES |
157 | int (*prepare_rx)(struct uart_port *port); |
158 | int (*prepare_tx)(struct uart_port *port); | |
159 | void (*schedule_rx)(struct uart_port *port); | |
160 | void (*schedule_tx)(struct uart_port *port); | |
161 | void (*release_rx)(struct uart_port *port); | |
162 | void (*release_tx)(struct uart_port *port); | |
afefc415 AV |
163 | }; |
164 | ||
7192f92c | 165 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
503bded9 | 166 | static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); |
afefc415 | 167 | |
1e6c9c28 | 168 | #ifdef SUPPORT_SYSRQ |
7192f92c | 169 | static struct console atmel_console; |
1e6c9c28 AV |
170 | #endif |
171 | ||
5fbe46b6 NF |
172 | #if defined(CONFIG_OF) |
173 | static const struct of_device_id atmel_serial_dt_ids[] = { | |
174 | { .compatible = "atmel,at91rm9200-usart" }, | |
175 | { .compatible = "atmel,at91sam9260-usart" }, | |
176 | { /* sentinel */ } | |
177 | }; | |
178 | ||
179 | MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); | |
180 | #endif | |
181 | ||
c811ab8c HS |
182 | static inline struct atmel_uart_port * |
183 | to_atmel_uart_port(struct uart_port *uart) | |
184 | { | |
185 | return container_of(uart, struct atmel_uart_port, uart); | |
186 | } | |
187 | ||
a6670615 | 188 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
64e22ebe | 189 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 | 190 | { |
c811ab8c | 191 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 192 | |
64e22ebe | 193 | return atmel_port->use_pdc_rx; |
a6670615 CC |
194 | } |
195 | ||
64e22ebe | 196 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 | 197 | { |
c811ab8c | 198 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 199 | |
64e22ebe | 200 | return atmel_port->use_pdc_tx; |
a6670615 CC |
201 | } |
202 | #else | |
64e22ebe | 203 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 CC |
204 | { |
205 | return false; | |
206 | } | |
207 | ||
64e22ebe | 208 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 CC |
209 | { |
210 | return false; | |
211 | } | |
212 | #endif | |
213 | ||
e8faff73 CS |
214 | /* Enable or disable the rs485 support */ |
215 | void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) | |
216 | { | |
217 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
218 | unsigned int mode; | |
dbf1115d | 219 | unsigned long flags; |
e8faff73 | 220 | |
dbf1115d | 221 | spin_lock_irqsave(&port->lock, flags); |
e8faff73 CS |
222 | |
223 | /* Disable interrupts */ | |
224 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
225 | ||
226 | mode = UART_GET_MR(port); | |
227 | ||
228 | /* Resetting serial mode to RS232 (0x0) */ | |
229 | mode &= ~ATMEL_US_USMODE; | |
230 | ||
231 | atmel_port->rs485 = *rs485conf; | |
232 | ||
233 | if (rs485conf->flags & SER_RS485_ENABLED) { | |
234 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
235 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
93f3350c | 236 | if ((rs485conf->delay_rts_after_send) > 0) |
1b633184 | 237 | UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); |
e8faff73 CS |
238 | mode |= ATMEL_US_USMODE_RS485; |
239 | } else { | |
240 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
64e22ebe | 241 | if (atmel_use_pdc_tx(port)) |
e8faff73 CS |
242 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | |
243 | ATMEL_US_TXBUFE; | |
244 | else | |
245 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
246 | } | |
247 | UART_PUT_MR(port, mode); | |
248 | ||
249 | /* Enable interrupts */ | |
250 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
251 | ||
dbf1115d | 252 | spin_unlock_irqrestore(&port->lock, flags); |
e8faff73 CS |
253 | |
254 | } | |
255 | ||
1e6c9c28 AV |
256 | /* |
257 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
258 | */ | |
7192f92c | 259 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 260 | { |
7192f92c | 261 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
262 | } |
263 | ||
264 | /* | |
265 | * Set state of the modem control output lines | |
266 | */ | |
7192f92c | 267 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
268 | { |
269 | unsigned int control = 0; | |
afefc415 | 270 | unsigned int mode; |
e8faff73 | 271 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 272 | |
c2f5ccfb | 273 | #ifdef CONFIG_ARCH_AT91RM9200 |
79da7a61 | 274 | if (cpu_is_at91rm9200()) { |
afefc415 | 275 | /* |
b843aa21 RB |
276 | * AT91RM9200 Errata #39: RTS0 is not internally connected |
277 | * to PA21. We need to drive the pin manually. | |
afefc415 | 278 | */ |
72729910 | 279 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 280 | if (mctrl & TIOCM_RTS) |
20e65276 | 281 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 282 | else |
20e65276 | 283 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 284 | } |
1e6c9c28 | 285 | } |
acca9b83 | 286 | #endif |
1e6c9c28 AV |
287 | |
288 | if (mctrl & TIOCM_RTS) | |
7192f92c | 289 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 290 | else |
7192f92c | 291 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
292 | |
293 | if (mctrl & TIOCM_DTR) | |
7192f92c | 294 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 295 | else |
7192f92c | 296 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 297 | |
afefc415 AV |
298 | UART_PUT_CR(port, control); |
299 | ||
300 | /* Local loopback mode? */ | |
7192f92c | 301 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 302 | if (mctrl & TIOCM_LOOP) |
7192f92c | 303 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 304 | else |
7192f92c | 305 | mode |= ATMEL_US_CHMODE_NORMAL; |
e8faff73 CS |
306 | |
307 | /* Resetting serial mode to RS232 (0x0) */ | |
308 | mode &= ~ATMEL_US_USMODE; | |
309 | ||
310 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
311 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
93f3350c | 312 | if ((atmel_port->rs485.delay_rts_after_send) > 0) |
1b633184 CS |
313 | UART_PUT_TTGR(port, |
314 | atmel_port->rs485.delay_rts_after_send); | |
e8faff73 CS |
315 | mode |= ATMEL_US_USMODE_RS485; |
316 | } else { | |
317 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
318 | } | |
afefc415 | 319 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
320 | } |
321 | ||
322 | /* | |
323 | * Get state of the modem control input lines | |
324 | */ | |
7192f92c | 325 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
326 | { |
327 | unsigned int status, ret = 0; | |
328 | ||
329 | status = UART_GET_CSR(port); | |
330 | ||
331 | /* | |
332 | * The control signals are active low. | |
333 | */ | |
7192f92c | 334 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 335 | ret |= TIOCM_CD; |
7192f92c | 336 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 337 | ret |= TIOCM_CTS; |
7192f92c | 338 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 339 | ret |= TIOCM_DSR; |
7192f92c | 340 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
341 | ret |= TIOCM_RI; |
342 | ||
343 | return ret; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Stop transmitting. | |
348 | */ | |
7192f92c | 349 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 350 | { |
e8faff73 CS |
351 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
352 | ||
64e22ebe | 353 | if (atmel_use_pdc_tx(port)) { |
a6670615 CC |
354 | /* disable PDC transmit */ |
355 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
e8faff73 CS |
356 | } |
357 | /* Disable interrupts */ | |
358 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
359 | ||
83cac9f3 BR |
360 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
361 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 | 362 | atmel_start_rx(port); |
1e6c9c28 AV |
363 | } |
364 | ||
365 | /* | |
366 | * Start transmitting. | |
367 | */ | |
7192f92c | 368 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 369 | { |
e8faff73 CS |
370 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
371 | ||
64e22ebe | 372 | if (atmel_use_pdc_tx(port)) { |
a6670615 CC |
373 | if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) |
374 | /* The transmitter is already running. Yes, we | |
375 | really need this.*/ | |
376 | return; | |
377 | ||
83cac9f3 BR |
378 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
379 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 CS |
380 | atmel_stop_rx(port); |
381 | ||
a6670615 CC |
382 | /* re-enable PDC transmit */ |
383 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
e8faff73 CS |
384 | } |
385 | /* Enable interrupts */ | |
386 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
387 | } | |
388 | ||
389 | /* | |
390 | * start receiving - port is in process of being opened. | |
391 | */ | |
392 | static void atmel_start_rx(struct uart_port *port) | |
393 | { | |
394 | UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ | |
395 | ||
57c36868 SG |
396 | UART_PUT_CR(port, ATMEL_US_RXEN); |
397 | ||
64e22ebe | 398 | if (atmel_use_pdc_rx(port)) { |
e8faff73 CS |
399 | /* enable PDC controller */ |
400 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
401 | port->read_status_mask); | |
402 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
403 | } else { | |
404 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
405 | } | |
1e6c9c28 AV |
406 | } |
407 | ||
408 | /* | |
409 | * Stop receiving - port is in process of being closed. | |
410 | */ | |
7192f92c | 411 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 412 | { |
57c36868 SG |
413 | UART_PUT_CR(port, ATMEL_US_RXDIS); |
414 | ||
64e22ebe | 415 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
416 | /* disable PDC receive */ |
417 | UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); | |
e8faff73 CS |
418 | UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | |
419 | port->read_status_mask); | |
420 | } else { | |
a6670615 | 421 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
e8faff73 | 422 | } |
1e6c9c28 AV |
423 | } |
424 | ||
425 | /* | |
426 | * Enable modem status interrupts | |
427 | */ | |
7192f92c | 428 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 429 | { |
b843aa21 RB |
430 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC |
431 | | ATMEL_US_DCDIC | ATMEL_US_CTSIC); | |
1e6c9c28 AV |
432 | } |
433 | ||
434 | /* | |
435 | * Control the transmission of a break signal | |
436 | */ | |
7192f92c | 437 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
438 | { |
439 | if (break_state != 0) | |
7192f92c | 440 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 441 | else |
7192f92c | 442 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
443 | } |
444 | ||
1ecc26bd RB |
445 | /* |
446 | * Stores the incoming character in the ring buffer | |
447 | */ | |
448 | static void | |
449 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
450 | unsigned int ch) | |
451 | { | |
c811ab8c | 452 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
453 | struct circ_buf *ring = &atmel_port->rx_ring; |
454 | struct atmel_uart_char *c; | |
455 | ||
456 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
457 | /* Buffer overflow, ignore char */ | |
458 | return; | |
459 | ||
460 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
461 | c->status = status; | |
462 | c->ch = ch; | |
463 | ||
464 | /* Make sure the character is stored before we update head. */ | |
465 | smp_wmb(); | |
466 | ||
467 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
468 | } | |
469 | ||
a6670615 CC |
470 | /* |
471 | * Deal with parity, framing and overrun errors. | |
472 | */ | |
473 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
474 | { | |
475 | /* clear error */ | |
476 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
477 | ||
478 | if (status & ATMEL_US_RXBRK) { | |
479 | /* ignore side-effect */ | |
480 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
481 | port->icount.brk++; | |
482 | } | |
483 | if (status & ATMEL_US_PARE) | |
484 | port->icount.parity++; | |
485 | if (status & ATMEL_US_FRAME) | |
486 | port->icount.frame++; | |
487 | if (status & ATMEL_US_OVRE) | |
488 | port->icount.overrun++; | |
489 | } | |
490 | ||
1e6c9c28 AV |
491 | /* |
492 | * Characters received (called from interrupt handler) | |
493 | */ | |
7d12e780 | 494 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 495 | { |
c811ab8c | 496 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 497 | unsigned int status, ch; |
1e6c9c28 | 498 | |
afefc415 | 499 | status = UART_GET_CSR(port); |
7192f92c | 500 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
501 | ch = UART_GET_CHAR(port); |
502 | ||
1e6c9c28 AV |
503 | /* |
504 | * note that the error handling code is | |
505 | * out of the main execution path | |
506 | */ | |
9e6077bd HS |
507 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
508 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
509 | || atmel_port->break_active)) { | |
1ecc26bd | 510 | |
b843aa21 RB |
511 | /* clear error */ |
512 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1ecc26bd | 513 | |
9e6077bd HS |
514 | if (status & ATMEL_US_RXBRK |
515 | && !atmel_port->break_active) { | |
9e6077bd HS |
516 | atmel_port->break_active = 1; |
517 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
9e6077bd HS |
518 | } else { |
519 | /* | |
520 | * This is either the end-of-break | |
521 | * condition or we've received at | |
522 | * least one character without RXBRK | |
523 | * being set. In both cases, the next | |
524 | * RXBRK will indicate start-of-break. | |
525 | */ | |
526 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
527 | status &= ~ATMEL_US_RXBRK; | |
528 | atmel_port->break_active = 0; | |
afefc415 | 529 | } |
1e6c9c28 AV |
530 | } |
531 | ||
1ecc26bd | 532 | atmel_buffer_rx_char(port, status, ch); |
afefc415 | 533 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
534 | } |
535 | ||
1ecc26bd | 536 | tasklet_schedule(&atmel_port->tasklet); |
1e6c9c28 AV |
537 | } |
538 | ||
539 | /* | |
1ecc26bd RB |
540 | * Transmit characters (called from tasklet with TXRDY interrupt |
541 | * disabled) | |
1e6c9c28 | 542 | */ |
7192f92c | 543 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 | 544 | { |
ebd2c8f6 | 545 | struct circ_buf *xmit = &port->state->xmit; |
e8faff73 | 546 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 547 | |
e8faff73 | 548 | if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
549 | UART_PUT_CHAR(port, port->x_char); |
550 | port->icount.tx++; | |
551 | port->x_char = 0; | |
1e6c9c28 | 552 | } |
1ecc26bd | 553 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 554 | return; |
1e6c9c28 | 555 | |
e8faff73 | 556 | while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
557 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
558 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
559 | port->icount.tx++; | |
560 | if (uart_circ_empty(xmit)) | |
561 | break; | |
562 | } | |
563 | ||
564 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
565 | uart_write_wakeup(port); | |
566 | ||
1ecc26bd | 567 | if (!uart_circ_empty(xmit)) |
e8faff73 CS |
568 | /* Enable interrupts */ |
569 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
1e6c9c28 AV |
570 | } |
571 | ||
b843aa21 RB |
572 | /* |
573 | * receive interrupt handler. | |
574 | */ | |
575 | static void | |
576 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
577 | { | |
c811ab8c | 578 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 579 | |
64e22ebe | 580 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
581 | /* |
582 | * PDC receive. Just schedule the tasklet and let it | |
583 | * figure out the details. | |
584 | * | |
585 | * TODO: We're not handling error flags correctly at | |
586 | * the moment. | |
587 | */ | |
588 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
589 | UART_PUT_IDR(port, (ATMEL_US_ENDRX | |
590 | | ATMEL_US_TIMEOUT)); | |
591 | tasklet_schedule(&atmel_port->tasklet); | |
592 | } | |
593 | ||
594 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
595 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
596 | atmel_pdc_rxerr(port, pending); | |
597 | } | |
598 | ||
b843aa21 RB |
599 | /* Interrupt receive */ |
600 | if (pending & ATMEL_US_RXRDY) | |
601 | atmel_rx_chars(port); | |
602 | else if (pending & ATMEL_US_RXBRK) { | |
603 | /* | |
604 | * End of break detected. If it came along with a | |
605 | * character, atmel_rx_chars will handle it. | |
606 | */ | |
607 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
608 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
609 | atmel_port->break_active = 0; | |
610 | } | |
611 | } | |
612 | ||
613 | /* | |
1ecc26bd | 614 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
615 | */ |
616 | static void | |
617 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
618 | { | |
c811ab8c | 619 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 620 | |
e8faff73 CS |
621 | if (pending & atmel_port->tx_done_mask) { |
622 | /* Either PDC or interrupt transmission */ | |
623 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
624 | tasklet_schedule(&atmel_port->tasklet); | |
1ecc26bd | 625 | } |
b843aa21 RB |
626 | } |
627 | ||
628 | /* | |
629 | * status flags interrupt handler. | |
630 | */ | |
631 | static void | |
632 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
633 | unsigned int status) | |
634 | { | |
c811ab8c | 635 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 636 | |
b843aa21 | 637 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd RB |
638 | | ATMEL_US_CTSIC)) { |
639 | atmel_port->irq_status = status; | |
640 | tasklet_schedule(&atmel_port->tasklet); | |
641 | } | |
b843aa21 RB |
642 | } |
643 | ||
1e6c9c28 AV |
644 | /* |
645 | * Interrupt handler | |
646 | */ | |
7d12e780 | 647 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
648 | { |
649 | struct uart_port *port = dev_id; | |
650 | unsigned int status, pending, pass_counter = 0; | |
651 | ||
a6670615 CC |
652 | do { |
653 | status = UART_GET_CSR(port); | |
654 | pending = status & UART_GET_IMR(port); | |
655 | if (!pending) | |
656 | break; | |
657 | ||
b843aa21 RB |
658 | atmel_handle_receive(port, pending); |
659 | atmel_handle_status(port, pending, status); | |
660 | atmel_handle_transmit(port, pending); | |
a6670615 | 661 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 662 | |
0400b697 | 663 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 664 | } |
1e6c9c28 | 665 | |
a930e528 ES |
666 | static void atmel_release_tx_pdc(struct uart_port *port) |
667 | { | |
668 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
669 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
670 | ||
671 | dma_unmap_single(port->dev, | |
672 | pdc->dma_addr, | |
673 | pdc->dma_size, | |
674 | DMA_TO_DEVICE); | |
675 | } | |
676 | ||
a6670615 CC |
677 | /* |
678 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
679 | */ | |
64e22ebe | 680 | static void atmel_tx_pdc(struct uart_port *port) |
a6670615 | 681 | { |
c811ab8c | 682 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 683 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
684 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; |
685 | int count; | |
686 | ||
ba0657ff MT |
687 | /* nothing left to transmit? */ |
688 | if (UART_GET_TCR(port)) | |
689 | return; | |
690 | ||
a6670615 CC |
691 | xmit->tail += pdc->ofs; |
692 | xmit->tail &= UART_XMIT_SIZE - 1; | |
693 | ||
694 | port->icount.tx += pdc->ofs; | |
695 | pdc->ofs = 0; | |
696 | ||
ba0657ff | 697 | /* more to transmit - setup next transfer */ |
a6670615 | 698 | |
ba0657ff MT |
699 | /* disable PDC transmit */ |
700 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
701 | ||
1f14081d | 702 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { |
a6670615 CC |
703 | dma_sync_single_for_device(port->dev, |
704 | pdc->dma_addr, | |
705 | pdc->dma_size, | |
706 | DMA_TO_DEVICE); | |
707 | ||
708 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
709 | pdc->ofs = count; | |
710 | ||
711 | UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); | |
712 | UART_PUT_TCR(port, count); | |
e8faff73 | 713 | /* re-enable PDC transmit */ |
a6670615 | 714 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); |
e8faff73 CS |
715 | /* Enable interrupts */ |
716 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
717 | } else { | |
83cac9f3 BR |
718 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
719 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
e8faff73 CS |
720 | /* DMA done, stop TX, start RX for RS485 */ |
721 | atmel_start_rx(port); | |
722 | } | |
1e6c9c28 | 723 | } |
a6670615 CC |
724 | |
725 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
726 | uart_write_wakeup(port); | |
1e6c9c28 AV |
727 | } |
728 | ||
a930e528 ES |
729 | static int atmel_prepare_tx_pdc(struct uart_port *port) |
730 | { | |
731 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
732 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
733 | struct circ_buf *xmit = &port->state->xmit; | |
734 | ||
735 | pdc->buf = xmit->buf; | |
736 | pdc->dma_addr = dma_map_single(port->dev, | |
737 | pdc->buf, | |
738 | UART_XMIT_SIZE, | |
739 | DMA_TO_DEVICE); | |
740 | pdc->dma_size = UART_XMIT_SIZE; | |
741 | pdc->ofs = 0; | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
1ecc26bd RB |
746 | static void atmel_rx_from_ring(struct uart_port *port) |
747 | { | |
c811ab8c | 748 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
749 | struct circ_buf *ring = &atmel_port->rx_ring; |
750 | unsigned int flg; | |
751 | unsigned int status; | |
752 | ||
753 | while (ring->head != ring->tail) { | |
754 | struct atmel_uart_char c; | |
755 | ||
756 | /* Make sure c is loaded after head. */ | |
757 | smp_rmb(); | |
758 | ||
759 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
760 | ||
761 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
762 | ||
763 | port->icount.rx++; | |
764 | status = c.status; | |
765 | flg = TTY_NORMAL; | |
766 | ||
767 | /* | |
768 | * note that the error handling code is | |
769 | * out of the main execution path | |
770 | */ | |
771 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
772 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
773 | if (status & ATMEL_US_RXBRK) { | |
774 | /* ignore side-effect */ | |
775 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
776 | ||
777 | port->icount.brk++; | |
778 | if (uart_handle_break(port)) | |
779 | continue; | |
780 | } | |
781 | if (status & ATMEL_US_PARE) | |
782 | port->icount.parity++; | |
783 | if (status & ATMEL_US_FRAME) | |
784 | port->icount.frame++; | |
785 | if (status & ATMEL_US_OVRE) | |
786 | port->icount.overrun++; | |
787 | ||
788 | status &= port->read_status_mask; | |
789 | ||
790 | if (status & ATMEL_US_RXBRK) | |
791 | flg = TTY_BREAK; | |
792 | else if (status & ATMEL_US_PARE) | |
793 | flg = TTY_PARITY; | |
794 | else if (status & ATMEL_US_FRAME) | |
795 | flg = TTY_FRAME; | |
796 | } | |
797 | ||
798 | ||
799 | if (uart_handle_sysrq_char(port, c.ch)) | |
800 | continue; | |
801 | ||
802 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
803 | } | |
804 | ||
805 | /* | |
806 | * Drop the lock here since it might end up calling | |
807 | * uart_start(), which takes the lock. | |
808 | */ | |
809 | spin_unlock(&port->lock); | |
2e124b4a | 810 | tty_flip_buffer_push(&port->state->port); |
1ecc26bd RB |
811 | spin_lock(&port->lock); |
812 | } | |
813 | ||
a930e528 ES |
814 | static void atmel_release_rx_pdc(struct uart_port *port) |
815 | { | |
816 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
817 | int i; | |
818 | ||
819 | for (i = 0; i < 2; i++) { | |
820 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
821 | ||
822 | dma_unmap_single(port->dev, | |
823 | pdc->dma_addr, | |
824 | pdc->dma_size, | |
825 | DMA_FROM_DEVICE); | |
826 | kfree(pdc->buf); | |
827 | } | |
828 | } | |
829 | ||
64e22ebe | 830 | static void atmel_rx_from_pdc(struct uart_port *port) |
a6670615 | 831 | { |
c811ab8c | 832 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
05c7cd39 | 833 | struct tty_port *tport = &port->state->port; |
a6670615 CC |
834 | struct atmel_dma_buffer *pdc; |
835 | int rx_idx = atmel_port->pdc_rx_idx; | |
836 | unsigned int head; | |
837 | unsigned int tail; | |
838 | unsigned int count; | |
839 | ||
840 | do { | |
841 | /* Reset the UART timeout early so that we don't miss one */ | |
842 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
843 | ||
844 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
845 | head = UART_GET_RPR(port) - pdc->dma_addr; | |
846 | tail = pdc->ofs; | |
847 | ||
848 | /* If the PDC has switched buffers, RPR won't contain | |
849 | * any address within the current buffer. Since head | |
850 | * is unsigned, we just need a one-way comparison to | |
851 | * find out. | |
852 | * | |
853 | * In this case, we just need to consume the entire | |
854 | * buffer and resubmit it for DMA. This will clear the | |
855 | * ENDRX bit as well, so that we can safely re-enable | |
856 | * all interrupts below. | |
857 | */ | |
858 | head = min(head, pdc->dma_size); | |
859 | ||
860 | if (likely(head != tail)) { | |
861 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
862 | pdc->dma_size, DMA_FROM_DEVICE); | |
863 | ||
864 | /* | |
865 | * head will only wrap around when we recycle | |
866 | * the DMA buffer, and when that happens, we | |
867 | * explicitly set tail to 0. So head will | |
868 | * always be greater than tail. | |
869 | */ | |
870 | count = head - tail; | |
871 | ||
05c7cd39 JS |
872 | tty_insert_flip_string(tport, pdc->buf + pdc->ofs, |
873 | count); | |
a6670615 CC |
874 | |
875 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
876 | pdc->dma_size, DMA_FROM_DEVICE); | |
877 | ||
878 | port->icount.rx += count; | |
879 | pdc->ofs = head; | |
880 | } | |
881 | ||
882 | /* | |
883 | * If the current buffer is full, we need to check if | |
884 | * the next one contains any additional data. | |
885 | */ | |
886 | if (head >= pdc->dma_size) { | |
887 | pdc->ofs = 0; | |
888 | UART_PUT_RNPR(port, pdc->dma_addr); | |
889 | UART_PUT_RNCR(port, pdc->dma_size); | |
890 | ||
891 | rx_idx = !rx_idx; | |
892 | atmel_port->pdc_rx_idx = rx_idx; | |
893 | } | |
894 | } while (head >= pdc->dma_size); | |
895 | ||
896 | /* | |
897 | * Drop the lock here since it might end up calling | |
898 | * uart_start(), which takes the lock. | |
899 | */ | |
900 | spin_unlock(&port->lock); | |
2e124b4a | 901 | tty_flip_buffer_push(tport); |
a6670615 CC |
902 | spin_lock(&port->lock); |
903 | ||
904 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
905 | } | |
906 | ||
a930e528 ES |
907 | static int atmel_prepare_rx_pdc(struct uart_port *port) |
908 | { | |
909 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
910 | int i; | |
911 | ||
912 | for (i = 0; i < 2; i++) { | |
913 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
914 | ||
915 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
916 | if (pdc->buf == NULL) { | |
917 | if (i != 0) { | |
918 | dma_unmap_single(port->dev, | |
919 | atmel_port->pdc_rx[0].dma_addr, | |
920 | PDC_BUFFER_SIZE, | |
921 | DMA_FROM_DEVICE); | |
922 | kfree(atmel_port->pdc_rx[0].buf); | |
923 | } | |
924 | atmel_port->use_pdc_rx = 0; | |
925 | return -ENOMEM; | |
926 | } | |
927 | pdc->dma_addr = dma_map_single(port->dev, | |
928 | pdc->buf, | |
929 | PDC_BUFFER_SIZE, | |
930 | DMA_FROM_DEVICE); | |
931 | pdc->dma_size = PDC_BUFFER_SIZE; | |
932 | pdc->ofs = 0; | |
933 | } | |
934 | ||
935 | atmel_port->pdc_rx_idx = 0; | |
936 | ||
937 | UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); | |
938 | UART_PUT_RCR(port, PDC_BUFFER_SIZE); | |
939 | ||
940 | UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); | |
941 | UART_PUT_RNCR(port, PDC_BUFFER_SIZE); | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
1ecc26bd RB |
946 | /* |
947 | * tasklet handling tty stuff outside the interrupt handler. | |
948 | */ | |
949 | static void atmel_tasklet_func(unsigned long data) | |
950 | { | |
951 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 952 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
953 | unsigned int status; |
954 | unsigned int status_change; | |
955 | ||
956 | /* The interrupt handler does not take the lock */ | |
957 | spin_lock(&port->lock); | |
958 | ||
a930e528 | 959 | atmel_port->schedule_tx(port); |
1ecc26bd RB |
960 | |
961 | status = atmel_port->irq_status; | |
962 | status_change = status ^ atmel_port->irq_status_prev; | |
963 | ||
964 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR | |
965 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
966 | /* TODO: All reads to CSR will clear these interrupts! */ | |
967 | if (status_change & ATMEL_US_RI) | |
968 | port->icount.rng++; | |
969 | if (status_change & ATMEL_US_DSR) | |
970 | port->icount.dsr++; | |
971 | if (status_change & ATMEL_US_DCD) | |
972 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
973 | if (status_change & ATMEL_US_CTS) | |
974 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
975 | ||
bdc04e31 | 976 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
1ecc26bd RB |
977 | |
978 | atmel_port->irq_status_prev = status; | |
979 | } | |
980 | ||
a930e528 | 981 | atmel_port->schedule_rx(port); |
1ecc26bd RB |
982 | |
983 | spin_unlock(&port->lock); | |
984 | } | |
985 | ||
a930e528 ES |
986 | static void atmel_set_ops(struct uart_port *port) |
987 | { | |
988 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
989 | ||
990 | if (atmel_use_pdc_rx(port)) { | |
991 | atmel_port->prepare_rx = &atmel_prepare_rx_pdc; | |
992 | atmel_port->schedule_rx = &atmel_rx_from_pdc; | |
993 | atmel_port->release_rx = &atmel_release_rx_pdc; | |
994 | } else { | |
995 | atmel_port->prepare_rx = NULL; | |
996 | atmel_port->schedule_rx = &atmel_rx_from_ring; | |
997 | atmel_port->release_rx = NULL; | |
998 | } | |
999 | ||
1000 | if (atmel_use_pdc_tx(port)) { | |
1001 | atmel_port->prepare_tx = &atmel_prepare_tx_pdc; | |
1002 | atmel_port->schedule_tx = &atmel_tx_pdc; | |
1003 | atmel_port->release_tx = &atmel_release_tx_pdc; | |
1004 | } else { | |
1005 | atmel_port->prepare_tx = NULL; | |
1006 | atmel_port->schedule_tx = &atmel_tx_chars; | |
1007 | atmel_port->release_tx = NULL; | |
1008 | } | |
1009 | } | |
1010 | ||
1e6c9c28 AV |
1011 | /* |
1012 | * Perform initialization and enable port for reception | |
1013 | */ | |
7192f92c | 1014 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 1015 | { |
c811ab8c | 1016 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 1017 | struct tty_struct *tty = port->state->port.tty; |
1e6c9c28 AV |
1018 | int retval; |
1019 | ||
1020 | /* | |
1021 | * Ensure that no interrupts are enabled otherwise when | |
1022 | * request_irq() is called we could get stuck trying to | |
1023 | * handle an unexpected interrupt | |
1024 | */ | |
1025 | UART_PUT_IDR(port, -1); | |
1026 | ||
1027 | /* | |
1028 | * Allocate the IRQ | |
1029 | */ | |
b843aa21 | 1030 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, |
ae161068 | 1031 | tty ? tty->name : "atmel_serial", port); |
1e6c9c28 | 1032 | if (retval) { |
7192f92c | 1033 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
1034 | return retval; |
1035 | } | |
1036 | ||
a6670615 CC |
1037 | /* |
1038 | * Initialize DMA (if necessary) | |
1039 | */ | |
a930e528 ES |
1040 | if (atmel_port->prepare_rx) { |
1041 | retval = atmel_port->prepare_rx(port); | |
1042 | if (retval < 0) | |
1043 | atmel_set_ops(port); | |
a6670615 | 1044 | } |
a6670615 | 1045 | |
a930e528 ES |
1046 | if (atmel_port->prepare_tx) { |
1047 | retval = atmel_port->prepare_tx(port); | |
1048 | if (retval < 0) | |
1049 | atmel_set_ops(port); | |
a6670615 | 1050 | } |
1e6c9c28 AV |
1051 | /* |
1052 | * If there is a specific "open" function (to register | |
1053 | * control line interrupts) | |
1054 | */ | |
71f2e2b8 HS |
1055 | if (atmel_open_hook) { |
1056 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
1057 | if (retval) { |
1058 | free_irq(port->irq, port); | |
1059 | return retval; | |
1060 | } | |
1061 | } | |
1062 | ||
27c0c8e5 AN |
1063 | /* Save current CSR for comparison in atmel_tasklet_func() */ |
1064 | atmel_port->irq_status_prev = UART_GET_CSR(port); | |
1065 | atmel_port->irq_status = atmel_port->irq_status_prev; | |
1066 | ||
1e6c9c28 AV |
1067 | /* |
1068 | * Finally, enable the serial port | |
1069 | */ | |
7192f92c | 1070 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 RB |
1071 | /* enable xmit & rcvr */ |
1072 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
afefc415 | 1073 | |
64e22ebe | 1074 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
1075 | /* set UART timeout */ |
1076 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
1077 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
1078 | ||
1079 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
1080 | /* enable PDC controller */ | |
1081 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
1082 | } else { | |
1083 | /* enable receive only */ | |
1084 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
1085 | } | |
afefc415 | 1086 | |
1e6c9c28 AV |
1087 | return 0; |
1088 | } | |
1089 | ||
1090 | /* | |
1091 | * Disable the port | |
1092 | */ | |
7192f92c | 1093 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 1094 | { |
c811ab8c | 1095 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
1096 | /* |
1097 | * Ensure everything is stopped. | |
1098 | */ | |
1099 | atmel_stop_rx(port); | |
1100 | atmel_stop_tx(port); | |
1101 | ||
1102 | /* | |
1103 | * Shut-down the DMA. | |
1104 | */ | |
a930e528 ES |
1105 | if (atmel_port->release_rx) |
1106 | atmel_port->release_rx(port); | |
1107 | if (atmel_port->release_tx) | |
1108 | atmel_port->release_tx(port); | |
a6670615 | 1109 | |
1e6c9c28 AV |
1110 | /* |
1111 | * Disable all interrupts, port and break condition. | |
1112 | */ | |
7192f92c | 1113 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
1114 | UART_PUT_IDR(port, -1); |
1115 | ||
1116 | /* | |
1117 | * Free the interrupt | |
1118 | */ | |
1119 | free_irq(port->irq, port); | |
1120 | ||
1121 | /* | |
1122 | * If there is a specific "close" function (to unregister | |
1123 | * control line interrupts) | |
1124 | */ | |
71f2e2b8 HS |
1125 | if (atmel_close_hook) |
1126 | atmel_close_hook(port); | |
1e6c9c28 AV |
1127 | } |
1128 | ||
9afd561a HS |
1129 | /* |
1130 | * Flush any TX data submitted for DMA. Called when the TX circular | |
1131 | * buffer is reset. | |
1132 | */ | |
1133 | static void atmel_flush_buffer(struct uart_port *port) | |
1134 | { | |
1135 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1136 | ||
64e22ebe | 1137 | if (atmel_use_pdc_tx(port)) { |
9afd561a HS |
1138 | UART_PUT_TCR(port, 0); |
1139 | atmel_port->pdc_tx.ofs = 0; | |
1140 | } | |
1141 | } | |
1142 | ||
1e6c9c28 AV |
1143 | /* |
1144 | * Power / Clock management. | |
1145 | */ | |
b843aa21 RB |
1146 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
1147 | unsigned int oldstate) | |
1e6c9c28 | 1148 | { |
c811ab8c | 1149 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1150 | |
1e6c9c28 | 1151 | switch (state) { |
b843aa21 RB |
1152 | case 0: |
1153 | /* | |
1154 | * Enable the peripheral clock for this serial port. | |
1155 | * This is called on uart_open() or a resume event. | |
1156 | */ | |
91f8c2d8 | 1157 | clk_prepare_enable(atmel_port->clk); |
f05596db AS |
1158 | |
1159 | /* re-enable interrupts if we disabled some on suspend */ | |
1160 | UART_PUT_IER(port, atmel_port->backup_imr); | |
b843aa21 RB |
1161 | break; |
1162 | case 3: | |
f05596db AS |
1163 | /* Back up the interrupt mask and disable all interrupts */ |
1164 | atmel_port->backup_imr = UART_GET_IMR(port); | |
1165 | UART_PUT_IDR(port, -1); | |
1166 | ||
b843aa21 RB |
1167 | /* |
1168 | * Disable the peripheral clock for this serial port. | |
1169 | * This is called on uart_close() or a suspend event. | |
1170 | */ | |
91f8c2d8 | 1171 | clk_disable_unprepare(atmel_port->clk); |
b843aa21 RB |
1172 | break; |
1173 | default: | |
1174 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); | |
1e6c9c28 AV |
1175 | } |
1176 | } | |
1177 | ||
1178 | /* | |
1179 | * Change the port parameters | |
1180 | */ | |
b843aa21 RB |
1181 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
1182 | struct ktermios *old) | |
1e6c9c28 AV |
1183 | { |
1184 | unsigned long flags; | |
1185 | unsigned int mode, imr, quot, baud; | |
e8faff73 | 1186 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1187 | |
03abeac0 | 1188 | /* Get current mode register */ |
b843aa21 | 1189 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL |
8e706c4d PM |
1190 | | ATMEL_US_NBSTOP | ATMEL_US_PAR |
1191 | | ATMEL_US_USMODE); | |
03abeac0 | 1192 | |
b843aa21 | 1193 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
1194 | quot = uart_get_divisor(port, baud); |
1195 | ||
b843aa21 | 1196 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
1197 | quot /= 8; |
1198 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
1199 | } | |
1e6c9c28 AV |
1200 | |
1201 | /* byte size */ | |
1202 | switch (termios->c_cflag & CSIZE) { | |
1203 | case CS5: | |
7192f92c | 1204 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
1205 | break; |
1206 | case CS6: | |
7192f92c | 1207 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
1208 | break; |
1209 | case CS7: | |
7192f92c | 1210 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
1211 | break; |
1212 | default: | |
7192f92c | 1213 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
1214 | break; |
1215 | } | |
1216 | ||
1217 | /* stop bits */ | |
1218 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 1219 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
1220 | |
1221 | /* parity */ | |
1222 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
1223 | /* Mark or Space parity */ |
1224 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 1225 | if (termios->c_cflag & PARODD) |
7192f92c | 1226 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 1227 | else |
7192f92c | 1228 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 1229 | } else if (termios->c_cflag & PARODD) |
7192f92c | 1230 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 1231 | else |
7192f92c | 1232 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 1233 | } else |
7192f92c | 1234 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 | 1235 | |
8e706c4d PM |
1236 | /* hardware handshake (RTS/CTS) */ |
1237 | if (termios->c_cflag & CRTSCTS) | |
1238 | mode |= ATMEL_US_USMODE_HWHS; | |
1239 | else | |
1240 | mode |= ATMEL_US_USMODE_NORMAL; | |
1241 | ||
1e6c9c28 AV |
1242 | spin_lock_irqsave(&port->lock, flags); |
1243 | ||
7192f92c | 1244 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 1245 | if (termios->c_iflag & INPCK) |
7192f92c | 1246 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1247 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 1248 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 1249 | |
64e22ebe | 1250 | if (atmel_use_pdc_rx(port)) |
a6670615 CC |
1251 | /* need to enable error interrupts */ |
1252 | UART_PUT_IER(port, port->read_status_mask); | |
1253 | ||
1e6c9c28 AV |
1254 | /* |
1255 | * Characters to ignore | |
1256 | */ | |
1257 | port->ignore_status_mask = 0; | |
1258 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1259 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1260 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 1261 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
1262 | /* |
1263 | * If we're ignoring parity and break indicators, | |
1264 | * ignore overruns too (for real raw support). | |
1265 | */ | |
1266 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1267 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 1268 | } |
b843aa21 | 1269 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
1270 | |
1271 | /* update the per-port timeout */ | |
1272 | uart_update_timeout(port, termios->c_cflag, baud); | |
1273 | ||
0ccad870 HS |
1274 | /* |
1275 | * save/disable interrupts. The tty layer will ensure that the | |
1276 | * transmitter is empty if requested by the caller, so there's | |
1277 | * no need to wait for it here. | |
1278 | */ | |
b843aa21 RB |
1279 | imr = UART_GET_IMR(port); |
1280 | UART_PUT_IDR(port, -1); | |
1e6c9c28 AV |
1281 | |
1282 | /* disable receiver and transmitter */ | |
7192f92c | 1283 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 | 1284 | |
e8faff73 CS |
1285 | /* Resetting serial mode to RS232 (0x0) */ |
1286 | mode &= ~ATMEL_US_USMODE; | |
1287 | ||
1288 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
1289 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
93f3350c | 1290 | if ((atmel_port->rs485.delay_rts_after_send) > 0) |
1b633184 CS |
1291 | UART_PUT_TTGR(port, |
1292 | atmel_port->rs485.delay_rts_after_send); | |
e8faff73 CS |
1293 | mode |= ATMEL_US_USMODE_RS485; |
1294 | } else { | |
1295 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
1296 | } | |
1297 | ||
1e6c9c28 AV |
1298 | /* set the parity, stop bits and data size */ |
1299 | UART_PUT_MR(port, mode); | |
1300 | ||
1301 | /* set the baud rate */ | |
1302 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
1303 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1304 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1305 | |
1306 | /* restore interrupts */ | |
1307 | UART_PUT_IER(port, imr); | |
1308 | ||
1309 | /* CTS flow-control and modem-status interrupts */ | |
1310 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1311 | port->ops->enable_ms(port); | |
1312 | ||
1313 | spin_unlock_irqrestore(&port->lock, flags); | |
1314 | } | |
1315 | ||
42bd7a4f VP |
1316 | static void atmel_set_ldisc(struct uart_port *port, int new) |
1317 | { | |
b54bf3b2 | 1318 | if (new == N_PPS) { |
42bd7a4f VP |
1319 | port->flags |= UPF_HARDPPS_CD; |
1320 | atmel_enable_ms(port); | |
1321 | } else { | |
1322 | port->flags &= ~UPF_HARDPPS_CD; | |
1323 | } | |
1324 | } | |
1325 | ||
1e6c9c28 AV |
1326 | /* |
1327 | * Return string describing the specified port | |
1328 | */ | |
7192f92c | 1329 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 1330 | { |
9ab4f88b | 1331 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
1332 | } |
1333 | ||
1334 | /* | |
1335 | * Release the memory region(s) being used by 'port'. | |
1336 | */ | |
7192f92c | 1337 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 1338 | { |
afefc415 AV |
1339 | struct platform_device *pdev = to_platform_device(port->dev); |
1340 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1341 | ||
1342 | release_mem_region(port->mapbase, size); | |
1343 | ||
1344 | if (port->flags & UPF_IOREMAP) { | |
1345 | iounmap(port->membase); | |
1346 | port->membase = NULL; | |
1347 | } | |
1e6c9c28 AV |
1348 | } |
1349 | ||
1350 | /* | |
1351 | * Request the memory region(s) being used by 'port'. | |
1352 | */ | |
7192f92c | 1353 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 1354 | { |
afefc415 AV |
1355 | struct platform_device *pdev = to_platform_device(port->dev); |
1356 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1357 | ||
7192f92c | 1358 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
1359 | return -EBUSY; |
1360 | ||
1361 | if (port->flags & UPF_IOREMAP) { | |
1362 | port->membase = ioremap(port->mapbase, size); | |
1363 | if (port->membase == NULL) { | |
1364 | release_mem_region(port->mapbase, size); | |
1365 | return -ENOMEM; | |
1366 | } | |
1367 | } | |
1e6c9c28 | 1368 | |
afefc415 | 1369 | return 0; |
1e6c9c28 AV |
1370 | } |
1371 | ||
1372 | /* | |
1373 | * Configure/autoconfigure the port. | |
1374 | */ | |
7192f92c | 1375 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
1376 | { |
1377 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 1378 | port->type = PORT_ATMEL; |
7192f92c | 1379 | atmel_request_port(port); |
1e6c9c28 AV |
1380 | } |
1381 | } | |
1382 | ||
1383 | /* | |
1384 | * Verify the new serial_struct (for TIOCSSERIAL). | |
1385 | */ | |
7192f92c | 1386 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
1387 | { |
1388 | int ret = 0; | |
9ab4f88b | 1389 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
1390 | ret = -EINVAL; |
1391 | if (port->irq != ser->irq) | |
1392 | ret = -EINVAL; | |
1393 | if (ser->io_type != SERIAL_IO_MEM) | |
1394 | ret = -EINVAL; | |
1395 | if (port->uartclk / 16 != ser->baud_base) | |
1396 | ret = -EINVAL; | |
1397 | if ((void *)port->mapbase != ser->iomem_base) | |
1398 | ret = -EINVAL; | |
1399 | if (port->iobase != ser->port) | |
1400 | ret = -EINVAL; | |
1401 | if (ser->hub6 != 0) | |
1402 | ret = -EINVAL; | |
1403 | return ret; | |
1404 | } | |
1405 | ||
8fe2d541 AT |
1406 | #ifdef CONFIG_CONSOLE_POLL |
1407 | static int atmel_poll_get_char(struct uart_port *port) | |
1408 | { | |
1409 | while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) | |
1410 | cpu_relax(); | |
1411 | ||
1412 | return UART_GET_CHAR(port); | |
1413 | } | |
1414 | ||
1415 | static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) | |
1416 | { | |
1417 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) | |
1418 | cpu_relax(); | |
1419 | ||
1420 | UART_PUT_CHAR(port, ch); | |
1421 | } | |
1422 | #endif | |
1423 | ||
e8faff73 CS |
1424 | static int |
1425 | atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) | |
1426 | { | |
1427 | struct serial_rs485 rs485conf; | |
1428 | ||
1429 | switch (cmd) { | |
1430 | case TIOCSRS485: | |
1431 | if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, | |
1432 | sizeof(rs485conf))) | |
1433 | return -EFAULT; | |
1434 | ||
1435 | atmel_config_rs485(port, &rs485conf); | |
1436 | break; | |
1437 | ||
1438 | case TIOCGRS485: | |
1439 | if (copy_to_user((struct serial_rs485 *) arg, | |
1440 | &(to_atmel_uart_port(port)->rs485), | |
1441 | sizeof(rs485conf))) | |
1442 | return -EFAULT; | |
1443 | break; | |
1444 | ||
1445 | default: | |
1446 | return -ENOIOCTLCMD; | |
1447 | } | |
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | ||
1452 | ||
7192f92c HS |
1453 | static struct uart_ops atmel_pops = { |
1454 | .tx_empty = atmel_tx_empty, | |
1455 | .set_mctrl = atmel_set_mctrl, | |
1456 | .get_mctrl = atmel_get_mctrl, | |
1457 | .stop_tx = atmel_stop_tx, | |
1458 | .start_tx = atmel_start_tx, | |
1459 | .stop_rx = atmel_stop_rx, | |
1460 | .enable_ms = atmel_enable_ms, | |
1461 | .break_ctl = atmel_break_ctl, | |
1462 | .startup = atmel_startup, | |
1463 | .shutdown = atmel_shutdown, | |
9afd561a | 1464 | .flush_buffer = atmel_flush_buffer, |
7192f92c | 1465 | .set_termios = atmel_set_termios, |
42bd7a4f | 1466 | .set_ldisc = atmel_set_ldisc, |
7192f92c HS |
1467 | .type = atmel_type, |
1468 | .release_port = atmel_release_port, | |
1469 | .request_port = atmel_request_port, | |
1470 | .config_port = atmel_config_port, | |
1471 | .verify_port = atmel_verify_port, | |
1472 | .pm = atmel_serial_pm, | |
e8faff73 | 1473 | .ioctl = atmel_ioctl, |
8fe2d541 AT |
1474 | #ifdef CONFIG_CONSOLE_POLL |
1475 | .poll_get_char = atmel_poll_get_char, | |
1476 | .poll_put_char = atmel_poll_put_char, | |
1477 | #endif | |
1e6c9c28 AV |
1478 | }; |
1479 | ||
9671f099 | 1480 | static void atmel_of_init_port(struct atmel_uart_port *atmel_port, |
5fbe46b6 NF |
1481 | struct device_node *np) |
1482 | { | |
1483 | u32 rs485_delay[2]; | |
1484 | ||
1485 | /* DMA/PDC usage specification */ | |
1486 | if (of_get_property(np, "atmel,use-dma-rx", NULL)) | |
64e22ebe | 1487 | atmel_port->use_pdc_rx = true; |
5fbe46b6 | 1488 | else |
64e22ebe ES |
1489 | atmel_port->use_pdc_rx = false; |
1490 | ||
5fbe46b6 | 1491 | if (of_get_property(np, "atmel,use-dma-tx", NULL)) |
64e22ebe | 1492 | atmel_port->use_pdc_tx = true; |
5fbe46b6 | 1493 | else |
64e22ebe | 1494 | atmel_port->use_pdc_tx = false; |
5fbe46b6 NF |
1495 | |
1496 | /* rs485 properties */ | |
1497 | if (of_property_read_u32_array(np, "rs485-rts-delay", | |
1498 | rs485_delay, 2) == 0) { | |
1499 | struct serial_rs485 *rs485conf = &atmel_port->rs485; | |
1500 | ||
1501 | rs485conf->delay_rts_before_send = rs485_delay[0]; | |
1502 | rs485conf->delay_rts_after_send = rs485_delay[1]; | |
1503 | rs485conf->flags = 0; | |
1504 | ||
5fbe46b6 NF |
1505 | if (of_get_property(np, "rs485-rx-during-tx", NULL)) |
1506 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | |
1507 | ||
1508 | if (of_get_property(np, "linux,rs485-enabled-at-boot-time", NULL)) | |
1509 | rs485conf->flags |= SER_RS485_ENABLED; | |
1510 | } | |
1511 | } | |
1512 | ||
afefc415 AV |
1513 | /* |
1514 | * Configure the port from the platform device resource info. | |
1515 | */ | |
91f8c2d8 | 1516 | static int atmel_init_port(struct atmel_uart_port *atmel_port, |
b843aa21 | 1517 | struct platform_device *pdev) |
1e6c9c28 | 1518 | { |
91f8c2d8 | 1519 | int ret; |
7192f92c | 1520 | struct uart_port *port = &atmel_port->uart; |
1acfc7ec | 1521 | struct atmel_uart_data *pdata = pdev->dev.platform_data; |
afefc415 | 1522 | |
5fbe46b6 NF |
1523 | if (pdev->dev.of_node) { |
1524 | atmel_of_init_port(atmel_port, pdev->dev.of_node); | |
1525 | } else { | |
64e22ebe ES |
1526 | atmel_port->use_pdc_rx = pdata->use_dma_rx; |
1527 | atmel_port->use_pdc_tx = pdata->use_dma_tx; | |
5fbe46b6 NF |
1528 | atmel_port->rs485 = pdata->rs485; |
1529 | } | |
afefc415 | 1530 | |
a930e528 ES |
1531 | atmel_set_ops(port); |
1532 | ||
e8faff73 CS |
1533 | port->iotype = UPIO_MEM; |
1534 | port->flags = UPF_BOOT_AUTOCONF; | |
1535 | port->ops = &atmel_pops; | |
1536 | port->fifosize = 1; | |
e8faff73 | 1537 | port->dev = &pdev->dev; |
afefc415 AV |
1538 | port->mapbase = pdev->resource[0].start; |
1539 | port->irq = pdev->resource[1].start; | |
1540 | ||
1ecc26bd RB |
1541 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
1542 | (unsigned long)port); | |
1543 | ||
1544 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | |
1545 | ||
5fbe46b6 | 1546 | if (pdata && pdata->regs) { |
75d35213 | 1547 | /* Already mapped by setup code */ |
1acfc7ec | 1548 | port->membase = pdata->regs; |
588edbf3 | 1549 | } else { |
afefc415 AV |
1550 | port->flags |= UPF_IOREMAP; |
1551 | port->membase = NULL; | |
1552 | } | |
1e6c9c28 | 1553 | |
b843aa21 RB |
1554 | /* for console, the clock could already be configured */ |
1555 | if (!atmel_port->clk) { | |
7192f92c | 1556 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
91f8c2d8 BB |
1557 | if (IS_ERR(atmel_port->clk)) { |
1558 | ret = PTR_ERR(atmel_port->clk); | |
1559 | atmel_port->clk = NULL; | |
1560 | return ret; | |
1561 | } | |
1562 | ret = clk_prepare_enable(atmel_port->clk); | |
1563 | if (ret) { | |
1564 | clk_put(atmel_port->clk); | |
1565 | atmel_port->clk = NULL; | |
1566 | return ret; | |
1567 | } | |
7192f92c | 1568 | port->uartclk = clk_get_rate(atmel_port->clk); |
91f8c2d8 | 1569 | clk_disable_unprepare(atmel_port->clk); |
06a7f058 | 1570 | /* only enable clock when USART is in use */ |
afefc415 | 1571 | } |
a6670615 | 1572 | |
e8faff73 CS |
1573 | /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ |
1574 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) | |
1575 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
64e22ebe | 1576 | else if (atmel_use_pdc_tx(port)) { |
a6670615 | 1577 | port->fifosize = PDC_BUFFER_SIZE; |
e8faff73 CS |
1578 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; |
1579 | } else { | |
1580 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
1581 | } | |
91f8c2d8 BB |
1582 | |
1583 | return 0; | |
1e6c9c28 AV |
1584 | } |
1585 | ||
69f6a27b JCPV |
1586 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
1587 | ||
749c4e60 | 1588 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 1589 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 1590 | { |
7192f92c | 1591 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
829dd811 | 1592 | cpu_relax(); |
d358788f RK |
1593 | UART_PUT_CHAR(port, ch); |
1594 | } | |
1e6c9c28 AV |
1595 | |
1596 | /* | |
1597 | * Interrupts are disabled on entering | |
1598 | */ | |
7192f92c | 1599 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 1600 | { |
7192f92c | 1601 | struct uart_port *port = &atmel_ports[co->index].uart; |
e8faff73 | 1602 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
d358788f | 1603 | unsigned int status, imr; |
39d4c922 | 1604 | unsigned int pdc_tx; |
1e6c9c28 AV |
1605 | |
1606 | /* | |
b843aa21 | 1607 | * First, save IMR and then disable interrupts |
1e6c9c28 | 1608 | */ |
b843aa21 | 1609 | imr = UART_GET_IMR(port); |
e8faff73 | 1610 | UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); |
1e6c9c28 | 1611 | |
39d4c922 MP |
1612 | /* Store PDC transmit status and disable it */ |
1613 | pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; | |
1614 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
1615 | ||
7192f92c | 1616 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
1617 | |
1618 | /* | |
b843aa21 RB |
1619 | * Finally, wait for transmitter to become empty |
1620 | * and restore IMR | |
1e6c9c28 AV |
1621 | */ |
1622 | do { | |
1623 | status = UART_GET_CSR(port); | |
7192f92c | 1624 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
1625 | |
1626 | /* Restore PDC transmit status */ | |
1627 | if (pdc_tx) | |
1628 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
1629 | ||
b843aa21 RB |
1630 | /* set interrupts back the way they were */ |
1631 | UART_PUT_IER(port, imr); | |
1e6c9c28 AV |
1632 | } |
1633 | ||
1634 | /* | |
b843aa21 RB |
1635 | * If the port was already initialised (eg, by a boot loader), |
1636 | * try to determine the current setup. | |
1e6c9c28 | 1637 | */ |
b843aa21 RB |
1638 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
1639 | int *parity, int *bits) | |
1e6c9c28 AV |
1640 | { |
1641 | unsigned int mr, quot; | |
1642 | ||
1c0fd82f HS |
1643 | /* |
1644 | * If the baud rate generator isn't running, the port wasn't | |
1645 | * initialized by the boot loader. | |
1646 | */ | |
9c81c5c9 | 1647 | quot = UART_GET_BRGR(port) & ATMEL_US_CD; |
1c0fd82f HS |
1648 | if (!quot) |
1649 | return; | |
1e6c9c28 | 1650 | |
7192f92c HS |
1651 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
1652 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
1653 | *bits = 8; |
1654 | else | |
1655 | *bits = 7; | |
1656 | ||
7192f92c HS |
1657 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
1658 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 1659 | *parity = 'e'; |
7192f92c | 1660 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
1661 | *parity = 'o'; |
1662 | ||
4d5e392c HS |
1663 | /* |
1664 | * The serial core only rounds down when matching this to a | |
1665 | * supported baud rate. Make sure we don't end up slightly | |
1666 | * lower than one of those, as it would make us fall through | |
1667 | * to a much lower baud rate than we really want. | |
1668 | */ | |
4d5e392c | 1669 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
1670 | } |
1671 | ||
7192f92c | 1672 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 1673 | { |
91f8c2d8 | 1674 | int ret; |
7192f92c | 1675 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
1676 | int baud = 115200; |
1677 | int bits = 8; | |
1678 | int parity = 'n'; | |
1679 | int flow = 'n'; | |
1680 | ||
b843aa21 RB |
1681 | if (port->membase == NULL) { |
1682 | /* Port not initialized yet - delay setup */ | |
afefc415 | 1683 | return -ENODEV; |
b843aa21 | 1684 | } |
1e6c9c28 | 1685 | |
91f8c2d8 BB |
1686 | ret = clk_prepare_enable(atmel_ports[co->index].clk); |
1687 | if (ret) | |
1688 | return ret; | |
06a7f058 | 1689 | |
b843aa21 | 1690 | UART_PUT_IDR(port, -1); |
7192f92c HS |
1691 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1692 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1693 | |
1694 | if (options) | |
1695 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1696 | else | |
7192f92c | 1697 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
1698 | |
1699 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1700 | } | |
1701 | ||
7192f92c | 1702 | static struct uart_driver atmel_uart; |
1e6c9c28 | 1703 | |
7192f92c HS |
1704 | static struct console atmel_console = { |
1705 | .name = ATMEL_DEVICENAME, | |
1706 | .write = atmel_console_write, | |
1e6c9c28 | 1707 | .device = uart_console_device, |
7192f92c | 1708 | .setup = atmel_console_setup, |
1e6c9c28 AV |
1709 | .flags = CON_PRINTBUFFER, |
1710 | .index = -1, | |
7192f92c | 1711 | .data = &atmel_uart, |
1e6c9c28 AV |
1712 | }; |
1713 | ||
06a7f058 | 1714 | #define ATMEL_CONSOLE_DEVICE (&atmel_console) |
1e6c9c28 | 1715 | |
afefc415 AV |
1716 | /* |
1717 | * Early console initialization (before VM subsystem initialized). | |
1718 | */ | |
7192f92c | 1719 | static int __init atmel_console_init(void) |
1e6c9c28 | 1720 | { |
91f8c2d8 | 1721 | int ret; |
73e2798b | 1722 | if (atmel_default_console_device) { |
0d0a3cc1 VN |
1723 | struct atmel_uart_data *pdata = |
1724 | atmel_default_console_device->dev.platform_data; | |
efb8d21b | 1725 | int id = pdata->num; |
4cbf9f48 NF |
1726 | struct atmel_uart_port *port = &atmel_ports[id]; |
1727 | ||
4cbf9f48 NF |
1728 | port->backup_imr = 0; |
1729 | port->uart.line = id; | |
0d0a3cc1 | 1730 | |
4cbf9f48 | 1731 | add_preferred_console(ATMEL_DEVICENAME, id, NULL); |
91f8c2d8 BB |
1732 | ret = atmel_init_port(port, atmel_default_console_device); |
1733 | if (ret) | |
1734 | return ret; | |
7192f92c | 1735 | register_console(&atmel_console); |
afefc415 | 1736 | } |
1e6c9c28 | 1737 | |
1e6c9c28 AV |
1738 | return 0; |
1739 | } | |
b843aa21 | 1740 | |
7192f92c | 1741 | console_initcall(atmel_console_init); |
1e6c9c28 | 1742 | |
afefc415 AV |
1743 | /* |
1744 | * Late console initialization. | |
1745 | */ | |
7192f92c | 1746 | static int __init atmel_late_console_init(void) |
afefc415 | 1747 | { |
b843aa21 RB |
1748 | if (atmel_default_console_device |
1749 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 1750 | register_console(&atmel_console); |
afefc415 AV |
1751 | |
1752 | return 0; | |
1753 | } | |
b843aa21 | 1754 | |
7192f92c | 1755 | core_initcall(atmel_late_console_init); |
afefc415 | 1756 | |
dfa7f343 HS |
1757 | static inline bool atmel_is_console_port(struct uart_port *port) |
1758 | { | |
1759 | return port->cons && port->cons->index == port->line; | |
1760 | } | |
1761 | ||
1e6c9c28 | 1762 | #else |
7192f92c | 1763 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
1764 | |
1765 | static inline bool atmel_is_console_port(struct uart_port *port) | |
1766 | { | |
1767 | return false; | |
1768 | } | |
1e6c9c28 AV |
1769 | #endif |
1770 | ||
7192f92c | 1771 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
1772 | .owner = THIS_MODULE, |
1773 | .driver_name = "atmel_serial", | |
1774 | .dev_name = ATMEL_DEVICENAME, | |
1775 | .major = SERIAL_ATMEL_MAJOR, | |
1776 | .minor = MINOR_START, | |
1777 | .nr = ATMEL_MAX_UART, | |
1778 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
1779 | }; |
1780 | ||
afefc415 | 1781 | #ifdef CONFIG_PM |
f826caa4 HS |
1782 | static bool atmel_serial_clk_will_stop(void) |
1783 | { | |
1784 | #ifdef CONFIG_ARCH_AT91 | |
1785 | return at91_suspend_entering_slow_clock(); | |
1786 | #else | |
1787 | return false; | |
1788 | #endif | |
1789 | } | |
1790 | ||
b843aa21 RB |
1791 | static int atmel_serial_suspend(struct platform_device *pdev, |
1792 | pm_message_t state) | |
1e6c9c28 | 1793 | { |
afefc415 | 1794 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 1795 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1796 | |
e1c609ef HS |
1797 | if (atmel_is_console_port(port) && console_suspend_enabled) { |
1798 | /* Drain the TX shifter */ | |
1799 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
1800 | cpu_relax(); | |
1801 | } | |
1802 | ||
f05596db AS |
1803 | /* we can not wake up if we're running on slow clock */ |
1804 | atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); | |
1805 | if (atmel_serial_clk_will_stop()) | |
1806 | device_set_wakeup_enable(&pdev->dev, 0); | |
1807 | ||
1808 | uart_suspend_port(&atmel_uart, port); | |
1e6c9c28 | 1809 | |
afefc415 AV |
1810 | return 0; |
1811 | } | |
1e6c9c28 | 1812 | |
7192f92c | 1813 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
1814 | { |
1815 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1816 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1817 | |
f05596db AS |
1818 | uart_resume_port(&atmel_uart, port); |
1819 | device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); | |
1e6c9c28 AV |
1820 | |
1821 | return 0; | |
1822 | } | |
afefc415 | 1823 | #else |
7192f92c HS |
1824 | #define atmel_serial_suspend NULL |
1825 | #define atmel_serial_resume NULL | |
afefc415 | 1826 | #endif |
1e6c9c28 | 1827 | |
9671f099 | 1828 | static int atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 1829 | { |
7192f92c | 1830 | struct atmel_uart_port *port; |
5fbe46b6 | 1831 | struct device_node *np = pdev->dev.of_node; |
deba1a0d | 1832 | struct atmel_uart_data *pdata = pdev->dev.platform_data; |
1ecc26bd | 1833 | void *data; |
4cbf9f48 | 1834 | int ret = -ENODEV; |
1e6c9c28 | 1835 | |
9d09daf8 | 1836 | BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); |
1ecc26bd | 1837 | |
5fbe46b6 NF |
1838 | if (np) |
1839 | ret = of_alias_get_id(np, "serial"); | |
1840 | else | |
1841 | if (pdata) | |
1842 | ret = pdata->num; | |
4cbf9f48 NF |
1843 | |
1844 | if (ret < 0) | |
5fbe46b6 | 1845 | /* port id not found in platform data nor device-tree aliases: |
4cbf9f48 | 1846 | * auto-enumerate it */ |
503bded9 | 1847 | ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); |
4cbf9f48 | 1848 | |
503bded9 | 1849 | if (ret >= ATMEL_MAX_UART) { |
4cbf9f48 NF |
1850 | ret = -ENODEV; |
1851 | goto err; | |
1852 | } | |
1853 | ||
503bded9 | 1854 | if (test_and_set_bit(ret, atmel_ports_in_use)) { |
4cbf9f48 NF |
1855 | /* port already in use */ |
1856 | ret = -EBUSY; | |
1857 | goto err; | |
1858 | } | |
1859 | ||
1860 | port = &atmel_ports[ret]; | |
f05596db | 1861 | port->backup_imr = 0; |
4cbf9f48 | 1862 | port->uart.line = ret; |
f05596db | 1863 | |
91f8c2d8 BB |
1864 | ret = atmel_init_port(port, pdev); |
1865 | if (ret) | |
1866 | goto err; | |
1e6c9c28 | 1867 | |
64e22ebe | 1868 | if (!atmel_use_pdc_rx(&port->uart)) { |
a6670615 | 1869 | ret = -ENOMEM; |
6433471d HS |
1870 | data = kmalloc(sizeof(struct atmel_uart_char) |
1871 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
1872 | if (!data) |
1873 | goto err_alloc_ring; | |
1874 | port->rx_ring.buf = data; | |
1875 | } | |
1ecc26bd | 1876 | |
7192f92c | 1877 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
dfa7f343 HS |
1878 | if (ret) |
1879 | goto err_add_port; | |
1880 | ||
8da14b5f | 1881 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
06a7f058 DB |
1882 | if (atmel_is_console_port(&port->uart) |
1883 | && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { | |
1884 | /* | |
1885 | * The serial core enabled the clock for us, so undo | |
91f8c2d8 | 1886 | * the clk_prepare_enable() in atmel_console_setup() |
06a7f058 | 1887 | */ |
91f8c2d8 | 1888 | clk_disable_unprepare(port->clk); |
06a7f058 | 1889 | } |
8da14b5f | 1890 | #endif |
06a7f058 | 1891 | |
dfa7f343 HS |
1892 | device_init_wakeup(&pdev->dev, 1); |
1893 | platform_set_drvdata(pdev, port); | |
1894 | ||
5dfbd1d7 CS |
1895 | if (port->rs485.flags & SER_RS485_ENABLED) { |
1896 | UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); | |
1897 | UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); | |
1898 | } | |
1899 | ||
dfa7f343 HS |
1900 | return 0; |
1901 | ||
1902 | err_add_port: | |
1ecc26bd RB |
1903 | kfree(port->rx_ring.buf); |
1904 | port->rx_ring.buf = NULL; | |
1905 | err_alloc_ring: | |
dfa7f343 | 1906 | if (!atmel_is_console_port(&port->uart)) { |
dfa7f343 HS |
1907 | clk_put(port->clk); |
1908 | port->clk = NULL; | |
afefc415 | 1909 | } |
4cbf9f48 | 1910 | err: |
afefc415 AV |
1911 | return ret; |
1912 | } | |
1913 | ||
ae8d8a14 | 1914 | static int atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
1915 | { |
1916 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1917 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 AV |
1918 | int ret = 0; |
1919 | ||
afefc415 | 1920 | device_init_wakeup(&pdev->dev, 0); |
afefc415 | 1921 | |
dfa7f343 HS |
1922 | ret = uart_remove_one_port(&atmel_uart, port); |
1923 | ||
1ecc26bd RB |
1924 | tasklet_kill(&atmel_port->tasklet); |
1925 | kfree(atmel_port->rx_ring.buf); | |
1926 | ||
dfa7f343 HS |
1927 | /* "port" is allocated statically, so we shouldn't free it */ |
1928 | ||
503bded9 | 1929 | clear_bit(port->line, atmel_ports_in_use); |
4cbf9f48 | 1930 | |
dfa7f343 | 1931 | clk_put(atmel_port->clk); |
afefc415 AV |
1932 | |
1933 | return ret; | |
1934 | } | |
1935 | ||
7192f92c HS |
1936 | static struct platform_driver atmel_serial_driver = { |
1937 | .probe = atmel_serial_probe, | |
2d47b716 | 1938 | .remove = atmel_serial_remove, |
7192f92c HS |
1939 | .suspend = atmel_serial_suspend, |
1940 | .resume = atmel_serial_resume, | |
afefc415 | 1941 | .driver = { |
1e8ea802 | 1942 | .name = "atmel_usart", |
afefc415 | 1943 | .owner = THIS_MODULE, |
5fbe46b6 | 1944 | .of_match_table = of_match_ptr(atmel_serial_dt_ids), |
afefc415 AV |
1945 | }, |
1946 | }; | |
1947 | ||
7192f92c | 1948 | static int __init atmel_serial_init(void) |
afefc415 AV |
1949 | { |
1950 | int ret; | |
1951 | ||
7192f92c | 1952 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
1953 | if (ret) |
1954 | return ret; | |
1955 | ||
7192f92c | 1956 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 1957 | if (ret) |
7192f92c | 1958 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
1959 | |
1960 | return ret; | |
1961 | } | |
1962 | ||
7192f92c | 1963 | static void __exit atmel_serial_exit(void) |
afefc415 | 1964 | { |
7192f92c HS |
1965 | platform_driver_unregister(&atmel_serial_driver); |
1966 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
1967 | } |
1968 | ||
7192f92c HS |
1969 | module_init(atmel_serial_init); |
1970 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
1971 | |
1972 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 1973 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 1974 | MODULE_LICENSE("GPL"); |
e169c139 | 1975 | MODULE_ALIAS("platform:atmel_usart"); |