Commit | Line | Data |
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1e6c9c28 | 1 | /* |
7192f92c | 2 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
3 | * Copyright (C) 2003 Rick Bronson |
4 | * | |
5 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
a6670615 CC |
8 | * DMA support added by Chip Coldwell. |
9 | * | |
1e6c9c28 AV |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
5fbe46b6 NF |
36 | #include <linux/of.h> |
37 | #include <linux/of_device.h> | |
a6670615 | 38 | #include <linux/dma-mapping.h> |
93a3ddc2 | 39 | #include <linux/atmel_pdc.h> |
fa3218d8 | 40 | #include <linux/atmel_serial.h> |
e8faff73 | 41 | #include <linux/uaccess.h> |
1e6c9c28 AV |
42 | |
43 | #include <asm/io.h> | |
f7512e7c | 44 | #include <asm/ioctls.h> |
1e6c9c28 | 45 | |
afefc415 | 46 | #include <asm/mach/serial_at91.h> |
a09e64fb | 47 | #include <mach/board.h> |
93a3ddc2 | 48 | |
acca9b83 | 49 | #ifdef CONFIG_ARM |
a09e64fb | 50 | #include <mach/cpu.h> |
60e8972d | 51 | #include <asm/gpio.h> |
acca9b83 | 52 | #endif |
1e6c9c28 | 53 | |
a6670615 CC |
54 | #define PDC_BUFFER_SIZE 512 |
55 | /* Revisit: We should calculate this based on the actual port settings */ | |
56 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
57 | ||
749c4e60 | 58 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
59 | #define SUPPORT_SYSRQ |
60 | #endif | |
61 | ||
62 | #include <linux/serial_core.h> | |
63 | ||
e8faff73 CS |
64 | static void atmel_start_rx(struct uart_port *port); |
65 | static void atmel_stop_rx(struct uart_port *port); | |
66 | ||
749c4e60 | 67 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
68 | |
69 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
70 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
71 | * UART. */ | |
7192f92c | 72 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 73 | #define MINOR_START 154 |
7192f92c | 74 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
75 | |
76 | #else | |
77 | ||
78 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
79 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 80 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 81 | #define MINOR_START 64 |
7192f92c | 82 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
83 | |
84 | #endif | |
85 | ||
7192f92c | 86 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 87 | |
b843aa21 | 88 | /* UART registers. CR is write-only, hence no GET macro */ |
544fc728 HS |
89 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
90 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
91 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
92 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
93 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
94 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
95 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
96 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
97 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
98 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
99 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
100 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
e8faff73 | 101 | #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) |
544fc728 | 102 | |
1e6c9c28 | 103 | /* PDC registers */ |
544fc728 HS |
104 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
105 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
106 | ||
107 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
108 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
109 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
110 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
111 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
112 | ||
113 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
114 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
39d4c922 | 115 | #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) |
1e6c9c28 | 116 | |
71f2e2b8 HS |
117 | static int (*atmel_open_hook)(struct uart_port *); |
118 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 119 | |
a6670615 CC |
120 | struct atmel_dma_buffer { |
121 | unsigned char *buf; | |
122 | dma_addr_t dma_addr; | |
123 | unsigned int dma_size; | |
124 | unsigned int ofs; | |
125 | }; | |
126 | ||
1ecc26bd RB |
127 | struct atmel_uart_char { |
128 | u16 status; | |
129 | u16 ch; | |
130 | }; | |
131 | ||
132 | #define ATMEL_SERIAL_RINGSIZE 1024 | |
133 | ||
afefc415 AV |
134 | /* |
135 | * We wrap our port structure around the generic uart_port. | |
136 | */ | |
7192f92c | 137 | struct atmel_uart_port { |
afefc415 AV |
138 | struct uart_port uart; /* uart */ |
139 | struct clk *clk; /* uart clock */ | |
f05596db AS |
140 | int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ |
141 | u32 backup_imr; /* IMR saved during suspend */ | |
9e6077bd | 142 | int break_active; /* break being received */ |
1ecc26bd | 143 | |
a6670615 CC |
144 | short use_dma_rx; /* enable PDC receiver */ |
145 | short pdc_rx_idx; /* current PDC RX buffer */ | |
146 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
147 | ||
148 | short use_dma_tx; /* enable PDC transmitter */ | |
149 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ | |
150 | ||
1ecc26bd RB |
151 | struct tasklet_struct tasklet; |
152 | unsigned int irq_status; | |
153 | unsigned int irq_status_prev; | |
154 | ||
155 | struct circ_buf rx_ring; | |
e8faff73 CS |
156 | |
157 | struct serial_rs485 rs485; /* rs485 settings */ | |
158 | unsigned int tx_done_mask; | |
afefc415 AV |
159 | }; |
160 | ||
7192f92c | 161 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
4cbf9f48 | 162 | static unsigned long atmel_ports_in_use; |
afefc415 | 163 | |
1e6c9c28 | 164 | #ifdef SUPPORT_SYSRQ |
7192f92c | 165 | static struct console atmel_console; |
1e6c9c28 AV |
166 | #endif |
167 | ||
5fbe46b6 NF |
168 | #if defined(CONFIG_OF) |
169 | static const struct of_device_id atmel_serial_dt_ids[] = { | |
170 | { .compatible = "atmel,at91rm9200-usart" }, | |
171 | { .compatible = "atmel,at91sam9260-usart" }, | |
172 | { /* sentinel */ } | |
173 | }; | |
174 | ||
175 | MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); | |
176 | #endif | |
177 | ||
c811ab8c HS |
178 | static inline struct atmel_uart_port * |
179 | to_atmel_uart_port(struct uart_port *uart) | |
180 | { | |
181 | return container_of(uart, struct atmel_uart_port, uart); | |
182 | } | |
183 | ||
a6670615 CC |
184 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
185 | static bool atmel_use_dma_rx(struct uart_port *port) | |
186 | { | |
c811ab8c | 187 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
188 | |
189 | return atmel_port->use_dma_rx; | |
190 | } | |
191 | ||
192 | static bool atmel_use_dma_tx(struct uart_port *port) | |
193 | { | |
c811ab8c | 194 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
195 | |
196 | return atmel_port->use_dma_tx; | |
197 | } | |
198 | #else | |
199 | static bool atmel_use_dma_rx(struct uart_port *port) | |
200 | { | |
201 | return false; | |
202 | } | |
203 | ||
204 | static bool atmel_use_dma_tx(struct uart_port *port) | |
205 | { | |
206 | return false; | |
207 | } | |
208 | #endif | |
209 | ||
e8faff73 CS |
210 | /* Enable or disable the rs485 support */ |
211 | void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) | |
212 | { | |
213 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
214 | unsigned int mode; | |
215 | ||
216 | spin_lock(&port->lock); | |
217 | ||
218 | /* Disable interrupts */ | |
219 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
220 | ||
221 | mode = UART_GET_MR(port); | |
222 | ||
223 | /* Resetting serial mode to RS232 (0x0) */ | |
224 | mode &= ~ATMEL_US_USMODE; | |
225 | ||
226 | atmel_port->rs485 = *rs485conf; | |
227 | ||
228 | if (rs485conf->flags & SER_RS485_ENABLED) { | |
229 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
230 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
1b633184 CS |
231 | if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) |
232 | UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); | |
e8faff73 CS |
233 | mode |= ATMEL_US_USMODE_RS485; |
234 | } else { | |
235 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
236 | if (atmel_use_dma_tx(port)) | |
237 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | | |
238 | ATMEL_US_TXBUFE; | |
239 | else | |
240 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
241 | } | |
242 | UART_PUT_MR(port, mode); | |
243 | ||
244 | /* Enable interrupts */ | |
245 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
246 | ||
247 | spin_unlock(&port->lock); | |
248 | ||
249 | } | |
250 | ||
1e6c9c28 AV |
251 | /* |
252 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
253 | */ | |
7192f92c | 254 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 255 | { |
7192f92c | 256 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
257 | } |
258 | ||
259 | /* | |
260 | * Set state of the modem control output lines | |
261 | */ | |
7192f92c | 262 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
263 | { |
264 | unsigned int control = 0; | |
afefc415 | 265 | unsigned int mode; |
e8faff73 | 266 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 267 | |
c2f5ccfb | 268 | #ifdef CONFIG_ARCH_AT91RM9200 |
79da7a61 | 269 | if (cpu_is_at91rm9200()) { |
afefc415 | 270 | /* |
b843aa21 RB |
271 | * AT91RM9200 Errata #39: RTS0 is not internally connected |
272 | * to PA21. We need to drive the pin manually. | |
afefc415 | 273 | */ |
72729910 | 274 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 275 | if (mctrl & TIOCM_RTS) |
20e65276 | 276 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 277 | else |
20e65276 | 278 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 279 | } |
1e6c9c28 | 280 | } |
acca9b83 | 281 | #endif |
1e6c9c28 AV |
282 | |
283 | if (mctrl & TIOCM_RTS) | |
7192f92c | 284 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 285 | else |
7192f92c | 286 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
287 | |
288 | if (mctrl & TIOCM_DTR) | |
7192f92c | 289 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 290 | else |
7192f92c | 291 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 292 | |
afefc415 AV |
293 | UART_PUT_CR(port, control); |
294 | ||
295 | /* Local loopback mode? */ | |
7192f92c | 296 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 297 | if (mctrl & TIOCM_LOOP) |
7192f92c | 298 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 299 | else |
7192f92c | 300 | mode |= ATMEL_US_CHMODE_NORMAL; |
e8faff73 CS |
301 | |
302 | /* Resetting serial mode to RS232 (0x0) */ | |
303 | mode &= ~ATMEL_US_USMODE; | |
304 | ||
305 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
306 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
1b633184 CS |
307 | if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND) |
308 | UART_PUT_TTGR(port, | |
309 | atmel_port->rs485.delay_rts_after_send); | |
e8faff73 CS |
310 | mode |= ATMEL_US_USMODE_RS485; |
311 | } else { | |
312 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
313 | } | |
afefc415 | 314 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
315 | } |
316 | ||
317 | /* | |
318 | * Get state of the modem control input lines | |
319 | */ | |
7192f92c | 320 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
321 | { |
322 | unsigned int status, ret = 0; | |
323 | ||
324 | status = UART_GET_CSR(port); | |
325 | ||
326 | /* | |
327 | * The control signals are active low. | |
328 | */ | |
7192f92c | 329 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 330 | ret |= TIOCM_CD; |
7192f92c | 331 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 332 | ret |= TIOCM_CTS; |
7192f92c | 333 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 334 | ret |= TIOCM_DSR; |
7192f92c | 335 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
336 | ret |= TIOCM_RI; |
337 | ||
338 | return ret; | |
339 | } | |
340 | ||
341 | /* | |
342 | * Stop transmitting. | |
343 | */ | |
7192f92c | 344 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 345 | { |
e8faff73 CS |
346 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
347 | ||
a6670615 CC |
348 | if (atmel_use_dma_tx(port)) { |
349 | /* disable PDC transmit */ | |
350 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
e8faff73 CS |
351 | } |
352 | /* Disable interrupts */ | |
353 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
354 | ||
83cac9f3 BR |
355 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
356 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 | 357 | atmel_start_rx(port); |
1e6c9c28 AV |
358 | } |
359 | ||
360 | /* | |
361 | * Start transmitting. | |
362 | */ | |
7192f92c | 363 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 364 | { |
e8faff73 CS |
365 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
366 | ||
a6670615 CC |
367 | if (atmel_use_dma_tx(port)) { |
368 | if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) | |
369 | /* The transmitter is already running. Yes, we | |
370 | really need this.*/ | |
371 | return; | |
372 | ||
83cac9f3 BR |
373 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
374 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 CS |
375 | atmel_stop_rx(port); |
376 | ||
a6670615 CC |
377 | /* re-enable PDC transmit */ |
378 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
e8faff73 CS |
379 | } |
380 | /* Enable interrupts */ | |
381 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
382 | } | |
383 | ||
384 | /* | |
385 | * start receiving - port is in process of being opened. | |
386 | */ | |
387 | static void atmel_start_rx(struct uart_port *port) | |
388 | { | |
389 | UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ | |
390 | ||
391 | if (atmel_use_dma_rx(port)) { | |
392 | /* enable PDC controller */ | |
393 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
394 | port->read_status_mask); | |
395 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
396 | } else { | |
397 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
398 | } | |
1e6c9c28 AV |
399 | } |
400 | ||
401 | /* | |
402 | * Stop receiving - port is in process of being closed. | |
403 | */ | |
7192f92c | 404 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 405 | { |
a6670615 CC |
406 | if (atmel_use_dma_rx(port)) { |
407 | /* disable PDC receive */ | |
408 | UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); | |
e8faff73 CS |
409 | UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | |
410 | port->read_status_mask); | |
411 | } else { | |
a6670615 | 412 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
e8faff73 | 413 | } |
1e6c9c28 AV |
414 | } |
415 | ||
416 | /* | |
417 | * Enable modem status interrupts | |
418 | */ | |
7192f92c | 419 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 420 | { |
b843aa21 RB |
421 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC |
422 | | ATMEL_US_DCDIC | ATMEL_US_CTSIC); | |
1e6c9c28 AV |
423 | } |
424 | ||
425 | /* | |
426 | * Control the transmission of a break signal | |
427 | */ | |
7192f92c | 428 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
429 | { |
430 | if (break_state != 0) | |
7192f92c | 431 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 432 | else |
7192f92c | 433 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
434 | } |
435 | ||
1ecc26bd RB |
436 | /* |
437 | * Stores the incoming character in the ring buffer | |
438 | */ | |
439 | static void | |
440 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
441 | unsigned int ch) | |
442 | { | |
c811ab8c | 443 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
444 | struct circ_buf *ring = &atmel_port->rx_ring; |
445 | struct atmel_uart_char *c; | |
446 | ||
447 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
448 | /* Buffer overflow, ignore char */ | |
449 | return; | |
450 | ||
451 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
452 | c->status = status; | |
453 | c->ch = ch; | |
454 | ||
455 | /* Make sure the character is stored before we update head. */ | |
456 | smp_wmb(); | |
457 | ||
458 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
459 | } | |
460 | ||
a6670615 CC |
461 | /* |
462 | * Deal with parity, framing and overrun errors. | |
463 | */ | |
464 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
465 | { | |
466 | /* clear error */ | |
467 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
468 | ||
469 | if (status & ATMEL_US_RXBRK) { | |
470 | /* ignore side-effect */ | |
471 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
472 | port->icount.brk++; | |
473 | } | |
474 | if (status & ATMEL_US_PARE) | |
475 | port->icount.parity++; | |
476 | if (status & ATMEL_US_FRAME) | |
477 | port->icount.frame++; | |
478 | if (status & ATMEL_US_OVRE) | |
479 | port->icount.overrun++; | |
480 | } | |
481 | ||
1e6c9c28 AV |
482 | /* |
483 | * Characters received (called from interrupt handler) | |
484 | */ | |
7d12e780 | 485 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 486 | { |
c811ab8c | 487 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 488 | unsigned int status, ch; |
1e6c9c28 | 489 | |
afefc415 | 490 | status = UART_GET_CSR(port); |
7192f92c | 491 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
492 | ch = UART_GET_CHAR(port); |
493 | ||
1e6c9c28 AV |
494 | /* |
495 | * note that the error handling code is | |
496 | * out of the main execution path | |
497 | */ | |
9e6077bd HS |
498 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
499 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
500 | || atmel_port->break_active)) { | |
1ecc26bd | 501 | |
b843aa21 RB |
502 | /* clear error */ |
503 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1ecc26bd | 504 | |
9e6077bd HS |
505 | if (status & ATMEL_US_RXBRK |
506 | && !atmel_port->break_active) { | |
9e6077bd HS |
507 | atmel_port->break_active = 1; |
508 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
9e6077bd HS |
509 | } else { |
510 | /* | |
511 | * This is either the end-of-break | |
512 | * condition or we've received at | |
513 | * least one character without RXBRK | |
514 | * being set. In both cases, the next | |
515 | * RXBRK will indicate start-of-break. | |
516 | */ | |
517 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
518 | status &= ~ATMEL_US_RXBRK; | |
519 | atmel_port->break_active = 0; | |
afefc415 | 520 | } |
1e6c9c28 AV |
521 | } |
522 | ||
1ecc26bd | 523 | atmel_buffer_rx_char(port, status, ch); |
afefc415 | 524 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
525 | } |
526 | ||
1ecc26bd | 527 | tasklet_schedule(&atmel_port->tasklet); |
1e6c9c28 AV |
528 | } |
529 | ||
530 | /* | |
1ecc26bd RB |
531 | * Transmit characters (called from tasklet with TXRDY interrupt |
532 | * disabled) | |
1e6c9c28 | 533 | */ |
7192f92c | 534 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 | 535 | { |
ebd2c8f6 | 536 | struct circ_buf *xmit = &port->state->xmit; |
e8faff73 | 537 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 538 | |
e8faff73 | 539 | if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
540 | UART_PUT_CHAR(port, port->x_char); |
541 | port->icount.tx++; | |
542 | port->x_char = 0; | |
1e6c9c28 | 543 | } |
1ecc26bd | 544 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 545 | return; |
1e6c9c28 | 546 | |
e8faff73 | 547 | while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
548 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
549 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
550 | port->icount.tx++; | |
551 | if (uart_circ_empty(xmit)) | |
552 | break; | |
553 | } | |
554 | ||
555 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
556 | uart_write_wakeup(port); | |
557 | ||
1ecc26bd | 558 | if (!uart_circ_empty(xmit)) |
e8faff73 CS |
559 | /* Enable interrupts */ |
560 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
1e6c9c28 AV |
561 | } |
562 | ||
b843aa21 RB |
563 | /* |
564 | * receive interrupt handler. | |
565 | */ | |
566 | static void | |
567 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
568 | { | |
c811ab8c | 569 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 570 | |
a6670615 CC |
571 | if (atmel_use_dma_rx(port)) { |
572 | /* | |
573 | * PDC receive. Just schedule the tasklet and let it | |
574 | * figure out the details. | |
575 | * | |
576 | * TODO: We're not handling error flags correctly at | |
577 | * the moment. | |
578 | */ | |
579 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
580 | UART_PUT_IDR(port, (ATMEL_US_ENDRX | |
581 | | ATMEL_US_TIMEOUT)); | |
582 | tasklet_schedule(&atmel_port->tasklet); | |
583 | } | |
584 | ||
585 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
586 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
587 | atmel_pdc_rxerr(port, pending); | |
588 | } | |
589 | ||
b843aa21 RB |
590 | /* Interrupt receive */ |
591 | if (pending & ATMEL_US_RXRDY) | |
592 | atmel_rx_chars(port); | |
593 | else if (pending & ATMEL_US_RXBRK) { | |
594 | /* | |
595 | * End of break detected. If it came along with a | |
596 | * character, atmel_rx_chars will handle it. | |
597 | */ | |
598 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
599 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
600 | atmel_port->break_active = 0; | |
601 | } | |
602 | } | |
603 | ||
604 | /* | |
1ecc26bd | 605 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
606 | */ |
607 | static void | |
608 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
609 | { | |
c811ab8c | 610 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 611 | |
e8faff73 CS |
612 | if (pending & atmel_port->tx_done_mask) { |
613 | /* Either PDC or interrupt transmission */ | |
614 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
615 | tasklet_schedule(&atmel_port->tasklet); | |
1ecc26bd | 616 | } |
b843aa21 RB |
617 | } |
618 | ||
619 | /* | |
620 | * status flags interrupt handler. | |
621 | */ | |
622 | static void | |
623 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
624 | unsigned int status) | |
625 | { | |
c811ab8c | 626 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 627 | |
b843aa21 | 628 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd RB |
629 | | ATMEL_US_CTSIC)) { |
630 | atmel_port->irq_status = status; | |
631 | tasklet_schedule(&atmel_port->tasklet); | |
632 | } | |
b843aa21 RB |
633 | } |
634 | ||
1e6c9c28 AV |
635 | /* |
636 | * Interrupt handler | |
637 | */ | |
7d12e780 | 638 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
639 | { |
640 | struct uart_port *port = dev_id; | |
641 | unsigned int status, pending, pass_counter = 0; | |
642 | ||
a6670615 CC |
643 | do { |
644 | status = UART_GET_CSR(port); | |
645 | pending = status & UART_GET_IMR(port); | |
646 | if (!pending) | |
647 | break; | |
648 | ||
b843aa21 RB |
649 | atmel_handle_receive(port, pending); |
650 | atmel_handle_status(port, pending, status); | |
651 | atmel_handle_transmit(port, pending); | |
a6670615 | 652 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 653 | |
0400b697 | 654 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 655 | } |
1e6c9c28 | 656 | |
a6670615 CC |
657 | /* |
658 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
659 | */ | |
660 | static void atmel_tx_dma(struct uart_port *port) | |
661 | { | |
c811ab8c | 662 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 663 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
664 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; |
665 | int count; | |
666 | ||
ba0657ff MT |
667 | /* nothing left to transmit? */ |
668 | if (UART_GET_TCR(port)) | |
669 | return; | |
670 | ||
a6670615 CC |
671 | xmit->tail += pdc->ofs; |
672 | xmit->tail &= UART_XMIT_SIZE - 1; | |
673 | ||
674 | port->icount.tx += pdc->ofs; | |
675 | pdc->ofs = 0; | |
676 | ||
ba0657ff | 677 | /* more to transmit - setup next transfer */ |
a6670615 | 678 | |
ba0657ff MT |
679 | /* disable PDC transmit */ |
680 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
681 | ||
1f14081d | 682 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { |
a6670615 CC |
683 | dma_sync_single_for_device(port->dev, |
684 | pdc->dma_addr, | |
685 | pdc->dma_size, | |
686 | DMA_TO_DEVICE); | |
687 | ||
688 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
689 | pdc->ofs = count; | |
690 | ||
691 | UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); | |
692 | UART_PUT_TCR(port, count); | |
e8faff73 | 693 | /* re-enable PDC transmit */ |
a6670615 | 694 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); |
e8faff73 CS |
695 | /* Enable interrupts */ |
696 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
697 | } else { | |
83cac9f3 BR |
698 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
699 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
e8faff73 CS |
700 | /* DMA done, stop TX, start RX for RS485 */ |
701 | atmel_start_rx(port); | |
702 | } | |
1e6c9c28 | 703 | } |
a6670615 CC |
704 | |
705 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
706 | uart_write_wakeup(port); | |
1e6c9c28 AV |
707 | } |
708 | ||
1ecc26bd RB |
709 | static void atmel_rx_from_ring(struct uart_port *port) |
710 | { | |
c811ab8c | 711 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
712 | struct circ_buf *ring = &atmel_port->rx_ring; |
713 | unsigned int flg; | |
714 | unsigned int status; | |
715 | ||
716 | while (ring->head != ring->tail) { | |
717 | struct atmel_uart_char c; | |
718 | ||
719 | /* Make sure c is loaded after head. */ | |
720 | smp_rmb(); | |
721 | ||
722 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
723 | ||
724 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
725 | ||
726 | port->icount.rx++; | |
727 | status = c.status; | |
728 | flg = TTY_NORMAL; | |
729 | ||
730 | /* | |
731 | * note that the error handling code is | |
732 | * out of the main execution path | |
733 | */ | |
734 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
735 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
736 | if (status & ATMEL_US_RXBRK) { | |
737 | /* ignore side-effect */ | |
738 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
739 | ||
740 | port->icount.brk++; | |
741 | if (uart_handle_break(port)) | |
742 | continue; | |
743 | } | |
744 | if (status & ATMEL_US_PARE) | |
745 | port->icount.parity++; | |
746 | if (status & ATMEL_US_FRAME) | |
747 | port->icount.frame++; | |
748 | if (status & ATMEL_US_OVRE) | |
749 | port->icount.overrun++; | |
750 | ||
751 | status &= port->read_status_mask; | |
752 | ||
753 | if (status & ATMEL_US_RXBRK) | |
754 | flg = TTY_BREAK; | |
755 | else if (status & ATMEL_US_PARE) | |
756 | flg = TTY_PARITY; | |
757 | else if (status & ATMEL_US_FRAME) | |
758 | flg = TTY_FRAME; | |
759 | } | |
760 | ||
761 | ||
762 | if (uart_handle_sysrq_char(port, c.ch)) | |
763 | continue; | |
764 | ||
765 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
766 | } | |
767 | ||
768 | /* | |
769 | * Drop the lock here since it might end up calling | |
770 | * uart_start(), which takes the lock. | |
771 | */ | |
772 | spin_unlock(&port->lock); | |
ebd2c8f6 | 773 | tty_flip_buffer_push(port->state->port.tty); |
1ecc26bd RB |
774 | spin_lock(&port->lock); |
775 | } | |
776 | ||
a6670615 CC |
777 | static void atmel_rx_from_dma(struct uart_port *port) |
778 | { | |
c811ab8c | 779 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 780 | struct tty_struct *tty = port->state->port.tty; |
a6670615 CC |
781 | struct atmel_dma_buffer *pdc; |
782 | int rx_idx = atmel_port->pdc_rx_idx; | |
783 | unsigned int head; | |
784 | unsigned int tail; | |
785 | unsigned int count; | |
786 | ||
787 | do { | |
788 | /* Reset the UART timeout early so that we don't miss one */ | |
789 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
790 | ||
791 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
792 | head = UART_GET_RPR(port) - pdc->dma_addr; | |
793 | tail = pdc->ofs; | |
794 | ||
795 | /* If the PDC has switched buffers, RPR won't contain | |
796 | * any address within the current buffer. Since head | |
797 | * is unsigned, we just need a one-way comparison to | |
798 | * find out. | |
799 | * | |
800 | * In this case, we just need to consume the entire | |
801 | * buffer and resubmit it for DMA. This will clear the | |
802 | * ENDRX bit as well, so that we can safely re-enable | |
803 | * all interrupts below. | |
804 | */ | |
805 | head = min(head, pdc->dma_size); | |
806 | ||
807 | if (likely(head != tail)) { | |
808 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
809 | pdc->dma_size, DMA_FROM_DEVICE); | |
810 | ||
811 | /* | |
812 | * head will only wrap around when we recycle | |
813 | * the DMA buffer, and when that happens, we | |
814 | * explicitly set tail to 0. So head will | |
815 | * always be greater than tail. | |
816 | */ | |
817 | count = head - tail; | |
818 | ||
819 | tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); | |
820 | ||
821 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
822 | pdc->dma_size, DMA_FROM_DEVICE); | |
823 | ||
824 | port->icount.rx += count; | |
825 | pdc->ofs = head; | |
826 | } | |
827 | ||
828 | /* | |
829 | * If the current buffer is full, we need to check if | |
830 | * the next one contains any additional data. | |
831 | */ | |
832 | if (head >= pdc->dma_size) { | |
833 | pdc->ofs = 0; | |
834 | UART_PUT_RNPR(port, pdc->dma_addr); | |
835 | UART_PUT_RNCR(port, pdc->dma_size); | |
836 | ||
837 | rx_idx = !rx_idx; | |
838 | atmel_port->pdc_rx_idx = rx_idx; | |
839 | } | |
840 | } while (head >= pdc->dma_size); | |
841 | ||
842 | /* | |
843 | * Drop the lock here since it might end up calling | |
844 | * uart_start(), which takes the lock. | |
845 | */ | |
846 | spin_unlock(&port->lock); | |
847 | tty_flip_buffer_push(tty); | |
848 | spin_lock(&port->lock); | |
849 | ||
850 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
851 | } | |
852 | ||
1ecc26bd RB |
853 | /* |
854 | * tasklet handling tty stuff outside the interrupt handler. | |
855 | */ | |
856 | static void atmel_tasklet_func(unsigned long data) | |
857 | { | |
858 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 859 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
860 | unsigned int status; |
861 | unsigned int status_change; | |
862 | ||
863 | /* The interrupt handler does not take the lock */ | |
864 | spin_lock(&port->lock); | |
865 | ||
a6670615 CC |
866 | if (atmel_use_dma_tx(port)) |
867 | atmel_tx_dma(port); | |
868 | else | |
869 | atmel_tx_chars(port); | |
1ecc26bd RB |
870 | |
871 | status = atmel_port->irq_status; | |
872 | status_change = status ^ atmel_port->irq_status_prev; | |
873 | ||
874 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR | |
875 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
876 | /* TODO: All reads to CSR will clear these interrupts! */ | |
877 | if (status_change & ATMEL_US_RI) | |
878 | port->icount.rng++; | |
879 | if (status_change & ATMEL_US_DSR) | |
880 | port->icount.dsr++; | |
881 | if (status_change & ATMEL_US_DCD) | |
882 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
883 | if (status_change & ATMEL_US_CTS) | |
884 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
885 | ||
bdc04e31 | 886 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
1ecc26bd RB |
887 | |
888 | atmel_port->irq_status_prev = status; | |
889 | } | |
890 | ||
a6670615 CC |
891 | if (atmel_use_dma_rx(port)) |
892 | atmel_rx_from_dma(port); | |
893 | else | |
894 | atmel_rx_from_ring(port); | |
1ecc26bd RB |
895 | |
896 | spin_unlock(&port->lock); | |
897 | } | |
898 | ||
1e6c9c28 AV |
899 | /* |
900 | * Perform initialization and enable port for reception | |
901 | */ | |
7192f92c | 902 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 903 | { |
c811ab8c | 904 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 905 | struct tty_struct *tty = port->state->port.tty; |
1e6c9c28 AV |
906 | int retval; |
907 | ||
908 | /* | |
909 | * Ensure that no interrupts are enabled otherwise when | |
910 | * request_irq() is called we could get stuck trying to | |
911 | * handle an unexpected interrupt | |
912 | */ | |
913 | UART_PUT_IDR(port, -1); | |
914 | ||
915 | /* | |
916 | * Allocate the IRQ | |
917 | */ | |
b843aa21 | 918 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, |
ae161068 | 919 | tty ? tty->name : "atmel_serial", port); |
1e6c9c28 | 920 | if (retval) { |
7192f92c | 921 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
922 | return retval; |
923 | } | |
924 | ||
a6670615 CC |
925 | /* |
926 | * Initialize DMA (if necessary) | |
927 | */ | |
928 | if (atmel_use_dma_rx(port)) { | |
929 | int i; | |
930 | ||
931 | for (i = 0; i < 2; i++) { | |
932 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
933 | ||
934 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
935 | if (pdc->buf == NULL) { | |
936 | if (i != 0) { | |
937 | dma_unmap_single(port->dev, | |
938 | atmel_port->pdc_rx[0].dma_addr, | |
939 | PDC_BUFFER_SIZE, | |
940 | DMA_FROM_DEVICE); | |
941 | kfree(atmel_port->pdc_rx[0].buf); | |
942 | } | |
943 | free_irq(port->irq, port); | |
944 | return -ENOMEM; | |
945 | } | |
946 | pdc->dma_addr = dma_map_single(port->dev, | |
947 | pdc->buf, | |
948 | PDC_BUFFER_SIZE, | |
949 | DMA_FROM_DEVICE); | |
950 | pdc->dma_size = PDC_BUFFER_SIZE; | |
951 | pdc->ofs = 0; | |
952 | } | |
953 | ||
954 | atmel_port->pdc_rx_idx = 0; | |
955 | ||
956 | UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); | |
957 | UART_PUT_RCR(port, PDC_BUFFER_SIZE); | |
958 | ||
959 | UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); | |
960 | UART_PUT_RNCR(port, PDC_BUFFER_SIZE); | |
961 | } | |
962 | if (atmel_use_dma_tx(port)) { | |
963 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
ebd2c8f6 | 964 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
965 | |
966 | pdc->buf = xmit->buf; | |
967 | pdc->dma_addr = dma_map_single(port->dev, | |
968 | pdc->buf, | |
969 | UART_XMIT_SIZE, | |
970 | DMA_TO_DEVICE); | |
971 | pdc->dma_size = UART_XMIT_SIZE; | |
972 | pdc->ofs = 0; | |
973 | } | |
974 | ||
1e6c9c28 AV |
975 | /* |
976 | * If there is a specific "open" function (to register | |
977 | * control line interrupts) | |
978 | */ | |
71f2e2b8 HS |
979 | if (atmel_open_hook) { |
980 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
981 | if (retval) { |
982 | free_irq(port->irq, port); | |
983 | return retval; | |
984 | } | |
985 | } | |
986 | ||
27c0c8e5 AN |
987 | /* Save current CSR for comparison in atmel_tasklet_func() */ |
988 | atmel_port->irq_status_prev = UART_GET_CSR(port); | |
989 | atmel_port->irq_status = atmel_port->irq_status_prev; | |
990 | ||
1e6c9c28 AV |
991 | /* |
992 | * Finally, enable the serial port | |
993 | */ | |
7192f92c | 994 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 RB |
995 | /* enable xmit & rcvr */ |
996 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
afefc415 | 997 | |
a6670615 CC |
998 | if (atmel_use_dma_rx(port)) { |
999 | /* set UART timeout */ | |
1000 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
1001 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
1002 | ||
1003 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
1004 | /* enable PDC controller */ | |
1005 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
1006 | } else { | |
1007 | /* enable receive only */ | |
1008 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
1009 | } | |
afefc415 | 1010 | |
1e6c9c28 AV |
1011 | return 0; |
1012 | } | |
1013 | ||
1014 | /* | |
1015 | * Disable the port | |
1016 | */ | |
7192f92c | 1017 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 1018 | { |
c811ab8c | 1019 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
1020 | /* |
1021 | * Ensure everything is stopped. | |
1022 | */ | |
1023 | atmel_stop_rx(port); | |
1024 | atmel_stop_tx(port); | |
1025 | ||
1026 | /* | |
1027 | * Shut-down the DMA. | |
1028 | */ | |
1029 | if (atmel_use_dma_rx(port)) { | |
1030 | int i; | |
1031 | ||
1032 | for (i = 0; i < 2; i++) { | |
1033 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1034 | ||
1035 | dma_unmap_single(port->dev, | |
1036 | pdc->dma_addr, | |
1037 | pdc->dma_size, | |
1038 | DMA_FROM_DEVICE); | |
1039 | kfree(pdc->buf); | |
1040 | } | |
1041 | } | |
1042 | if (atmel_use_dma_tx(port)) { | |
1043 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1044 | ||
1045 | dma_unmap_single(port->dev, | |
1046 | pdc->dma_addr, | |
1047 | pdc->dma_size, | |
1048 | DMA_TO_DEVICE); | |
1049 | } | |
1050 | ||
1e6c9c28 AV |
1051 | /* |
1052 | * Disable all interrupts, port and break condition. | |
1053 | */ | |
7192f92c | 1054 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
1055 | UART_PUT_IDR(port, -1); |
1056 | ||
1057 | /* | |
1058 | * Free the interrupt | |
1059 | */ | |
1060 | free_irq(port->irq, port); | |
1061 | ||
1062 | /* | |
1063 | * If there is a specific "close" function (to unregister | |
1064 | * control line interrupts) | |
1065 | */ | |
71f2e2b8 HS |
1066 | if (atmel_close_hook) |
1067 | atmel_close_hook(port); | |
1e6c9c28 AV |
1068 | } |
1069 | ||
9afd561a HS |
1070 | /* |
1071 | * Flush any TX data submitted for DMA. Called when the TX circular | |
1072 | * buffer is reset. | |
1073 | */ | |
1074 | static void atmel_flush_buffer(struct uart_port *port) | |
1075 | { | |
1076 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1077 | ||
1078 | if (atmel_use_dma_tx(port)) { | |
1079 | UART_PUT_TCR(port, 0); | |
1080 | atmel_port->pdc_tx.ofs = 0; | |
1081 | } | |
1082 | } | |
1083 | ||
1e6c9c28 AV |
1084 | /* |
1085 | * Power / Clock management. | |
1086 | */ | |
b843aa21 RB |
1087 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
1088 | unsigned int oldstate) | |
1e6c9c28 | 1089 | { |
c811ab8c | 1090 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1091 | |
1e6c9c28 | 1092 | switch (state) { |
b843aa21 RB |
1093 | case 0: |
1094 | /* | |
1095 | * Enable the peripheral clock for this serial port. | |
1096 | * This is called on uart_open() or a resume event. | |
1097 | */ | |
1098 | clk_enable(atmel_port->clk); | |
f05596db AS |
1099 | |
1100 | /* re-enable interrupts if we disabled some on suspend */ | |
1101 | UART_PUT_IER(port, atmel_port->backup_imr); | |
b843aa21 RB |
1102 | break; |
1103 | case 3: | |
f05596db AS |
1104 | /* Back up the interrupt mask and disable all interrupts */ |
1105 | atmel_port->backup_imr = UART_GET_IMR(port); | |
1106 | UART_PUT_IDR(port, -1); | |
1107 | ||
b843aa21 RB |
1108 | /* |
1109 | * Disable the peripheral clock for this serial port. | |
1110 | * This is called on uart_close() or a suspend event. | |
1111 | */ | |
1112 | clk_disable(atmel_port->clk); | |
1113 | break; | |
1114 | default: | |
1115 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); | |
1e6c9c28 AV |
1116 | } |
1117 | } | |
1118 | ||
1119 | /* | |
1120 | * Change the port parameters | |
1121 | */ | |
b843aa21 RB |
1122 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
1123 | struct ktermios *old) | |
1e6c9c28 AV |
1124 | { |
1125 | unsigned long flags; | |
1126 | unsigned int mode, imr, quot, baud; | |
e8faff73 | 1127 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1128 | |
03abeac0 | 1129 | /* Get current mode register */ |
b843aa21 | 1130 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL |
8e706c4d PM |
1131 | | ATMEL_US_NBSTOP | ATMEL_US_PAR |
1132 | | ATMEL_US_USMODE); | |
03abeac0 | 1133 | |
b843aa21 | 1134 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
1135 | quot = uart_get_divisor(port, baud); |
1136 | ||
b843aa21 | 1137 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
1138 | quot /= 8; |
1139 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
1140 | } | |
1e6c9c28 AV |
1141 | |
1142 | /* byte size */ | |
1143 | switch (termios->c_cflag & CSIZE) { | |
1144 | case CS5: | |
7192f92c | 1145 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
1146 | break; |
1147 | case CS6: | |
7192f92c | 1148 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
1149 | break; |
1150 | case CS7: | |
7192f92c | 1151 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
1152 | break; |
1153 | default: | |
7192f92c | 1154 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
1155 | break; |
1156 | } | |
1157 | ||
1158 | /* stop bits */ | |
1159 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 1160 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
1161 | |
1162 | /* parity */ | |
1163 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
1164 | /* Mark or Space parity */ |
1165 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 1166 | if (termios->c_cflag & PARODD) |
7192f92c | 1167 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 1168 | else |
7192f92c | 1169 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 1170 | } else if (termios->c_cflag & PARODD) |
7192f92c | 1171 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 1172 | else |
7192f92c | 1173 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 1174 | } else |
7192f92c | 1175 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 | 1176 | |
8e706c4d PM |
1177 | /* hardware handshake (RTS/CTS) */ |
1178 | if (termios->c_cflag & CRTSCTS) | |
1179 | mode |= ATMEL_US_USMODE_HWHS; | |
1180 | else | |
1181 | mode |= ATMEL_US_USMODE_NORMAL; | |
1182 | ||
1e6c9c28 AV |
1183 | spin_lock_irqsave(&port->lock, flags); |
1184 | ||
7192f92c | 1185 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 1186 | if (termios->c_iflag & INPCK) |
7192f92c | 1187 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1188 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 1189 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 1190 | |
a6670615 CC |
1191 | if (atmel_use_dma_rx(port)) |
1192 | /* need to enable error interrupts */ | |
1193 | UART_PUT_IER(port, port->read_status_mask); | |
1194 | ||
1e6c9c28 AV |
1195 | /* |
1196 | * Characters to ignore | |
1197 | */ | |
1198 | port->ignore_status_mask = 0; | |
1199 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1200 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1201 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 1202 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
1203 | /* |
1204 | * If we're ignoring parity and break indicators, | |
1205 | * ignore overruns too (for real raw support). | |
1206 | */ | |
1207 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1208 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 1209 | } |
b843aa21 | 1210 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
1211 | |
1212 | /* update the per-port timeout */ | |
1213 | uart_update_timeout(port, termios->c_cflag, baud); | |
1214 | ||
0ccad870 HS |
1215 | /* |
1216 | * save/disable interrupts. The tty layer will ensure that the | |
1217 | * transmitter is empty if requested by the caller, so there's | |
1218 | * no need to wait for it here. | |
1219 | */ | |
b843aa21 RB |
1220 | imr = UART_GET_IMR(port); |
1221 | UART_PUT_IDR(port, -1); | |
1e6c9c28 AV |
1222 | |
1223 | /* disable receiver and transmitter */ | |
7192f92c | 1224 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 | 1225 | |
e8faff73 CS |
1226 | /* Resetting serial mode to RS232 (0x0) */ |
1227 | mode &= ~ATMEL_US_USMODE; | |
1228 | ||
1229 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
1230 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
1b633184 CS |
1231 | if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND) |
1232 | UART_PUT_TTGR(port, | |
1233 | atmel_port->rs485.delay_rts_after_send); | |
e8faff73 CS |
1234 | mode |= ATMEL_US_USMODE_RS485; |
1235 | } else { | |
1236 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
1237 | } | |
1238 | ||
1e6c9c28 AV |
1239 | /* set the parity, stop bits and data size */ |
1240 | UART_PUT_MR(port, mode); | |
1241 | ||
1242 | /* set the baud rate */ | |
1243 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
1244 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1245 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1246 | |
1247 | /* restore interrupts */ | |
1248 | UART_PUT_IER(port, imr); | |
1249 | ||
1250 | /* CTS flow-control and modem-status interrupts */ | |
1251 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1252 | port->ops->enable_ms(port); | |
1253 | ||
1254 | spin_unlock_irqrestore(&port->lock, flags); | |
1255 | } | |
1256 | ||
42bd7a4f VP |
1257 | static void atmel_set_ldisc(struct uart_port *port, int new) |
1258 | { | |
1259 | int line = port->line; | |
1260 | ||
1261 | if (line >= port->state->port.tty->driver->num) | |
1262 | return; | |
1263 | ||
1264 | if (port->state->port.tty->ldisc->ops->num == N_PPS) { | |
1265 | port->flags |= UPF_HARDPPS_CD; | |
1266 | atmel_enable_ms(port); | |
1267 | } else { | |
1268 | port->flags &= ~UPF_HARDPPS_CD; | |
1269 | } | |
1270 | } | |
1271 | ||
1e6c9c28 AV |
1272 | /* |
1273 | * Return string describing the specified port | |
1274 | */ | |
7192f92c | 1275 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 1276 | { |
9ab4f88b | 1277 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
1278 | } |
1279 | ||
1280 | /* | |
1281 | * Release the memory region(s) being used by 'port'. | |
1282 | */ | |
7192f92c | 1283 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 1284 | { |
afefc415 AV |
1285 | struct platform_device *pdev = to_platform_device(port->dev); |
1286 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1287 | ||
1288 | release_mem_region(port->mapbase, size); | |
1289 | ||
1290 | if (port->flags & UPF_IOREMAP) { | |
1291 | iounmap(port->membase); | |
1292 | port->membase = NULL; | |
1293 | } | |
1e6c9c28 AV |
1294 | } |
1295 | ||
1296 | /* | |
1297 | * Request the memory region(s) being used by 'port'. | |
1298 | */ | |
7192f92c | 1299 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 1300 | { |
afefc415 AV |
1301 | struct platform_device *pdev = to_platform_device(port->dev); |
1302 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1303 | ||
7192f92c | 1304 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
1305 | return -EBUSY; |
1306 | ||
1307 | if (port->flags & UPF_IOREMAP) { | |
1308 | port->membase = ioremap(port->mapbase, size); | |
1309 | if (port->membase == NULL) { | |
1310 | release_mem_region(port->mapbase, size); | |
1311 | return -ENOMEM; | |
1312 | } | |
1313 | } | |
1e6c9c28 | 1314 | |
afefc415 | 1315 | return 0; |
1e6c9c28 AV |
1316 | } |
1317 | ||
1318 | /* | |
1319 | * Configure/autoconfigure the port. | |
1320 | */ | |
7192f92c | 1321 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
1322 | { |
1323 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 1324 | port->type = PORT_ATMEL; |
7192f92c | 1325 | atmel_request_port(port); |
1e6c9c28 AV |
1326 | } |
1327 | } | |
1328 | ||
1329 | /* | |
1330 | * Verify the new serial_struct (for TIOCSSERIAL). | |
1331 | */ | |
7192f92c | 1332 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
1333 | { |
1334 | int ret = 0; | |
9ab4f88b | 1335 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
1336 | ret = -EINVAL; |
1337 | if (port->irq != ser->irq) | |
1338 | ret = -EINVAL; | |
1339 | if (ser->io_type != SERIAL_IO_MEM) | |
1340 | ret = -EINVAL; | |
1341 | if (port->uartclk / 16 != ser->baud_base) | |
1342 | ret = -EINVAL; | |
1343 | if ((void *)port->mapbase != ser->iomem_base) | |
1344 | ret = -EINVAL; | |
1345 | if (port->iobase != ser->port) | |
1346 | ret = -EINVAL; | |
1347 | if (ser->hub6 != 0) | |
1348 | ret = -EINVAL; | |
1349 | return ret; | |
1350 | } | |
1351 | ||
8fe2d541 AT |
1352 | #ifdef CONFIG_CONSOLE_POLL |
1353 | static int atmel_poll_get_char(struct uart_port *port) | |
1354 | { | |
1355 | while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) | |
1356 | cpu_relax(); | |
1357 | ||
1358 | return UART_GET_CHAR(port); | |
1359 | } | |
1360 | ||
1361 | static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) | |
1362 | { | |
1363 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) | |
1364 | cpu_relax(); | |
1365 | ||
1366 | UART_PUT_CHAR(port, ch); | |
1367 | } | |
1368 | #endif | |
1369 | ||
e8faff73 CS |
1370 | static int |
1371 | atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) | |
1372 | { | |
1373 | struct serial_rs485 rs485conf; | |
1374 | ||
1375 | switch (cmd) { | |
1376 | case TIOCSRS485: | |
1377 | if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, | |
1378 | sizeof(rs485conf))) | |
1379 | return -EFAULT; | |
1380 | ||
1381 | atmel_config_rs485(port, &rs485conf); | |
1382 | break; | |
1383 | ||
1384 | case TIOCGRS485: | |
1385 | if (copy_to_user((struct serial_rs485 *) arg, | |
1386 | &(to_atmel_uart_port(port)->rs485), | |
1387 | sizeof(rs485conf))) | |
1388 | return -EFAULT; | |
1389 | break; | |
1390 | ||
1391 | default: | |
1392 | return -ENOIOCTLCMD; | |
1393 | } | |
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | ||
1398 | ||
7192f92c HS |
1399 | static struct uart_ops atmel_pops = { |
1400 | .tx_empty = atmel_tx_empty, | |
1401 | .set_mctrl = atmel_set_mctrl, | |
1402 | .get_mctrl = atmel_get_mctrl, | |
1403 | .stop_tx = atmel_stop_tx, | |
1404 | .start_tx = atmel_start_tx, | |
1405 | .stop_rx = atmel_stop_rx, | |
1406 | .enable_ms = atmel_enable_ms, | |
1407 | .break_ctl = atmel_break_ctl, | |
1408 | .startup = atmel_startup, | |
1409 | .shutdown = atmel_shutdown, | |
9afd561a | 1410 | .flush_buffer = atmel_flush_buffer, |
7192f92c | 1411 | .set_termios = atmel_set_termios, |
42bd7a4f | 1412 | .set_ldisc = atmel_set_ldisc, |
7192f92c HS |
1413 | .type = atmel_type, |
1414 | .release_port = atmel_release_port, | |
1415 | .request_port = atmel_request_port, | |
1416 | .config_port = atmel_config_port, | |
1417 | .verify_port = atmel_verify_port, | |
1418 | .pm = atmel_serial_pm, | |
e8faff73 | 1419 | .ioctl = atmel_ioctl, |
8fe2d541 AT |
1420 | #ifdef CONFIG_CONSOLE_POLL |
1421 | .poll_get_char = atmel_poll_get_char, | |
1422 | .poll_put_char = atmel_poll_put_char, | |
1423 | #endif | |
1e6c9c28 AV |
1424 | }; |
1425 | ||
5fbe46b6 NF |
1426 | static void __devinit atmel_of_init_port(struct atmel_uart_port *atmel_port, |
1427 | struct device_node *np) | |
1428 | { | |
1429 | u32 rs485_delay[2]; | |
1430 | ||
1431 | /* DMA/PDC usage specification */ | |
1432 | if (of_get_property(np, "atmel,use-dma-rx", NULL)) | |
1433 | atmel_port->use_dma_rx = 1; | |
1434 | else | |
1435 | atmel_port->use_dma_rx = 0; | |
1436 | if (of_get_property(np, "atmel,use-dma-tx", NULL)) | |
1437 | atmel_port->use_dma_tx = 1; | |
1438 | else | |
1439 | atmel_port->use_dma_tx = 0; | |
1440 | ||
1441 | /* rs485 properties */ | |
1442 | if (of_property_read_u32_array(np, "rs485-rts-delay", | |
1443 | rs485_delay, 2) == 0) { | |
1444 | struct serial_rs485 *rs485conf = &atmel_port->rs485; | |
1445 | ||
1446 | rs485conf->delay_rts_before_send = rs485_delay[0]; | |
1447 | rs485conf->delay_rts_after_send = rs485_delay[1]; | |
1448 | rs485conf->flags = 0; | |
1449 | ||
1450 | if (rs485conf->delay_rts_before_send == 0 && | |
1451 | rs485conf->delay_rts_after_send == 0) { | |
1452 | rs485conf->flags |= SER_RS485_RTS_ON_SEND; | |
1453 | } else { | |
1454 | if (rs485conf->delay_rts_before_send) | |
1455 | rs485conf->flags |= SER_RS485_RTS_BEFORE_SEND; | |
1456 | if (rs485conf->delay_rts_after_send) | |
1457 | rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; | |
1458 | } | |
1459 | ||
1460 | if (of_get_property(np, "rs485-rx-during-tx", NULL)) | |
1461 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | |
1462 | ||
1463 | if (of_get_property(np, "linux,rs485-enabled-at-boot-time", NULL)) | |
1464 | rs485conf->flags |= SER_RS485_ENABLED; | |
1465 | } | |
1466 | } | |
1467 | ||
afefc415 AV |
1468 | /* |
1469 | * Configure the port from the platform device resource info. | |
1470 | */ | |
b843aa21 RB |
1471 | static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, |
1472 | struct platform_device *pdev) | |
1e6c9c28 | 1473 | { |
7192f92c | 1474 | struct uart_port *port = &atmel_port->uart; |
1acfc7ec | 1475 | struct atmel_uart_data *pdata = pdev->dev.platform_data; |
afefc415 | 1476 | |
5fbe46b6 NF |
1477 | if (pdev->dev.of_node) { |
1478 | atmel_of_init_port(atmel_port, pdev->dev.of_node); | |
1479 | } else { | |
1480 | atmel_port->use_dma_rx = pdata->use_dma_rx; | |
1481 | atmel_port->use_dma_tx = pdata->use_dma_tx; | |
1482 | atmel_port->rs485 = pdata->rs485; | |
1483 | } | |
afefc415 | 1484 | |
e8faff73 CS |
1485 | port->iotype = UPIO_MEM; |
1486 | port->flags = UPF_BOOT_AUTOCONF; | |
1487 | port->ops = &atmel_pops; | |
1488 | port->fifosize = 1; | |
e8faff73 | 1489 | port->dev = &pdev->dev; |
afefc415 AV |
1490 | port->mapbase = pdev->resource[0].start; |
1491 | port->irq = pdev->resource[1].start; | |
1492 | ||
1ecc26bd RB |
1493 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
1494 | (unsigned long)port); | |
1495 | ||
1496 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | |
1497 | ||
5fbe46b6 | 1498 | if (pdata && pdata->regs) { |
75d35213 | 1499 | /* Already mapped by setup code */ |
1acfc7ec | 1500 | port->membase = pdata->regs; |
588edbf3 | 1501 | } else { |
afefc415 AV |
1502 | port->flags |= UPF_IOREMAP; |
1503 | port->membase = NULL; | |
1504 | } | |
1e6c9c28 | 1505 | |
b843aa21 RB |
1506 | /* for console, the clock could already be configured */ |
1507 | if (!atmel_port->clk) { | |
7192f92c HS |
1508 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
1509 | clk_enable(atmel_port->clk); | |
1510 | port->uartclk = clk_get_rate(atmel_port->clk); | |
06a7f058 DB |
1511 | clk_disable(atmel_port->clk); |
1512 | /* only enable clock when USART is in use */ | |
afefc415 | 1513 | } |
a6670615 | 1514 | |
e8faff73 CS |
1515 | /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ |
1516 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) | |
1517 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
1518 | else if (atmel_use_dma_tx(port)) { | |
a6670615 | 1519 | port->fifosize = PDC_BUFFER_SIZE; |
e8faff73 CS |
1520 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; |
1521 | } else { | |
1522 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
1523 | } | |
1e6c9c28 AV |
1524 | } |
1525 | ||
afefc415 AV |
1526 | /* |
1527 | * Register board-specific modem-control line handlers. | |
1528 | */ | |
71f2e2b8 | 1529 | void __init atmel_register_uart_fns(struct atmel_port_fns *fns) |
1e6c9c28 AV |
1530 | { |
1531 | if (fns->enable_ms) | |
7192f92c | 1532 | atmel_pops.enable_ms = fns->enable_ms; |
1e6c9c28 | 1533 | if (fns->get_mctrl) |
7192f92c | 1534 | atmel_pops.get_mctrl = fns->get_mctrl; |
1e6c9c28 | 1535 | if (fns->set_mctrl) |
7192f92c | 1536 | atmel_pops.set_mctrl = fns->set_mctrl; |
71f2e2b8 HS |
1537 | atmel_open_hook = fns->open; |
1538 | atmel_close_hook = fns->close; | |
7192f92c HS |
1539 | atmel_pops.pm = fns->pm; |
1540 | atmel_pops.set_wake = fns->set_wake; | |
1e6c9c28 AV |
1541 | } |
1542 | ||
749c4e60 | 1543 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 1544 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 1545 | { |
7192f92c | 1546 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
829dd811 | 1547 | cpu_relax(); |
d358788f RK |
1548 | UART_PUT_CHAR(port, ch); |
1549 | } | |
1e6c9c28 AV |
1550 | |
1551 | /* | |
1552 | * Interrupts are disabled on entering | |
1553 | */ | |
7192f92c | 1554 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 1555 | { |
7192f92c | 1556 | struct uart_port *port = &atmel_ports[co->index].uart; |
e8faff73 | 1557 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
d358788f | 1558 | unsigned int status, imr; |
39d4c922 | 1559 | unsigned int pdc_tx; |
1e6c9c28 AV |
1560 | |
1561 | /* | |
b843aa21 | 1562 | * First, save IMR and then disable interrupts |
1e6c9c28 | 1563 | */ |
b843aa21 | 1564 | imr = UART_GET_IMR(port); |
e8faff73 | 1565 | UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); |
1e6c9c28 | 1566 | |
39d4c922 MP |
1567 | /* Store PDC transmit status and disable it */ |
1568 | pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; | |
1569 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
1570 | ||
7192f92c | 1571 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
1572 | |
1573 | /* | |
b843aa21 RB |
1574 | * Finally, wait for transmitter to become empty |
1575 | * and restore IMR | |
1e6c9c28 AV |
1576 | */ |
1577 | do { | |
1578 | status = UART_GET_CSR(port); | |
7192f92c | 1579 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
1580 | |
1581 | /* Restore PDC transmit status */ | |
1582 | if (pdc_tx) | |
1583 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
1584 | ||
b843aa21 RB |
1585 | /* set interrupts back the way they were */ |
1586 | UART_PUT_IER(port, imr); | |
1e6c9c28 AV |
1587 | } |
1588 | ||
1589 | /* | |
b843aa21 RB |
1590 | * If the port was already initialised (eg, by a boot loader), |
1591 | * try to determine the current setup. | |
1e6c9c28 | 1592 | */ |
b843aa21 RB |
1593 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
1594 | int *parity, int *bits) | |
1e6c9c28 AV |
1595 | { |
1596 | unsigned int mr, quot; | |
1597 | ||
1c0fd82f HS |
1598 | /* |
1599 | * If the baud rate generator isn't running, the port wasn't | |
1600 | * initialized by the boot loader. | |
1601 | */ | |
9c81c5c9 | 1602 | quot = UART_GET_BRGR(port) & ATMEL_US_CD; |
1c0fd82f HS |
1603 | if (!quot) |
1604 | return; | |
1e6c9c28 | 1605 | |
7192f92c HS |
1606 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
1607 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
1608 | *bits = 8; |
1609 | else | |
1610 | *bits = 7; | |
1611 | ||
7192f92c HS |
1612 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
1613 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 1614 | *parity = 'e'; |
7192f92c | 1615 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
1616 | *parity = 'o'; |
1617 | ||
4d5e392c HS |
1618 | /* |
1619 | * The serial core only rounds down when matching this to a | |
1620 | * supported baud rate. Make sure we don't end up slightly | |
1621 | * lower than one of those, as it would make us fall through | |
1622 | * to a much lower baud rate than we really want. | |
1623 | */ | |
4d5e392c | 1624 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
1625 | } |
1626 | ||
7192f92c | 1627 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 1628 | { |
7192f92c | 1629 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
1630 | int baud = 115200; |
1631 | int bits = 8; | |
1632 | int parity = 'n'; | |
1633 | int flow = 'n'; | |
1634 | ||
b843aa21 RB |
1635 | if (port->membase == NULL) { |
1636 | /* Port not initialized yet - delay setup */ | |
afefc415 | 1637 | return -ENODEV; |
b843aa21 | 1638 | } |
1e6c9c28 | 1639 | |
06a7f058 DB |
1640 | clk_enable(atmel_ports[co->index].clk); |
1641 | ||
b843aa21 | 1642 | UART_PUT_IDR(port, -1); |
7192f92c HS |
1643 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1644 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1645 | |
1646 | if (options) | |
1647 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1648 | else | |
7192f92c | 1649 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
1650 | |
1651 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1652 | } | |
1653 | ||
7192f92c | 1654 | static struct uart_driver atmel_uart; |
1e6c9c28 | 1655 | |
7192f92c HS |
1656 | static struct console atmel_console = { |
1657 | .name = ATMEL_DEVICENAME, | |
1658 | .write = atmel_console_write, | |
1e6c9c28 | 1659 | .device = uart_console_device, |
7192f92c | 1660 | .setup = atmel_console_setup, |
1e6c9c28 AV |
1661 | .flags = CON_PRINTBUFFER, |
1662 | .index = -1, | |
7192f92c | 1663 | .data = &atmel_uart, |
1e6c9c28 AV |
1664 | }; |
1665 | ||
06a7f058 | 1666 | #define ATMEL_CONSOLE_DEVICE (&atmel_console) |
1e6c9c28 | 1667 | |
afefc415 AV |
1668 | /* |
1669 | * Early console initialization (before VM subsystem initialized). | |
1670 | */ | |
7192f92c | 1671 | static int __init atmel_console_init(void) |
1e6c9c28 | 1672 | { |
73e2798b | 1673 | if (atmel_default_console_device) { |
0d0a3cc1 VN |
1674 | struct atmel_uart_data *pdata = |
1675 | atmel_default_console_device->dev.platform_data; | |
efb8d21b | 1676 | int id = pdata->num; |
4cbf9f48 NF |
1677 | struct atmel_uart_port *port = &atmel_ports[id]; |
1678 | ||
4cbf9f48 NF |
1679 | port->backup_imr = 0; |
1680 | port->uart.line = id; | |
0d0a3cc1 | 1681 | |
4cbf9f48 NF |
1682 | add_preferred_console(ATMEL_DEVICENAME, id, NULL); |
1683 | atmel_init_port(port, atmel_default_console_device); | |
7192f92c | 1684 | register_console(&atmel_console); |
afefc415 | 1685 | } |
1e6c9c28 | 1686 | |
1e6c9c28 AV |
1687 | return 0; |
1688 | } | |
b843aa21 | 1689 | |
7192f92c | 1690 | console_initcall(atmel_console_init); |
1e6c9c28 | 1691 | |
afefc415 AV |
1692 | /* |
1693 | * Late console initialization. | |
1694 | */ | |
7192f92c | 1695 | static int __init atmel_late_console_init(void) |
afefc415 | 1696 | { |
b843aa21 RB |
1697 | if (atmel_default_console_device |
1698 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 1699 | register_console(&atmel_console); |
afefc415 AV |
1700 | |
1701 | return 0; | |
1702 | } | |
b843aa21 | 1703 | |
7192f92c | 1704 | core_initcall(atmel_late_console_init); |
afefc415 | 1705 | |
dfa7f343 HS |
1706 | static inline bool atmel_is_console_port(struct uart_port *port) |
1707 | { | |
1708 | return port->cons && port->cons->index == port->line; | |
1709 | } | |
1710 | ||
1e6c9c28 | 1711 | #else |
7192f92c | 1712 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
1713 | |
1714 | static inline bool atmel_is_console_port(struct uart_port *port) | |
1715 | { | |
1716 | return false; | |
1717 | } | |
1e6c9c28 AV |
1718 | #endif |
1719 | ||
7192f92c | 1720 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
1721 | .owner = THIS_MODULE, |
1722 | .driver_name = "atmel_serial", | |
1723 | .dev_name = ATMEL_DEVICENAME, | |
1724 | .major = SERIAL_ATMEL_MAJOR, | |
1725 | .minor = MINOR_START, | |
1726 | .nr = ATMEL_MAX_UART, | |
1727 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
1728 | }; |
1729 | ||
afefc415 | 1730 | #ifdef CONFIG_PM |
f826caa4 HS |
1731 | static bool atmel_serial_clk_will_stop(void) |
1732 | { | |
1733 | #ifdef CONFIG_ARCH_AT91 | |
1734 | return at91_suspend_entering_slow_clock(); | |
1735 | #else | |
1736 | return false; | |
1737 | #endif | |
1738 | } | |
1739 | ||
b843aa21 RB |
1740 | static int atmel_serial_suspend(struct platform_device *pdev, |
1741 | pm_message_t state) | |
1e6c9c28 | 1742 | { |
afefc415 | 1743 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 1744 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1745 | |
e1c609ef HS |
1746 | if (atmel_is_console_port(port) && console_suspend_enabled) { |
1747 | /* Drain the TX shifter */ | |
1748 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
1749 | cpu_relax(); | |
1750 | } | |
1751 | ||
f05596db AS |
1752 | /* we can not wake up if we're running on slow clock */ |
1753 | atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); | |
1754 | if (atmel_serial_clk_will_stop()) | |
1755 | device_set_wakeup_enable(&pdev->dev, 0); | |
1756 | ||
1757 | uart_suspend_port(&atmel_uart, port); | |
1e6c9c28 | 1758 | |
afefc415 AV |
1759 | return 0; |
1760 | } | |
1e6c9c28 | 1761 | |
7192f92c | 1762 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
1763 | { |
1764 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1765 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1766 | |
f05596db AS |
1767 | uart_resume_port(&atmel_uart, port); |
1768 | device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); | |
1e6c9c28 AV |
1769 | |
1770 | return 0; | |
1771 | } | |
afefc415 | 1772 | #else |
7192f92c HS |
1773 | #define atmel_serial_suspend NULL |
1774 | #define atmel_serial_resume NULL | |
afefc415 | 1775 | #endif |
1e6c9c28 | 1776 | |
7192f92c | 1777 | static int __devinit atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 1778 | { |
7192f92c | 1779 | struct atmel_uart_port *port; |
5fbe46b6 | 1780 | struct device_node *np = pdev->dev.of_node; |
deba1a0d | 1781 | struct atmel_uart_data *pdata = pdev->dev.platform_data; |
1ecc26bd | 1782 | void *data; |
4cbf9f48 | 1783 | int ret = -ENODEV; |
1e6c9c28 | 1784 | |
9d09daf8 | 1785 | BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); |
1ecc26bd | 1786 | |
5fbe46b6 NF |
1787 | if (np) |
1788 | ret = of_alias_get_id(np, "serial"); | |
1789 | else | |
1790 | if (pdata) | |
1791 | ret = pdata->num; | |
4cbf9f48 NF |
1792 | |
1793 | if (ret < 0) | |
5fbe46b6 | 1794 | /* port id not found in platform data nor device-tree aliases: |
4cbf9f48 NF |
1795 | * auto-enumerate it */ |
1796 | ret = find_first_zero_bit(&atmel_ports_in_use, | |
1797 | sizeof(atmel_ports_in_use)); | |
1798 | ||
1799 | if (ret > ATMEL_MAX_UART) { | |
1800 | ret = -ENODEV; | |
1801 | goto err; | |
1802 | } | |
1803 | ||
1804 | if (test_and_set_bit(ret, &atmel_ports_in_use)) { | |
1805 | /* port already in use */ | |
1806 | ret = -EBUSY; | |
1807 | goto err; | |
1808 | } | |
1809 | ||
1810 | port = &atmel_ports[ret]; | |
f05596db | 1811 | port->backup_imr = 0; |
4cbf9f48 | 1812 | port->uart.line = ret; |
f05596db | 1813 | |
7192f92c | 1814 | atmel_init_port(port, pdev); |
1e6c9c28 | 1815 | |
a6670615 CC |
1816 | if (!atmel_use_dma_rx(&port->uart)) { |
1817 | ret = -ENOMEM; | |
6433471d HS |
1818 | data = kmalloc(sizeof(struct atmel_uart_char) |
1819 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
1820 | if (!data) |
1821 | goto err_alloc_ring; | |
1822 | port->rx_ring.buf = data; | |
1823 | } | |
1ecc26bd | 1824 | |
7192f92c | 1825 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
dfa7f343 HS |
1826 | if (ret) |
1827 | goto err_add_port; | |
1828 | ||
8da14b5f | 1829 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
06a7f058 DB |
1830 | if (atmel_is_console_port(&port->uart) |
1831 | && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { | |
1832 | /* | |
1833 | * The serial core enabled the clock for us, so undo | |
1834 | * the clk_enable() in atmel_console_setup() | |
1835 | */ | |
1836 | clk_disable(port->clk); | |
1837 | } | |
8da14b5f | 1838 | #endif |
06a7f058 | 1839 | |
dfa7f343 HS |
1840 | device_init_wakeup(&pdev->dev, 1); |
1841 | platform_set_drvdata(pdev, port); | |
1842 | ||
5dfbd1d7 CS |
1843 | if (port->rs485.flags & SER_RS485_ENABLED) { |
1844 | UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); | |
1845 | UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); | |
1846 | } | |
1847 | ||
dfa7f343 HS |
1848 | return 0; |
1849 | ||
1850 | err_add_port: | |
1ecc26bd RB |
1851 | kfree(port->rx_ring.buf); |
1852 | port->rx_ring.buf = NULL; | |
1853 | err_alloc_ring: | |
dfa7f343 | 1854 | if (!atmel_is_console_port(&port->uart)) { |
dfa7f343 HS |
1855 | clk_put(port->clk); |
1856 | port->clk = NULL; | |
afefc415 | 1857 | } |
4cbf9f48 | 1858 | err: |
afefc415 AV |
1859 | return ret; |
1860 | } | |
1861 | ||
7192f92c | 1862 | static int __devexit atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
1863 | { |
1864 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1865 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 AV |
1866 | int ret = 0; |
1867 | ||
afefc415 AV |
1868 | device_init_wakeup(&pdev->dev, 0); |
1869 | platform_set_drvdata(pdev, NULL); | |
1870 | ||
dfa7f343 HS |
1871 | ret = uart_remove_one_port(&atmel_uart, port); |
1872 | ||
1ecc26bd RB |
1873 | tasklet_kill(&atmel_port->tasklet); |
1874 | kfree(atmel_port->rx_ring.buf); | |
1875 | ||
dfa7f343 HS |
1876 | /* "port" is allocated statically, so we shouldn't free it */ |
1877 | ||
4cbf9f48 NF |
1878 | clear_bit(port->line, &atmel_ports_in_use); |
1879 | ||
dfa7f343 | 1880 | clk_put(atmel_port->clk); |
afefc415 AV |
1881 | |
1882 | return ret; | |
1883 | } | |
1884 | ||
7192f92c HS |
1885 | static struct platform_driver atmel_serial_driver = { |
1886 | .probe = atmel_serial_probe, | |
1887 | .remove = __devexit_p(atmel_serial_remove), | |
1888 | .suspend = atmel_serial_suspend, | |
1889 | .resume = atmel_serial_resume, | |
afefc415 | 1890 | .driver = { |
1e8ea802 | 1891 | .name = "atmel_usart", |
afefc415 | 1892 | .owner = THIS_MODULE, |
5fbe46b6 | 1893 | .of_match_table = of_match_ptr(atmel_serial_dt_ids), |
afefc415 AV |
1894 | }, |
1895 | }; | |
1896 | ||
7192f92c | 1897 | static int __init atmel_serial_init(void) |
afefc415 AV |
1898 | { |
1899 | int ret; | |
1900 | ||
7192f92c | 1901 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
1902 | if (ret) |
1903 | return ret; | |
1904 | ||
7192f92c | 1905 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 1906 | if (ret) |
7192f92c | 1907 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
1908 | |
1909 | return ret; | |
1910 | } | |
1911 | ||
7192f92c | 1912 | static void __exit atmel_serial_exit(void) |
afefc415 | 1913 | { |
7192f92c HS |
1914 | platform_driver_unregister(&atmel_serial_driver); |
1915 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
1916 | } |
1917 | ||
7192f92c HS |
1918 | module_init(atmel_serial_init); |
1919 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
1920 | |
1921 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 1922 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 1923 | MODULE_LICENSE("GPL"); |
e169c139 | 1924 | MODULE_ALIAS("platform:atmel_usart"); |