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tty/serial: at91: use correct type for dma_sync_*_for_cpu() and dma_sync_*_for_device()
[linux-2.6-block.git] / drivers / tty / serial / atmel_serial.c
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1e6c9c28 1/*
7192f92c 2 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV		 3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
a6670615
CC		 8 * DMA support added by Chip Coldwell.
9 *
1e6c9c28
AV		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV		 25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
afefc415 31#include <linux/clk.h>
1e6c9c28
AV		 32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
afefc415 35#include <linux/platform_device.h>
5fbe46b6
NF		 36#include <linux/of.h>
37#include <linux/of_device.h>
354e57f3 38#include <linux/of_gpio.h>
a6670615 39#include <linux/dma-mapping.h>
6b997bab 40#include <linux/dmaengine.h>
93a3ddc2 41#include <linux/atmel_pdc.h>
fa3218d8 42#include <linux/atmel_serial.h>
e8faff73 43#include <linux/uaccess.h>
bcd2360c 44#include <linux/platform_data/atmel.h>
2e68c22f 45#include <linux/timer.h>
354e57f3 46#include <linux/gpio.h>
e0b0baad
RG		 47#include <linux/gpio/consumer.h>
48#include <linux/err.h>
ab5e4e41 49#include <linux/irq.h>
1e6c9c28
AV		 50
51#include <asm/io.h>
f7512e7c 52#include <asm/ioctls.h>
1e6c9c28 53
a6670615
CC		 54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
749c4e60 58#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 59#define SUPPORT_SYSRQ
60#endif
61
62#include <linux/serial_core.h>
63
e0b0baad
RG		 64#include "serial_mctrl_gpio.h"
65
e8faff73
CS		 66static void atmel_start_rx(struct uart_port *port);
67static void atmel_stop_rx(struct uart_port *port);
68
749c4e60 69#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 70
71/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
72 * should coexist with the 8250 driver, such as if we have an external 16C550
73 * UART. */
7192f92c 74#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 75#define MINOR_START 154
7192f92c 76#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 77
78#else
79
80/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
81 * name, but it is legally reserved for the 8250 driver. */
7192f92c 82#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 83#define MINOR_START 64
7192f92c 84#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 85
86#endif
87
7192f92c 88#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 89
b843aa21 90/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS		 91#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
92#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
93#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
94#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
95#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
96#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
97#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
98#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
99#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
100#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
101#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
102#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
e8faff73 103#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
055560b0 104#define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
731d9cae 105#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
544fc728 106
1e6c9c28 107 /* PDC registers */
544fc728
HS		 108#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
109#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
110
111#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
112#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
113#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
114#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
115#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
116
117#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
118#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
39d4c922 119#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
1e6c9c28 120
a6670615
CC		 121struct atmel_dma_buffer {
122 unsigned char *buf;
123 dma_addr_t dma_addr;
124 unsigned int dma_size;
125 unsigned int ofs;
126};
127
1ecc26bd
RB		 128struct atmel_uart_char {
129 u16 status;
130 u16 ch;
131};
132
133#define ATMEL_SERIAL_RINGSIZE 1024
134
afefc415
AV		 135/*
136 * We wrap our port structure around the generic uart_port.
137 */
7192f92c 138struct atmel_uart_port {
afefc415
AV		 139 struct uart_port uart; /* uart */
140 struct clk *clk; /* uart clock */
f05596db
AS		 141 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
142 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 143 int break_active; /* break being received */
1ecc26bd 144
34df42f5 145 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 146 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 147 short pdc_rx_idx; /* current PDC RX buffer */
148 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
149
08f738be 150 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 151 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 152 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
153
08f738be 154 spinlock_t lock_tx; /* port lock */
34df42f5 155 spinlock_t lock_rx; /* port lock */
08f738be 156 struct dma_chan *chan_tx;
34df42f5 157 struct dma_chan *chan_rx;
08f738be 158 struct dma_async_tx_descriptor *desc_tx;
34df42f5 159 struct dma_async_tx_descriptor *desc_rx;
08f738be 160 dma_cookie_t cookie_tx;
34df42f5 161 dma_cookie_t cookie_rx;
08f738be 162 struct scatterlist sg_tx;
34df42f5 163 struct scatterlist sg_rx;
1ecc26bd
RB		 164 struct tasklet_struct tasklet;
165 unsigned int irq_status;
166 unsigned int irq_status_prev;
167
168 struct circ_buf rx_ring;
e8faff73 169
e0b0baad 170 struct mctrl_gpios *gpios;
ab5e4e41 171 int gpio_irq[UART_GPIO_MAX];
e8faff73 172 unsigned int tx_done_mask;
ab5e4e41 173 bool ms_irq_enabled;
055560b0 174 bool is_usart; /* usart or uart */
2e68c22f 175 struct timer_list uart_timer; /* uart timer */
a930e528
ES		 176 int (*prepare_rx)(struct uart_port *port);
177 int (*prepare_tx)(struct uart_port *port);
178 void (*schedule_rx)(struct uart_port *port);
179 void (*schedule_tx)(struct uart_port *port);
180 void (*release_rx)(struct uart_port *port);
181 void (*release_tx)(struct uart_port *port);
afefc415
AV		 182};
183
7192f92c 184static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 185static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 186
1e6c9c28 187#ifdef SUPPORT_SYSRQ
7192f92c 188static struct console atmel_console;
1e6c9c28
AV		 189#endif
190
5fbe46b6
NF		 191#if defined(CONFIG_OF)
192static const struct of_device_id atmel_serial_dt_ids[] = {
193 { .compatible = "atmel,at91rm9200-usart" },
194 { .compatible = "atmel,at91sam9260-usart" },
195 { /* sentinel */ }
196};
197
198MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
199#endif
200
c811ab8c
HS		 201static inline struct atmel_uart_port *
202to_atmel_uart_port(struct uart_port *uart)
203{
204 return container_of(uart, struct atmel_uart_port, uart);
205}
206
a6670615 207#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 208static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 209{
c811ab8c 210 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 211
64e22ebe 212 return atmel_port->use_pdc_rx;
a6670615
CC		 213}
214
64e22ebe 215static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 216{
c811ab8c 217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 218
64e22ebe 219 return atmel_port->use_pdc_tx;
a6670615
CC		 220}
221#else
64e22ebe 222static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 223{
224 return false;
225}
226
64e22ebe 227static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 228{
229 return false;
230}
231#endif
232
08f738be
ES		 233static bool atmel_use_dma_tx(struct uart_port *port)
234{
235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
236
237 return atmel_port->use_dma_tx;
238}
239
34df42f5
ES		 240static bool atmel_use_dma_rx(struct uart_port *port)
241{
242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
243
244 return atmel_port->use_dma_rx;
245}
246
e0b0baad
RG		 247static unsigned int atmel_get_lines_status(struct uart_port *port)
248{
249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
250 unsigned int status, ret = 0;
251
252 status = UART_GET_CSR(port);
253
254 mctrl_gpio_get(atmel_port->gpios, &ret);
255
256 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
257 UART_GPIO_CTS))) {
258 if (ret & TIOCM_CTS)
259 status &= ~ATMEL_US_CTS;
260 else
261 status |= ATMEL_US_CTS;
262 }
263
264 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
265 UART_GPIO_DSR))) {
266 if (ret & TIOCM_DSR)
267 status &= ~ATMEL_US_DSR;
268 else
269 status |= ATMEL_US_DSR;
270 }
271
272 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
273 UART_GPIO_RI))) {
274 if (ret & TIOCM_RI)
275 status &= ~ATMEL_US_RI;
276 else
277 status |= ATMEL_US_RI;
278 }
279
280 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
281 UART_GPIO_DCD))) {
282 if (ret & TIOCM_CD)
283 status &= ~ATMEL_US_DCD;
284 else
285 status |= ATMEL_US_DCD;
286 }
287
288 return status;
289}
290
e8faff73 291/* Enable or disable the rs485 support */
13bd3e6f
RRD		 292static int atmel_config_rs485(struct uart_port *port,
293 struct serial_rs485 *rs485conf)
e8faff73
CS		 294{
295 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
296 unsigned int mode;
e8faff73
CS		 297
298 /* Disable interrupts */
299 UART_PUT_IDR(port, atmel_port->tx_done_mask);
300
301 mode = UART_GET_MR(port);
302
303 /* Resetting serial mode to RS232 (0x0) */
304 mode &= ~ATMEL_US_USMODE;
305
13bd3e6f 306 port->rs485 = *rs485conf;
e8faff73
CS		 307
308 if (rs485conf->flags & SER_RS485_ENABLED) {
309 dev_dbg(port->dev, "Setting UART to RS485\n");
310 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
93f3350c 311 if ((rs485conf->delay_rts_after_send) > 0)
1b633184 312 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
e8faff73
CS		 313 mode |= ATMEL_US_USMODE_RS485;
314 } else {
315 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 316 if (atmel_use_pdc_tx(port))
e8faff73
CS		 317 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
318 ATMEL_US_TXBUFE;
319 else
320 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
321 }
322 UART_PUT_MR(port, mode);
323
324 /* Enable interrupts */
325 UART_PUT_IER(port, atmel_port->tx_done_mask);
326
13bd3e6f 327 return 0;
e8faff73
CS		 328}
329
1e6c9c28
AV		 330/*
331 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
332 */
7192f92c 333static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 334{
7192f92c 335 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV		 336}
337
338/*
339 * Set state of the modem control output lines
340 */
7192f92c 341static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 342{
343 unsigned int control = 0;
afefc415 344 unsigned int mode;
e8faff73 345 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 346
1e6c9c28 347 if (mctrl & TIOCM_RTS)
7192f92c 348 control |= ATMEL_US_RTSEN;
1e6c9c28 349 else
7192f92c 350 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV		 351
352 if (mctrl & TIOCM_DTR)
7192f92c 353 control |= ATMEL_US_DTREN;
1e6c9c28 354 else
7192f92c 355 control |= ATMEL_US_DTRDIS;
1e6c9c28 356
afefc415
AV		 357 UART_PUT_CR(port, control);
358
e0b0baad
RG		 359 mctrl_gpio_set(atmel_port->gpios, mctrl);
360
afefc415 361 /* Local loopback mode? */
7192f92c 362 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 363 if (mctrl & TIOCM_LOOP)
7192f92c 364 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 365 else
7192f92c 366 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73
CS		 367
368 /* Resetting serial mode to RS232 (0x0) */
369 mode &= ~ATMEL_US_USMODE;
370
13bd3e6f 371 if (port->rs485.flags & SER_RS485_ENABLED) {
e8faff73 372 dev_dbg(port->dev, "Setting UART to RS485\n");
13bd3e6f
RRD		 373 if ((port->rs485.delay_rts_after_send) > 0)
374 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send);
e8faff73
CS		 375 mode |= ATMEL_US_USMODE_RS485;
376 } else {
377 dev_dbg(port->dev, "Setting UART to RS232\n");
378 }
afefc415 379 UART_PUT_MR(port, mode);
1e6c9c28
AV		 380}
381
382/*
383 * Get state of the modem control input lines
384 */
7192f92c 385static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 386{
e0b0baad
RG		 387 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
388 unsigned int ret = 0, status;
1e6c9c28
AV		 389
390 status = UART_GET_CSR(port);
391
392 /*
393 * The control signals are active low.
394 */
7192f92c 395 if (!(status & ATMEL_US_DCD))
1e6c9c28 396 ret |= TIOCM_CD;
7192f92c 397 if (!(status & ATMEL_US_CTS))
1e6c9c28 398 ret |= TIOCM_CTS;
7192f92c 399 if (!(status & ATMEL_US_DSR))
1e6c9c28 400 ret |= TIOCM_DSR;
7192f92c 401 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 402 ret |= TIOCM_RI;
403
e0b0baad 404 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 405}
406
407/*
408 * Stop transmitting.
409 */
7192f92c 410static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 411{
e8faff73
CS		 412 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
413
64e22ebe 414 if (atmel_use_pdc_tx(port)) {
a6670615
CC		 415 /* disable PDC transmit */
416 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
e8faff73
CS		 417 }
418 /* Disable interrupts */
419 UART_PUT_IDR(port, atmel_port->tx_done_mask);
420
13bd3e6f
RRD		 421 if ((port->rs485.flags & SER_RS485_ENABLED) &&
422 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73 423 atmel_start_rx(port);
1e6c9c28
AV		 424}
425
426/*
427 * Start transmitting.
428 */
7192f92c 429static void atmel_start_tx(struct uart_port *port)
1e6c9c28 430{
e8faff73
CS		 431 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
432
64e22ebe 433 if (atmel_use_pdc_tx(port)) {
a6670615
CC		 434 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
435 /* The transmitter is already running. Yes, we
436 really need this.*/
437 return;
438
13bd3e6f
RRD		 439 if ((port->rs485.flags & SER_RS485_ENABLED) &&
440 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73
CS		 441 atmel_stop_rx(port);
442
a6670615
CC		 443 /* re-enable PDC transmit */
444 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
e8faff73
CS		 445 }
446 /* Enable interrupts */
447 UART_PUT_IER(port, atmel_port->tx_done_mask);
448}
449
450/*
451 * start receiving - port is in process of being opened.
452 */
453static void atmel_start_rx(struct uart_port *port)
454{
455 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
456
57c36868
SG		 457 UART_PUT_CR(port, ATMEL_US_RXEN);
458
64e22ebe 459 if (atmel_use_pdc_rx(port)) {
e8faff73
CS		 460 /* enable PDC controller */
461 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
462 port->read_status_mask);
463 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
464 } else {
465 UART_PUT_IER(port, ATMEL_US_RXRDY);
466 }
1e6c9c28
AV		 467}
468
469/*
470 * Stop receiving - port is in process of being closed.
471 */
7192f92c 472static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 473{
57c36868
SG		 474 UART_PUT_CR(port, ATMEL_US_RXDIS);
475
64e22ebe 476 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 477 /* disable PDC receive */
478 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
e8faff73
CS		 479 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
480 port->read_status_mask);
481 } else {
a6670615 482 UART_PUT_IDR(port, ATMEL_US_RXRDY);
e8faff73 483 }
1e6c9c28
AV		 484}
485
486/*
487 * Enable modem status interrupts
488 */
7192f92c 489static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 490{
ab5e4e41
RG		 491 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
492 uint32_t ier = 0;
493
494 /*
495 * Interrupt should not be enabled twice
496 */
497 if (atmel_port->ms_irq_enabled)
498 return;
499
500 atmel_port->ms_irq_enabled = true;
501
502 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
503 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
504 else
505 ier |= ATMEL_US_CTSIC;
506
507 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
508 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
509 else
510 ier |= ATMEL_US_DSRIC;
511
512 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
513 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
514 else
515 ier |= ATMEL_US_RIIC;
516
517 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
518 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
519 else
520 ier |= ATMEL_US_DCDIC;
521
522 UART_PUT_IER(port, ier);
1e6c9c28
AV		 523}
524
35b675b9
RG		 525/*
526 * Disable modem status interrupts
527 */
528static void atmel_disable_ms(struct uart_port *port)
529{
530 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
531 uint32_t idr = 0;
532
533 /*
534 * Interrupt should not be disabled twice
535 */
536 if (!atmel_port->ms_irq_enabled)
537 return;
538
539 atmel_port->ms_irq_enabled = false;
540
541 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
542 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
543 else
544 idr |= ATMEL_US_CTSIC;
545
546 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
547 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
548 else
549 idr |= ATMEL_US_DSRIC;
550
551 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
552 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
553 else
554 idr |= ATMEL_US_RIIC;
555
556 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
557 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
558 else
559 idr |= ATMEL_US_DCDIC;
560
561 UART_PUT_IDR(port, idr);
562}
563
1e6c9c28
AV		 564/*
565 * Control the transmission of a break signal
566 */
7192f92c 567static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 568{
569 if (break_state != 0)
7192f92c 570 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 571 else
7192f92c 572 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV		 573}
574
1ecc26bd
RB		 575/*
576 * Stores the incoming character in the ring buffer
577 */
578static void
579atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
580 unsigned int ch)
581{
c811ab8c 582 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 583 struct circ_buf *ring = &atmel_port->rx_ring;
584 struct atmel_uart_char *c;
585
586 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
587 /* Buffer overflow, ignore char */
588 return;
589
590 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
591 c->status = status;
592 c->ch = ch;
593
594 /* Make sure the character is stored before we update head. */
595 smp_wmb();
596
597 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
598}
599
a6670615
CC		 600/*
601 * Deal with parity, framing and overrun errors.
602 */
603static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
604{
605 /* clear error */
606 UART_PUT_CR(port, ATMEL_US_RSTSTA);
607
608 if (status & ATMEL_US_RXBRK) {
609 /* ignore side-effect */
610 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
611 port->icount.brk++;
612 }
613 if (status & ATMEL_US_PARE)
614 port->icount.parity++;
615 if (status & ATMEL_US_FRAME)
616 port->icount.frame++;
617 if (status & ATMEL_US_OVRE)
618 port->icount.overrun++;
619}
620
1e6c9c28
AV		 621/*
622 * Characters received (called from interrupt handler)
623 */
7d12e780 624static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 625{
c811ab8c 626 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 627 unsigned int status, ch;
1e6c9c28 628
afefc415 629 status = UART_GET_CSR(port);
7192f92c 630 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV		 631 ch = UART_GET_CHAR(port);
632
1e6c9c28
AV		 633 /*
634 * note that the error handling code is
635 * out of the main execution path
636 */
9e6077bd
HS		 637 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
638 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
639 || atmel_port->break_active)) {
1ecc26bd 640
b843aa21
RB		 641 /* clear error */
642 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 643
9e6077bd
HS		 644 if (status & ATMEL_US_RXBRK
645 && !atmel_port->break_active) {
9e6077bd
HS		 646 atmel_port->break_active = 1;
647 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS		 648 } else {
649 /*
650 * This is either the end-of-break
651 * condition or we've received at
652 * least one character without RXBRK
653 * being set. In both cases, the next
654 * RXBRK will indicate start-of-break.
655 */
656 UART_PUT_IDR(port, ATMEL_US_RXBRK);
657 status &= ~ATMEL_US_RXBRK;
658 atmel_port->break_active = 0;
afefc415 659 }
1e6c9c28
AV		 660 }
661
1ecc26bd 662 atmel_buffer_rx_char(port, status, ch);
afefc415 663 status = UART_GET_CSR(port);
1e6c9c28
AV		 664 }
665
1ecc26bd 666 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV		 667}
668
669/*
1ecc26bd
RB		 670 * Transmit characters (called from tasklet with TXRDY interrupt
671 * disabled)
1e6c9c28 672 */
7192f92c 673static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 674{
ebd2c8f6 675 struct circ_buf *xmit = &port->state->xmit;
e8faff73 676 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 677
e8faff73 678 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
1e6c9c28
AV		 679 UART_PUT_CHAR(port, port->x_char);
680 port->icount.tx++;
681 port->x_char = 0;
1e6c9c28 682 }
1ecc26bd 683 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 684 return;
1e6c9c28 685
e8faff73 686 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
1e6c9c28
AV		 687 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
688 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
689 port->icount.tx++;
690 if (uart_circ_empty(xmit))
691 break;
692 }
693
694 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
695 uart_write_wakeup(port);
696
1ecc26bd 697 if (!uart_circ_empty(xmit))
e8faff73
CS		 698 /* Enable interrupts */
699 UART_PUT_IER(port, atmel_port->tx_done_mask);
1e6c9c28
AV		 700}
701
08f738be
ES		 702static void atmel_complete_tx_dma(void *arg)
703{
704 struct atmel_uart_port *atmel_port = arg;
705 struct uart_port *port = &atmel_port->uart;
706 struct circ_buf *xmit = &port->state->xmit;
707 struct dma_chan *chan = atmel_port->chan_tx;
708 unsigned long flags;
709
710 spin_lock_irqsave(&port->lock, flags);
711
712 if (chan)
713 dmaengine_terminate_all(chan);
714 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
715 xmit->tail &= UART_XMIT_SIZE - 1;
716
717 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
718
719 spin_lock_irq(&atmel_port->lock_tx);
720 async_tx_ack(atmel_port->desc_tx);
721 atmel_port->cookie_tx = -EINVAL;
722 atmel_port->desc_tx = NULL;
723 spin_unlock_irq(&atmel_port->lock_tx);
724
725 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
726 uart_write_wakeup(port);
727
728 /* Do we really need this? */
729 if (!uart_circ_empty(xmit))
730 tasklet_schedule(&atmel_port->tasklet);
731
732 spin_unlock_irqrestore(&port->lock, flags);
733}
734
735static void atmel_release_tx_dma(struct uart_port *port)
736{
737 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
738 struct dma_chan *chan = atmel_port->chan_tx;
739
740 if (chan) {
741 dmaengine_terminate_all(chan);
742 dma_release_channel(chan);
743 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 744 DMA_TO_DEVICE);
08f738be
ES		 745 }
746
747 atmel_port->desc_tx = NULL;
748 atmel_port->chan_tx = NULL;
749 atmel_port->cookie_tx = -EINVAL;
750}
751
752/*
753 * Called from tasklet with TXRDY interrupt is disabled.
754 */
755static void atmel_tx_dma(struct uart_port *port)
756{
757 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
758 struct circ_buf *xmit = &port->state->xmit;
759 struct dma_chan *chan = atmel_port->chan_tx;
760 struct dma_async_tx_descriptor *desc;
761 struct scatterlist *sg = &atmel_port->sg_tx;
762
763 /* Make sure we have an idle channel */
764 if (atmel_port->desc_tx != NULL)
765 return;
766
767 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
768 /*
769 * DMA is idle now.
770 * Port xmit buffer is already mapped,
771 * and it is one page... Just adjust
772 * offsets and lengths. Since it is a circular buffer,
773 * we have to transmit till the end, and then the rest.
774 * Take the port lock to get a
775 * consistent xmit buffer state.
776 */
777 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
778 sg_dma_address(sg) = (sg_dma_address(sg) &
779 ~(UART_XMIT_SIZE - 1))
780 + sg->offset;
781 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
782 xmit->tail,
783 UART_XMIT_SIZE);
784 BUG_ON(!sg_dma_len(sg));
785
786 desc = dmaengine_prep_slave_sg(chan,
787 sg,
788 1,
789 DMA_MEM_TO_DEV,
790 DMA_PREP_INTERRUPT |
791 DMA_CTRL_ACK);
792 if (!desc) {
793 dev_err(port->dev, "Failed to send via dma!\n");
794 return;
795 }
796
485819b5 797 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
08f738be
ES		 798
799 atmel_port->desc_tx = desc;
800 desc->callback = atmel_complete_tx_dma;
801 desc->callback_param = atmel_port;
802 atmel_port->cookie_tx = dmaengine_submit(desc);
803
804 } else {
13bd3e6f 805 if (port->rs485.flags & SER_RS485_ENABLED) {
08f738be
ES		 806 /* DMA done, stop TX, start RX for RS485 */
807 atmel_start_rx(port);
808 }
809 }
810
811 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
812 uart_write_wakeup(port);
813}
814
815static int atmel_prepare_tx_dma(struct uart_port *port)
816{
817 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
818 dma_cap_mask_t mask;
819 struct dma_slave_config config;
820 int ret, nent;
821
822 dma_cap_zero(mask);
823 dma_cap_set(DMA_SLAVE, mask);
824
825 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
826 if (atmel_port->chan_tx == NULL)
827 goto chan_err;
828 dev_info(port->dev, "using %s for tx DMA transfers\n",
829 dma_chan_name(atmel_port->chan_tx));
830
831 spin_lock_init(&atmel_port->lock_tx);
832 sg_init_table(&atmel_port->sg_tx, 1);
833 /* UART circular tx buffer is an aligned page. */
834 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
835 sg_set_page(&atmel_port->sg_tx,
836 virt_to_page(port->state->xmit.buf),
837 UART_XMIT_SIZE,
838 (int)port->state->xmit.buf & ~PAGE_MASK);
839 nent = dma_map_sg(port->dev,
840 &atmel_port->sg_tx,
841 1,
48479148 842 DMA_TO_DEVICE);
08f738be
ES		 843
844 if (!nent) {
845 dev_dbg(port->dev, "need to release resource of dma\n");
846 goto chan_err;
847 } else {
848 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
849 sg_dma_len(&atmel_port->sg_tx),
850 port->state->xmit.buf,
851 sg_dma_address(&atmel_port->sg_tx));
852 }
853
854 /* Configure the slave DMA */
855 memset(&config, 0, sizeof(config));
856 config.direction = DMA_MEM_TO_DEV;
857 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
858 config.dst_addr = port->mapbase + ATMEL_US_THR;
859
5483c10e
MR		 860 ret = dmaengine_slave_config(atmel_port->chan_tx,
861 &config);
08f738be
ES		 862 if (ret) {
863 dev_err(port->dev, "DMA tx slave configuration failed\n");
864 goto chan_err;
865 }
866
867 return 0;
868
869chan_err:
870 dev_err(port->dev, "TX channel not available, switch to pio\n");
871 atmel_port->use_dma_tx = 0;
872 if (atmel_port->chan_tx)
873 atmel_release_tx_dma(port);
874 return -EINVAL;
875}
876
34df42f5
ES		 877static void atmel_complete_rx_dma(void *arg)
878{
879 struct uart_port *port = arg;
880 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
881
882 tasklet_schedule(&atmel_port->tasklet);
883}
884
885static void atmel_release_rx_dma(struct uart_port *port)
886{
887 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
888 struct dma_chan *chan = atmel_port->chan_rx;
889
890 if (chan) {
891 dmaengine_terminate_all(chan);
892 dma_release_channel(chan);
893 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 894 DMA_FROM_DEVICE);
34df42f5
ES		 895 }
896
897 atmel_port->desc_rx = NULL;
898 atmel_port->chan_rx = NULL;
899 atmel_port->cookie_rx = -EINVAL;
900}
901
902static void atmel_rx_from_dma(struct uart_port *port)
903{
904 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 905 struct tty_port *tport = &port->state->port;
34df42f5
ES		 906 struct circ_buf *ring = &atmel_port->rx_ring;
907 struct dma_chan *chan = atmel_port->chan_rx;
908 struct dma_tx_state state;
909 enum dma_status dmastat;
66f37aaf 910 size_t count;
34df42f5
ES		 911
912
913 /* Reset the UART timeout early so that we don't miss one */
914 UART_PUT_CR(port, ATMEL_US_STTTO);
915 dmastat = dmaengine_tx_status(chan,
916 atmel_port->cookie_rx,
917 &state);
918 /* Restart a new tasklet if DMA status is error */
919 if (dmastat == DMA_ERROR) {
920 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
921 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
922 tasklet_schedule(&atmel_port->tasklet);
923 return;
924 }
34df42f5 925
66f37aaf
CP		 926 /* CPU claims ownership of RX DMA buffer */
927 dma_sync_sg_for_cpu(port->dev,
928 &atmel_port->sg_rx,
929 1,
485819b5 930 DMA_FROM_DEVICE);
66f37aaf
CP		 931
932 /*
933 * ring->head points to the end of data already written by the DMA.
934 * ring->tail points to the beginning of data to be read by the
935 * framework.
936 * The current transfer size should not be larger than the dma buffer
937 * length.
938 */
939 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
940 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 941 /*
66f37aaf
CP		 942 * At this point ring->head may point to the first byte right after the
943 * last byte of the dma buffer:
944 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
945 *
946 * However ring->tail must always points inside the dma buffer:
947 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
948 *
949 * Since we use a ring buffer, we have to handle the case
950 * where head is lower than tail. In such a case, we first read from
951 * tail to the end of the buffer then reset tail.
34df42f5 952 */
66f37aaf
CP		 953 if (ring->head < ring->tail) {
954 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 955
66f37aaf
CP		 956 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
957 ring->tail = 0;
958 port->icount.rx += count;
959 }
34df42f5 960
66f37aaf
CP		 961 /* Finally we read data from tail to head */
962 if (ring->tail < ring->head) {
963 count = ring->head - ring->tail;
34df42f5 964
66f37aaf
CP		 965 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
966 /* Wrap ring->head if needed */
967 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
968 ring->head = 0;
969 ring->tail = ring->head;
34df42f5
ES		 970 port->icount.rx += count;
971 }
972
66f37aaf
CP		 973 /* USART retreives ownership of RX DMA buffer */
974 dma_sync_sg_for_device(port->dev,
975 &atmel_port->sg_rx,
976 1,
485819b5 977 DMA_FROM_DEVICE);
66f37aaf
CP		 978
979 /*
980 * Drop the lock here since it might end up calling
981 * uart_start(), which takes the lock.
982 */
983 spin_unlock(&port->lock);
984 tty_flip_buffer_push(tport);
985 spin_lock(&port->lock);
986
34df42f5
ES		 987 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
988}
989
990static int atmel_prepare_rx_dma(struct uart_port *port)
991{
992 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
993 struct dma_async_tx_descriptor *desc;
994 dma_cap_mask_t mask;
995 struct dma_slave_config config;
996 struct circ_buf *ring;
997 int ret, nent;
998
999 ring = &atmel_port->rx_ring;
1000
1001 dma_cap_zero(mask);
1002 dma_cap_set(DMA_CYCLIC, mask);
1003
1004 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1005 if (atmel_port->chan_rx == NULL)
1006 goto chan_err;
1007 dev_info(port->dev, "using %s for rx DMA transfers\n",
1008 dma_chan_name(atmel_port->chan_rx));
1009
1010 spin_lock_init(&atmel_port->lock_rx);
1011 sg_init_table(&atmel_port->sg_rx, 1);
1012 /* UART circular rx buffer is an aligned page. */
1013 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1014 sg_set_page(&atmel_port->sg_rx,
1015 virt_to_page(ring->buf),
1016 ATMEL_SERIAL_RINGSIZE,
1017 (int)ring->buf & ~PAGE_MASK);
1018 nent = dma_map_sg(port->dev,
1019 &atmel_port->sg_rx,
1020 1,
48479148 1021 DMA_FROM_DEVICE);
34df42f5
ES		 1022
1023 if (!nent) {
1024 dev_dbg(port->dev, "need to release resource of dma\n");
1025 goto chan_err;
1026 } else {
1027 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1028 sg_dma_len(&atmel_port->sg_rx),
1029 ring->buf,
1030 sg_dma_address(&atmel_port->sg_rx));
1031 }
1032
1033 /* Configure the slave DMA */
1034 memset(&config, 0, sizeof(config));
1035 config.direction = DMA_DEV_TO_MEM;
1036 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1037 config.src_addr = port->mapbase + ATMEL_US_RHR;
1038
5483c10e
MR		 1039 ret = dmaengine_slave_config(atmel_port->chan_rx,
1040 &config);
34df42f5
ES		 1041 if (ret) {
1042 dev_err(port->dev, "DMA rx slave configuration failed\n");
1043 goto chan_err;
1044 }
1045 /*
1046 * Prepare a cyclic dma transfer, assign 2 descriptors,
1047 * each one is half ring buffer size
1048 */
1049 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1050 sg_dma_address(&atmel_port->sg_rx),
1051 sg_dma_len(&atmel_port->sg_rx),
1052 sg_dma_len(&atmel_port->sg_rx)/2,
1053 DMA_DEV_TO_MEM,
1054 DMA_PREP_INTERRUPT);
1055 desc->callback = atmel_complete_rx_dma;
1056 desc->callback_param = port;
1057 atmel_port->desc_rx = desc;
1058 atmel_port->cookie_rx = dmaengine_submit(desc);
1059
1060 return 0;
1061
1062chan_err:
1063 dev_err(port->dev, "RX channel not available, switch to pio\n");
1064 atmel_port->use_dma_rx = 0;
1065 if (atmel_port->chan_rx)
1066 atmel_release_rx_dma(port);
1067 return -EINVAL;
1068}
1069
2e68c22f
ES		 1070static void atmel_uart_timer_callback(unsigned long data)
1071{
1072 struct uart_port *port = (void *)data;
1073 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1074
1075 tasklet_schedule(&atmel_port->tasklet);
1076 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1077}
1078
b843aa21
RB		 1079/*
1080 * receive interrupt handler.
1081 */
1082static void
1083atmel_handle_receive(struct uart_port *port, unsigned int pending)
1084{
c811ab8c 1085 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1086
64e22ebe 1087 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1088 /*
1089 * PDC receive. Just schedule the tasklet and let it
1090 * figure out the details.
1091 *
1092 * TODO: We're not handling error flags correctly at
1093 * the moment.
1094 */
1095 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1096 UART_PUT_IDR(port, (ATMEL_US_ENDRX
1097 | ATMEL_US_TIMEOUT));
1098 tasklet_schedule(&atmel_port->tasklet);
1099 }
1100
1101 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1102 ATMEL_US_FRAME | ATMEL_US_PARE))
1103 atmel_pdc_rxerr(port, pending);
1104 }
1105
34df42f5
ES		 1106 if (atmel_use_dma_rx(port)) {
1107 if (pending & ATMEL_US_TIMEOUT) {
1108 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
1109 tasklet_schedule(&atmel_port->tasklet);
1110 }
1111 }
1112
b843aa21
RB		 1113 /* Interrupt receive */
1114 if (pending & ATMEL_US_RXRDY)
1115 atmel_rx_chars(port);
1116 else if (pending & ATMEL_US_RXBRK) {
1117 /*
1118 * End of break detected. If it came along with a
1119 * character, atmel_rx_chars will handle it.
1120 */
1121 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1122 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1123 atmel_port->break_active = 0;
1124 }
1125}
1126
1127/*
1ecc26bd 1128 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1129 */
1130static void
1131atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1132{
c811ab8c 1133 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1134
e8faff73
CS		 1135 if (pending & atmel_port->tx_done_mask) {
1136 /* Either PDC or interrupt transmission */
1137 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1138 tasklet_schedule(&atmel_port->tasklet);
1ecc26bd 1139 }
b843aa21
RB		 1140}
1141
1142/*
1143 * status flags interrupt handler.
1144 */
1145static void
1146atmel_handle_status(struct uart_port *port, unsigned int pending,
1147 unsigned int status)
1148{
c811ab8c 1149 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1150
b843aa21 1151 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB		 1152 | ATMEL_US_CTSIC)) {
1153 atmel_port->irq_status = status;
1154 tasklet_schedule(&atmel_port->tasklet);
1155 }
b843aa21
RB		 1156}
1157
1e6c9c28
AV		 1158/*
1159 * Interrupt handler
1160 */
7d12e780 1161static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1162{
1163 struct uart_port *port = dev_id;
ab5e4e41 1164 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 1165 unsigned int status, pending, pass_counter = 0;
ab5e4e41 1166 bool gpio_handled = false;
1e6c9c28 1167
a6670615 1168 do {
e0b0baad 1169 status = atmel_get_lines_status(port);
a6670615 1170 pending = status & UART_GET_IMR(port);
ab5e4e41
RG		 1171 if (!gpio_handled) {
1172 /*
1173 * Dealing with GPIO interrupt
1174 */
1175 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1176 pending |= ATMEL_US_CTSIC;
1177
1178 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1179 pending |= ATMEL_US_DSRIC;
1180
1181 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1182 pending |= ATMEL_US_RIIC;
1183
1184 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1185 pending |= ATMEL_US_DCDIC;
1186
1187 gpio_handled = true;
1188 }
a6670615
CC		 1189 if (!pending)
1190 break;
1191
b843aa21
RB		 1192 atmel_handle_receive(port, pending);
1193 atmel_handle_status(port, pending, status);
1194 atmel_handle_transmit(port, pending);
a6670615 1195 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1196
0400b697 1197 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1198}
1e6c9c28 1199
a930e528
ES		 1200static void atmel_release_tx_pdc(struct uart_port *port)
1201{
1202 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1203 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1204
1205 dma_unmap_single(port->dev,
1206 pdc->dma_addr,
1207 pdc->dma_size,
1208 DMA_TO_DEVICE);
1209}
1210
a6670615
CC		 1211/*
1212 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1213 */
64e22ebe 1214static void atmel_tx_pdc(struct uart_port *port)
a6670615 1215{
c811ab8c 1216 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1217 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1218 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1219 int count;
1220
ba0657ff
MT		 1221 /* nothing left to transmit? */
1222 if (UART_GET_TCR(port))
1223 return;
1224
a6670615
CC		 1225 xmit->tail += pdc->ofs;
1226 xmit->tail &= UART_XMIT_SIZE - 1;
1227
1228 port->icount.tx += pdc->ofs;
1229 pdc->ofs = 0;
1230
ba0657ff 1231 /* more to transmit - setup next transfer */
a6670615 1232
ba0657ff
MT		 1233 /* disable PDC transmit */
1234 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1235
1f14081d 1236 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1237 dma_sync_single_for_device(port->dev,
1238 pdc->dma_addr,
1239 pdc->dma_size,
1240 DMA_TO_DEVICE);
1241
1242 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1243 pdc->ofs = count;
1244
1245 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1246 UART_PUT_TCR(port, count);
e8faff73 1247 /* re-enable PDC transmit */
a6670615 1248 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
e8faff73
CS		 1249 /* Enable interrupts */
1250 UART_PUT_IER(port, atmel_port->tx_done_mask);
1251 } else {
13bd3e6f
RRD		 1252 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1253 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
e8faff73
CS		 1254 /* DMA done, stop TX, start RX for RS485 */
1255 atmel_start_rx(port);
1256 }
1e6c9c28 1257 }
a6670615
CC		 1258
1259 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1260 uart_write_wakeup(port);
1e6c9c28
AV		 1261}
1262
a930e528
ES		 1263static int atmel_prepare_tx_pdc(struct uart_port *port)
1264{
1265 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1266 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1267 struct circ_buf *xmit = &port->state->xmit;
1268
1269 pdc->buf = xmit->buf;
1270 pdc->dma_addr = dma_map_single(port->dev,
1271 pdc->buf,
1272 UART_XMIT_SIZE,
1273 DMA_TO_DEVICE);
1274 pdc->dma_size = UART_XMIT_SIZE;
1275 pdc->ofs = 0;
1276
1277 return 0;
1278}
1279
1ecc26bd
RB		 1280static void atmel_rx_from_ring(struct uart_port *port)
1281{
c811ab8c 1282 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1283 struct circ_buf *ring = &atmel_port->rx_ring;
1284 unsigned int flg;
1285 unsigned int status;
1286
1287 while (ring->head != ring->tail) {
1288 struct atmel_uart_char c;
1289
1290 /* Make sure c is loaded after head. */
1291 smp_rmb();
1292
1293 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1294
1295 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1296
1297 port->icount.rx++;
1298 status = c.status;
1299 flg = TTY_NORMAL;
1300
1301 /*
1302 * note that the error handling code is
1303 * out of the main execution path
1304 */
1305 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1306 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1307 if (status & ATMEL_US_RXBRK) {
1308 /* ignore side-effect */
1309 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1310
1311 port->icount.brk++;
1312 if (uart_handle_break(port))
1313 continue;
1314 }
1315 if (status & ATMEL_US_PARE)
1316 port->icount.parity++;
1317 if (status & ATMEL_US_FRAME)
1318 port->icount.frame++;
1319 if (status & ATMEL_US_OVRE)
1320 port->icount.overrun++;
1321
1322 status &= port->read_status_mask;
1323
1324 if (status & ATMEL_US_RXBRK)
1325 flg = TTY_BREAK;
1326 else if (status & ATMEL_US_PARE)
1327 flg = TTY_PARITY;
1328 else if (status & ATMEL_US_FRAME)
1329 flg = TTY_FRAME;
1330 }
1331
1332
1333 if (uart_handle_sysrq_char(port, c.ch))
1334 continue;
1335
1336 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1337 }
1338
1339 /*
1340 * Drop the lock here since it might end up calling
1341 * uart_start(), which takes the lock.
1342 */
1343 spin_unlock(&port->lock);
2e124b4a 1344 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1345 spin_lock(&port->lock);
1346}
1347
a930e528
ES		 1348static void atmel_release_rx_pdc(struct uart_port *port)
1349{
1350 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1351 int i;
1352
1353 for (i = 0; i < 2; i++) {
1354 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1355
1356 dma_unmap_single(port->dev,
1357 pdc->dma_addr,
1358 pdc->dma_size,
1359 DMA_FROM_DEVICE);
1360 kfree(pdc->buf);
1361 }
1362}
1363
64e22ebe 1364static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1365{
c811ab8c 1366 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1367 struct tty_port *tport = &port->state->port;
a6670615
CC		 1368 struct atmel_dma_buffer *pdc;
1369 int rx_idx = atmel_port->pdc_rx_idx;
1370 unsigned int head;
1371 unsigned int tail;
1372 unsigned int count;
1373
1374 do {
1375 /* Reset the UART timeout early so that we don't miss one */
1376 UART_PUT_CR(port, ATMEL_US_STTTO);
1377
1378 pdc = &atmel_port->pdc_rx[rx_idx];
1379 head = UART_GET_RPR(port) - pdc->dma_addr;
1380 tail = pdc->ofs;
1381
1382 /* If the PDC has switched buffers, RPR won't contain
1383 * any address within the current buffer. Since head
1384 * is unsigned, we just need a one-way comparison to
1385 * find out.
1386 *
1387 * In this case, we just need to consume the entire
1388 * buffer and resubmit it for DMA. This will clear the
1389 * ENDRX bit as well, so that we can safely re-enable
1390 * all interrupts below.
1391 */
1392 head = min(head, pdc->dma_size);
1393
1394 if (likely(head != tail)) {
1395 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1396 pdc->dma_size, DMA_FROM_DEVICE);
1397
1398 /*
1399 * head will only wrap around when we recycle
1400 * the DMA buffer, and when that happens, we
1401 * explicitly set tail to 0. So head will
1402 * always be greater than tail.
1403 */
1404 count = head - tail;
1405
05c7cd39
JS		 1406 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1407 count);
a6670615
CC		 1408
1409 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1410 pdc->dma_size, DMA_FROM_DEVICE);
1411
1412 port->icount.rx += count;
1413 pdc->ofs = head;
1414 }
1415
1416 /*
1417 * If the current buffer is full, we need to check if
1418 * the next one contains any additional data.
1419 */
1420 if (head >= pdc->dma_size) {
1421 pdc->ofs = 0;
1422 UART_PUT_RNPR(port, pdc->dma_addr);
1423 UART_PUT_RNCR(port, pdc->dma_size);
1424
1425 rx_idx = !rx_idx;
1426 atmel_port->pdc_rx_idx = rx_idx;
1427 }
1428 } while (head >= pdc->dma_size);
1429
1430 /*
1431 * Drop the lock here since it might end up calling
1432 * uart_start(), which takes the lock.
1433 */
1434 spin_unlock(&port->lock);
2e124b4a 1435 tty_flip_buffer_push(tport);
a6670615
CC		 1436 spin_lock(&port->lock);
1437
1438 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1439}
1440
a930e528
ES		 1441static int atmel_prepare_rx_pdc(struct uart_port *port)
1442{
1443 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1444 int i;
1445
1446 for (i = 0; i < 2; i++) {
1447 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1448
1449 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1450 if (pdc->buf == NULL) {
1451 if (i != 0) {
1452 dma_unmap_single(port->dev,
1453 atmel_port->pdc_rx[0].dma_addr,
1454 PDC_BUFFER_SIZE,
1455 DMA_FROM_DEVICE);
1456 kfree(atmel_port->pdc_rx[0].buf);
1457 }
1458 atmel_port->use_pdc_rx = 0;
1459 return -ENOMEM;
1460 }
1461 pdc->dma_addr = dma_map_single(port->dev,
1462 pdc->buf,
1463 PDC_BUFFER_SIZE,
1464 DMA_FROM_DEVICE);
1465 pdc->dma_size = PDC_BUFFER_SIZE;
1466 pdc->ofs = 0;
1467 }
1468
1469 atmel_port->pdc_rx_idx = 0;
1470
1471 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1472 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1473
1474 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1475 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1476
1477 return 0;
1478}
1479
1ecc26bd
RB		 1480/*
1481 * tasklet handling tty stuff outside the interrupt handler.
1482 */
1483static void atmel_tasklet_func(unsigned long data)
1484{
1485 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1486 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1487 unsigned int status;
1488 unsigned int status_change;
1489
1490 /* The interrupt handler does not take the lock */
1491 spin_lock(&port->lock);
1492
a930e528 1493 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1494
1495 status = atmel_port->irq_status;
1496 status_change = status ^ atmel_port->irq_status_prev;
1497
1498 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1499 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1500 /* TODO: All reads to CSR will clear these interrupts! */
1501 if (status_change & ATMEL_US_RI)
1502 port->icount.rng++;
1503 if (status_change & ATMEL_US_DSR)
1504 port->icount.dsr++;
1505 if (status_change & ATMEL_US_DCD)
1506 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1507 if (status_change & ATMEL_US_CTS)
1508 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1509
bdc04e31 1510 wake_up_interruptible(&port->state->port.delta_msr_wait);
1ecc26bd
RB		 1511
1512 atmel_port->irq_status_prev = status;
1513 }
1514
a930e528 1515 atmel_port->schedule_rx(port);
1ecc26bd
RB		 1516
1517 spin_unlock(&port->lock);
1518}
1519
33d64c4f
ES		 1520static int atmel_init_property(struct atmel_uart_port *atmel_port,
1521 struct platform_device *pdev)
1522{
1523 struct device_node *np = pdev->dev.of_node;
574de559 1524 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1525
1526 if (np) {
1527 /* DMA/PDC usage specification */
1528 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1529 if (of_get_property(np, "dmas", NULL)) {
1530 atmel_port->use_dma_rx = true;
1531 atmel_port->use_pdc_rx = false;
1532 } else {
1533 atmel_port->use_dma_rx = false;
1534 atmel_port->use_pdc_rx = true;
1535 }
1536 } else {
1537 atmel_port->use_dma_rx = false;
1538 atmel_port->use_pdc_rx = false;
1539 }
1540
1541 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1542 if (of_get_property(np, "dmas", NULL)) {
1543 atmel_port->use_dma_tx = true;
1544 atmel_port->use_pdc_tx = false;
1545 } else {
1546 atmel_port->use_dma_tx = false;
1547 atmel_port->use_pdc_tx = true;
1548 }
1549 } else {
1550 atmel_port->use_dma_tx = false;
1551 atmel_port->use_pdc_tx = false;
1552 }
1553
1554 } else {
1555 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1556 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1557 atmel_port->use_dma_rx = false;
1558 atmel_port->use_dma_tx = false;
1559 }
1560
1561 return 0;
1562}
1563
13bd3e6f 1564static void atmel_init_rs485(struct uart_port *port,
33d64c4f
ES		 1565 struct platform_device *pdev)
1566{
1567 struct device_node *np = pdev->dev.of_node;
574de559 1568 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1569
1570 if (np) {
1571 u32 rs485_delay[2];
1572 /* rs485 properties */
1573 if (of_property_read_u32_array(np, "rs485-rts-delay",
1574 rs485_delay, 2) == 0) {
13bd3e6f 1575 struct serial_rs485 *rs485conf = &port->rs485;
33d64c4f
ES		 1576
1577 rs485conf->delay_rts_before_send = rs485_delay[0];
1578 rs485conf->delay_rts_after_send = rs485_delay[1];
1579 rs485conf->flags = 0;
1580
1581 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1582 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1583
1584 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1585 NULL))
1586 rs485conf->flags |= SER_RS485_ENABLED;
1587 }
1588 } else {
13bd3e6f 1589 port->rs485 = pdata->rs485;
33d64c4f
ES		 1590 }
1591
1592}
1593
a930e528
ES		 1594static void atmel_set_ops(struct uart_port *port)
1595{
1596 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1597
34df42f5
ES		 1598 if (atmel_use_dma_rx(port)) {
1599 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1600 atmel_port->schedule_rx = &atmel_rx_from_dma;
1601 atmel_port->release_rx = &atmel_release_rx_dma;
1602 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1603 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1604 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1605 atmel_port->release_rx = &atmel_release_rx_pdc;
1606 } else {
1607 atmel_port->prepare_rx = NULL;
1608 atmel_port->schedule_rx = &atmel_rx_from_ring;
1609 atmel_port->release_rx = NULL;
1610 }
1611
08f738be
ES		 1612 if (atmel_use_dma_tx(port)) {
1613 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1614 atmel_port->schedule_tx = &atmel_tx_dma;
1615 atmel_port->release_tx = &atmel_release_tx_dma;
1616 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1617 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1618 atmel_port->schedule_tx = &atmel_tx_pdc;
1619 atmel_port->release_tx = &atmel_release_tx_pdc;
1620 } else {
1621 atmel_port->prepare_tx = NULL;
1622 atmel_port->schedule_tx = &atmel_tx_chars;
1623 atmel_port->release_tx = NULL;
1624 }
1625}
1626
055560b0
ES		 1627/*
1628 * Get ip name usart or uart
1629 */
892db58b 1630static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1631{
1632 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1633 int name = UART_GET_IP_NAME(port);
731d9cae 1634 u32 version;
055560b0
ES		 1635 int usart, uart;
1636 /* usart and uart ascii */
1637 usart = 0x55534152;
1638 uart = 0x44424755;
1639
1640 atmel_port->is_usart = false;
1641
1642 if (name == usart) {
1643 dev_dbg(port->dev, "This is usart\n");
1644 atmel_port->is_usart = true;
1645 } else if (name == uart) {
1646 dev_dbg(port->dev, "This is uart\n");
1647 atmel_port->is_usart = false;
1648 } else {
731d9cae
NF		 1649 /* fallback for older SoCs: use version field */
1650 version = UART_GET_IP_VERSION(port);
1651 switch (version) {
1652 case 0x302:
1653 case 0x10213:
1654 dev_dbg(port->dev, "This version is usart\n");
1655 atmel_port->is_usart = true;
1656 break;
1657 case 0x203:
1658 case 0x10202:
1659 dev_dbg(port->dev, "This version is uart\n");
1660 atmel_port->is_usart = false;
1661 break;
1662 default:
1663 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1664 }
055560b0 1665 }
055560b0
ES		 1666}
1667
ab5e4e41
RG		 1668static void atmel_free_gpio_irq(struct uart_port *port)
1669{
1670 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1671 enum mctrl_gpio_idx i;
1672
1673 for (i = 0; i < UART_GPIO_MAX; i++)
1674 if (atmel_port->gpio_irq[i] >= 0)
1675 free_irq(atmel_port->gpio_irq[i], port);
1676}
1677
1678static int atmel_request_gpio_irq(struct uart_port *port)
1679{
1680 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1681 int *irq = atmel_port->gpio_irq;
1682 enum mctrl_gpio_idx i;
1683 int err = 0;
1684
1685 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1686 if (irq[i] < 0)
1687 continue;
1688
1689 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1690 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1691 "atmel_serial", port);
1692 if (err)
1693 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1694 irq[i]);
1695 }
1696
1697 /*
1698 * If something went wrong, rollback.
1699 */
1700 while (err && (--i >= 0))
1701 if (irq[i] >= 0)
1702 free_irq(irq[i], port);
1703
1704 return err;
1705}
1706
1e6c9c28
AV		 1707/*
1708 * Perform initialization and enable port for reception
1709 */
7192f92c 1710static int atmel_startup(struct uart_port *port)
1e6c9c28 1711{
33d64c4f 1712 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1713 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1714 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV		 1715 int retval;
1716
1717 /*
1718 * Ensure that no interrupts are enabled otherwise when
1719 * request_irq() is called we could get stuck trying to
1720 * handle an unexpected interrupt
1721 */
1722 UART_PUT_IDR(port, -1);
ab5e4e41 1723 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1724
1725 /*
1726 * Allocate the IRQ
1727 */
b843aa21 1728 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
ae161068 1729 tty ? tty->name : "atmel_serial", port);
1e6c9c28 1730 if (retval) {
ddaa6037 1731 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1732 return retval;
1733 }
1734
ab5e4e41
RG		 1735 /*
1736 * Get the GPIO lines IRQ
1737 */
1738 retval = atmel_request_gpio_irq(port);
1739 if (retval)
1740 goto free_irq;
1741
a6670615
CC		 1742 /*
1743 * Initialize DMA (if necessary)
1744 */
33d64c4f
ES		 1745 atmel_init_property(atmel_port, pdev);
1746
a930e528
ES		 1747 if (atmel_port->prepare_rx) {
1748 retval = atmel_port->prepare_rx(port);
1749 if (retval < 0)
1750 atmel_set_ops(port);
a6670615 1751 }
a6670615 1752
a930e528
ES		 1753 if (atmel_port->prepare_tx) {
1754 retval = atmel_port->prepare_tx(port);
1755 if (retval < 0)
1756 atmel_set_ops(port);
a6670615 1757 }
1e6c9c28 1758
27c0c8e5 1759 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 1760 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5
AN		 1761 atmel_port->irq_status = atmel_port->irq_status_prev;
1762
1e6c9c28
AV		 1763 /*
1764 * Finally, enable the serial port
1765 */
7192f92c 1766 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB		 1767 /* enable xmit & rcvr */
1768 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 1769
8bc661bf
MR		 1770 setup_timer(&atmel_port->uart_timer,
1771 atmel_uart_timer_callback,
1772 (unsigned long)port);
1773
64e22ebe 1774 if (atmel_use_pdc_rx(port)) {
a6670615 1775 /* set UART timeout */
2e68c22f 1776 if (!atmel_port->is_usart) {
2e68c22f
ES		 1777 mod_timer(&atmel_port->uart_timer,
1778 jiffies + uart_poll_timeout(port));
1779 /* set USART timeout */
1780 } else {
1781 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1782 UART_PUT_CR(port, ATMEL_US_STTTO);
a6670615 1783
2e68c22f
ES		 1784 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1785 }
a6670615
CC		 1786 /* enable PDC controller */
1787 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
34df42f5 1788 } else if (atmel_use_dma_rx(port)) {
2e68c22f
ES		 1789 /* set UART timeout */
1790 if (!atmel_port->is_usart) {
2e68c22f
ES		 1791 mod_timer(&atmel_port->uart_timer,
1792 jiffies + uart_poll_timeout(port));
1793 /* set USART timeout */
1794 } else {
1795 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1796 UART_PUT_CR(port, ATMEL_US_STTTO);
34df42f5 1797
2e68c22f
ES		 1798 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1799 }
a6670615
CC		 1800 } else {
1801 /* enable receive only */
1802 UART_PUT_IER(port, ATMEL_US_RXRDY);
1803 }
afefc415 1804
1e6c9c28 1805 return 0;
ab5e4e41
RG		 1806
1807free_irq:
1808 free_irq(port->irq, port);
1809
1810 return retval;
1e6c9c28
AV		 1811}
1812
479e9b94
PH		 1813/*
1814 * Flush any TX data submitted for DMA. Called when the TX circular
1815 * buffer is reset.
1816 */
1817static void atmel_flush_buffer(struct uart_port *port)
1818{
1819 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1820
1821 if (atmel_use_pdc_tx(port)) {
1822 UART_PUT_TCR(port, 0);
1823 atmel_port->pdc_tx.ofs = 0;
1824 }
1825}
1826
1e6c9c28
AV		 1827/*
1828 * Disable the port
1829 */
7192f92c 1830static void atmel_shutdown(struct uart_port *port)
1e6c9c28 1831{
c811ab8c 1832 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 1833
8bc661bf
MR		 1834 /*
1835 * Prevent any tasklets being scheduled during
1836 * cleanup
1837 */
1838 del_timer_sync(&atmel_port->uart_timer);
1839
0cc7c6c7
MR		 1840 /*
1841 * Clear out any scheduled tasklets before
1842 * we destroy the buffers
1843 */
1844 tasklet_kill(&atmel_port->tasklet);
1845
a6670615 1846 /*
0cc7c6c7
MR		 1847 * Ensure everything is stopped and
1848 * disable all interrupts, port and break condition.
a6670615
CC		 1849 */
1850 atmel_stop_rx(port);
1851 atmel_stop_tx(port);
1852
0cc7c6c7
MR		 1853 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1854 UART_PUT_IDR(port, -1);
1855
1856
a6670615
CC		 1857 /*
1858 * Shut-down the DMA.
1859 */
a930e528
ES		 1860 if (atmel_port->release_rx)
1861 atmel_port->release_rx(port);
1862 if (atmel_port->release_tx)
1863 atmel_port->release_tx(port);
a6670615 1864
bb7e73c5
MD		 1865 /*
1866 * Reset ring buffer pointers
1867 */
1868 atmel_port->rx_ring.head = 0;
1869 atmel_port->rx_ring.tail = 0;
1870
1e6c9c28 1871 /*
ab5e4e41 1872 * Free the interrupts
1e6c9c28
AV		 1873 */
1874 free_irq(port->irq, port);
ab5e4e41
RG		 1875 atmel_free_gpio_irq(port);
1876
1877 atmel_port->ms_irq_enabled = false;
1e6c9c28 1878
479e9b94 1879 atmel_flush_buffer(port);
9afd561a
HS		 1880}
1881
1e6c9c28
AV		 1882/*
1883 * Power / Clock management.
1884 */
b843aa21
RB		 1885static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1886 unsigned int oldstate)
1e6c9c28 1887{
c811ab8c 1888 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1889
1e6c9c28 1890 switch (state) {
b843aa21
RB		 1891 case 0:
1892 /*
1893 * Enable the peripheral clock for this serial port.
1894 * This is called on uart_open() or a resume event.
1895 */
91f8c2d8 1896 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 1897
1898 /* re-enable interrupts if we disabled some on suspend */
1899 UART_PUT_IER(port, atmel_port->backup_imr);
b843aa21
RB		 1900 break;
1901 case 3:
f05596db
AS		 1902 /* Back up the interrupt mask and disable all interrupts */
1903 atmel_port->backup_imr = UART_GET_IMR(port);
1904 UART_PUT_IDR(port, -1);
1905
b843aa21
RB		 1906 /*
1907 * Disable the peripheral clock for this serial port.
1908 * This is called on uart_close() or a suspend event.
1909 */
91f8c2d8 1910 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 1911 break;
1912 default:
ddaa6037 1913 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 1914 }
1915}
1916
1917/*
1918 * Change the port parameters
1919 */
b843aa21
RB		 1920static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1921 struct ktermios *old)
1e6c9c28
AV		 1922{
1923 unsigned long flags;
1924 unsigned int mode, imr, quot, baud;
1925
03abeac0 1926 /* Get current mode register */
b843aa21 1927 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
8e706c4d
PM		 1928 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1929 | ATMEL_US_USMODE);
03abeac0 1930
b843aa21 1931 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 1932 quot = uart_get_divisor(port, baud);
1933
b843aa21 1934 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV		 1935 quot /= 8;
1936 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1937 }
1e6c9c28
AV		 1938
1939 /* byte size */
1940 switch (termios->c_cflag & CSIZE) {
1941 case CS5:
7192f92c 1942 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 1943 break;
1944 case CS6:
7192f92c 1945 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 1946 break;
1947 case CS7:
7192f92c 1948 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 1949 break;
1950 default:
7192f92c 1951 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 1952 break;
1953 }
1954
1955 /* stop bits */
1956 if (termios->c_cflag & CSTOPB)
7192f92c 1957 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 1958
1959 /* parity */
1960 if (termios->c_cflag & PARENB) {
b843aa21
RB		 1961 /* Mark or Space parity */
1962 if (termios->c_cflag & CMSPAR) {
1e6c9c28 1963 if (termios->c_cflag & PARODD)
7192f92c 1964 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 1965 else
7192f92c 1966 mode |= ATMEL_US_PAR_SPACE;
b843aa21 1967 } else if (termios->c_cflag & PARODD)
7192f92c 1968 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 1969 else
7192f92c 1970 mode |= ATMEL_US_PAR_EVEN;
b843aa21 1971 } else
7192f92c 1972 mode |= ATMEL_US_PAR_NONE;
1e6c9c28 1973
8e706c4d
PM		 1974 /* hardware handshake (RTS/CTS) */
1975 if (termios->c_cflag & CRTSCTS)
1976 mode |= ATMEL_US_USMODE_HWHS;
1977 else
1978 mode |= ATMEL_US_USMODE_NORMAL;
1979
1e6c9c28
AV		 1980 spin_lock_irqsave(&port->lock, flags);
1981
7192f92c 1982 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 1983 if (termios->c_iflag & INPCK)
7192f92c 1984 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 1985 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 1986 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 1987
64e22ebe 1988 if (atmel_use_pdc_rx(port))
a6670615
CC		 1989 /* need to enable error interrupts */
1990 UART_PUT_IER(port, port->read_status_mask);
1991
1e6c9c28
AV		 1992 /*
1993 * Characters to ignore
1994 */
1995 port->ignore_status_mask = 0;
1996 if (termios->c_iflag & IGNPAR)
7192f92c 1997 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1998 if (termios->c_iflag & IGNBRK) {
7192f92c 1999 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2000 /*
2001 * If we're ignoring parity and break indicators,
2002 * ignore overruns too (for real raw support).
2003 */
2004 if (termios->c_iflag & IGNPAR)
7192f92c 2005 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2006 }
b843aa21 2007 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2008
2009 /* update the per-port timeout */
2010 uart_update_timeout(port, termios->c_cflag, baud);
2011
0ccad870
HS		 2012 /*
2013 * save/disable interrupts. The tty layer will ensure that the
2014 * transmitter is empty if requested by the caller, so there's
2015 * no need to wait for it here.
2016 */
b843aa21
RB		 2017 imr = UART_GET_IMR(port);
2018 UART_PUT_IDR(port, -1);
1e6c9c28
AV		 2019
2020 /* disable receiver and transmitter */
7192f92c 2021 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28 2022
e8faff73
CS		 2023 /* Resetting serial mode to RS232 (0x0) */
2024 mode &= ~ATMEL_US_USMODE;
2025
13bd3e6f
RRD		 2026 if (port->rs485.flags & SER_RS485_ENABLED) {
2027 if ((port->rs485.delay_rts_after_send) > 0)
2028 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send);
e8faff73 2029 mode |= ATMEL_US_USMODE_RS485;
e8faff73
CS		 2030 }
2031
1e6c9c28
AV		 2032 /* set the parity, stop bits and data size */
2033 UART_PUT_MR(port, mode);
2034
2035 /* set the baud rate */
2036 UART_PUT_BRGR(port, quot);
7192f92c
HS		 2037 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2038 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2039
2040 /* restore interrupts */
2041 UART_PUT_IER(port, imr);
2042
2043 /* CTS flow-control and modem-status interrupts */
2044 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2045 atmel_enable_ms(port);
2046 else
2047 atmel_disable_ms(port);
1e6c9c28
AV		 2048
2049 spin_unlock_irqrestore(&port->lock, flags);
2050}
2051
732a84a0 2052static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2053{
732a84a0 2054 if (termios->c_line == N_PPS) {
42bd7a4f 2055 port->flags |= UPF_HARDPPS_CD;
d41510ce 2056 spin_lock_irq(&port->lock);
42bd7a4f 2057 atmel_enable_ms(port);
d41510ce 2058 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2059 } else {
2060 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2061 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2062 spin_lock_irq(&port->lock);
2063 atmel_disable_ms(port);
2064 spin_unlock_irq(&port->lock);
2065 }
42bd7a4f
VP		 2066 }
2067}
2068
1e6c9c28
AV		 2069/*
2070 * Return string describing the specified port
2071 */
7192f92c 2072static const char *atmel_type(struct uart_port *port)
1e6c9c28 2073{
9ab4f88b 2074 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2075}
2076
2077/*
2078 * Release the memory region(s) being used by 'port'.
2079 */
7192f92c 2080static void atmel_release_port(struct uart_port *port)
1e6c9c28 2081{
afefc415
AV		 2082 struct platform_device *pdev = to_platform_device(port->dev);
2083 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2084
2085 release_mem_region(port->mapbase, size);
2086
2087 if (port->flags & UPF_IOREMAP) {
2088 iounmap(port->membase);
2089 port->membase = NULL;
2090 }
1e6c9c28
AV		 2091}
2092
2093/*
2094 * Request the memory region(s) being used by 'port'.
2095 */
7192f92c 2096static int atmel_request_port(struct uart_port *port)
1e6c9c28 2097{
afefc415
AV		 2098 struct platform_device *pdev = to_platform_device(port->dev);
2099 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2100
7192f92c 2101 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2102 return -EBUSY;
2103
2104 if (port->flags & UPF_IOREMAP) {
2105 port->membase = ioremap(port->mapbase, size);
2106 if (port->membase == NULL) {
2107 release_mem_region(port->mapbase, size);
2108 return -ENOMEM;
2109 }
2110 }
1e6c9c28 2111
afefc415 2112 return 0;
1e6c9c28
AV		 2113}
2114
2115/*
2116 * Configure/autoconfigure the port.
2117 */
7192f92c 2118static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2119{
2120 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2121 port->type = PORT_ATMEL;
7192f92c 2122 atmel_request_port(port);
1e6c9c28
AV		 2123 }
2124}
2125
2126/*
2127 * Verify the new serial_struct (for TIOCSSERIAL).
2128 */
7192f92c 2129static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2130{
2131 int ret = 0;
9ab4f88b 2132 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2133 ret = -EINVAL;
2134 if (port->irq != ser->irq)
2135 ret = -EINVAL;
2136 if (ser->io_type != SERIAL_IO_MEM)
2137 ret = -EINVAL;
2138 if (port->uartclk / 16 != ser->baud_base)
2139 ret = -EINVAL;
2140 if ((void *)port->mapbase != ser->iomem_base)
2141 ret = -EINVAL;
2142 if (port->iobase != ser->port)
2143 ret = -EINVAL;
2144 if (ser->hub6 != 0)
2145 ret = -EINVAL;
2146 return ret;
2147}
2148
8fe2d541
AT		 2149#ifdef CONFIG_CONSOLE_POLL
2150static int atmel_poll_get_char(struct uart_port *port)
2151{
2152 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
2153 cpu_relax();
2154
2155 return UART_GET_CHAR(port);
2156}
2157
2158static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2159{
2160 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2161 cpu_relax();
2162
2163 UART_PUT_CHAR(port, ch);
2164}
2165#endif
2166
7192f92c
HS		 2167static struct uart_ops atmel_pops = {
2168 .tx_empty = atmel_tx_empty,
2169 .set_mctrl = atmel_set_mctrl,
2170 .get_mctrl = atmel_get_mctrl,
2171 .stop_tx = atmel_stop_tx,
2172 .start_tx = atmel_start_tx,
2173 .stop_rx = atmel_stop_rx,
2174 .enable_ms = atmel_enable_ms,
2175 .break_ctl = atmel_break_ctl,
2176 .startup = atmel_startup,
2177 .shutdown = atmel_shutdown,
9afd561a 2178 .flush_buffer = atmel_flush_buffer,
7192f92c 2179 .set_termios = atmel_set_termios,
42bd7a4f 2180 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2181 .type = atmel_type,
2182 .release_port = atmel_release_port,
2183 .request_port = atmel_request_port,
2184 .config_port = atmel_config_port,
2185 .verify_port = atmel_verify_port,
2186 .pm = atmel_serial_pm,
8fe2d541
AT		 2187#ifdef CONFIG_CONSOLE_POLL
2188 .poll_get_char = atmel_poll_get_char,
2189 .poll_put_char = atmel_poll_put_char,
2190#endif
1e6c9c28
AV		 2191};
2192
afefc415
AV		 2193/*
2194 * Configure the port from the platform device resource info.
2195 */
91f8c2d8 2196static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2197 struct platform_device *pdev)
1e6c9c28 2198{
91f8c2d8 2199 int ret;
7192f92c 2200 struct uart_port *port = &atmel_port->uart;
574de559 2201 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
afefc415 2202
33d64c4f
ES		 2203 if (!atmel_init_property(atmel_port, pdev))
2204 atmel_set_ops(port);
afefc415 2205
13bd3e6f 2206 atmel_init_rs485(port, pdev);
a930e528 2207
e8faff73
CS		 2208 port->iotype = UPIO_MEM;
2209 port->flags = UPF_BOOT_AUTOCONF;
2210 port->ops = &atmel_pops;
2211 port->fifosize = 1;
e8faff73 2212 port->dev = &pdev->dev;
afefc415
AV		 2213 port->mapbase = pdev->resource[0].start;
2214 port->irq = pdev->resource[1].start;
13bd3e6f 2215 port->rs485_config = atmel_config_rs485;
afefc415 2216
1ecc26bd
RB		 2217 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2218 (unsigned long)port);
2219
2220 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2221
5fbe46b6 2222 if (pdata && pdata->regs) {
75d35213 2223 /* Already mapped by setup code */
1acfc7ec 2224 port->membase = pdata->regs;
588edbf3 2225 } else {
afefc415
AV		 2226 port->flags |= UPF_IOREMAP;
2227 port->membase = NULL;
2228 }
1e6c9c28 2229
b843aa21
RB		 2230 /* for console, the clock could already be configured */
2231 if (!atmel_port->clk) {
7192f92c 2232 atmel_port->clk = clk_get(&pdev->dev, "usart");
91f8c2d8
BB		 2233 if (IS_ERR(atmel_port->clk)) {
2234 ret = PTR_ERR(atmel_port->clk);
2235 atmel_port->clk = NULL;
2236 return ret;
2237 }
2238 ret = clk_prepare_enable(atmel_port->clk);
2239 if (ret) {
2240 clk_put(atmel_port->clk);
2241 atmel_port->clk = NULL;
2242 return ret;
2243 }
7192f92c 2244 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2245 clk_disable_unprepare(atmel_port->clk);
06a7f058 2246 /* only enable clock when USART is in use */
afefc415 2247 }
a6670615 2248
e8faff73 2249 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
13bd3e6f 2250 if (port->rs485.flags & SER_RS485_ENABLED)
e8faff73 2251 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2252 else if (atmel_use_pdc_tx(port)) {
a6670615 2253 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2254 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2255 } else {
2256 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2257 }
91f8c2d8
BB		 2258
2259 return 0;
1e6c9c28
AV		 2260}
2261
69f6a27b
JCPV		 2262struct platform_device *atmel_default_console_device; /* the serial console device */
2263
749c4e60 2264#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2265static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2266{
7192f92c 2267 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 2268 cpu_relax();
d358788f
RK		 2269 UART_PUT_CHAR(port, ch);
2270}
1e6c9c28
AV		 2271
2272/*
2273 * Interrupts are disabled on entering
2274 */
7192f92c 2275static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2276{
7192f92c 2277 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2279 unsigned int status, imr;
39d4c922 2280 unsigned int pdc_tx;
1e6c9c28
AV		 2281
2282 /*
b843aa21 2283 * First, save IMR and then disable interrupts
1e6c9c28 2284 */
b843aa21 2285 imr = UART_GET_IMR(port);
e8faff73 2286 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2287
39d4c922
MP		 2288 /* Store PDC transmit status and disable it */
2289 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2290 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2291
7192f92c 2292 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2293
2294 /*
b843aa21
RB		 2295 * Finally, wait for transmitter to become empty
2296 * and restore IMR
1e6c9c28
AV		 2297 */
2298 do {
2299 status = UART_GET_CSR(port);
7192f92c 2300 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2301
2302 /* Restore PDC transmit status */
2303 if (pdc_tx)
2304 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2305
b843aa21
RB		 2306 /* set interrupts back the way they were */
2307 UART_PUT_IER(port, imr);
1e6c9c28
AV		 2308}
2309
2310/*
b843aa21
RB		 2311 * If the port was already initialised (eg, by a boot loader),
2312 * try to determine the current setup.
1e6c9c28 2313 */
b843aa21
RB		 2314static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2315 int *parity, int *bits)
1e6c9c28
AV		 2316{
2317 unsigned int mr, quot;
2318
1c0fd82f
HS		 2319 /*
2320 * If the baud rate generator isn't running, the port wasn't
2321 * initialized by the boot loader.
2322 */
9c81c5c9 2323 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1c0fd82f
HS		 2324 if (!quot)
2325 return;
1e6c9c28 2326
7192f92c
HS		 2327 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2328 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2329 *bits = 8;
2330 else
2331 *bits = 7;
2332
7192f92c
HS		 2333 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2334 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2335 *parity = 'e';
7192f92c 2336 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2337 *parity = 'o';
2338
4d5e392c
HS		 2339 /*
2340 * The serial core only rounds down when matching this to a
2341 * supported baud rate. Make sure we don't end up slightly
2342 * lower than one of those, as it would make us fall through
2343 * to a much lower baud rate than we really want.
2344 */
4d5e392c 2345 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2346}
2347
7192f92c 2348static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2349{
91f8c2d8 2350 int ret;
7192f92c 2351 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV		 2352 int baud = 115200;
2353 int bits = 8;
2354 int parity = 'n';
2355 int flow = 'n';
2356
b843aa21
RB		 2357 if (port->membase == NULL) {
2358 /* Port not initialized yet - delay setup */
afefc415 2359 return -ENODEV;
b843aa21 2360 }
1e6c9c28 2361
91f8c2d8
BB		 2362 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2363 if (ret)
2364 return ret;
06a7f058 2365
b843aa21 2366 UART_PUT_IDR(port, -1);
7192f92c
HS		 2367 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2368 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2369
2370 if (options)
2371 uart_parse_options(options, &baud, &parity, &bits, &flow);
2372 else
7192f92c 2373 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2374
2375 return uart_set_options(port, co, baud, parity, bits, flow);
2376}
2377
7192f92c 2378static struct uart_driver atmel_uart;
1e6c9c28 2379
7192f92c
HS		 2380static struct console atmel_console = {
2381 .name = ATMEL_DEVICENAME,
2382 .write = atmel_console_write,
1e6c9c28 2383 .device = uart_console_device,
7192f92c 2384 .setup = atmel_console_setup,
1e6c9c28
AV		 2385 .flags = CON_PRINTBUFFER,
2386 .index = -1,
7192f92c 2387 .data = &atmel_uart,
1e6c9c28
AV		 2388};
2389
06a7f058 2390#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2391
afefc415
AV		 2392/*
2393 * Early console initialization (before VM subsystem initialized).
2394 */
7192f92c 2395static int __init atmel_console_init(void)
1e6c9c28 2396{
91f8c2d8 2397 int ret;
73e2798b 2398 if (atmel_default_console_device) {
0d0a3cc1 2399 struct atmel_uart_data *pdata =
574de559 2400 dev_get_platdata(&atmel_default_console_device->dev);
efb8d21b 2401 int id = pdata->num;
4cbf9f48
NF		 2402 struct atmel_uart_port *port = &atmel_ports[id];
2403
4cbf9f48
NF		 2404 port->backup_imr = 0;
2405 port->uart.line = id;
0d0a3cc1 2406
4cbf9f48 2407 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
91f8c2d8
BB		 2408 ret = atmel_init_port(port, atmel_default_console_device);
2409 if (ret)
2410 return ret;
7192f92c 2411 register_console(&atmel_console);
afefc415 2412 }
1e6c9c28 2413
1e6c9c28
AV		 2414 return 0;
2415}
b843aa21 2416
7192f92c 2417console_initcall(atmel_console_init);
1e6c9c28 2418
afefc415
AV		 2419/*
2420 * Late console initialization.
2421 */
7192f92c 2422static int __init atmel_late_console_init(void)
afefc415 2423{
b843aa21
RB		 2424 if (atmel_default_console_device
2425 && !(atmel_console.flags & CON_ENABLED))
7192f92c 2426 register_console(&atmel_console);
afefc415
AV		 2427
2428 return 0;
2429}
b843aa21 2430
7192f92c 2431core_initcall(atmel_late_console_init);
afefc415 2432
dfa7f343
HS		 2433static inline bool atmel_is_console_port(struct uart_port *port)
2434{
2435 return port->cons && port->cons->index == port->line;
2436}
2437
1e6c9c28 2438#else
7192f92c 2439#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2440
2441static inline bool atmel_is_console_port(struct uart_port *port)
2442{
2443 return false;
2444}
1e6c9c28
AV		 2445#endif
2446
7192f92c 2447static struct uart_driver atmel_uart = {
b843aa21
RB		 2448 .owner = THIS_MODULE,
2449 .driver_name = "atmel_serial",
2450 .dev_name = ATMEL_DEVICENAME,
2451 .major = SERIAL_ATMEL_MAJOR,
2452 .minor = MINOR_START,
2453 .nr = ATMEL_MAX_UART,
2454 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2455};
2456
afefc415 2457#ifdef CONFIG_PM
f826caa4
HS		 2458static bool atmel_serial_clk_will_stop(void)
2459{
2460#ifdef CONFIG_ARCH_AT91
2461 return at91_suspend_entering_slow_clock();
2462#else
2463 return false;
2464#endif
2465}
2466
b843aa21
RB		 2467static int atmel_serial_suspend(struct platform_device *pdev,
2468 pm_message_t state)
1e6c9c28 2469{
afefc415 2470 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2471 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2472
e1c609ef
HS		 2473 if (atmel_is_console_port(port) && console_suspend_enabled) {
2474 /* Drain the TX shifter */
2475 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2476 cpu_relax();
2477 }
2478
f05596db
AS		 2479 /* we can not wake up if we're running on slow clock */
2480 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2481 if (atmel_serial_clk_will_stop())
2482 device_set_wakeup_enable(&pdev->dev, 0);
2483
2484 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2485
afefc415
AV		 2486 return 0;
2487}
1e6c9c28 2488
7192f92c 2489static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2490{
2491 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2492 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2493
f05596db
AS		 2494 uart_resume_port(&atmel_uart, port);
2495 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2496
2497 return 0;
2498}
afefc415 2499#else
7192f92c
HS		 2500#define atmel_serial_suspend NULL
2501#define atmel_serial_resume NULL
afefc415 2502#endif
1e6c9c28 2503
e0b0baad
RG		 2504static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2505{
ab5e4e41
RG		 2506 enum mctrl_gpio_idx i;
2507 struct gpio_desc *gpiod;
2508
e0b0baad
RG		 2509 p->gpios = mctrl_gpio_init(dev, 0);
2510 if (IS_ERR_OR_NULL(p->gpios))
2511 return -1;
2512
ab5e4e41
RG		 2513 for (i = 0; i < UART_GPIO_MAX; i++) {
2514 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2515 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2516 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2517 else
2518 p->gpio_irq[i] = -EINVAL;
2519 }
2520
e0b0baad
RG		 2521 return 0;
2522}
2523
9671f099 2524static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2525{
7192f92c 2526 struct atmel_uart_port *port;
5fbe46b6 2527 struct device_node *np = pdev->dev.of_node;
574de559 2528 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1ecc26bd 2529 void *data;
4cbf9f48 2530 int ret = -ENODEV;
bd737f87 2531 bool rs485_enabled;
1e6c9c28 2532
9d09daf8 2533 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2534
5fbe46b6
NF		 2535 if (np)
2536 ret = of_alias_get_id(np, "serial");
2537 else
2538 if (pdata)
2539 ret = pdata->num;
4cbf9f48
NF		 2540
2541 if (ret < 0)
5fbe46b6 2542 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2543 * auto-enumerate it */
503bded9 2544 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2545
503bded9 2546 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2547 ret = -ENODEV;
2548 goto err;
2549 }
2550
503bded9 2551 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2552 /* port already in use */
2553 ret = -EBUSY;
2554 goto err;
2555 }
2556
2557 port = &atmel_ports[ret];
f05596db 2558 port->backup_imr = 0;
4cbf9f48 2559 port->uart.line = ret;
e0b0baad
RG		 2560
2561 ret = atmel_init_gpios(port, &pdev->dev);
2562 if (ret < 0)
2563 dev_err(&pdev->dev, "%s",
2564 "Failed to initialize GPIOs. The serial port may not work as expected");
f05596db 2565
91f8c2d8
BB		 2566 ret = atmel_init_port(port, pdev);
2567 if (ret)
2568 goto err;
1e6c9c28 2569
64e22ebe 2570 if (!atmel_use_pdc_rx(&port->uart)) {
a6670615 2571 ret = -ENOMEM;
6433471d
HS		 2572 data = kmalloc(sizeof(struct atmel_uart_char)
2573 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC		 2574 if (!data)
2575 goto err_alloc_ring;
2576 port->rx_ring.buf = data;
2577 }
1ecc26bd 2578
bd737f87
RRD		 2579 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED;
2580
7192f92c 2581 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS		 2582 if (ret)
2583 goto err_add_port;
2584
8da14b5f 2585#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
06a7f058
DB		 2586 if (atmel_is_console_port(&port->uart)
2587 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2588 /*
2589 * The serial core enabled the clock for us, so undo
91f8c2d8 2590 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2591 */
91f8c2d8 2592 clk_disable_unprepare(port->clk);
06a7f058 2593 }
8da14b5f 2594#endif
06a7f058 2595
dfa7f343
HS		 2596 device_init_wakeup(&pdev->dev, 1);
2597 platform_set_drvdata(pdev, port);
2598
bd737f87 2599 if (rs485_enabled) {
5dfbd1d7
CS		 2600 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2601 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2602 }
2603
055560b0
ES		 2604 /*
2605 * Get port name of usart or uart
2606 */
892db58b 2607 atmel_get_ip_name(&port->uart);
055560b0 2608
dfa7f343
HS		 2609 return 0;
2610
2611err_add_port:
1ecc26bd
RB		 2612 kfree(port->rx_ring.buf);
2613 port->rx_ring.buf = NULL;
2614err_alloc_ring:
dfa7f343 2615 if (!atmel_is_console_port(&port->uart)) {
dfa7f343
HS		 2616 clk_put(port->clk);
2617 port->clk = NULL;
afefc415 2618 }
4cbf9f48 2619err:
afefc415
AV		 2620 return ret;
2621}
2622
ae8d8a14 2623static int atmel_serial_remove(struct platform_device *pdev)
afefc415
AV		 2624{
2625 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2626 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415
AV		 2627 int ret = 0;
2628
f50c995f
MR		 2629 tasklet_kill(&atmel_port->tasklet);
2630
afefc415 2631 device_init_wakeup(&pdev->dev, 0);
afefc415 2632
dfa7f343
HS		 2633 ret = uart_remove_one_port(&atmel_uart, port);
2634
1ecc26bd
RB		 2635 kfree(atmel_port->rx_ring.buf);
2636
dfa7f343
HS		 2637 /* "port" is allocated statically, so we shouldn't free it */
2638
503bded9 2639 clear_bit(port->line, atmel_ports_in_use);
4cbf9f48 2640
dfa7f343 2641 clk_put(atmel_port->clk);
afefc415
AV		 2642
2643 return ret;
2644}
2645
7192f92c
HS		 2646static struct platform_driver atmel_serial_driver = {
2647 .probe = atmel_serial_probe,
2d47b716 2648 .remove = atmel_serial_remove,
7192f92c
HS		 2649 .suspend = atmel_serial_suspend,
2650 .resume = atmel_serial_resume,
afefc415 2651 .driver = {
1e8ea802 2652 .name = "atmel_usart",
5fbe46b6 2653 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 2654 },
2655};
2656
7192f92c 2657static int __init atmel_serial_init(void)
afefc415
AV		 2658{
2659 int ret;
2660
7192f92c 2661 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 2662 if (ret)
2663 return ret;
2664
7192f92c 2665 ret = platform_driver_register(&atmel_serial_driver);
afefc415 2666 if (ret)
7192f92c 2667 uart_unregister_driver(&atmel_uart);
afefc415
AV		 2668
2669 return ret;
2670}
2671
7192f92c 2672static void __exit atmel_serial_exit(void)
afefc415 2673{
7192f92c
HS		 2674 platform_driver_unregister(&atmel_serial_driver);
2675 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV		 2676}
2677
7192f92c
HS		 2678module_init(atmel_serial_init);
2679module_exit(atmel_serial_exit);
1e6c9c28
AV		 2680
2681MODULE_AUTHOR("Rick Bronson");
7192f92c 2682MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 2683MODULE_LICENSE("GPL");
e169c139 2684MODULE_ALIAS("platform:atmel_usart");
Linux 6.x block layer and io_uring tree(s)