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tty: serial: Fix mediatek UART driver setting baudrate issue
[linux-2.6-block.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
7192f92c 2 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV		 3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
a6670615
CC		 8 * DMA support added by Chip Coldwell.
9 *
1e6c9c28
AV		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV		 25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
afefc415 31#include <linux/clk.h>
1e6c9c28
AV		 32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
afefc415 35#include <linux/platform_device.h>
5fbe46b6
NF		 36#include <linux/of.h>
37#include <linux/of_device.h>
354e57f3 38#include <linux/of_gpio.h>
a6670615 39#include <linux/dma-mapping.h>
6b997bab 40#include <linux/dmaengine.h>
93a3ddc2 41#include <linux/atmel_pdc.h>
fa3218d8 42#include <linux/atmel_serial.h>
e8faff73 43#include <linux/uaccess.h>
bcd2360c 44#include <linux/platform_data/atmel.h>
2e68c22f 45#include <linux/timer.h>
354e57f3 46#include <linux/gpio.h>
e0b0baad
RG		 47#include <linux/gpio/consumer.h>
48#include <linux/err.h>
ab5e4e41 49#include <linux/irq.h>
1e6c9c28
AV		 50
51#include <asm/io.h>
f7512e7c 52#include <asm/ioctls.h>
1e6c9c28 53
a6670615
CC		 54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
749c4e60 58#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 59#define SUPPORT_SYSRQ
60#endif
61
62#include <linux/serial_core.h>
63
e0b0baad
RG		 64#include "serial_mctrl_gpio.h"
65
e8faff73
CS		 66static void atmel_start_rx(struct uart_port *port);
67static void atmel_stop_rx(struct uart_port *port);
68
749c4e60 69#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 70
71/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
72 * should coexist with the 8250 driver, such as if we have an external 16C550
73 * UART. */
7192f92c 74#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 75#define MINOR_START 154
7192f92c 76#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 77
78#else
79
80/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
81 * name, but it is legally reserved for the 8250 driver. */
7192f92c 82#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 83#define MINOR_START 64
7192f92c 84#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 85
86#endif
87
7192f92c 88#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 89
b843aa21 90/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS		 91#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
92#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
93#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
94#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
95#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
96#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
97#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
98#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
99#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
100#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
101#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
102#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
e8faff73 103#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
055560b0 104#define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
731d9cae 105#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
544fc728 106
1e6c9c28 107 /* PDC registers */
544fc728
HS		 108#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
109#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
110
111#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
112#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
113#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
114#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
115#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
116
117#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
118#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
39d4c922 119#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
1e6c9c28 120
a6670615
CC		 121struct atmel_dma_buffer {
122 unsigned char *buf;
123 dma_addr_t dma_addr;
124 unsigned int dma_size;
125 unsigned int ofs;
126};
127
1ecc26bd
RB		 128struct atmel_uart_char {
129 u16 status;
130 u16 ch;
131};
132
133#define ATMEL_SERIAL_RINGSIZE 1024
134
afefc415
AV		 135/*
136 * We wrap our port structure around the generic uart_port.
137 */
7192f92c 138struct atmel_uart_port {
afefc415
AV		 139 struct uart_port uart; /* uart */
140 struct clk *clk; /* uart clock */
f05596db
AS		 141 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
142 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 143 int break_active; /* break being received */
1ecc26bd 144
34df42f5 145 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 146 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 147 short pdc_rx_idx; /* current PDC RX buffer */
148 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
149
08f738be 150 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 151 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 152 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
153
08f738be 154 spinlock_t lock_tx; /* port lock */
34df42f5 155 spinlock_t lock_rx; /* port lock */
08f738be 156 struct dma_chan *chan_tx;
34df42f5 157 struct dma_chan *chan_rx;
08f738be 158 struct dma_async_tx_descriptor *desc_tx;
34df42f5 159 struct dma_async_tx_descriptor *desc_rx;
08f738be 160 dma_cookie_t cookie_tx;
34df42f5 161 dma_cookie_t cookie_rx;
08f738be 162 struct scatterlist sg_tx;
34df42f5 163 struct scatterlist sg_rx;
1ecc26bd
RB		 164 struct tasklet_struct tasklet;
165 unsigned int irq_status;
166 unsigned int irq_status_prev;
167
168 struct circ_buf rx_ring;
e8faff73
CS		 169
170 struct serial_rs485 rs485; /* rs485 settings */
e0b0baad 171 struct mctrl_gpios *gpios;
ab5e4e41 172 int gpio_irq[UART_GPIO_MAX];
e8faff73 173 unsigned int tx_done_mask;
ab5e4e41 174 bool ms_irq_enabled;
055560b0 175 bool is_usart; /* usart or uart */
2e68c22f 176 struct timer_list uart_timer; /* uart timer */
a930e528
ES		 177 int (*prepare_rx)(struct uart_port *port);
178 int (*prepare_tx)(struct uart_port *port);
179 void (*schedule_rx)(struct uart_port *port);
180 void (*schedule_tx)(struct uart_port *port);
181 void (*release_rx)(struct uart_port *port);
182 void (*release_tx)(struct uart_port *port);
afefc415
AV		 183};
184
7192f92c 185static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 186static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 187
1e6c9c28 188#ifdef SUPPORT_SYSRQ
7192f92c 189static struct console atmel_console;
1e6c9c28
AV		 190#endif
191
5fbe46b6
NF		 192#if defined(CONFIG_OF)
193static const struct of_device_id atmel_serial_dt_ids[] = {
194 { .compatible = "atmel,at91rm9200-usart" },
195 { .compatible = "atmel,at91sam9260-usart" },
196 { /* sentinel */ }
197};
198
199MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
200#endif
201
c811ab8c
HS		 202static inline struct atmel_uart_port *
203to_atmel_uart_port(struct uart_port *uart)
204{
205 return container_of(uart, struct atmel_uart_port, uart);
206}
207
a6670615 208#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 209static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 210{
c811ab8c 211 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 212
64e22ebe 213 return atmel_port->use_pdc_rx;
a6670615
CC		 214}
215
64e22ebe 216static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 217{
c811ab8c 218 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 219
64e22ebe 220 return atmel_port->use_pdc_tx;
a6670615
CC		 221}
222#else
64e22ebe 223static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 224{
225 return false;
226}
227
64e22ebe 228static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 229{
230 return false;
231}
232#endif
233
08f738be
ES		 234static bool atmel_use_dma_tx(struct uart_port *port)
235{
236 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
237
238 return atmel_port->use_dma_tx;
239}
240
34df42f5
ES		 241static bool atmel_use_dma_rx(struct uart_port *port)
242{
243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
244
245 return atmel_port->use_dma_rx;
246}
247
e0b0baad
RG		 248static unsigned int atmel_get_lines_status(struct uart_port *port)
249{
250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
251 unsigned int status, ret = 0;
252
253 status = UART_GET_CSR(port);
254
255 mctrl_gpio_get(atmel_port->gpios, &ret);
256
257 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
258 UART_GPIO_CTS))) {
259 if (ret & TIOCM_CTS)
260 status &= ~ATMEL_US_CTS;
261 else
262 status |= ATMEL_US_CTS;
263 }
264
265 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
266 UART_GPIO_DSR))) {
267 if (ret & TIOCM_DSR)
268 status &= ~ATMEL_US_DSR;
269 else
270 status |= ATMEL_US_DSR;
271 }
272
273 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
274 UART_GPIO_RI))) {
275 if (ret & TIOCM_RI)
276 status &= ~ATMEL_US_RI;
277 else
278 status |= ATMEL_US_RI;
279 }
280
281 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
282 UART_GPIO_DCD))) {
283 if (ret & TIOCM_CD)
284 status &= ~ATMEL_US_DCD;
285 else
286 status |= ATMEL_US_DCD;
287 }
288
289 return status;
290}
291
e8faff73
CS		 292/* Enable or disable the rs485 support */
293void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
294{
295 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
296 unsigned int mode;
dbf1115d 297 unsigned long flags;
e8faff73 298
dbf1115d 299 spin_lock_irqsave(&port->lock, flags);
e8faff73
CS		 300
301 /* Disable interrupts */
302 UART_PUT_IDR(port, atmel_port->tx_done_mask);
303
304 mode = UART_GET_MR(port);
305
306 /* Resetting serial mode to RS232 (0x0) */
307 mode &= ~ATMEL_US_USMODE;
308
309 atmel_port->rs485 = *rs485conf;
310
311 if (rs485conf->flags & SER_RS485_ENABLED) {
312 dev_dbg(port->dev, "Setting UART to RS485\n");
313 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
93f3350c 314 if ((rs485conf->delay_rts_after_send) > 0)
1b633184 315 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
e8faff73
CS		 316 mode |= ATMEL_US_USMODE_RS485;
317 } else {
318 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 319 if (atmel_use_pdc_tx(port))
e8faff73
CS		 320 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
321 ATMEL_US_TXBUFE;
322 else
323 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
324 }
325 UART_PUT_MR(port, mode);
326
327 /* Enable interrupts */
328 UART_PUT_IER(port, atmel_port->tx_done_mask);
329
dbf1115d 330 spin_unlock_irqrestore(&port->lock, flags);
e8faff73
CS		 331
332}
333
1e6c9c28
AV		 334/*
335 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
336 */
7192f92c 337static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 338{
7192f92c 339 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV		 340}
341
342/*
343 * Set state of the modem control output lines
344 */
7192f92c 345static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 346{
347 unsigned int control = 0;
afefc415 348 unsigned int mode;
e8faff73 349 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 350
1e6c9c28 351 if (mctrl & TIOCM_RTS)
7192f92c 352 control |= ATMEL_US_RTSEN;
1e6c9c28 353 else
7192f92c 354 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV		 355
356 if (mctrl & TIOCM_DTR)
7192f92c 357 control |= ATMEL_US_DTREN;
1e6c9c28 358 else
7192f92c 359 control |= ATMEL_US_DTRDIS;
1e6c9c28 360
afefc415
AV		 361 UART_PUT_CR(port, control);
362
e0b0baad
RG		 363 mctrl_gpio_set(atmel_port->gpios, mctrl);
364
afefc415 365 /* Local loopback mode? */
7192f92c 366 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 367 if (mctrl & TIOCM_LOOP)
7192f92c 368 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 369 else
7192f92c 370 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73
CS		 371
372 /* Resetting serial mode to RS232 (0x0) */
373 mode &= ~ATMEL_US_USMODE;
374
375 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
376 dev_dbg(port->dev, "Setting UART to RS485\n");
93f3350c 377 if ((atmel_port->rs485.delay_rts_after_send) > 0)
1b633184
CS		 378 UART_PUT_TTGR(port,
379 atmel_port->rs485.delay_rts_after_send);
e8faff73
CS		 380 mode |= ATMEL_US_USMODE_RS485;
381 } else {
382 dev_dbg(port->dev, "Setting UART to RS232\n");
383 }
afefc415 384 UART_PUT_MR(port, mode);
1e6c9c28
AV		 385}
386
387/*
388 * Get state of the modem control input lines
389 */
7192f92c 390static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 391{
e0b0baad
RG		 392 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
393 unsigned int ret = 0, status;
1e6c9c28
AV		 394
395 status = UART_GET_CSR(port);
396
397 /*
398 * The control signals are active low.
399 */
7192f92c 400 if (!(status & ATMEL_US_DCD))
1e6c9c28 401 ret |= TIOCM_CD;
7192f92c 402 if (!(status & ATMEL_US_CTS))
1e6c9c28 403 ret |= TIOCM_CTS;
7192f92c 404 if (!(status & ATMEL_US_DSR))
1e6c9c28 405 ret |= TIOCM_DSR;
7192f92c 406 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 407 ret |= TIOCM_RI;
408
e0b0baad 409 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 410}
411
412/*
413 * Stop transmitting.
414 */
7192f92c 415static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 416{
e8faff73
CS		 417 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
418
64e22ebe 419 if (atmel_use_pdc_tx(port)) {
a6670615
CC		 420 /* disable PDC transmit */
421 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
e8faff73
CS		 422 }
423 /* Disable interrupts */
424 UART_PUT_IDR(port, atmel_port->tx_done_mask);
425
83cac9f3
BR		 426 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
427 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73 428 atmel_start_rx(port);
1e6c9c28
AV		 429}
430
431/*
432 * Start transmitting.
433 */
7192f92c 434static void atmel_start_tx(struct uart_port *port)
1e6c9c28 435{
e8faff73
CS		 436 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
437
64e22ebe 438 if (atmel_use_pdc_tx(port)) {
a6670615
CC		 439 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
440 /* The transmitter is already running. Yes, we
441 really need this.*/
442 return;
443
83cac9f3
BR		 444 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
445 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73
CS		 446 atmel_stop_rx(port);
447
a6670615
CC		 448 /* re-enable PDC transmit */
449 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
e8faff73
CS		 450 }
451 /* Enable interrupts */
452 UART_PUT_IER(port, atmel_port->tx_done_mask);
453}
454
455/*
456 * start receiving - port is in process of being opened.
457 */
458static void atmel_start_rx(struct uart_port *port)
459{
460 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
461
57c36868
SG		 462 UART_PUT_CR(port, ATMEL_US_RXEN);
463
64e22ebe 464 if (atmel_use_pdc_rx(port)) {
e8faff73
CS		 465 /* enable PDC controller */
466 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
467 port->read_status_mask);
468 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
469 } else {
470 UART_PUT_IER(port, ATMEL_US_RXRDY);
471 }
1e6c9c28
AV		 472}
473
474/*
475 * Stop receiving - port is in process of being closed.
476 */
7192f92c 477static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 478{
57c36868
SG		 479 UART_PUT_CR(port, ATMEL_US_RXDIS);
480
64e22ebe 481 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 482 /* disable PDC receive */
483 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
e8faff73
CS		 484 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
485 port->read_status_mask);
486 } else {
a6670615 487 UART_PUT_IDR(port, ATMEL_US_RXRDY);
e8faff73 488 }
1e6c9c28
AV		 489}
490
491/*
492 * Enable modem status interrupts
493 */
7192f92c 494static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 495{
ab5e4e41
RG		 496 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
497 uint32_t ier = 0;
498
499 /*
500 * Interrupt should not be enabled twice
501 */
502 if (atmel_port->ms_irq_enabled)
503 return;
504
505 atmel_port->ms_irq_enabled = true;
506
507 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
508 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
509 else
510 ier |= ATMEL_US_CTSIC;
511
512 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
513 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
514 else
515 ier |= ATMEL_US_DSRIC;
516
517 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
518 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
519 else
520 ier |= ATMEL_US_RIIC;
521
522 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
523 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
524 else
525 ier |= ATMEL_US_DCDIC;
526
527 UART_PUT_IER(port, ier);
1e6c9c28
AV		 528}
529
35b675b9
RG		 530/*
531 * Disable modem status interrupts
532 */
533static void atmel_disable_ms(struct uart_port *port)
534{
535 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
536 uint32_t idr = 0;
537
538 /*
539 * Interrupt should not be disabled twice
540 */
541 if (!atmel_port->ms_irq_enabled)
542 return;
543
544 atmel_port->ms_irq_enabled = false;
545
546 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
547 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
548 else
549 idr |= ATMEL_US_CTSIC;
550
551 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
552 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
553 else
554 idr |= ATMEL_US_DSRIC;
555
556 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
557 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
558 else
559 idr |= ATMEL_US_RIIC;
560
561 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
562 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
563 else
564 idr |= ATMEL_US_DCDIC;
565
566 UART_PUT_IDR(port, idr);
567}
568
1e6c9c28
AV		 569/*
570 * Control the transmission of a break signal
571 */
7192f92c 572static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 573{
574 if (break_state != 0)
7192f92c 575 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 576 else
7192f92c 577 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV		 578}
579
1ecc26bd
RB		 580/*
581 * Stores the incoming character in the ring buffer
582 */
583static void
584atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
585 unsigned int ch)
586{
c811ab8c 587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 588 struct circ_buf *ring = &atmel_port->rx_ring;
589 struct atmel_uart_char *c;
590
591 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
592 /* Buffer overflow, ignore char */
593 return;
594
595 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
596 c->status = status;
597 c->ch = ch;
598
599 /* Make sure the character is stored before we update head. */
600 smp_wmb();
601
602 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
603}
604
a6670615
CC		 605/*
606 * Deal with parity, framing and overrun errors.
607 */
608static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
609{
610 /* clear error */
611 UART_PUT_CR(port, ATMEL_US_RSTSTA);
612
613 if (status & ATMEL_US_RXBRK) {
614 /* ignore side-effect */
615 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
616 port->icount.brk++;
617 }
618 if (status & ATMEL_US_PARE)
619 port->icount.parity++;
620 if (status & ATMEL_US_FRAME)
621 port->icount.frame++;
622 if (status & ATMEL_US_OVRE)
623 port->icount.overrun++;
624}
625
1e6c9c28
AV		 626/*
627 * Characters received (called from interrupt handler)
628 */
7d12e780 629static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 630{
c811ab8c 631 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 632 unsigned int status, ch;
1e6c9c28 633
afefc415 634 status = UART_GET_CSR(port);
7192f92c 635 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV		 636 ch = UART_GET_CHAR(port);
637
1e6c9c28
AV		 638 /*
639 * note that the error handling code is
640 * out of the main execution path
641 */
9e6077bd
HS		 642 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
643 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
644 || atmel_port->break_active)) {
1ecc26bd 645
b843aa21
RB		 646 /* clear error */
647 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 648
9e6077bd
HS		 649 if (status & ATMEL_US_RXBRK
650 && !atmel_port->break_active) {
9e6077bd
HS		 651 atmel_port->break_active = 1;
652 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS		 653 } else {
654 /*
655 * This is either the end-of-break
656 * condition or we've received at
657 * least one character without RXBRK
658 * being set. In both cases, the next
659 * RXBRK will indicate start-of-break.
660 */
661 UART_PUT_IDR(port, ATMEL_US_RXBRK);
662 status &= ~ATMEL_US_RXBRK;
663 atmel_port->break_active = 0;
afefc415 664 }
1e6c9c28
AV		 665 }
666
1ecc26bd 667 atmel_buffer_rx_char(port, status, ch);
afefc415 668 status = UART_GET_CSR(port);
1e6c9c28
AV		 669 }
670
1ecc26bd 671 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV		 672}
673
674/*
1ecc26bd
RB		 675 * Transmit characters (called from tasklet with TXRDY interrupt
676 * disabled)
1e6c9c28 677 */
7192f92c 678static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 679{
ebd2c8f6 680 struct circ_buf *xmit = &port->state->xmit;
e8faff73 681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 682
e8faff73 683 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
1e6c9c28
AV		 684 UART_PUT_CHAR(port, port->x_char);
685 port->icount.tx++;
686 port->x_char = 0;
1e6c9c28 687 }
1ecc26bd 688 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 689 return;
1e6c9c28 690
e8faff73 691 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
1e6c9c28
AV		 692 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
693 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
694 port->icount.tx++;
695 if (uart_circ_empty(xmit))
696 break;
697 }
698
699 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
700 uart_write_wakeup(port);
701
1ecc26bd 702 if (!uart_circ_empty(xmit))
e8faff73
CS		 703 /* Enable interrupts */
704 UART_PUT_IER(port, atmel_port->tx_done_mask);
1e6c9c28
AV		 705}
706
08f738be
ES		 707static void atmel_complete_tx_dma(void *arg)
708{
709 struct atmel_uart_port *atmel_port = arg;
710 struct uart_port *port = &atmel_port->uart;
711 struct circ_buf *xmit = &port->state->xmit;
712 struct dma_chan *chan = atmel_port->chan_tx;
713 unsigned long flags;
714
715 spin_lock_irqsave(&port->lock, flags);
716
717 if (chan)
718 dmaengine_terminate_all(chan);
719 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
720 xmit->tail &= UART_XMIT_SIZE - 1;
721
722 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
723
724 spin_lock_irq(&atmel_port->lock_tx);
725 async_tx_ack(atmel_port->desc_tx);
726 atmel_port->cookie_tx = -EINVAL;
727 atmel_port->desc_tx = NULL;
728 spin_unlock_irq(&atmel_port->lock_tx);
729
730 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
731 uart_write_wakeup(port);
732
733 /* Do we really need this? */
734 if (!uart_circ_empty(xmit))
735 tasklet_schedule(&atmel_port->tasklet);
736
737 spin_unlock_irqrestore(&port->lock, flags);
738}
739
740static void atmel_release_tx_dma(struct uart_port *port)
741{
742 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
743 struct dma_chan *chan = atmel_port->chan_tx;
744
745 if (chan) {
746 dmaengine_terminate_all(chan);
747 dma_release_channel(chan);
748 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 749 DMA_TO_DEVICE);
08f738be
ES		 750 }
751
752 atmel_port->desc_tx = NULL;
753 atmel_port->chan_tx = NULL;
754 atmel_port->cookie_tx = -EINVAL;
755}
756
757/*
758 * Called from tasklet with TXRDY interrupt is disabled.
759 */
760static void atmel_tx_dma(struct uart_port *port)
761{
762 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
763 struct circ_buf *xmit = &port->state->xmit;
764 struct dma_chan *chan = atmel_port->chan_tx;
765 struct dma_async_tx_descriptor *desc;
766 struct scatterlist *sg = &atmel_port->sg_tx;
767
768 /* Make sure we have an idle channel */
769 if (atmel_port->desc_tx != NULL)
770 return;
771
772 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
773 /*
774 * DMA is idle now.
775 * Port xmit buffer is already mapped,
776 * and it is one page... Just adjust
777 * offsets and lengths. Since it is a circular buffer,
778 * we have to transmit till the end, and then the rest.
779 * Take the port lock to get a
780 * consistent xmit buffer state.
781 */
782 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
783 sg_dma_address(sg) = (sg_dma_address(sg) &
784 ~(UART_XMIT_SIZE - 1))
785 + sg->offset;
786 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
787 xmit->tail,
788 UART_XMIT_SIZE);
789 BUG_ON(!sg_dma_len(sg));
790
791 desc = dmaengine_prep_slave_sg(chan,
792 sg,
793 1,
794 DMA_MEM_TO_DEV,
795 DMA_PREP_INTERRUPT |
796 DMA_CTRL_ACK);
797 if (!desc) {
798 dev_err(port->dev, "Failed to send via dma!\n");
799 return;
800 }
801
802 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV);
803
804 atmel_port->desc_tx = desc;
805 desc->callback = atmel_complete_tx_dma;
806 desc->callback_param = atmel_port;
807 atmel_port->cookie_tx = dmaengine_submit(desc);
808
809 } else {
810 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
811 /* DMA done, stop TX, start RX for RS485 */
812 atmel_start_rx(port);
813 }
814 }
815
816 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
817 uart_write_wakeup(port);
818}
819
820static int atmel_prepare_tx_dma(struct uart_port *port)
821{
822 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
823 dma_cap_mask_t mask;
824 struct dma_slave_config config;
825 int ret, nent;
826
827 dma_cap_zero(mask);
828 dma_cap_set(DMA_SLAVE, mask);
829
830 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
831 if (atmel_port->chan_tx == NULL)
832 goto chan_err;
833 dev_info(port->dev, "using %s for tx DMA transfers\n",
834 dma_chan_name(atmel_port->chan_tx));
835
836 spin_lock_init(&atmel_port->lock_tx);
837 sg_init_table(&atmel_port->sg_tx, 1);
838 /* UART circular tx buffer is an aligned page. */
839 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
840 sg_set_page(&atmel_port->sg_tx,
841 virt_to_page(port->state->xmit.buf),
842 UART_XMIT_SIZE,
843 (int)port->state->xmit.buf & ~PAGE_MASK);
844 nent = dma_map_sg(port->dev,
845 &atmel_port->sg_tx,
846 1,
48479148 847 DMA_TO_DEVICE);
08f738be
ES		 848
849 if (!nent) {
850 dev_dbg(port->dev, "need to release resource of dma\n");
851 goto chan_err;
852 } else {
853 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
854 sg_dma_len(&atmel_port->sg_tx),
855 port->state->xmit.buf,
856 sg_dma_address(&atmel_port->sg_tx));
857 }
858
859 /* Configure the slave DMA */
860 memset(&config, 0, sizeof(config));
861 config.direction = DMA_MEM_TO_DEV;
862 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
863 config.dst_addr = port->mapbase + ATMEL_US_THR;
864
865 ret = dmaengine_device_control(atmel_port->chan_tx,
866 DMA_SLAVE_CONFIG,
867 (unsigned long)&config);
868 if (ret) {
869 dev_err(port->dev, "DMA tx slave configuration failed\n");
870 goto chan_err;
871 }
872
873 return 0;
874
875chan_err:
876 dev_err(port->dev, "TX channel not available, switch to pio\n");
877 atmel_port->use_dma_tx = 0;
878 if (atmel_port->chan_tx)
879 atmel_release_tx_dma(port);
880 return -EINVAL;
881}
882
34df42f5
ES		 883static void atmel_complete_rx_dma(void *arg)
884{
885 struct uart_port *port = arg;
886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
887
888 tasklet_schedule(&atmel_port->tasklet);
889}
890
891static void atmel_release_rx_dma(struct uart_port *port)
892{
893 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
894 struct dma_chan *chan = atmel_port->chan_rx;
895
896 if (chan) {
897 dmaengine_terminate_all(chan);
898 dma_release_channel(chan);
899 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 900 DMA_FROM_DEVICE);
34df42f5
ES		 901 }
902
903 atmel_port->desc_rx = NULL;
904 atmel_port->chan_rx = NULL;
905 atmel_port->cookie_rx = -EINVAL;
906}
907
908static void atmel_rx_from_dma(struct uart_port *port)
909{
910 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 911 struct tty_port *tport = &port->state->port;
34df42f5
ES		 912 struct circ_buf *ring = &atmel_port->rx_ring;
913 struct dma_chan *chan = atmel_port->chan_rx;
914 struct dma_tx_state state;
915 enum dma_status dmastat;
66f37aaf 916 size_t count;
34df42f5
ES		 917
918
919 /* Reset the UART timeout early so that we don't miss one */
920 UART_PUT_CR(port, ATMEL_US_STTTO);
921 dmastat = dmaengine_tx_status(chan,
922 atmel_port->cookie_rx,
923 &state);
924 /* Restart a new tasklet if DMA status is error */
925 if (dmastat == DMA_ERROR) {
926 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
927 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
928 tasklet_schedule(&atmel_port->tasklet);
929 return;
930 }
34df42f5 931
66f37aaf
CP		 932 /* CPU claims ownership of RX DMA buffer */
933 dma_sync_sg_for_cpu(port->dev,
934 &atmel_port->sg_rx,
935 1,
936 DMA_DEV_TO_MEM);
937
938 /*
939 * ring->head points to the end of data already written by the DMA.
940 * ring->tail points to the beginning of data to be read by the
941 * framework.
942 * The current transfer size should not be larger than the dma buffer
943 * length.
944 */
945 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
946 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 947 /*
66f37aaf
CP		 948 * At this point ring->head may point to the first byte right after the
949 * last byte of the dma buffer:
950 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
951 *
952 * However ring->tail must always points inside the dma buffer:
953 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
954 *
955 * Since we use a ring buffer, we have to handle the case
956 * where head is lower than tail. In such a case, we first read from
957 * tail to the end of the buffer then reset tail.
34df42f5 958 */
66f37aaf
CP		 959 if (ring->head < ring->tail) {
960 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 961
66f37aaf
CP		 962 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
963 ring->tail = 0;
964 port->icount.rx += count;
965 }
34df42f5 966
66f37aaf
CP		 967 /* Finally we read data from tail to head */
968 if (ring->tail < ring->head) {
969 count = ring->head - ring->tail;
34df42f5 970
66f37aaf
CP		 971 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
972 /* Wrap ring->head if needed */
973 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
974 ring->head = 0;
975 ring->tail = ring->head;
34df42f5
ES		 976 port->icount.rx += count;
977 }
978
66f37aaf
CP		 979 /* USART retreives ownership of RX DMA buffer */
980 dma_sync_sg_for_device(port->dev,
981 &atmel_port->sg_rx,
982 1,
983 DMA_DEV_TO_MEM);
984
985 /*
986 * Drop the lock here since it might end up calling
987 * uart_start(), which takes the lock.
988 */
989 spin_unlock(&port->lock);
990 tty_flip_buffer_push(tport);
991 spin_lock(&port->lock);
992
34df42f5
ES		 993 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
994}
995
996static int atmel_prepare_rx_dma(struct uart_port *port)
997{
998 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
999 struct dma_async_tx_descriptor *desc;
1000 dma_cap_mask_t mask;
1001 struct dma_slave_config config;
1002 struct circ_buf *ring;
1003 int ret, nent;
1004
1005 ring = &atmel_port->rx_ring;
1006
1007 dma_cap_zero(mask);
1008 dma_cap_set(DMA_CYCLIC, mask);
1009
1010 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1011 if (atmel_port->chan_rx == NULL)
1012 goto chan_err;
1013 dev_info(port->dev, "using %s for rx DMA transfers\n",
1014 dma_chan_name(atmel_port->chan_rx));
1015
1016 spin_lock_init(&atmel_port->lock_rx);
1017 sg_init_table(&atmel_port->sg_rx, 1);
1018 /* UART circular rx buffer is an aligned page. */
1019 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1020 sg_set_page(&atmel_port->sg_rx,
1021 virt_to_page(ring->buf),
1022 ATMEL_SERIAL_RINGSIZE,
1023 (int)ring->buf & ~PAGE_MASK);
1024 nent = dma_map_sg(port->dev,
1025 &atmel_port->sg_rx,
1026 1,
48479148 1027 DMA_FROM_DEVICE);
34df42f5
ES		 1028
1029 if (!nent) {
1030 dev_dbg(port->dev, "need to release resource of dma\n");
1031 goto chan_err;
1032 } else {
1033 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1034 sg_dma_len(&atmel_port->sg_rx),
1035 ring->buf,
1036 sg_dma_address(&atmel_port->sg_rx));
1037 }
1038
1039 /* Configure the slave DMA */
1040 memset(&config, 0, sizeof(config));
1041 config.direction = DMA_DEV_TO_MEM;
1042 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1043 config.src_addr = port->mapbase + ATMEL_US_RHR;
1044
1045 ret = dmaengine_device_control(atmel_port->chan_rx,
1046 DMA_SLAVE_CONFIG,
1047 (unsigned long)&config);
1048 if (ret) {
1049 dev_err(port->dev, "DMA rx slave configuration failed\n");
1050 goto chan_err;
1051 }
1052 /*
1053 * Prepare a cyclic dma transfer, assign 2 descriptors,
1054 * each one is half ring buffer size
1055 */
1056 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1057 sg_dma_address(&atmel_port->sg_rx),
1058 sg_dma_len(&atmel_port->sg_rx),
1059 sg_dma_len(&atmel_port->sg_rx)/2,
1060 DMA_DEV_TO_MEM,
1061 DMA_PREP_INTERRUPT);
1062 desc->callback = atmel_complete_rx_dma;
1063 desc->callback_param = port;
1064 atmel_port->desc_rx = desc;
1065 atmel_port->cookie_rx = dmaengine_submit(desc);
1066
1067 return 0;
1068
1069chan_err:
1070 dev_err(port->dev, "RX channel not available, switch to pio\n");
1071 atmel_port->use_dma_rx = 0;
1072 if (atmel_port->chan_rx)
1073 atmel_release_rx_dma(port);
1074 return -EINVAL;
1075}
1076
2e68c22f
ES		 1077static void atmel_uart_timer_callback(unsigned long data)
1078{
1079 struct uart_port *port = (void *)data;
1080 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1081
1082 tasklet_schedule(&atmel_port->tasklet);
1083 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1084}
1085
b843aa21
RB		 1086/*
1087 * receive interrupt handler.
1088 */
1089static void
1090atmel_handle_receive(struct uart_port *port, unsigned int pending)
1091{
c811ab8c 1092 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1093
64e22ebe 1094 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1095 /*
1096 * PDC receive. Just schedule the tasklet and let it
1097 * figure out the details.
1098 *
1099 * TODO: We're not handling error flags correctly at
1100 * the moment.
1101 */
1102 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1103 UART_PUT_IDR(port, (ATMEL_US_ENDRX
1104 | ATMEL_US_TIMEOUT));
1105 tasklet_schedule(&atmel_port->tasklet);
1106 }
1107
1108 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1109 ATMEL_US_FRAME | ATMEL_US_PARE))
1110 atmel_pdc_rxerr(port, pending);
1111 }
1112
34df42f5
ES		 1113 if (atmel_use_dma_rx(port)) {
1114 if (pending & ATMEL_US_TIMEOUT) {
1115 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
1116 tasklet_schedule(&atmel_port->tasklet);
1117 }
1118 }
1119
b843aa21
RB		 1120 /* Interrupt receive */
1121 if (pending & ATMEL_US_RXRDY)
1122 atmel_rx_chars(port);
1123 else if (pending & ATMEL_US_RXBRK) {
1124 /*
1125 * End of break detected. If it came along with a
1126 * character, atmel_rx_chars will handle it.
1127 */
1128 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1129 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1130 atmel_port->break_active = 0;
1131 }
1132}
1133
1134/*
1ecc26bd 1135 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1136 */
1137static void
1138atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1139{
c811ab8c 1140 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1141
e8faff73
CS		 1142 if (pending & atmel_port->tx_done_mask) {
1143 /* Either PDC or interrupt transmission */
1144 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1145 tasklet_schedule(&atmel_port->tasklet);
1ecc26bd 1146 }
b843aa21
RB		 1147}
1148
1149/*
1150 * status flags interrupt handler.
1151 */
1152static void
1153atmel_handle_status(struct uart_port *port, unsigned int pending,
1154 unsigned int status)
1155{
c811ab8c 1156 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1157
b843aa21 1158 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB		 1159 | ATMEL_US_CTSIC)) {
1160 atmel_port->irq_status = status;
1161 tasklet_schedule(&atmel_port->tasklet);
1162 }
b843aa21
RB		 1163}
1164
1e6c9c28
AV		 1165/*
1166 * Interrupt handler
1167 */
7d12e780 1168static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1169{
1170 struct uart_port *port = dev_id;
ab5e4e41 1171 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 1172 unsigned int status, pending, pass_counter = 0;
ab5e4e41 1173 bool gpio_handled = false;
1e6c9c28 1174
a6670615 1175 do {
e0b0baad 1176 status = atmel_get_lines_status(port);
a6670615 1177 pending = status & UART_GET_IMR(port);
ab5e4e41
RG		 1178 if (!gpio_handled) {
1179 /*
1180 * Dealing with GPIO interrupt
1181 */
1182 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1183 pending |= ATMEL_US_CTSIC;
1184
1185 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1186 pending |= ATMEL_US_DSRIC;
1187
1188 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1189 pending |= ATMEL_US_RIIC;
1190
1191 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1192 pending |= ATMEL_US_DCDIC;
1193
1194 gpio_handled = true;
1195 }
a6670615
CC		 1196 if (!pending)
1197 break;
1198
b843aa21
RB		 1199 atmel_handle_receive(port, pending);
1200 atmel_handle_status(port, pending, status);
1201 atmel_handle_transmit(port, pending);
a6670615 1202 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1203
0400b697 1204 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1205}
1e6c9c28 1206
a930e528
ES		 1207static void atmel_release_tx_pdc(struct uart_port *port)
1208{
1209 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1210 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1211
1212 dma_unmap_single(port->dev,
1213 pdc->dma_addr,
1214 pdc->dma_size,
1215 DMA_TO_DEVICE);
1216}
1217
a6670615
CC		 1218/*
1219 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1220 */
64e22ebe 1221static void atmel_tx_pdc(struct uart_port *port)
a6670615 1222{
c811ab8c 1223 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1224 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1225 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1226 int count;
1227
ba0657ff
MT		 1228 /* nothing left to transmit? */
1229 if (UART_GET_TCR(port))
1230 return;
1231
a6670615
CC		 1232 xmit->tail += pdc->ofs;
1233 xmit->tail &= UART_XMIT_SIZE - 1;
1234
1235 port->icount.tx += pdc->ofs;
1236 pdc->ofs = 0;
1237
ba0657ff 1238 /* more to transmit - setup next transfer */
a6670615 1239
ba0657ff
MT		 1240 /* disable PDC transmit */
1241 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1242
1f14081d 1243 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1244 dma_sync_single_for_device(port->dev,
1245 pdc->dma_addr,
1246 pdc->dma_size,
1247 DMA_TO_DEVICE);
1248
1249 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1250 pdc->ofs = count;
1251
1252 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1253 UART_PUT_TCR(port, count);
e8faff73 1254 /* re-enable PDC transmit */
a6670615 1255 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
e8faff73
CS		 1256 /* Enable interrupts */
1257 UART_PUT_IER(port, atmel_port->tx_done_mask);
1258 } else {
83cac9f3
BR		 1259 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
1260 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) {
e8faff73
CS		 1261 /* DMA done, stop TX, start RX for RS485 */
1262 atmel_start_rx(port);
1263 }
1e6c9c28 1264 }
a6670615
CC		 1265
1266 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1267 uart_write_wakeup(port);
1e6c9c28
AV		 1268}
1269
a930e528
ES		 1270static int atmel_prepare_tx_pdc(struct uart_port *port)
1271{
1272 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1273 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1274 struct circ_buf *xmit = &port->state->xmit;
1275
1276 pdc->buf = xmit->buf;
1277 pdc->dma_addr = dma_map_single(port->dev,
1278 pdc->buf,
1279 UART_XMIT_SIZE,
1280 DMA_TO_DEVICE);
1281 pdc->dma_size = UART_XMIT_SIZE;
1282 pdc->ofs = 0;
1283
1284 return 0;
1285}
1286
1ecc26bd
RB		 1287static void atmel_rx_from_ring(struct uart_port *port)
1288{
c811ab8c 1289 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1290 struct circ_buf *ring = &atmel_port->rx_ring;
1291 unsigned int flg;
1292 unsigned int status;
1293
1294 while (ring->head != ring->tail) {
1295 struct atmel_uart_char c;
1296
1297 /* Make sure c is loaded after head. */
1298 smp_rmb();
1299
1300 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1301
1302 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1303
1304 port->icount.rx++;
1305 status = c.status;
1306 flg = TTY_NORMAL;
1307
1308 /*
1309 * note that the error handling code is
1310 * out of the main execution path
1311 */
1312 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1313 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1314 if (status & ATMEL_US_RXBRK) {
1315 /* ignore side-effect */
1316 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1317
1318 port->icount.brk++;
1319 if (uart_handle_break(port))
1320 continue;
1321 }
1322 if (status & ATMEL_US_PARE)
1323 port->icount.parity++;
1324 if (status & ATMEL_US_FRAME)
1325 port->icount.frame++;
1326 if (status & ATMEL_US_OVRE)
1327 port->icount.overrun++;
1328
1329 status &= port->read_status_mask;
1330
1331 if (status & ATMEL_US_RXBRK)
1332 flg = TTY_BREAK;
1333 else if (status & ATMEL_US_PARE)
1334 flg = TTY_PARITY;
1335 else if (status & ATMEL_US_FRAME)
1336 flg = TTY_FRAME;
1337 }
1338
1339
1340 if (uart_handle_sysrq_char(port, c.ch))
1341 continue;
1342
1343 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1344 }
1345
1346 /*
1347 * Drop the lock here since it might end up calling
1348 * uart_start(), which takes the lock.
1349 */
1350 spin_unlock(&port->lock);
2e124b4a 1351 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1352 spin_lock(&port->lock);
1353}
1354
a930e528
ES		 1355static void atmel_release_rx_pdc(struct uart_port *port)
1356{
1357 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1358 int i;
1359
1360 for (i = 0; i < 2; i++) {
1361 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1362
1363 dma_unmap_single(port->dev,
1364 pdc->dma_addr,
1365 pdc->dma_size,
1366 DMA_FROM_DEVICE);
1367 kfree(pdc->buf);
1368 }
1369}
1370
64e22ebe 1371static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1372{
c811ab8c 1373 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1374 struct tty_port *tport = &port->state->port;
a6670615
CC		 1375 struct atmel_dma_buffer *pdc;
1376 int rx_idx = atmel_port->pdc_rx_idx;
1377 unsigned int head;
1378 unsigned int tail;
1379 unsigned int count;
1380
1381 do {
1382 /* Reset the UART timeout early so that we don't miss one */
1383 UART_PUT_CR(port, ATMEL_US_STTTO);
1384
1385 pdc = &atmel_port->pdc_rx[rx_idx];
1386 head = UART_GET_RPR(port) - pdc->dma_addr;
1387 tail = pdc->ofs;
1388
1389 /* If the PDC has switched buffers, RPR won't contain
1390 * any address within the current buffer. Since head
1391 * is unsigned, we just need a one-way comparison to
1392 * find out.
1393 *
1394 * In this case, we just need to consume the entire
1395 * buffer and resubmit it for DMA. This will clear the
1396 * ENDRX bit as well, so that we can safely re-enable
1397 * all interrupts below.
1398 */
1399 head = min(head, pdc->dma_size);
1400
1401 if (likely(head != tail)) {
1402 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1403 pdc->dma_size, DMA_FROM_DEVICE);
1404
1405 /*
1406 * head will only wrap around when we recycle
1407 * the DMA buffer, and when that happens, we
1408 * explicitly set tail to 0. So head will
1409 * always be greater than tail.
1410 */
1411 count = head - tail;
1412
05c7cd39
JS		 1413 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1414 count);
a6670615
CC		 1415
1416 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1417 pdc->dma_size, DMA_FROM_DEVICE);
1418
1419 port->icount.rx += count;
1420 pdc->ofs = head;
1421 }
1422
1423 /*
1424 * If the current buffer is full, we need to check if
1425 * the next one contains any additional data.
1426 */
1427 if (head >= pdc->dma_size) {
1428 pdc->ofs = 0;
1429 UART_PUT_RNPR(port, pdc->dma_addr);
1430 UART_PUT_RNCR(port, pdc->dma_size);
1431
1432 rx_idx = !rx_idx;
1433 atmel_port->pdc_rx_idx = rx_idx;
1434 }
1435 } while (head >= pdc->dma_size);
1436
1437 /*
1438 * Drop the lock here since it might end up calling
1439 * uart_start(), which takes the lock.
1440 */
1441 spin_unlock(&port->lock);
2e124b4a 1442 tty_flip_buffer_push(tport);
a6670615
CC		 1443 spin_lock(&port->lock);
1444
1445 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1446}
1447
a930e528
ES		 1448static int atmel_prepare_rx_pdc(struct uart_port *port)
1449{
1450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1451 int i;
1452
1453 for (i = 0; i < 2; i++) {
1454 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1455
1456 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1457 if (pdc->buf == NULL) {
1458 if (i != 0) {
1459 dma_unmap_single(port->dev,
1460 atmel_port->pdc_rx[0].dma_addr,
1461 PDC_BUFFER_SIZE,
1462 DMA_FROM_DEVICE);
1463 kfree(atmel_port->pdc_rx[0].buf);
1464 }
1465 atmel_port->use_pdc_rx = 0;
1466 return -ENOMEM;
1467 }
1468 pdc->dma_addr = dma_map_single(port->dev,
1469 pdc->buf,
1470 PDC_BUFFER_SIZE,
1471 DMA_FROM_DEVICE);
1472 pdc->dma_size = PDC_BUFFER_SIZE;
1473 pdc->ofs = 0;
1474 }
1475
1476 atmel_port->pdc_rx_idx = 0;
1477
1478 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1479 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1480
1481 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1482 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1483
1484 return 0;
1485}
1486
1ecc26bd
RB		 1487/*
1488 * tasklet handling tty stuff outside the interrupt handler.
1489 */
1490static void atmel_tasklet_func(unsigned long data)
1491{
1492 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1493 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1494 unsigned int status;
1495 unsigned int status_change;
1496
1497 /* The interrupt handler does not take the lock */
1498 spin_lock(&port->lock);
1499
a930e528 1500 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1501
1502 status = atmel_port->irq_status;
1503 status_change = status ^ atmel_port->irq_status_prev;
1504
1505 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1506 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1507 /* TODO: All reads to CSR will clear these interrupts! */
1508 if (status_change & ATMEL_US_RI)
1509 port->icount.rng++;
1510 if (status_change & ATMEL_US_DSR)
1511 port->icount.dsr++;
1512 if (status_change & ATMEL_US_DCD)
1513 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1514 if (status_change & ATMEL_US_CTS)
1515 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1516
bdc04e31 1517 wake_up_interruptible(&port->state->port.delta_msr_wait);
1ecc26bd
RB		 1518
1519 atmel_port->irq_status_prev = status;
1520 }
1521
a930e528 1522 atmel_port->schedule_rx(port);
1ecc26bd
RB		 1523
1524 spin_unlock(&port->lock);
1525}
1526
33d64c4f
ES		 1527static int atmel_init_property(struct atmel_uart_port *atmel_port,
1528 struct platform_device *pdev)
1529{
1530 struct device_node *np = pdev->dev.of_node;
574de559 1531 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1532
1533 if (np) {
1534 /* DMA/PDC usage specification */
1535 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1536 if (of_get_property(np, "dmas", NULL)) {
1537 atmel_port->use_dma_rx = true;
1538 atmel_port->use_pdc_rx = false;
1539 } else {
1540 atmel_port->use_dma_rx = false;
1541 atmel_port->use_pdc_rx = true;
1542 }
1543 } else {
1544 atmel_port->use_dma_rx = false;
1545 atmel_port->use_pdc_rx = false;
1546 }
1547
1548 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1549 if (of_get_property(np, "dmas", NULL)) {
1550 atmel_port->use_dma_tx = true;
1551 atmel_port->use_pdc_tx = false;
1552 } else {
1553 atmel_port->use_dma_tx = false;
1554 atmel_port->use_pdc_tx = true;
1555 }
1556 } else {
1557 atmel_port->use_dma_tx = false;
1558 atmel_port->use_pdc_tx = false;
1559 }
1560
1561 } else {
1562 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1563 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1564 atmel_port->use_dma_rx = false;
1565 atmel_port->use_dma_tx = false;
1566 }
1567
1568 return 0;
1569}
1570
1571static void atmel_init_rs485(struct atmel_uart_port *atmel_port,
1572 struct platform_device *pdev)
1573{
1574 struct device_node *np = pdev->dev.of_node;
574de559 1575 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1576
1577 if (np) {
1578 u32 rs485_delay[2];
1579 /* rs485 properties */
1580 if (of_property_read_u32_array(np, "rs485-rts-delay",
1581 rs485_delay, 2) == 0) {
1582 struct serial_rs485 *rs485conf = &atmel_port->rs485;
1583
1584 rs485conf->delay_rts_before_send = rs485_delay[0];
1585 rs485conf->delay_rts_after_send = rs485_delay[1];
1586 rs485conf->flags = 0;
1587
1588 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1589 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1590
1591 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1592 NULL))
1593 rs485conf->flags |= SER_RS485_ENABLED;
1594 }
1595 } else {
1596 atmel_port->rs485 = pdata->rs485;
1597 }
1598
1599}
1600
a930e528
ES		 1601static void atmel_set_ops(struct uart_port *port)
1602{
1603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1604
34df42f5
ES		 1605 if (atmel_use_dma_rx(port)) {
1606 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1607 atmel_port->schedule_rx = &atmel_rx_from_dma;
1608 atmel_port->release_rx = &atmel_release_rx_dma;
1609 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1610 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1611 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1612 atmel_port->release_rx = &atmel_release_rx_pdc;
1613 } else {
1614 atmel_port->prepare_rx = NULL;
1615 atmel_port->schedule_rx = &atmel_rx_from_ring;
1616 atmel_port->release_rx = NULL;
1617 }
1618
08f738be
ES		 1619 if (atmel_use_dma_tx(port)) {
1620 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1621 atmel_port->schedule_tx = &atmel_tx_dma;
1622 atmel_port->release_tx = &atmel_release_tx_dma;
1623 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1624 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1625 atmel_port->schedule_tx = &atmel_tx_pdc;
1626 atmel_port->release_tx = &atmel_release_tx_pdc;
1627 } else {
1628 atmel_port->prepare_tx = NULL;
1629 atmel_port->schedule_tx = &atmel_tx_chars;
1630 atmel_port->release_tx = NULL;
1631 }
1632}
1633
055560b0
ES		 1634/*
1635 * Get ip name usart or uart
1636 */
892db58b 1637static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1638{
1639 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1640 int name = UART_GET_IP_NAME(port);
731d9cae 1641 u32 version;
055560b0
ES		 1642 int usart, uart;
1643 /* usart and uart ascii */
1644 usart = 0x55534152;
1645 uart = 0x44424755;
1646
1647 atmel_port->is_usart = false;
1648
1649 if (name == usart) {
1650 dev_dbg(port->dev, "This is usart\n");
1651 atmel_port->is_usart = true;
1652 } else if (name == uart) {
1653 dev_dbg(port->dev, "This is uart\n");
1654 atmel_port->is_usart = false;
1655 } else {
731d9cae
NF		 1656 /* fallback for older SoCs: use version field */
1657 version = UART_GET_IP_VERSION(port);
1658 switch (version) {
1659 case 0x302:
1660 case 0x10213:
1661 dev_dbg(port->dev, "This version is usart\n");
1662 atmel_port->is_usart = true;
1663 break;
1664 case 0x203:
1665 case 0x10202:
1666 dev_dbg(port->dev, "This version is uart\n");
1667 atmel_port->is_usart = false;
1668 break;
1669 default:
1670 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1671 }
055560b0 1672 }
055560b0
ES		 1673}
1674
ab5e4e41
RG		 1675static void atmel_free_gpio_irq(struct uart_port *port)
1676{
1677 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1678 enum mctrl_gpio_idx i;
1679
1680 for (i = 0; i < UART_GPIO_MAX; i++)
1681 if (atmel_port->gpio_irq[i] >= 0)
1682 free_irq(atmel_port->gpio_irq[i], port);
1683}
1684
1685static int atmel_request_gpio_irq(struct uart_port *port)
1686{
1687 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1688 int *irq = atmel_port->gpio_irq;
1689 enum mctrl_gpio_idx i;
1690 int err = 0;
1691
1692 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1693 if (irq[i] < 0)
1694 continue;
1695
1696 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1697 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1698 "atmel_serial", port);
1699 if (err)
1700 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1701 irq[i]);
1702 }
1703
1704 /*
1705 * If something went wrong, rollback.
1706 */
1707 while (err && (--i >= 0))
1708 if (irq[i] >= 0)
1709 free_irq(irq[i], port);
1710
1711 return err;
1712}
1713
1e6c9c28
AV		 1714/*
1715 * Perform initialization and enable port for reception
1716 */
7192f92c 1717static int atmel_startup(struct uart_port *port)
1e6c9c28 1718{
33d64c4f 1719 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1720 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1721 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV		 1722 int retval;
1723
1724 /*
1725 * Ensure that no interrupts are enabled otherwise when
1726 * request_irq() is called we could get stuck trying to
1727 * handle an unexpected interrupt
1728 */
1729 UART_PUT_IDR(port, -1);
ab5e4e41 1730 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1731
1732 /*
1733 * Allocate the IRQ
1734 */
b843aa21 1735 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
ae161068 1736 tty ? tty->name : "atmel_serial", port);
1e6c9c28 1737 if (retval) {
ddaa6037 1738 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1739 return retval;
1740 }
1741
ab5e4e41
RG		 1742 /*
1743 * Get the GPIO lines IRQ
1744 */
1745 retval = atmel_request_gpio_irq(port);
1746 if (retval)
1747 goto free_irq;
1748
a6670615
CC		 1749 /*
1750 * Initialize DMA (if necessary)
1751 */
33d64c4f
ES		 1752 atmel_init_property(atmel_port, pdev);
1753
a930e528
ES		 1754 if (atmel_port->prepare_rx) {
1755 retval = atmel_port->prepare_rx(port);
1756 if (retval < 0)
1757 atmel_set_ops(port);
a6670615 1758 }
a6670615 1759
a930e528
ES		 1760 if (atmel_port->prepare_tx) {
1761 retval = atmel_port->prepare_tx(port);
1762 if (retval < 0)
1763 atmel_set_ops(port);
a6670615 1764 }
1e6c9c28 1765
27c0c8e5 1766 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 1767 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5
AN		 1768 atmel_port->irq_status = atmel_port->irq_status_prev;
1769
1e6c9c28
AV		 1770 /*
1771 * Finally, enable the serial port
1772 */
7192f92c 1773 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB		 1774 /* enable xmit & rcvr */
1775 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 1776
8bc661bf
MR		 1777 setup_timer(&atmel_port->uart_timer,
1778 atmel_uart_timer_callback,
1779 (unsigned long)port);
1780
64e22ebe 1781 if (atmel_use_pdc_rx(port)) {
a6670615 1782 /* set UART timeout */
2e68c22f 1783 if (!atmel_port->is_usart) {
2e68c22f
ES		 1784 mod_timer(&atmel_port->uart_timer,
1785 jiffies + uart_poll_timeout(port));
1786 /* set USART timeout */
1787 } else {
1788 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1789 UART_PUT_CR(port, ATMEL_US_STTTO);
a6670615 1790
2e68c22f
ES		 1791 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1792 }
a6670615
CC		 1793 /* enable PDC controller */
1794 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
34df42f5 1795 } else if (atmel_use_dma_rx(port)) {
2e68c22f
ES		 1796 /* set UART timeout */
1797 if (!atmel_port->is_usart) {
2e68c22f
ES		 1798 mod_timer(&atmel_port->uart_timer,
1799 jiffies + uart_poll_timeout(port));
1800 /* set USART timeout */
1801 } else {
1802 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1803 UART_PUT_CR(port, ATMEL_US_STTTO);
34df42f5 1804
2e68c22f
ES		 1805 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1806 }
a6670615
CC		 1807 } else {
1808 /* enable receive only */
1809 UART_PUT_IER(port, ATMEL_US_RXRDY);
1810 }
afefc415 1811
1e6c9c28 1812 return 0;
ab5e4e41
RG		 1813
1814free_irq:
1815 free_irq(port->irq, port);
1816
1817 return retval;
1e6c9c28
AV		 1818}
1819
479e9b94
PH		 1820/*
1821 * Flush any TX data submitted for DMA. Called when the TX circular
1822 * buffer is reset.
1823 */
1824static void atmel_flush_buffer(struct uart_port *port)
1825{
1826 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1827
1828 if (atmel_use_pdc_tx(port)) {
1829 UART_PUT_TCR(port, 0);
1830 atmel_port->pdc_tx.ofs = 0;
1831 }
1832}
1833
1e6c9c28
AV		 1834/*
1835 * Disable the port
1836 */
7192f92c 1837static void atmel_shutdown(struct uart_port *port)
1e6c9c28 1838{
c811ab8c 1839 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 1840
8bc661bf
MR		 1841 /*
1842 * Prevent any tasklets being scheduled during
1843 * cleanup
1844 */
1845 del_timer_sync(&atmel_port->uart_timer);
1846
0cc7c6c7
MR		 1847 /*
1848 * Clear out any scheduled tasklets before
1849 * we destroy the buffers
1850 */
1851 tasklet_kill(&atmel_port->tasklet);
1852
a6670615 1853 /*
0cc7c6c7
MR		 1854 * Ensure everything is stopped and
1855 * disable all interrupts, port and break condition.
a6670615
CC		 1856 */
1857 atmel_stop_rx(port);
1858 atmel_stop_tx(port);
1859
0cc7c6c7
MR		 1860 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1861 UART_PUT_IDR(port, -1);
1862
1863
a6670615
CC		 1864 /*
1865 * Shut-down the DMA.
1866 */
a930e528
ES		 1867 if (atmel_port->release_rx)
1868 atmel_port->release_rx(port);
1869 if (atmel_port->release_tx)
1870 atmel_port->release_tx(port);
a6670615 1871
bb7e73c5
MD		 1872 /*
1873 * Reset ring buffer pointers
1874 */
1875 atmel_port->rx_ring.head = 0;
1876 atmel_port->rx_ring.tail = 0;
1877
1e6c9c28 1878 /*
ab5e4e41 1879 * Free the interrupts
1e6c9c28
AV		 1880 */
1881 free_irq(port->irq, port);
ab5e4e41
RG		 1882 atmel_free_gpio_irq(port);
1883
1884 atmel_port->ms_irq_enabled = false;
1e6c9c28 1885
479e9b94 1886 atmel_flush_buffer(port);
9afd561a
HS		 1887}
1888
1e6c9c28
AV		 1889/*
1890 * Power / Clock management.
1891 */
b843aa21
RB		 1892static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1893 unsigned int oldstate)
1e6c9c28 1894{
c811ab8c 1895 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1896
1e6c9c28 1897 switch (state) {
b843aa21
RB		 1898 case 0:
1899 /*
1900 * Enable the peripheral clock for this serial port.
1901 * This is called on uart_open() or a resume event.
1902 */
91f8c2d8 1903 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 1904
1905 /* re-enable interrupts if we disabled some on suspend */
1906 UART_PUT_IER(port, atmel_port->backup_imr);
b843aa21
RB		 1907 break;
1908 case 3:
f05596db
AS		 1909 /* Back up the interrupt mask and disable all interrupts */
1910 atmel_port->backup_imr = UART_GET_IMR(port);
1911 UART_PUT_IDR(port, -1);
1912
b843aa21
RB		 1913 /*
1914 * Disable the peripheral clock for this serial port.
1915 * This is called on uart_close() or a suspend event.
1916 */
91f8c2d8 1917 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 1918 break;
1919 default:
ddaa6037 1920 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 1921 }
1922}
1923
1924/*
1925 * Change the port parameters
1926 */
b843aa21
RB		 1927static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1928 struct ktermios *old)
1e6c9c28
AV		 1929{
1930 unsigned long flags;
1931 unsigned int mode, imr, quot, baud;
e8faff73 1932 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 1933
03abeac0 1934 /* Get current mode register */
b843aa21 1935 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
8e706c4d
PM		 1936 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1937 | ATMEL_US_USMODE);
03abeac0 1938
b843aa21 1939 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 1940 quot = uart_get_divisor(port, baud);
1941
b843aa21 1942 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV		 1943 quot /= 8;
1944 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1945 }
1e6c9c28
AV		 1946
1947 /* byte size */
1948 switch (termios->c_cflag & CSIZE) {
1949 case CS5:
7192f92c 1950 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 1951 break;
1952 case CS6:
7192f92c 1953 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 1954 break;
1955 case CS7:
7192f92c 1956 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 1957 break;
1958 default:
7192f92c 1959 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 1960 break;
1961 }
1962
1963 /* stop bits */
1964 if (termios->c_cflag & CSTOPB)
7192f92c 1965 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 1966
1967 /* parity */
1968 if (termios->c_cflag & PARENB) {
b843aa21
RB		 1969 /* Mark or Space parity */
1970 if (termios->c_cflag & CMSPAR) {
1e6c9c28 1971 if (termios->c_cflag & PARODD)
7192f92c 1972 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 1973 else
7192f92c 1974 mode |= ATMEL_US_PAR_SPACE;
b843aa21 1975 } else if (termios->c_cflag & PARODD)
7192f92c 1976 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 1977 else
7192f92c 1978 mode |= ATMEL_US_PAR_EVEN;
b843aa21 1979 } else
7192f92c 1980 mode |= ATMEL_US_PAR_NONE;
1e6c9c28 1981
8e706c4d
PM		 1982 /* hardware handshake (RTS/CTS) */
1983 if (termios->c_cflag & CRTSCTS)
1984 mode |= ATMEL_US_USMODE_HWHS;
1985 else
1986 mode |= ATMEL_US_USMODE_NORMAL;
1987
1e6c9c28
AV		 1988 spin_lock_irqsave(&port->lock, flags);
1989
7192f92c 1990 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 1991 if (termios->c_iflag & INPCK)
7192f92c 1992 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 1993 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 1994 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 1995
64e22ebe 1996 if (atmel_use_pdc_rx(port))
a6670615
CC		 1997 /* need to enable error interrupts */
1998 UART_PUT_IER(port, port->read_status_mask);
1999
1e6c9c28
AV		 2000 /*
2001 * Characters to ignore
2002 */
2003 port->ignore_status_mask = 0;
2004 if (termios->c_iflag & IGNPAR)
7192f92c 2005 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2006 if (termios->c_iflag & IGNBRK) {
7192f92c 2007 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2008 /*
2009 * If we're ignoring parity and break indicators,
2010 * ignore overruns too (for real raw support).
2011 */
2012 if (termios->c_iflag & IGNPAR)
7192f92c 2013 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2014 }
b843aa21 2015 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2016
2017 /* update the per-port timeout */
2018 uart_update_timeout(port, termios->c_cflag, baud);
2019
0ccad870
HS		 2020 /*
2021 * save/disable interrupts. The tty layer will ensure that the
2022 * transmitter is empty if requested by the caller, so there's
2023 * no need to wait for it here.
2024 */
b843aa21
RB		 2025 imr = UART_GET_IMR(port);
2026 UART_PUT_IDR(port, -1);
1e6c9c28
AV		 2027
2028 /* disable receiver and transmitter */
7192f92c 2029 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28 2030
e8faff73
CS		 2031 /* Resetting serial mode to RS232 (0x0) */
2032 mode &= ~ATMEL_US_USMODE;
2033
2034 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
93f3350c 2035 if ((atmel_port->rs485.delay_rts_after_send) > 0)
1b633184
CS		 2036 UART_PUT_TTGR(port,
2037 atmel_port->rs485.delay_rts_after_send);
e8faff73 2038 mode |= ATMEL_US_USMODE_RS485;
e8faff73
CS		 2039 }
2040
1e6c9c28
AV		 2041 /* set the parity, stop bits and data size */
2042 UART_PUT_MR(port, mode);
2043
2044 /* set the baud rate */
2045 UART_PUT_BRGR(port, quot);
7192f92c
HS		 2046 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2047 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2048
2049 /* restore interrupts */
2050 UART_PUT_IER(port, imr);
2051
2052 /* CTS flow-control and modem-status interrupts */
2053 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2054 atmel_enable_ms(port);
2055 else
2056 atmel_disable_ms(port);
1e6c9c28
AV		 2057
2058 spin_unlock_irqrestore(&port->lock, flags);
2059}
2060
42bd7a4f
VP		 2061static void atmel_set_ldisc(struct uart_port *port, int new)
2062{
b54bf3b2 2063 if (new == N_PPS) {
42bd7a4f
VP		 2064 port->flags |= UPF_HARDPPS_CD;
2065 atmel_enable_ms(port);
2066 } else {
2067 port->flags &= ~UPF_HARDPPS_CD;
2068 }
2069}
2070
1e6c9c28
AV		 2071/*
2072 * Return string describing the specified port
2073 */
7192f92c 2074static const char *atmel_type(struct uart_port *port)
1e6c9c28 2075{
9ab4f88b 2076 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2077}
2078
2079/*
2080 * Release the memory region(s) being used by 'port'.
2081 */
7192f92c 2082static void atmel_release_port(struct uart_port *port)
1e6c9c28 2083{
afefc415
AV		 2084 struct platform_device *pdev = to_platform_device(port->dev);
2085 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2086
2087 release_mem_region(port->mapbase, size);
2088
2089 if (port->flags & UPF_IOREMAP) {
2090 iounmap(port->membase);
2091 port->membase = NULL;
2092 }
1e6c9c28
AV		 2093}
2094
2095/*
2096 * Request the memory region(s) being used by 'port'.
2097 */
7192f92c 2098static int atmel_request_port(struct uart_port *port)
1e6c9c28 2099{
afefc415
AV		 2100 struct platform_device *pdev = to_platform_device(port->dev);
2101 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2102
7192f92c 2103 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2104 return -EBUSY;
2105
2106 if (port->flags & UPF_IOREMAP) {
2107 port->membase = ioremap(port->mapbase, size);
2108 if (port->membase == NULL) {
2109 release_mem_region(port->mapbase, size);
2110 return -ENOMEM;
2111 }
2112 }
1e6c9c28 2113
afefc415 2114 return 0;
1e6c9c28
AV		 2115}
2116
2117/*
2118 * Configure/autoconfigure the port.
2119 */
7192f92c 2120static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2121{
2122 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2123 port->type = PORT_ATMEL;
7192f92c 2124 atmel_request_port(port);
1e6c9c28
AV		 2125 }
2126}
2127
2128/*
2129 * Verify the new serial_struct (for TIOCSSERIAL).
2130 */
7192f92c 2131static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2132{
2133 int ret = 0;
9ab4f88b 2134 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2135 ret = -EINVAL;
2136 if (port->irq != ser->irq)
2137 ret = -EINVAL;
2138 if (ser->io_type != SERIAL_IO_MEM)
2139 ret = -EINVAL;
2140 if (port->uartclk / 16 != ser->baud_base)
2141 ret = -EINVAL;
2142 if ((void *)port->mapbase != ser->iomem_base)
2143 ret = -EINVAL;
2144 if (port->iobase != ser->port)
2145 ret = -EINVAL;
2146 if (ser->hub6 != 0)
2147 ret = -EINVAL;
2148 return ret;
2149}
2150
8fe2d541
AT		 2151#ifdef CONFIG_CONSOLE_POLL
2152static int atmel_poll_get_char(struct uart_port *port)
2153{
2154 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
2155 cpu_relax();
2156
2157 return UART_GET_CHAR(port);
2158}
2159
2160static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2161{
2162 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2163 cpu_relax();
2164
2165 UART_PUT_CHAR(port, ch);
2166}
2167#endif
2168
e8faff73
CS		 2169static int
2170atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
2171{
2172 struct serial_rs485 rs485conf;
2173
2174 switch (cmd) {
2175 case TIOCSRS485:
2176 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
2177 sizeof(rs485conf)))
2178 return -EFAULT;
2179
2180 atmel_config_rs485(port, &rs485conf);
2181 break;
2182
2183 case TIOCGRS485:
2184 if (copy_to_user((struct serial_rs485 *) arg,
2185 &(to_atmel_uart_port(port)->rs485),
2186 sizeof(rs485conf)))
2187 return -EFAULT;
2188 break;
2189
2190 default:
2191 return -ENOIOCTLCMD;
2192 }
2193 return 0;
2194}
2195
2196
2197
7192f92c
HS		 2198static struct uart_ops atmel_pops = {
2199 .tx_empty = atmel_tx_empty,
2200 .set_mctrl = atmel_set_mctrl,
2201 .get_mctrl = atmel_get_mctrl,
2202 .stop_tx = atmel_stop_tx,
2203 .start_tx = atmel_start_tx,
2204 .stop_rx = atmel_stop_rx,
2205 .enable_ms = atmel_enable_ms,
2206 .break_ctl = atmel_break_ctl,
2207 .startup = atmel_startup,
2208 .shutdown = atmel_shutdown,
9afd561a 2209 .flush_buffer = atmel_flush_buffer,
7192f92c 2210 .set_termios = atmel_set_termios,
42bd7a4f 2211 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2212 .type = atmel_type,
2213 .release_port = atmel_release_port,
2214 .request_port = atmel_request_port,
2215 .config_port = atmel_config_port,
2216 .verify_port = atmel_verify_port,
2217 .pm = atmel_serial_pm,
e8faff73 2218 .ioctl = atmel_ioctl,
8fe2d541
AT		 2219#ifdef CONFIG_CONSOLE_POLL
2220 .poll_get_char = atmel_poll_get_char,
2221 .poll_put_char = atmel_poll_put_char,
2222#endif
1e6c9c28
AV		 2223};
2224
afefc415
AV		 2225/*
2226 * Configure the port from the platform device resource info.
2227 */
91f8c2d8 2228static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2229 struct platform_device *pdev)
1e6c9c28 2230{
91f8c2d8 2231 int ret;
7192f92c 2232 struct uart_port *port = &atmel_port->uart;
574de559 2233 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
afefc415 2234
33d64c4f
ES		 2235 if (!atmel_init_property(atmel_port, pdev))
2236 atmel_set_ops(port);
afefc415 2237
33d64c4f 2238 atmel_init_rs485(atmel_port, pdev);
a930e528 2239
e8faff73
CS		 2240 port->iotype = UPIO_MEM;
2241 port->flags = UPF_BOOT_AUTOCONF;
2242 port->ops = &atmel_pops;
2243 port->fifosize = 1;
e8faff73 2244 port->dev = &pdev->dev;
afefc415
AV		 2245 port->mapbase = pdev->resource[0].start;
2246 port->irq = pdev->resource[1].start;
2247
1ecc26bd
RB		 2248 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2249 (unsigned long)port);
2250
2251 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2252
5fbe46b6 2253 if (pdata && pdata->regs) {
75d35213 2254 /* Already mapped by setup code */
1acfc7ec 2255 port->membase = pdata->regs;
588edbf3 2256 } else {
afefc415
AV		 2257 port->flags |= UPF_IOREMAP;
2258 port->membase = NULL;
2259 }
1e6c9c28 2260
b843aa21
RB		 2261 /* for console, the clock could already be configured */
2262 if (!atmel_port->clk) {
7192f92c 2263 atmel_port->clk = clk_get(&pdev->dev, "usart");
91f8c2d8
BB		 2264 if (IS_ERR(atmel_port->clk)) {
2265 ret = PTR_ERR(atmel_port->clk);
2266 atmel_port->clk = NULL;
2267 return ret;
2268 }
2269 ret = clk_prepare_enable(atmel_port->clk);
2270 if (ret) {
2271 clk_put(atmel_port->clk);
2272 atmel_port->clk = NULL;
2273 return ret;
2274 }
7192f92c 2275 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2276 clk_disable_unprepare(atmel_port->clk);
06a7f058 2277 /* only enable clock when USART is in use */
afefc415 2278 }
a6670615 2279
e8faff73
CS		 2280 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2281 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
2282 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2283 else if (atmel_use_pdc_tx(port)) {
a6670615 2284 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2285 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2286 } else {
2287 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2288 }
91f8c2d8
BB		 2289
2290 return 0;
1e6c9c28
AV		 2291}
2292
69f6a27b
JCPV		 2293struct platform_device *atmel_default_console_device; /* the serial console device */
2294
749c4e60 2295#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2296static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2297{
7192f92c 2298 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 2299 cpu_relax();
d358788f
RK		 2300 UART_PUT_CHAR(port, ch);
2301}
1e6c9c28
AV		 2302
2303/*
2304 * Interrupts are disabled on entering
2305 */
7192f92c 2306static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2307{
7192f92c 2308 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2309 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2310 unsigned int status, imr;
39d4c922 2311 unsigned int pdc_tx;
1e6c9c28
AV		 2312
2313 /*
b843aa21 2314 * First, save IMR and then disable interrupts
1e6c9c28 2315 */
b843aa21 2316 imr = UART_GET_IMR(port);
e8faff73 2317 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2318
39d4c922
MP		 2319 /* Store PDC transmit status and disable it */
2320 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2321 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2322
7192f92c 2323 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2324
2325 /*
b843aa21
RB		 2326 * Finally, wait for transmitter to become empty
2327 * and restore IMR
1e6c9c28
AV		 2328 */
2329 do {
2330 status = UART_GET_CSR(port);
7192f92c 2331 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2332
2333 /* Restore PDC transmit status */
2334 if (pdc_tx)
2335 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2336
b843aa21
RB		 2337 /* set interrupts back the way they were */
2338 UART_PUT_IER(port, imr);
1e6c9c28
AV		 2339}
2340
2341/*
b843aa21
RB		 2342 * If the port was already initialised (eg, by a boot loader),
2343 * try to determine the current setup.
1e6c9c28 2344 */
b843aa21
RB		 2345static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2346 int *parity, int *bits)
1e6c9c28
AV		 2347{
2348 unsigned int mr, quot;
2349
1c0fd82f
HS		 2350 /*
2351 * If the baud rate generator isn't running, the port wasn't
2352 * initialized by the boot loader.
2353 */
9c81c5c9 2354 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1c0fd82f
HS		 2355 if (!quot)
2356 return;
1e6c9c28 2357
7192f92c
HS		 2358 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2359 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2360 *bits = 8;
2361 else
2362 *bits = 7;
2363
7192f92c
HS		 2364 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2365 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2366 *parity = 'e';
7192f92c 2367 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2368 *parity = 'o';
2369
4d5e392c
HS		 2370 /*
2371 * The serial core only rounds down when matching this to a
2372 * supported baud rate. Make sure we don't end up slightly
2373 * lower than one of those, as it would make us fall through
2374 * to a much lower baud rate than we really want.
2375 */
4d5e392c 2376 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2377}
2378
7192f92c 2379static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2380{
91f8c2d8 2381 int ret;
7192f92c 2382 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV		 2383 int baud = 115200;
2384 int bits = 8;
2385 int parity = 'n';
2386 int flow = 'n';
2387
b843aa21
RB		 2388 if (port->membase == NULL) {
2389 /* Port not initialized yet - delay setup */
afefc415 2390 return -ENODEV;
b843aa21 2391 }
1e6c9c28 2392
91f8c2d8
BB		 2393 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2394 if (ret)
2395 return ret;
06a7f058 2396
b843aa21 2397 UART_PUT_IDR(port, -1);
7192f92c
HS		 2398 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2399 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2400
2401 if (options)
2402 uart_parse_options(options, &baud, &parity, &bits, &flow);
2403 else
7192f92c 2404 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2405
2406 return uart_set_options(port, co, baud, parity, bits, flow);
2407}
2408
7192f92c 2409static struct uart_driver atmel_uart;
1e6c9c28 2410
7192f92c
HS		 2411static struct console atmel_console = {
2412 .name = ATMEL_DEVICENAME,
2413 .write = atmel_console_write,
1e6c9c28 2414 .device = uart_console_device,
7192f92c 2415 .setup = atmel_console_setup,
1e6c9c28
AV		 2416 .flags = CON_PRINTBUFFER,
2417 .index = -1,
7192f92c 2418 .data = &atmel_uart,
1e6c9c28
AV		 2419};
2420
06a7f058 2421#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2422
afefc415
AV		 2423/*
2424 * Early console initialization (before VM subsystem initialized).
2425 */
7192f92c 2426static int __init atmel_console_init(void)
1e6c9c28 2427{
91f8c2d8 2428 int ret;
73e2798b 2429 if (atmel_default_console_device) {
0d0a3cc1 2430 struct atmel_uart_data *pdata =
574de559 2431 dev_get_platdata(&atmel_default_console_device->dev);
efb8d21b 2432 int id = pdata->num;
4cbf9f48
NF		 2433 struct atmel_uart_port *port = &atmel_ports[id];
2434
4cbf9f48
NF		 2435 port->backup_imr = 0;
2436 port->uart.line = id;
0d0a3cc1 2437
4cbf9f48 2438 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
91f8c2d8
BB		 2439 ret = atmel_init_port(port, atmel_default_console_device);
2440 if (ret)
2441 return ret;
7192f92c 2442 register_console(&atmel_console);
afefc415 2443 }
1e6c9c28 2444
1e6c9c28
AV		 2445 return 0;
2446}
b843aa21 2447
7192f92c 2448console_initcall(atmel_console_init);
1e6c9c28 2449
afefc415
AV		 2450/*
2451 * Late console initialization.
2452 */
7192f92c 2453static int __init atmel_late_console_init(void)
afefc415 2454{
b843aa21
RB		 2455 if (atmel_default_console_device
2456 && !(atmel_console.flags & CON_ENABLED))
7192f92c 2457 register_console(&atmel_console);
afefc415
AV		 2458
2459 return 0;
2460}
b843aa21 2461
7192f92c 2462core_initcall(atmel_late_console_init);
afefc415 2463
dfa7f343
HS		 2464static inline bool atmel_is_console_port(struct uart_port *port)
2465{
2466 return port->cons && port->cons->index == port->line;
2467}
2468
1e6c9c28 2469#else
7192f92c 2470#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2471
2472static inline bool atmel_is_console_port(struct uart_port *port)
2473{
2474 return false;
2475}
1e6c9c28
AV		 2476#endif
2477
7192f92c 2478static struct uart_driver atmel_uart = {
b843aa21
RB		 2479 .owner = THIS_MODULE,
2480 .driver_name = "atmel_serial",
2481 .dev_name = ATMEL_DEVICENAME,
2482 .major = SERIAL_ATMEL_MAJOR,
2483 .minor = MINOR_START,
2484 .nr = ATMEL_MAX_UART,
2485 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2486};
2487
afefc415 2488#ifdef CONFIG_PM
f826caa4
HS		 2489static bool atmel_serial_clk_will_stop(void)
2490{
2491#ifdef CONFIG_ARCH_AT91
2492 return at91_suspend_entering_slow_clock();
2493#else
2494 return false;
2495#endif
2496}
2497
b843aa21
RB		 2498static int atmel_serial_suspend(struct platform_device *pdev,
2499 pm_message_t state)
1e6c9c28 2500{
afefc415 2501 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2503
e1c609ef
HS		 2504 if (atmel_is_console_port(port) && console_suspend_enabled) {
2505 /* Drain the TX shifter */
2506 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2507 cpu_relax();
2508 }
2509
f05596db
AS		 2510 /* we can not wake up if we're running on slow clock */
2511 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2512 if (atmel_serial_clk_will_stop())
2513 device_set_wakeup_enable(&pdev->dev, 0);
2514
2515 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2516
afefc415
AV		 2517 return 0;
2518}
1e6c9c28 2519
7192f92c 2520static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2521{
2522 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2524
f05596db
AS		 2525 uart_resume_port(&atmel_uart, port);
2526 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2527
2528 return 0;
2529}
afefc415 2530#else
7192f92c
HS		 2531#define atmel_serial_suspend NULL
2532#define atmel_serial_resume NULL
afefc415 2533#endif
1e6c9c28 2534
e0b0baad
RG		 2535static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2536{
ab5e4e41
RG		 2537 enum mctrl_gpio_idx i;
2538 struct gpio_desc *gpiod;
2539
e0b0baad
RG		 2540 p->gpios = mctrl_gpio_init(dev, 0);
2541 if (IS_ERR_OR_NULL(p->gpios))
2542 return -1;
2543
ab5e4e41
RG		 2544 for (i = 0; i < UART_GPIO_MAX; i++) {
2545 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2546 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2547 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2548 else
2549 p->gpio_irq[i] = -EINVAL;
2550 }
2551
e0b0baad
RG		 2552 return 0;
2553}
2554
9671f099 2555static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2556{
7192f92c 2557 struct atmel_uart_port *port;
5fbe46b6 2558 struct device_node *np = pdev->dev.of_node;
574de559 2559 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1ecc26bd 2560 void *data;
4cbf9f48 2561 int ret = -ENODEV;
1e6c9c28 2562
9d09daf8 2563 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2564
5fbe46b6
NF		 2565 if (np)
2566 ret = of_alias_get_id(np, "serial");
2567 else
2568 if (pdata)
2569 ret = pdata->num;
4cbf9f48
NF		 2570
2571 if (ret < 0)
5fbe46b6 2572 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2573 * auto-enumerate it */
503bded9 2574 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2575
503bded9 2576 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2577 ret = -ENODEV;
2578 goto err;
2579 }
2580
503bded9 2581 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2582 /* port already in use */
2583 ret = -EBUSY;
2584 goto err;
2585 }
2586
2587 port = &atmel_ports[ret];
f05596db 2588 port->backup_imr = 0;
4cbf9f48 2589 port->uart.line = ret;
e0b0baad
RG		 2590
2591 ret = atmel_init_gpios(port, &pdev->dev);
2592 if (ret < 0)
2593 dev_err(&pdev->dev, "%s",
2594 "Failed to initialize GPIOs. The serial port may not work as expected");
f05596db 2595
91f8c2d8
BB		 2596 ret = atmel_init_port(port, pdev);
2597 if (ret)
2598 goto err;
1e6c9c28 2599
64e22ebe 2600 if (!atmel_use_pdc_rx(&port->uart)) {
a6670615 2601 ret = -ENOMEM;
6433471d
HS		 2602 data = kmalloc(sizeof(struct atmel_uart_char)
2603 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC		 2604 if (!data)
2605 goto err_alloc_ring;
2606 port->rx_ring.buf = data;
2607 }
1ecc26bd 2608
7192f92c 2609 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS		 2610 if (ret)
2611 goto err_add_port;
2612
8da14b5f 2613#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
06a7f058
DB		 2614 if (atmel_is_console_port(&port->uart)
2615 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2616 /*
2617 * The serial core enabled the clock for us, so undo
91f8c2d8 2618 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2619 */
91f8c2d8 2620 clk_disable_unprepare(port->clk);
06a7f058 2621 }
8da14b5f 2622#endif
06a7f058 2623
dfa7f343
HS		 2624 device_init_wakeup(&pdev->dev, 1);
2625 platform_set_drvdata(pdev, port);
2626
5dfbd1d7
CS		 2627 if (port->rs485.flags & SER_RS485_ENABLED) {
2628 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2629 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2630 }
2631
055560b0
ES		 2632 /*
2633 * Get port name of usart or uart
2634 */
892db58b 2635 atmel_get_ip_name(&port->uart);
055560b0 2636
dfa7f343
HS		 2637 return 0;
2638
2639err_add_port:
1ecc26bd
RB		 2640 kfree(port->rx_ring.buf);
2641 port->rx_ring.buf = NULL;
2642err_alloc_ring:
dfa7f343 2643 if (!atmel_is_console_port(&port->uart)) {
dfa7f343
HS		 2644 clk_put(port->clk);
2645 port->clk = NULL;
afefc415 2646 }
4cbf9f48 2647err:
afefc415
AV		 2648 return ret;
2649}
2650
ae8d8a14 2651static int atmel_serial_remove(struct platform_device *pdev)
afefc415
AV		 2652{
2653 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2654 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415
AV		 2655 int ret = 0;
2656
f50c995f
MR		 2657 tasklet_kill(&atmel_port->tasklet);
2658
afefc415 2659 device_init_wakeup(&pdev->dev, 0);
afefc415 2660
dfa7f343
HS		 2661 ret = uart_remove_one_port(&atmel_uart, port);
2662
1ecc26bd
RB		 2663 kfree(atmel_port->rx_ring.buf);
2664
dfa7f343
HS		 2665 /* "port" is allocated statically, so we shouldn't free it */
2666
503bded9 2667 clear_bit(port->line, atmel_ports_in_use);
4cbf9f48 2668
dfa7f343 2669 clk_put(atmel_port->clk);
afefc415
AV		 2670
2671 return ret;
2672}
2673
7192f92c
HS		 2674static struct platform_driver atmel_serial_driver = {
2675 .probe = atmel_serial_probe,
2d47b716 2676 .remove = atmel_serial_remove,
7192f92c
HS		 2677 .suspend = atmel_serial_suspend,
2678 .resume = atmel_serial_resume,
afefc415 2679 .driver = {
1e8ea802 2680 .name = "atmel_usart",
afefc415 2681 .owner = THIS_MODULE,
5fbe46b6 2682 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 2683 },
2684};
2685
7192f92c 2686static int __init atmel_serial_init(void)
afefc415
AV		 2687{
2688 int ret;
2689
7192f92c 2690 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 2691 if (ret)
2692 return ret;
2693
7192f92c 2694 ret = platform_driver_register(&atmel_serial_driver);
afefc415 2695 if (ret)
7192f92c 2696 uart_unregister_driver(&atmel_uart);
afefc415
AV		 2697
2698 return ret;
2699}
2700
7192f92c 2701static void __exit atmel_serial_exit(void)
afefc415 2702{
7192f92c
HS		 2703 platform_driver_unregister(&atmel_serial_driver);
2704 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV		 2705}
2706
7192f92c
HS		 2707module_init(atmel_serial_init);
2708module_exit(atmel_serial_exit);
1e6c9c28
AV		 2709
2710MODULE_AUTHOR("Rick Bronson");
7192f92c 2711MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 2712MODULE_LICENSE("GPL");
e169c139 2713MODULE_ALIAS("platform:atmel_usart");
Linux 6.x block layer and io_uring tree(s)