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ACPI / SBS: Add 5 us delay to fix SBS hangs on MacBook
[linux-2.6-block.git] / drivers / tty / serial / atmel_serial.c
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1e6c9c28 1/*
7192f92c 2 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV		 3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
a6670615
CC		 8 * DMA support added by Chip Coldwell.
9 *
1e6c9c28
AV		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV		 25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
afefc415 31#include <linux/clk.h>
1e6c9c28
AV		 32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
afefc415 35#include <linux/platform_device.h>
5fbe46b6
NF		 36#include <linux/of.h>
37#include <linux/of_device.h>
354e57f3 38#include <linux/of_gpio.h>
a6670615 39#include <linux/dma-mapping.h>
6b997bab 40#include <linux/dmaengine.h>
93a3ddc2 41#include <linux/atmel_pdc.h>
fa3218d8 42#include <linux/atmel_serial.h>
e8faff73 43#include <linux/uaccess.h>
bcd2360c 44#include <linux/platform_data/atmel.h>
2e68c22f 45#include <linux/timer.h>
354e57f3 46#include <linux/gpio.h>
e0b0baad
RG		 47#include <linux/gpio/consumer.h>
48#include <linux/err.h>
ab5e4e41 49#include <linux/irq.h>
2c7af5ba 50#include <linux/suspend.h>
1e6c9c28
AV		 51
52#include <asm/io.h>
f7512e7c 53#include <asm/ioctls.h>
1e6c9c28 54
a6670615
CC		 55#define PDC_BUFFER_SIZE 512
56/* Revisit: We should calculate this based on the actual port settings */
57#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58
749c4e60 59#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 60#define SUPPORT_SYSRQ
61#endif
62
63#include <linux/serial_core.h>
64
e0b0baad
RG		 65#include "serial_mctrl_gpio.h"
66
e8faff73
CS		 67static void atmel_start_rx(struct uart_port *port);
68static void atmel_stop_rx(struct uart_port *port);
69
749c4e60 70#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 71
72/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
73 * should coexist with the 8250 driver, such as if we have an external 16C550
74 * UART. */
7192f92c 75#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 76#define MINOR_START 154
7192f92c 77#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 78
79#else
80
81/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
82 * name, but it is legally reserved for the 8250 driver. */
7192f92c 83#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 84#define MINOR_START 64
7192f92c 85#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 86
87#endif
88
7192f92c 89#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 90
b843aa21 91/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS		 92#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
93#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
94#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
95#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
96#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
97#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
98#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
99#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
100#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
101#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
102#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
103#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
e8faff73 104#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
055560b0 105#define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
731d9cae 106#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
544fc728 107
1e6c9c28 108 /* PDC registers */
544fc728
HS		 109#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
110#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
111
112#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
113#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
114#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
115#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
116#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
117
118#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
119#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
39d4c922 120#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
1e6c9c28 121
a6670615
CC		 122struct atmel_dma_buffer {
123 unsigned char *buf;
124 dma_addr_t dma_addr;
125 unsigned int dma_size;
126 unsigned int ofs;
127};
128
1ecc26bd
RB		 129struct atmel_uart_char {
130 u16 status;
131 u16 ch;
132};
133
134#define ATMEL_SERIAL_RINGSIZE 1024
135
afefc415
AV		 136/*
137 * We wrap our port structure around the generic uart_port.
138 */
7192f92c 139struct atmel_uart_port {
afefc415
AV		 140 struct uart_port uart; /* uart */
141 struct clk *clk; /* uart clock */
f05596db
AS		 142 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
143 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 144 int break_active; /* break being received */
1ecc26bd 145
34df42f5 146 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 147 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 148 short pdc_rx_idx; /* current PDC RX buffer */
149 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
150
08f738be 151 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 152 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 153 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
154
08f738be 155 spinlock_t lock_tx; /* port lock */
34df42f5 156 spinlock_t lock_rx; /* port lock */
08f738be 157 struct dma_chan *chan_tx;
34df42f5 158 struct dma_chan *chan_rx;
08f738be 159 struct dma_async_tx_descriptor *desc_tx;
34df42f5 160 struct dma_async_tx_descriptor *desc_rx;
08f738be 161 dma_cookie_t cookie_tx;
34df42f5 162 dma_cookie_t cookie_rx;
08f738be 163 struct scatterlist sg_tx;
34df42f5 164 struct scatterlist sg_rx;
1ecc26bd
RB		 165 struct tasklet_struct tasklet;
166 unsigned int irq_status;
167 unsigned int irq_status_prev;
168
169 struct circ_buf rx_ring;
e8faff73 170
e0b0baad 171 struct mctrl_gpios *gpios;
ab5e4e41 172 int gpio_irq[UART_GPIO_MAX];
e8faff73 173 unsigned int tx_done_mask;
ab5e4e41 174 bool ms_irq_enabled;
055560b0 175 bool is_usart; /* usart or uart */
2e68c22f 176 struct timer_list uart_timer; /* uart timer */
2c7af5ba
BB		 177
178 bool suspended;
179 unsigned int pending;
180 unsigned int pending_status;
181 spinlock_t lock_suspended;
182
a930e528
ES		 183 int (*prepare_rx)(struct uart_port *port);
184 int (*prepare_tx)(struct uart_port *port);
185 void (*schedule_rx)(struct uart_port *port);
186 void (*schedule_tx)(struct uart_port *port);
187 void (*release_rx)(struct uart_port *port);
188 void (*release_tx)(struct uart_port *port);
afefc415
AV		 189};
190
7192f92c 191static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 192static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 193
1e6c9c28 194#ifdef SUPPORT_SYSRQ
7192f92c 195static struct console atmel_console;
1e6c9c28
AV		 196#endif
197
5fbe46b6
NF		 198#if defined(CONFIG_OF)
199static const struct of_device_id atmel_serial_dt_ids[] = {
200 { .compatible = "atmel,at91rm9200-usart" },
201 { .compatible = "atmel,at91sam9260-usart" },
202 { /* sentinel */ }
203};
204
205MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
206#endif
207
c811ab8c
HS		 208static inline struct atmel_uart_port *
209to_atmel_uart_port(struct uart_port *uart)
210{
211 return container_of(uart, struct atmel_uart_port, uart);
212}
213
a6670615 214#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 215static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 216{
c811ab8c 217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 218
64e22ebe 219 return atmel_port->use_pdc_rx;
a6670615
CC		 220}
221
64e22ebe 222static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 223{
c811ab8c 224 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 225
64e22ebe 226 return atmel_port->use_pdc_tx;
a6670615
CC		 227}
228#else
64e22ebe 229static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 230{
231 return false;
232}
233
64e22ebe 234static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 235{
236 return false;
237}
238#endif
239
08f738be
ES		 240static bool atmel_use_dma_tx(struct uart_port *port)
241{
242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
243
244 return atmel_port->use_dma_tx;
245}
246
34df42f5
ES		 247static bool atmel_use_dma_rx(struct uart_port *port)
248{
249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
250
251 return atmel_port->use_dma_rx;
252}
253
e0b0baad
RG		 254static unsigned int atmel_get_lines_status(struct uart_port *port)
255{
256 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
257 unsigned int status, ret = 0;
258
259 status = UART_GET_CSR(port);
260
261 mctrl_gpio_get(atmel_port->gpios, &ret);
262
263 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
264 UART_GPIO_CTS))) {
265 if (ret & TIOCM_CTS)
266 status &= ~ATMEL_US_CTS;
267 else
268 status |= ATMEL_US_CTS;
269 }
270
271 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
272 UART_GPIO_DSR))) {
273 if (ret & TIOCM_DSR)
274 status &= ~ATMEL_US_DSR;
275 else
276 status |= ATMEL_US_DSR;
277 }
278
279 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
280 UART_GPIO_RI))) {
281 if (ret & TIOCM_RI)
282 status &= ~ATMEL_US_RI;
283 else
284 status |= ATMEL_US_RI;
285 }
286
287 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
288 UART_GPIO_DCD))) {
289 if (ret & TIOCM_CD)
290 status &= ~ATMEL_US_DCD;
291 else
292 status |= ATMEL_US_DCD;
293 }
294
295 return status;
296}
297
e8faff73 298/* Enable or disable the rs485 support */
13bd3e6f
RRD		 299static int atmel_config_rs485(struct uart_port *port,
300 struct serial_rs485 *rs485conf)
e8faff73
CS		 301{
302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
303 unsigned int mode;
e8faff73
CS		 304
305 /* Disable interrupts */
306 UART_PUT_IDR(port, atmel_port->tx_done_mask);
307
308 mode = UART_GET_MR(port);
309
310 /* Resetting serial mode to RS232 (0x0) */
311 mode &= ~ATMEL_US_USMODE;
312
13bd3e6f 313 port->rs485 = *rs485conf;
e8faff73
CS		 314
315 if (rs485conf->flags & SER_RS485_ENABLED) {
316 dev_dbg(port->dev, "Setting UART to RS485\n");
317 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
93f3350c 318 if ((rs485conf->delay_rts_after_send) > 0)
1b633184 319 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
e8faff73
CS		 320 mode |= ATMEL_US_USMODE_RS485;
321 } else {
322 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 323 if (atmel_use_pdc_tx(port))
e8faff73
CS		 324 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
325 ATMEL_US_TXBUFE;
326 else
327 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
328 }
329 UART_PUT_MR(port, mode);
330
331 /* Enable interrupts */
332 UART_PUT_IER(port, atmel_port->tx_done_mask);
333
13bd3e6f 334 return 0;
e8faff73
CS		 335}
336
1e6c9c28
AV		 337/*
338 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
339 */
7192f92c 340static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 341{
7192f92c 342 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV		 343}
344
345/*
346 * Set state of the modem control output lines
347 */
7192f92c 348static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 349{
350 unsigned int control = 0;
1cf6e8fc
CP		 351 unsigned int mode = UART_GET_MR(port);
352 unsigned int rts_paused, rts_ready;
e8faff73 353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 354
1cf6e8fc
CP		 355 /* override mode to RS485 if needed, otherwise keep the current mode */
356 if (port->rs485.flags & SER_RS485_ENABLED) {
357 if ((port->rs485.delay_rts_after_send) > 0)
358 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send);
359 mode &= ~ATMEL_US_USMODE;
360 mode |= ATMEL_US_USMODE_RS485;
361 }
362
363 /* set the RTS line state according to the mode */
364 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
365 /* force RTS line to high level */
366 rts_paused = ATMEL_US_RTSEN;
367
368 /* give the control of the RTS line back to the hardware */
369 rts_ready = ATMEL_US_RTSDIS;
370 } else {
371 /* force RTS line to high level */
372 rts_paused = ATMEL_US_RTSDIS;
373
374 /* force RTS line to low level */
375 rts_ready = ATMEL_US_RTSEN;
376 }
377
1e6c9c28 378 if (mctrl & TIOCM_RTS)
1cf6e8fc 379 control |= rts_ready;
1e6c9c28 380 else
1cf6e8fc 381 control |= rts_paused;
1e6c9c28
AV		 382
383 if (mctrl & TIOCM_DTR)
7192f92c 384 control |= ATMEL_US_DTREN;
1e6c9c28 385 else
7192f92c 386 control |= ATMEL_US_DTRDIS;
1e6c9c28 387
afefc415
AV		 388 UART_PUT_CR(port, control);
389
e0b0baad
RG		 390 mctrl_gpio_set(atmel_port->gpios, mctrl);
391
afefc415 392 /* Local loopback mode? */
1cf6e8fc 393 mode &= ~ATMEL_US_CHMODE;
afefc415 394 if (mctrl & TIOCM_LOOP)
7192f92c 395 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 396 else
7192f92c 397 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 398
afefc415 399 UART_PUT_MR(port, mode);
1e6c9c28
AV		 400}
401
402/*
403 * Get state of the modem control input lines
404 */
7192f92c 405static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 406{
e0b0baad
RG		 407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
408 unsigned int ret = 0, status;
1e6c9c28
AV		 409
410 status = UART_GET_CSR(port);
411
412 /*
413 * The control signals are active low.
414 */
7192f92c 415 if (!(status & ATMEL_US_DCD))
1e6c9c28 416 ret |= TIOCM_CD;
7192f92c 417 if (!(status & ATMEL_US_CTS))
1e6c9c28 418 ret |= TIOCM_CTS;
7192f92c 419 if (!(status & ATMEL_US_DSR))
1e6c9c28 420 ret |= TIOCM_DSR;
7192f92c 421 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 422 ret |= TIOCM_RI;
423
e0b0baad 424 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 425}
426
427/*
428 * Stop transmitting.
429 */
7192f92c 430static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 431{
e8faff73
CS		 432 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
433
64e22ebe 434 if (atmel_use_pdc_tx(port)) {
a6670615
CC		 435 /* disable PDC transmit */
436 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
e8faff73
CS		 437 }
438 /* Disable interrupts */
439 UART_PUT_IDR(port, atmel_port->tx_done_mask);
440
13bd3e6f
RRD		 441 if ((port->rs485.flags & SER_RS485_ENABLED) &&
442 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73 443 atmel_start_rx(port);
1e6c9c28
AV		 444}
445
446/*
447 * Start transmitting.
448 */
7192f92c 449static void atmel_start_tx(struct uart_port *port)
1e6c9c28 450{
e8faff73
CS		 451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
452
64e22ebe 453 if (atmel_use_pdc_tx(port)) {
a6670615
CC		 454 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
455 /* The transmitter is already running. Yes, we
456 really need this.*/
457 return;
458
13bd3e6f
RRD		 459 if ((port->rs485.flags & SER_RS485_ENABLED) &&
460 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73
CS		 461 atmel_stop_rx(port);
462
a6670615
CC		 463 /* re-enable PDC transmit */
464 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
e8faff73
CS		 465 }
466 /* Enable interrupts */
467 UART_PUT_IER(port, atmel_port->tx_done_mask);
468}
469
470/*
471 * start receiving - port is in process of being opened.
472 */
473static void atmel_start_rx(struct uart_port *port)
474{
475 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
476
57c36868
SG		 477 UART_PUT_CR(port, ATMEL_US_RXEN);
478
64e22ebe 479 if (atmel_use_pdc_rx(port)) {
e8faff73
CS		 480 /* enable PDC controller */
481 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
482 port->read_status_mask);
483 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
484 } else {
485 UART_PUT_IER(port, ATMEL_US_RXRDY);
486 }
1e6c9c28
AV		 487}
488
489/*
490 * Stop receiving - port is in process of being closed.
491 */
7192f92c 492static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 493{
57c36868
SG		 494 UART_PUT_CR(port, ATMEL_US_RXDIS);
495
64e22ebe 496 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 497 /* disable PDC receive */
498 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
e8faff73
CS		 499 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
500 port->read_status_mask);
501 } else {
a6670615 502 UART_PUT_IDR(port, ATMEL_US_RXRDY);
e8faff73 503 }
1e6c9c28
AV		 504}
505
506/*
507 * Enable modem status interrupts
508 */
7192f92c 509static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 510{
ab5e4e41
RG		 511 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
512 uint32_t ier = 0;
513
514 /*
515 * Interrupt should not be enabled twice
516 */
517 if (atmel_port->ms_irq_enabled)
518 return;
519
520 atmel_port->ms_irq_enabled = true;
521
522 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
523 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
524 else
525 ier |= ATMEL_US_CTSIC;
526
527 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
528 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
529 else
530 ier |= ATMEL_US_DSRIC;
531
532 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
533 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
534 else
535 ier |= ATMEL_US_RIIC;
536
537 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
538 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
539 else
540 ier |= ATMEL_US_DCDIC;
541
542 UART_PUT_IER(port, ier);
1e6c9c28
AV		 543}
544
35b675b9
RG		 545/*
546 * Disable modem status interrupts
547 */
548static void atmel_disable_ms(struct uart_port *port)
549{
550 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
551 uint32_t idr = 0;
552
553 /*
554 * Interrupt should not be disabled twice
555 */
556 if (!atmel_port->ms_irq_enabled)
557 return;
558
559 atmel_port->ms_irq_enabled = false;
560
561 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
562 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
563 else
564 idr |= ATMEL_US_CTSIC;
565
566 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
567 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
568 else
569 idr |= ATMEL_US_DSRIC;
570
571 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
572 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
573 else
574 idr |= ATMEL_US_RIIC;
575
576 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
577 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
578 else
579 idr |= ATMEL_US_DCDIC;
580
581 UART_PUT_IDR(port, idr);
582}
583
1e6c9c28
AV		 584/*
585 * Control the transmission of a break signal
586 */
7192f92c 587static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 588{
589 if (break_state != 0)
7192f92c 590 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 591 else
7192f92c 592 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV		 593}
594
1ecc26bd
RB		 595/*
596 * Stores the incoming character in the ring buffer
597 */
598static void
599atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
600 unsigned int ch)
601{
c811ab8c 602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 603 struct circ_buf *ring = &atmel_port->rx_ring;
604 struct atmel_uart_char *c;
605
606 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
607 /* Buffer overflow, ignore char */
608 return;
609
610 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
611 c->status = status;
612 c->ch = ch;
613
614 /* Make sure the character is stored before we update head. */
615 smp_wmb();
616
617 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
618}
619
a6670615
CC		 620/*
621 * Deal with parity, framing and overrun errors.
622 */
623static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
624{
625 /* clear error */
626 UART_PUT_CR(port, ATMEL_US_RSTSTA);
627
628 if (status & ATMEL_US_RXBRK) {
629 /* ignore side-effect */
630 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
631 port->icount.brk++;
632 }
633 if (status & ATMEL_US_PARE)
634 port->icount.parity++;
635 if (status & ATMEL_US_FRAME)
636 port->icount.frame++;
637 if (status & ATMEL_US_OVRE)
638 port->icount.overrun++;
639}
640
1e6c9c28
AV		 641/*
642 * Characters received (called from interrupt handler)
643 */
7d12e780 644static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 645{
c811ab8c 646 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 647 unsigned int status, ch;
1e6c9c28 648
afefc415 649 status = UART_GET_CSR(port);
7192f92c 650 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV		 651 ch = UART_GET_CHAR(port);
652
1e6c9c28
AV		 653 /*
654 * note that the error handling code is
655 * out of the main execution path
656 */
9e6077bd
HS		 657 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
658 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
659 || atmel_port->break_active)) {
1ecc26bd 660
b843aa21
RB		 661 /* clear error */
662 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 663
9e6077bd
HS		 664 if (status & ATMEL_US_RXBRK
665 && !atmel_port->break_active) {
9e6077bd
HS		 666 atmel_port->break_active = 1;
667 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS		 668 } else {
669 /*
670 * This is either the end-of-break
671 * condition or we've received at
672 * least one character without RXBRK
673 * being set. In both cases, the next
674 * RXBRK will indicate start-of-break.
675 */
676 UART_PUT_IDR(port, ATMEL_US_RXBRK);
677 status &= ~ATMEL_US_RXBRK;
678 atmel_port->break_active = 0;
afefc415 679 }
1e6c9c28
AV		 680 }
681
1ecc26bd 682 atmel_buffer_rx_char(port, status, ch);
afefc415 683 status = UART_GET_CSR(port);
1e6c9c28
AV		 684 }
685
1ecc26bd 686 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV		 687}
688
689/*
1ecc26bd
RB		 690 * Transmit characters (called from tasklet with TXRDY interrupt
691 * disabled)
1e6c9c28 692 */
7192f92c 693static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 694{
ebd2c8f6 695 struct circ_buf *xmit = &port->state->xmit;
e8faff73 696 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 697
e8faff73 698 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
1e6c9c28
AV		 699 UART_PUT_CHAR(port, port->x_char);
700 port->icount.tx++;
701 port->x_char = 0;
1e6c9c28 702 }
1ecc26bd 703 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 704 return;
1e6c9c28 705
e8faff73 706 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
1e6c9c28
AV		 707 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
708 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
709 port->icount.tx++;
710 if (uart_circ_empty(xmit))
711 break;
712 }
713
714 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
715 uart_write_wakeup(port);
716
1ecc26bd 717 if (!uart_circ_empty(xmit))
e8faff73
CS		 718 /* Enable interrupts */
719 UART_PUT_IER(port, atmel_port->tx_done_mask);
1e6c9c28
AV		 720}
721
08f738be
ES		 722static void atmel_complete_tx_dma(void *arg)
723{
724 struct atmel_uart_port *atmel_port = arg;
725 struct uart_port *port = &atmel_port->uart;
726 struct circ_buf *xmit = &port->state->xmit;
727 struct dma_chan *chan = atmel_port->chan_tx;
728 unsigned long flags;
729
730 spin_lock_irqsave(&port->lock, flags);
731
732 if (chan)
733 dmaengine_terminate_all(chan);
734 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
735 xmit->tail &= UART_XMIT_SIZE - 1;
736
737 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
738
739 spin_lock_irq(&atmel_port->lock_tx);
740 async_tx_ack(atmel_port->desc_tx);
741 atmel_port->cookie_tx = -EINVAL;
742 atmel_port->desc_tx = NULL;
743 spin_unlock_irq(&atmel_port->lock_tx);
744
745 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
746 uart_write_wakeup(port);
747
1842dc2e
CP		 748 /*
749 * xmit is a circular buffer so, if we have just send data from
750 * xmit->tail to the end of xmit->buf, now we have to transmit the
751 * remaining data from the beginning of xmit->buf to xmit->head.
752 */
08f738be
ES		 753 if (!uart_circ_empty(xmit))
754 tasklet_schedule(&atmel_port->tasklet);
755
756 spin_unlock_irqrestore(&port->lock, flags);
757}
758
759static void atmel_release_tx_dma(struct uart_port *port)
760{
761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
762 struct dma_chan *chan = atmel_port->chan_tx;
763
764 if (chan) {
765 dmaengine_terminate_all(chan);
766 dma_release_channel(chan);
767 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 768 DMA_TO_DEVICE);
08f738be
ES		 769 }
770
771 atmel_port->desc_tx = NULL;
772 atmel_port->chan_tx = NULL;
773 atmel_port->cookie_tx = -EINVAL;
774}
775
776/*
777 * Called from tasklet with TXRDY interrupt is disabled.
778 */
779static void atmel_tx_dma(struct uart_port *port)
780{
781 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
782 struct circ_buf *xmit = &port->state->xmit;
783 struct dma_chan *chan = atmel_port->chan_tx;
784 struct dma_async_tx_descriptor *desc;
785 struct scatterlist *sg = &atmel_port->sg_tx;
786
787 /* Make sure we have an idle channel */
788 if (atmel_port->desc_tx != NULL)
789 return;
790
791 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
792 /*
793 * DMA is idle now.
794 * Port xmit buffer is already mapped,
795 * and it is one page... Just adjust
796 * offsets and lengths. Since it is a circular buffer,
797 * we have to transmit till the end, and then the rest.
798 * Take the port lock to get a
799 * consistent xmit buffer state.
800 */
801 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
802 sg_dma_address(sg) = (sg_dma_address(sg) &
803 ~(UART_XMIT_SIZE - 1))
804 + sg->offset;
805 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
806 xmit->tail,
807 UART_XMIT_SIZE);
808 BUG_ON(!sg_dma_len(sg));
809
810 desc = dmaengine_prep_slave_sg(chan,
1842dc2e
CP		 811 sg,
812 1,
813 DMA_MEM_TO_DEV,
814 DMA_PREP_INTERRUPT |
815 DMA_CTRL_ACK);
08f738be
ES		 816 if (!desc) {
817 dev_err(port->dev, "Failed to send via dma!\n");
818 return;
819 }
820
485819b5 821 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
08f738be
ES		 822
823 atmel_port->desc_tx = desc;
824 desc->callback = atmel_complete_tx_dma;
825 desc->callback_param = atmel_port;
826 atmel_port->cookie_tx = dmaengine_submit(desc);
827
828 } else {
13bd3e6f 829 if (port->rs485.flags & SER_RS485_ENABLED) {
08f738be
ES		 830 /* DMA done, stop TX, start RX for RS485 */
831 atmel_start_rx(port);
832 }
833 }
834
835 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
836 uart_write_wakeup(port);
837}
838
839static int atmel_prepare_tx_dma(struct uart_port *port)
840{
841 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
842 dma_cap_mask_t mask;
843 struct dma_slave_config config;
844 int ret, nent;
845
846 dma_cap_zero(mask);
847 dma_cap_set(DMA_SLAVE, mask);
848
849 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
850 if (atmel_port->chan_tx == NULL)
851 goto chan_err;
852 dev_info(port->dev, "using %s for tx DMA transfers\n",
853 dma_chan_name(atmel_port->chan_tx));
854
855 spin_lock_init(&atmel_port->lock_tx);
856 sg_init_table(&atmel_port->sg_tx, 1);
857 /* UART circular tx buffer is an aligned page. */
2c277054 858 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 859 sg_set_page(&atmel_port->sg_tx,
860 virt_to_page(port->state->xmit.buf),
861 UART_XMIT_SIZE,
862 (int)port->state->xmit.buf & ~PAGE_MASK);
863 nent = dma_map_sg(port->dev,
864 &atmel_port->sg_tx,
865 1,
48479148 866 DMA_TO_DEVICE);
08f738be
ES		 867
868 if (!nent) {
869 dev_dbg(port->dev, "need to release resource of dma\n");
870 goto chan_err;
871 } else {
872 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
873 sg_dma_len(&atmel_port->sg_tx),
874 port->state->xmit.buf,
875 sg_dma_address(&atmel_port->sg_tx));
876 }
877
878 /* Configure the slave DMA */
879 memset(&config, 0, sizeof(config));
880 config.direction = DMA_MEM_TO_DEV;
881 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
882 config.dst_addr = port->mapbase + ATMEL_US_THR;
883
5483c10e
MR		 884 ret = dmaengine_slave_config(atmel_port->chan_tx,
885 &config);
08f738be
ES		 886 if (ret) {
887 dev_err(port->dev, "DMA tx slave configuration failed\n");
888 goto chan_err;
889 }
890
891 return 0;
892
893chan_err:
894 dev_err(port->dev, "TX channel not available, switch to pio\n");
895 atmel_port->use_dma_tx = 0;
896 if (atmel_port->chan_tx)
897 atmel_release_tx_dma(port);
898 return -EINVAL;
899}
900
34df42f5
ES		 901static void atmel_complete_rx_dma(void *arg)
902{
903 struct uart_port *port = arg;
904 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
905
906 tasklet_schedule(&atmel_port->tasklet);
907}
908
909static void atmel_release_rx_dma(struct uart_port *port)
910{
911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
912 struct dma_chan *chan = atmel_port->chan_rx;
913
914 if (chan) {
915 dmaengine_terminate_all(chan);
916 dma_release_channel(chan);
917 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 918 DMA_FROM_DEVICE);
34df42f5
ES		 919 }
920
921 atmel_port->desc_rx = NULL;
922 atmel_port->chan_rx = NULL;
923 atmel_port->cookie_rx = -EINVAL;
924}
925
926static void atmel_rx_from_dma(struct uart_port *port)
927{
928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 929 struct tty_port *tport = &port->state->port;
34df42f5
ES		 930 struct circ_buf *ring = &atmel_port->rx_ring;
931 struct dma_chan *chan = atmel_port->chan_rx;
932 struct dma_tx_state state;
933 enum dma_status dmastat;
66f37aaf 934 size_t count;
34df42f5
ES		 935
936
937 /* Reset the UART timeout early so that we don't miss one */
938 UART_PUT_CR(port, ATMEL_US_STTTO);
939 dmastat = dmaengine_tx_status(chan,
940 atmel_port->cookie_rx,
941 &state);
942 /* Restart a new tasklet if DMA status is error */
943 if (dmastat == DMA_ERROR) {
944 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
945 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
946 tasklet_schedule(&atmel_port->tasklet);
947 return;
948 }
34df42f5 949
66f37aaf
CP		 950 /* CPU claims ownership of RX DMA buffer */
951 dma_sync_sg_for_cpu(port->dev,
952 &atmel_port->sg_rx,
953 1,
485819b5 954 DMA_FROM_DEVICE);
66f37aaf
CP		 955
956 /*
957 * ring->head points to the end of data already written by the DMA.
958 * ring->tail points to the beginning of data to be read by the
959 * framework.
960 * The current transfer size should not be larger than the dma buffer
961 * length.
962 */
963 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
964 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 965 /*
66f37aaf
CP		 966 * At this point ring->head may point to the first byte right after the
967 * last byte of the dma buffer:
968 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
969 *
970 * However ring->tail must always points inside the dma buffer:
971 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
972 *
973 * Since we use a ring buffer, we have to handle the case
974 * where head is lower than tail. In such a case, we first read from
975 * tail to the end of the buffer then reset tail.
34df42f5 976 */
66f37aaf
CP		 977 if (ring->head < ring->tail) {
978 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 979
66f37aaf
CP		 980 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
981 ring->tail = 0;
982 port->icount.rx += count;
983 }
34df42f5 984
66f37aaf
CP		 985 /* Finally we read data from tail to head */
986 if (ring->tail < ring->head) {
987 count = ring->head - ring->tail;
34df42f5 988
66f37aaf
CP		 989 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
990 /* Wrap ring->head if needed */
991 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
992 ring->head = 0;
993 ring->tail = ring->head;
34df42f5
ES		 994 port->icount.rx += count;
995 }
996
66f37aaf
CP		 997 /* USART retreives ownership of RX DMA buffer */
998 dma_sync_sg_for_device(port->dev,
999 &atmel_port->sg_rx,
1000 1,
485819b5 1001 DMA_FROM_DEVICE);
66f37aaf
CP		 1002
1003 /*
1004 * Drop the lock here since it might end up calling
1005 * uart_start(), which takes the lock.
1006 */
1007 spin_unlock(&port->lock);
1008 tty_flip_buffer_push(tport);
1009 spin_lock(&port->lock);
1010
34df42f5
ES		 1011 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1012}
1013
1014static int atmel_prepare_rx_dma(struct uart_port *port)
1015{
1016 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1017 struct dma_async_tx_descriptor *desc;
1018 dma_cap_mask_t mask;
1019 struct dma_slave_config config;
1020 struct circ_buf *ring;
1021 int ret, nent;
1022
1023 ring = &atmel_port->rx_ring;
1024
1025 dma_cap_zero(mask);
1026 dma_cap_set(DMA_CYCLIC, mask);
1027
1028 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1029 if (atmel_port->chan_rx == NULL)
1030 goto chan_err;
1031 dev_info(port->dev, "using %s for rx DMA transfers\n",
1032 dma_chan_name(atmel_port->chan_rx));
1033
1034 spin_lock_init(&atmel_port->lock_rx);
1035 sg_init_table(&atmel_port->sg_rx, 1);
1036 /* UART circular rx buffer is an aligned page. */
2c277054 1037 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1038 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1039 virt_to_page(ring->buf),
a510880f 1040 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1842dc2e
CP		 1041 (int)ring->buf & ~PAGE_MASK);
1042 nent = dma_map_sg(port->dev,
1043 &atmel_port->sg_rx,
1044 1,
1045 DMA_FROM_DEVICE);
34df42f5
ES		 1046
1047 if (!nent) {
1048 dev_dbg(port->dev, "need to release resource of dma\n");
1049 goto chan_err;
1050 } else {
1051 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1052 sg_dma_len(&atmel_port->sg_rx),
1053 ring->buf,
1054 sg_dma_address(&atmel_port->sg_rx));
1055 }
1056
1057 /* Configure the slave DMA */
1058 memset(&config, 0, sizeof(config));
1059 config.direction = DMA_DEV_TO_MEM;
1060 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1061 config.src_addr = port->mapbase + ATMEL_US_RHR;
1062
5483c10e
MR		 1063 ret = dmaengine_slave_config(atmel_port->chan_rx,
1064 &config);
34df42f5
ES		 1065 if (ret) {
1066 dev_err(port->dev, "DMA rx slave configuration failed\n");
1067 goto chan_err;
1068 }
1069 /*
1070 * Prepare a cyclic dma transfer, assign 2 descriptors,
1071 * each one is half ring buffer size
1072 */
1073 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1074 sg_dma_address(&atmel_port->sg_rx),
1075 sg_dma_len(&atmel_port->sg_rx),
1076 sg_dma_len(&atmel_port->sg_rx)/2,
1077 DMA_DEV_TO_MEM,
1078 DMA_PREP_INTERRUPT);
34df42f5
ES		 1079 desc->callback = atmel_complete_rx_dma;
1080 desc->callback_param = port;
1081 atmel_port->desc_rx = desc;
1082 atmel_port->cookie_rx = dmaengine_submit(desc);
1083
1084 return 0;
1085
1086chan_err:
1087 dev_err(port->dev, "RX channel not available, switch to pio\n");
1088 atmel_port->use_dma_rx = 0;
1089 if (atmel_port->chan_rx)
1090 atmel_release_rx_dma(port);
1091 return -EINVAL;
1092}
1093
2e68c22f
ES		 1094static void atmel_uart_timer_callback(unsigned long data)
1095{
1096 struct uart_port *port = (void *)data;
1097 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1098
1099 tasklet_schedule(&atmel_port->tasklet);
1100 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1101}
1102
b843aa21
RB		 1103/*
1104 * receive interrupt handler.
1105 */
1106static void
1107atmel_handle_receive(struct uart_port *port, unsigned int pending)
1108{
c811ab8c 1109 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1110
64e22ebe 1111 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1112 /*
1113 * PDC receive. Just schedule the tasklet and let it
1114 * figure out the details.
1115 *
1116 * TODO: We're not handling error flags correctly at
1117 * the moment.
1118 */
1119 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1120 UART_PUT_IDR(port, (ATMEL_US_ENDRX
1121 | ATMEL_US_TIMEOUT));
1122 tasklet_schedule(&atmel_port->tasklet);
1123 }
1124
1125 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1126 ATMEL_US_FRAME | ATMEL_US_PARE))
1127 atmel_pdc_rxerr(port, pending);
1128 }
1129
34df42f5
ES		 1130 if (atmel_use_dma_rx(port)) {
1131 if (pending & ATMEL_US_TIMEOUT) {
1132 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
1133 tasklet_schedule(&atmel_port->tasklet);
1134 }
1135 }
1136
b843aa21
RB		 1137 /* Interrupt receive */
1138 if (pending & ATMEL_US_RXRDY)
1139 atmel_rx_chars(port);
1140 else if (pending & ATMEL_US_RXBRK) {
1141 /*
1142 * End of break detected. If it came along with a
1143 * character, atmel_rx_chars will handle it.
1144 */
1145 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1146 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1147 atmel_port->break_active = 0;
1148 }
1149}
1150
1151/*
1ecc26bd 1152 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1153 */
1154static void
1155atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1156{
c811ab8c 1157 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1158
e8faff73
CS		 1159 if (pending & atmel_port->tx_done_mask) {
1160 /* Either PDC or interrupt transmission */
1161 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1162 tasklet_schedule(&atmel_port->tasklet);
1ecc26bd 1163 }
b843aa21
RB		 1164}
1165
1166/*
1167 * status flags interrupt handler.
1168 */
1169static void
1170atmel_handle_status(struct uart_port *port, unsigned int pending,
1171 unsigned int status)
1172{
c811ab8c 1173 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1174
b843aa21 1175 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB		 1176 | ATMEL_US_CTSIC)) {
1177 atmel_port->irq_status = status;
1178 tasklet_schedule(&atmel_port->tasklet);
1179 }
b843aa21
RB		 1180}
1181
1e6c9c28
AV		 1182/*
1183 * Interrupt handler
1184 */
7d12e780 1185static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1186{
1187 struct uart_port *port = dev_id;
ab5e4e41 1188 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1189 unsigned int status, pending, mask, pass_counter = 0;
ab5e4e41 1190 bool gpio_handled = false;
1e6c9c28 1191
2c7af5ba
BB		 1192 spin_lock(&atmel_port->lock_suspended);
1193
a6670615 1194 do {
e0b0baad 1195 status = atmel_get_lines_status(port);
2c7af5ba
BB		 1196 mask = UART_GET_IMR(port);
1197 pending = status & mask;
ab5e4e41
RG		 1198 if (!gpio_handled) {
1199 /*
1200 * Dealing with GPIO interrupt
1201 */
1202 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1203 pending |= ATMEL_US_CTSIC;
1204
1205 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1206 pending |= ATMEL_US_DSRIC;
1207
1208 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1209 pending |= ATMEL_US_RIIC;
1210
1211 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1212 pending |= ATMEL_US_DCDIC;
1213
1214 gpio_handled = true;
1215 }
a6670615
CC		 1216 if (!pending)
1217 break;
1218
2c7af5ba
BB		 1219 if (atmel_port->suspended) {
1220 atmel_port->pending |= pending;
1221 atmel_port->pending_status = status;
1222 UART_PUT_IDR(port, mask);
1223 pm_system_wakeup();
1224 break;
1225 }
1226
b843aa21
RB		 1227 atmel_handle_receive(port, pending);
1228 atmel_handle_status(port, pending, status);
1229 atmel_handle_transmit(port, pending);
a6670615 1230 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1231
2c7af5ba
BB		 1232 spin_unlock(&atmel_port->lock_suspended);
1233
0400b697 1234 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1235}
1e6c9c28 1236
a930e528
ES		 1237static void atmel_release_tx_pdc(struct uart_port *port)
1238{
1239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1240 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1241
1242 dma_unmap_single(port->dev,
1243 pdc->dma_addr,
1244 pdc->dma_size,
1245 DMA_TO_DEVICE);
1246}
1247
a6670615
CC		 1248/*
1249 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1250 */
64e22ebe 1251static void atmel_tx_pdc(struct uart_port *port)
a6670615 1252{
c811ab8c 1253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1254 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1255 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1256 int count;
1257
ba0657ff
MT		 1258 /* nothing left to transmit? */
1259 if (UART_GET_TCR(port))
1260 return;
1261
a6670615
CC		 1262 xmit->tail += pdc->ofs;
1263 xmit->tail &= UART_XMIT_SIZE - 1;
1264
1265 port->icount.tx += pdc->ofs;
1266 pdc->ofs = 0;
1267
ba0657ff 1268 /* more to transmit - setup next transfer */
a6670615 1269
ba0657ff
MT		 1270 /* disable PDC transmit */
1271 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1272
1f14081d 1273 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1274 dma_sync_single_for_device(port->dev,
1275 pdc->dma_addr,
1276 pdc->dma_size,
1277 DMA_TO_DEVICE);
1278
1279 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1280 pdc->ofs = count;
1281
1282 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1283 UART_PUT_TCR(port, count);
e8faff73 1284 /* re-enable PDC transmit */
a6670615 1285 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
e8faff73
CS		 1286 /* Enable interrupts */
1287 UART_PUT_IER(port, atmel_port->tx_done_mask);
1288 } else {
13bd3e6f
RRD		 1289 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1290 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
e8faff73
CS		 1291 /* DMA done, stop TX, start RX for RS485 */
1292 atmel_start_rx(port);
1293 }
1e6c9c28 1294 }
a6670615
CC		 1295
1296 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1297 uart_write_wakeup(port);
1e6c9c28
AV		 1298}
1299
a930e528
ES		 1300static int atmel_prepare_tx_pdc(struct uart_port *port)
1301{
1302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1303 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1304 struct circ_buf *xmit = &port->state->xmit;
1305
1306 pdc->buf = xmit->buf;
1307 pdc->dma_addr = dma_map_single(port->dev,
1308 pdc->buf,
1309 UART_XMIT_SIZE,
1310 DMA_TO_DEVICE);
1311 pdc->dma_size = UART_XMIT_SIZE;
1312 pdc->ofs = 0;
1313
1314 return 0;
1315}
1316
1ecc26bd
RB		 1317static void atmel_rx_from_ring(struct uart_port *port)
1318{
c811ab8c 1319 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1320 struct circ_buf *ring = &atmel_port->rx_ring;
1321 unsigned int flg;
1322 unsigned int status;
1323
1324 while (ring->head != ring->tail) {
1325 struct atmel_uart_char c;
1326
1327 /* Make sure c is loaded after head. */
1328 smp_rmb();
1329
1330 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1331
1332 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1333
1334 port->icount.rx++;
1335 status = c.status;
1336 flg = TTY_NORMAL;
1337
1338 /*
1339 * note that the error handling code is
1340 * out of the main execution path
1341 */
1342 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1343 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1344 if (status & ATMEL_US_RXBRK) {
1345 /* ignore side-effect */
1346 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1347
1348 port->icount.brk++;
1349 if (uart_handle_break(port))
1350 continue;
1351 }
1352 if (status & ATMEL_US_PARE)
1353 port->icount.parity++;
1354 if (status & ATMEL_US_FRAME)
1355 port->icount.frame++;
1356 if (status & ATMEL_US_OVRE)
1357 port->icount.overrun++;
1358
1359 status &= port->read_status_mask;
1360
1361 if (status & ATMEL_US_RXBRK)
1362 flg = TTY_BREAK;
1363 else if (status & ATMEL_US_PARE)
1364 flg = TTY_PARITY;
1365 else if (status & ATMEL_US_FRAME)
1366 flg = TTY_FRAME;
1367 }
1368
1369
1370 if (uart_handle_sysrq_char(port, c.ch))
1371 continue;
1372
1373 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1374 }
1375
1376 /*
1377 * Drop the lock here since it might end up calling
1378 * uart_start(), which takes the lock.
1379 */
1380 spin_unlock(&port->lock);
2e124b4a 1381 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1382 spin_lock(&port->lock);
1383}
1384
a930e528
ES		 1385static void atmel_release_rx_pdc(struct uart_port *port)
1386{
1387 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1388 int i;
1389
1390 for (i = 0; i < 2; i++) {
1391 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1392
1393 dma_unmap_single(port->dev,
1394 pdc->dma_addr,
1395 pdc->dma_size,
1396 DMA_FROM_DEVICE);
1397 kfree(pdc->buf);
1398 }
1399}
1400
64e22ebe 1401static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1402{
c811ab8c 1403 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1404 struct tty_port *tport = &port->state->port;
a6670615
CC		 1405 struct atmel_dma_buffer *pdc;
1406 int rx_idx = atmel_port->pdc_rx_idx;
1407 unsigned int head;
1408 unsigned int tail;
1409 unsigned int count;
1410
1411 do {
1412 /* Reset the UART timeout early so that we don't miss one */
1413 UART_PUT_CR(port, ATMEL_US_STTTO);
1414
1415 pdc = &atmel_port->pdc_rx[rx_idx];
1416 head = UART_GET_RPR(port) - pdc->dma_addr;
1417 tail = pdc->ofs;
1418
1419 /* If the PDC has switched buffers, RPR won't contain
1420 * any address within the current buffer. Since head
1421 * is unsigned, we just need a one-way comparison to
1422 * find out.
1423 *
1424 * In this case, we just need to consume the entire
1425 * buffer and resubmit it for DMA. This will clear the
1426 * ENDRX bit as well, so that we can safely re-enable
1427 * all interrupts below.
1428 */
1429 head = min(head, pdc->dma_size);
1430
1431 if (likely(head != tail)) {
1432 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1433 pdc->dma_size, DMA_FROM_DEVICE);
1434
1435 /*
1436 * head will only wrap around when we recycle
1437 * the DMA buffer, and when that happens, we
1438 * explicitly set tail to 0. So head will
1439 * always be greater than tail.
1440 */
1441 count = head - tail;
1442
05c7cd39
JS		 1443 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1444 count);
a6670615
CC		 1445
1446 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1447 pdc->dma_size, DMA_FROM_DEVICE);
1448
1449 port->icount.rx += count;
1450 pdc->ofs = head;
1451 }
1452
1453 /*
1454 * If the current buffer is full, we need to check if
1455 * the next one contains any additional data.
1456 */
1457 if (head >= pdc->dma_size) {
1458 pdc->ofs = 0;
1459 UART_PUT_RNPR(port, pdc->dma_addr);
1460 UART_PUT_RNCR(port, pdc->dma_size);
1461
1462 rx_idx = !rx_idx;
1463 atmel_port->pdc_rx_idx = rx_idx;
1464 }
1465 } while (head >= pdc->dma_size);
1466
1467 /*
1468 * Drop the lock here since it might end up calling
1469 * uart_start(), which takes the lock.
1470 */
1471 spin_unlock(&port->lock);
2e124b4a 1472 tty_flip_buffer_push(tport);
a6670615
CC		 1473 spin_lock(&port->lock);
1474
1475 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1476}
1477
a930e528
ES		 1478static int atmel_prepare_rx_pdc(struct uart_port *port)
1479{
1480 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1481 int i;
1482
1483 for (i = 0; i < 2; i++) {
1484 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1485
1486 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1487 if (pdc->buf == NULL) {
1488 if (i != 0) {
1489 dma_unmap_single(port->dev,
1490 atmel_port->pdc_rx[0].dma_addr,
1491 PDC_BUFFER_SIZE,
1492 DMA_FROM_DEVICE);
1493 kfree(atmel_port->pdc_rx[0].buf);
1494 }
1495 atmel_port->use_pdc_rx = 0;
1496 return -ENOMEM;
1497 }
1498 pdc->dma_addr = dma_map_single(port->dev,
1499 pdc->buf,
1500 PDC_BUFFER_SIZE,
1501 DMA_FROM_DEVICE);
1502 pdc->dma_size = PDC_BUFFER_SIZE;
1503 pdc->ofs = 0;
1504 }
1505
1506 atmel_port->pdc_rx_idx = 0;
1507
1508 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1509 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1510
1511 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1512 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1513
1514 return 0;
1515}
1516
1ecc26bd
RB		 1517/*
1518 * tasklet handling tty stuff outside the interrupt handler.
1519 */
1520static void atmel_tasklet_func(unsigned long data)
1521{
1522 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1524 unsigned int status;
1525 unsigned int status_change;
1526
1527 /* The interrupt handler does not take the lock */
1528 spin_lock(&port->lock);
1529
a930e528 1530 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1531
1532 status = atmel_port->irq_status;
1533 status_change = status ^ atmel_port->irq_status_prev;
1534
1535 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1536 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1537 /* TODO: All reads to CSR will clear these interrupts! */
1538 if (status_change & ATMEL_US_RI)
1539 port->icount.rng++;
1540 if (status_change & ATMEL_US_DSR)
1541 port->icount.dsr++;
1542 if (status_change & ATMEL_US_DCD)
1543 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1544 if (status_change & ATMEL_US_CTS)
1545 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1546
bdc04e31 1547 wake_up_interruptible(&port->state->port.delta_msr_wait);
1ecc26bd
RB		 1548
1549 atmel_port->irq_status_prev = status;
1550 }
1551
a930e528 1552 atmel_port->schedule_rx(port);
1ecc26bd
RB		 1553
1554 spin_unlock(&port->lock);
1555}
1556
4a1e8888 1557static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1558 struct platform_device *pdev)
1559{
1560 struct device_node *np = pdev->dev.of_node;
574de559 1561 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1562
1563 if (np) {
1564 /* DMA/PDC usage specification */
1565 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1566 if (of_get_property(np, "dmas", NULL)) {
1567 atmel_port->use_dma_rx = true;
1568 atmel_port->use_pdc_rx = false;
1569 } else {
1570 atmel_port->use_dma_rx = false;
1571 atmel_port->use_pdc_rx = true;
1572 }
1573 } else {
1574 atmel_port->use_dma_rx = false;
1575 atmel_port->use_pdc_rx = false;
1576 }
1577
1578 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1579 if (of_get_property(np, "dmas", NULL)) {
1580 atmel_port->use_dma_tx = true;
1581 atmel_port->use_pdc_tx = false;
1582 } else {
1583 atmel_port->use_dma_tx = false;
1584 atmel_port->use_pdc_tx = true;
1585 }
1586 } else {
1587 atmel_port->use_dma_tx = false;
1588 atmel_port->use_pdc_tx = false;
1589 }
1590
1591 } else {
1592 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1593 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1594 atmel_port->use_dma_rx = false;
1595 atmel_port->use_dma_tx = false;
1596 }
1597
33d64c4f
ES		 1598}
1599
13bd3e6f 1600static void atmel_init_rs485(struct uart_port *port,
33d64c4f
ES		 1601 struct platform_device *pdev)
1602{
1603 struct device_node *np = pdev->dev.of_node;
574de559 1604 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1605
1606 if (np) {
1607 u32 rs485_delay[2];
1608 /* rs485 properties */
1609 if (of_property_read_u32_array(np, "rs485-rts-delay",
1610 rs485_delay, 2) == 0) {
13bd3e6f 1611 struct serial_rs485 *rs485conf = &port->rs485;
33d64c4f
ES		 1612
1613 rs485conf->delay_rts_before_send = rs485_delay[0];
1614 rs485conf->delay_rts_after_send = rs485_delay[1];
1615 rs485conf->flags = 0;
1616
1617 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1618 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1619
1620 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1621 NULL))
1622 rs485conf->flags |= SER_RS485_ENABLED;
1623 }
1624 } else {
13bd3e6f 1625 port->rs485 = pdata->rs485;
33d64c4f
ES		 1626 }
1627
1628}
1629
a930e528
ES		 1630static void atmel_set_ops(struct uart_port *port)
1631{
1632 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1633
34df42f5
ES		 1634 if (atmel_use_dma_rx(port)) {
1635 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1636 atmel_port->schedule_rx = &atmel_rx_from_dma;
1637 atmel_port->release_rx = &atmel_release_rx_dma;
1638 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1639 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1640 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1641 atmel_port->release_rx = &atmel_release_rx_pdc;
1642 } else {
1643 atmel_port->prepare_rx = NULL;
1644 atmel_port->schedule_rx = &atmel_rx_from_ring;
1645 atmel_port->release_rx = NULL;
1646 }
1647
08f738be
ES		 1648 if (atmel_use_dma_tx(port)) {
1649 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1650 atmel_port->schedule_tx = &atmel_tx_dma;
1651 atmel_port->release_tx = &atmel_release_tx_dma;
1652 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1653 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1654 atmel_port->schedule_tx = &atmel_tx_pdc;
1655 atmel_port->release_tx = &atmel_release_tx_pdc;
1656 } else {
1657 atmel_port->prepare_tx = NULL;
1658 atmel_port->schedule_tx = &atmel_tx_chars;
1659 atmel_port->release_tx = NULL;
1660 }
1661}
1662
055560b0
ES		 1663/*
1664 * Get ip name usart or uart
1665 */
892db58b 1666static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1667{
1668 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1669 int name = UART_GET_IP_NAME(port);
731d9cae 1670 u32 version;
055560b0
ES		 1671 int usart, uart;
1672 /* usart and uart ascii */
1673 usart = 0x55534152;
1674 uart = 0x44424755;
1675
1676 atmel_port->is_usart = false;
1677
1678 if (name == usart) {
1679 dev_dbg(port->dev, "This is usart\n");
1680 atmel_port->is_usart = true;
1681 } else if (name == uart) {
1682 dev_dbg(port->dev, "This is uart\n");
1683 atmel_port->is_usart = false;
1684 } else {
731d9cae
NF		 1685 /* fallback for older SoCs: use version field */
1686 version = UART_GET_IP_VERSION(port);
1687 switch (version) {
1688 case 0x302:
1689 case 0x10213:
1690 dev_dbg(port->dev, "This version is usart\n");
1691 atmel_port->is_usart = true;
1692 break;
1693 case 0x203:
1694 case 0x10202:
1695 dev_dbg(port->dev, "This version is uart\n");
1696 atmel_port->is_usart = false;
1697 break;
1698 default:
1699 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1700 }
055560b0 1701 }
055560b0
ES		 1702}
1703
ab5e4e41
RG		 1704static void atmel_free_gpio_irq(struct uart_port *port)
1705{
1706 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1707 enum mctrl_gpio_idx i;
1708
1709 for (i = 0; i < UART_GPIO_MAX; i++)
1710 if (atmel_port->gpio_irq[i] >= 0)
1711 free_irq(atmel_port->gpio_irq[i], port);
1712}
1713
1714static int atmel_request_gpio_irq(struct uart_port *port)
1715{
1716 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1717 int *irq = atmel_port->gpio_irq;
1718 enum mctrl_gpio_idx i;
1719 int err = 0;
1720
1721 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1722 if (irq[i] < 0)
1723 continue;
1724
1725 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1726 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1727 "atmel_serial", port);
1728 if (err)
1729 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1730 irq[i]);
1731 }
1732
1733 /*
1734 * If something went wrong, rollback.
1735 */
1736 while (err && (--i >= 0))
1737 if (irq[i] >= 0)
1738 free_irq(irq[i], port);
1739
1740 return err;
1741}
1742
1e6c9c28
AV		 1743/*
1744 * Perform initialization and enable port for reception
1745 */
7192f92c 1746static int atmel_startup(struct uart_port *port)
1e6c9c28 1747{
33d64c4f 1748 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1749 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1750 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV		 1751 int retval;
1752
1753 /*
1754 * Ensure that no interrupts are enabled otherwise when
1755 * request_irq() is called we could get stuck trying to
1756 * handle an unexpected interrupt
1757 */
1758 UART_PUT_IDR(port, -1);
ab5e4e41 1759 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1760
1761 /*
1762 * Allocate the IRQ
1763 */
2c7af5ba
BB		 1764 retval = request_irq(port->irq, atmel_interrupt,
1765 IRQF_SHARED | IRQF_COND_SUSPEND,
ae161068 1766 tty ? tty->name : "atmel_serial", port);
1e6c9c28 1767 if (retval) {
ddaa6037 1768 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1769 return retval;
1770 }
1771
ab5e4e41
RG		 1772 /*
1773 * Get the GPIO lines IRQ
1774 */
1775 retval = atmel_request_gpio_irq(port);
1776 if (retval)
1777 goto free_irq;
1778
1e125786
LZ		 1779 tasklet_enable(&atmel_port->tasklet);
1780
a6670615
CC		 1781 /*
1782 * Initialize DMA (if necessary)
1783 */
33d64c4f 1784 atmel_init_property(atmel_port, pdev);
4d9628a1 1785 atmel_set_ops(port);
33d64c4f 1786
a930e528
ES		 1787 if (atmel_port->prepare_rx) {
1788 retval = atmel_port->prepare_rx(port);
1789 if (retval < 0)
1790 atmel_set_ops(port);
a6670615 1791 }
a6670615 1792
a930e528
ES		 1793 if (atmel_port->prepare_tx) {
1794 retval = atmel_port->prepare_tx(port);
1795 if (retval < 0)
1796 atmel_set_ops(port);
a6670615 1797 }
1e6c9c28 1798
27c0c8e5 1799 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 1800 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5
AN		 1801 atmel_port->irq_status = atmel_port->irq_status_prev;
1802
1e6c9c28
AV		 1803 /*
1804 * Finally, enable the serial port
1805 */
7192f92c 1806 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB		 1807 /* enable xmit & rcvr */
1808 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 1809
8bc661bf
MR		 1810 setup_timer(&atmel_port->uart_timer,
1811 atmel_uart_timer_callback,
1812 (unsigned long)port);
1813
64e22ebe 1814 if (atmel_use_pdc_rx(port)) {
a6670615 1815 /* set UART timeout */
2e68c22f 1816 if (!atmel_port->is_usart) {
2e68c22f
ES		 1817 mod_timer(&atmel_port->uart_timer,
1818 jiffies + uart_poll_timeout(port));
1819 /* set USART timeout */
1820 } else {
1821 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1822 UART_PUT_CR(port, ATMEL_US_STTTO);
a6670615 1823
2e68c22f
ES		 1824 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1825 }
a6670615
CC		 1826 /* enable PDC controller */
1827 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
34df42f5 1828 } else if (atmel_use_dma_rx(port)) {
2e68c22f
ES		 1829 /* set UART timeout */
1830 if (!atmel_port->is_usart) {
2e68c22f
ES		 1831 mod_timer(&atmel_port->uart_timer,
1832 jiffies + uart_poll_timeout(port));
1833 /* set USART timeout */
1834 } else {
1835 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1836 UART_PUT_CR(port, ATMEL_US_STTTO);
34df42f5 1837
2e68c22f
ES		 1838 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1839 }
a6670615
CC		 1840 } else {
1841 /* enable receive only */
1842 UART_PUT_IER(port, ATMEL_US_RXRDY);
1843 }
afefc415 1844
1e6c9c28 1845 return 0;
ab5e4e41
RG		 1846
1847free_irq:
1848 free_irq(port->irq, port);
1849
1850 return retval;
1e6c9c28
AV		 1851}
1852
479e9b94
PH		 1853/*
1854 * Flush any TX data submitted for DMA. Called when the TX circular
1855 * buffer is reset.
1856 */
1857static void atmel_flush_buffer(struct uart_port *port)
1858{
1859 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1860
1861 if (atmel_use_pdc_tx(port)) {
1862 UART_PUT_TCR(port, 0);
1863 atmel_port->pdc_tx.ofs = 0;
1864 }
1865}
1866
1e6c9c28
AV		 1867/*
1868 * Disable the port
1869 */
7192f92c 1870static void atmel_shutdown(struct uart_port *port)
1e6c9c28 1871{
c811ab8c 1872 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 1873
8bc661bf
MR		 1874 /*
1875 * Prevent any tasklets being scheduled during
1876 * cleanup
1877 */
1878 del_timer_sync(&atmel_port->uart_timer);
1879
0cc7c6c7
MR		 1880 /*
1881 * Clear out any scheduled tasklets before
1882 * we destroy the buffers
1883 */
1e125786 1884 tasklet_disable(&atmel_port->tasklet);
0cc7c6c7
MR		 1885 tasklet_kill(&atmel_port->tasklet);
1886
a6670615 1887 /*
0cc7c6c7
MR		 1888 * Ensure everything is stopped and
1889 * disable all interrupts, port and break condition.
a6670615
CC		 1890 */
1891 atmel_stop_rx(port);
1892 atmel_stop_tx(port);
1893
0cc7c6c7
MR		 1894 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1895 UART_PUT_IDR(port, -1);
1896
1897
a6670615
CC		 1898 /*
1899 * Shut-down the DMA.
1900 */
a930e528
ES		 1901 if (atmel_port->release_rx)
1902 atmel_port->release_rx(port);
1903 if (atmel_port->release_tx)
1904 atmel_port->release_tx(port);
a6670615 1905
bb7e73c5
MD		 1906 /*
1907 * Reset ring buffer pointers
1908 */
1909 atmel_port->rx_ring.head = 0;
1910 atmel_port->rx_ring.tail = 0;
1911
1e6c9c28 1912 /*
ab5e4e41 1913 * Free the interrupts
1e6c9c28
AV		 1914 */
1915 free_irq(port->irq, port);
ab5e4e41
RG		 1916 atmel_free_gpio_irq(port);
1917
1918 atmel_port->ms_irq_enabled = false;
1e6c9c28 1919
479e9b94 1920 atmel_flush_buffer(port);
9afd561a
HS		 1921}
1922
1e6c9c28
AV		 1923/*
1924 * Power / Clock management.
1925 */
b843aa21
RB		 1926static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1927 unsigned int oldstate)
1e6c9c28 1928{
c811ab8c 1929 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1930
1e6c9c28 1931 switch (state) {
b843aa21
RB		 1932 case 0:
1933 /*
1934 * Enable the peripheral clock for this serial port.
1935 * This is called on uart_open() or a resume event.
1936 */
91f8c2d8 1937 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 1938
1939 /* re-enable interrupts if we disabled some on suspend */
1940 UART_PUT_IER(port, atmel_port->backup_imr);
b843aa21
RB		 1941 break;
1942 case 3:
f05596db
AS		 1943 /* Back up the interrupt mask and disable all interrupts */
1944 atmel_port->backup_imr = UART_GET_IMR(port);
1945 UART_PUT_IDR(port, -1);
1946
b843aa21
RB		 1947 /*
1948 * Disable the peripheral clock for this serial port.
1949 * This is called on uart_close() or a suspend event.
1950 */
91f8c2d8 1951 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 1952 break;
1953 default:
ddaa6037 1954 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 1955 }
1956}
1957
1958/*
1959 * Change the port parameters
1960 */
b843aa21
RB		 1961static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1962 struct ktermios *old)
1e6c9c28
AV		 1963{
1964 unsigned long flags;
1cf6e8fc
CP		 1965 unsigned int old_mode, mode, imr, quot, baud;
1966
1967 /* save the current mode register */
1968 mode = old_mode = UART_GET_MR(port);
1e6c9c28 1969
1cf6e8fc
CP		 1970 /* reset the mode, clock divisor, parity, stop bits and data size */
1971 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
1972 ATMEL_US_PAR | ATMEL_US_USMODE);
03abeac0 1973
b843aa21 1974 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 1975 quot = uart_get_divisor(port, baud);
1976
b843aa21 1977 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV		 1978 quot /= 8;
1979 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1980 }
1e6c9c28
AV		 1981
1982 /* byte size */
1983 switch (termios->c_cflag & CSIZE) {
1984 case CS5:
7192f92c 1985 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 1986 break;
1987 case CS6:
7192f92c 1988 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 1989 break;
1990 case CS7:
7192f92c 1991 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 1992 break;
1993 default:
7192f92c 1994 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 1995 break;
1996 }
1997
1998 /* stop bits */
1999 if (termios->c_cflag & CSTOPB)
7192f92c 2000 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2001
2002 /* parity */
2003 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2004 /* Mark or Space parity */
2005 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2006 if (termios->c_cflag & PARODD)
7192f92c 2007 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2008 else
7192f92c 2009 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2010 } else if (termios->c_cflag & PARODD)
7192f92c 2011 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2012 else
7192f92c 2013 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2014 } else
7192f92c 2015 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2016
2017 spin_lock_irqsave(&port->lock, flags);
2018
7192f92c 2019 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2020 if (termios->c_iflag & INPCK)
7192f92c 2021 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2022 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2023 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2024
64e22ebe 2025 if (atmel_use_pdc_rx(port))
a6670615
CC		 2026 /* need to enable error interrupts */
2027 UART_PUT_IER(port, port->read_status_mask);
2028
1e6c9c28
AV		 2029 /*
2030 * Characters to ignore
2031 */
2032 port->ignore_status_mask = 0;
2033 if (termios->c_iflag & IGNPAR)
7192f92c 2034 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2035 if (termios->c_iflag & IGNBRK) {
7192f92c 2036 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2037 /*
2038 * If we're ignoring parity and break indicators,
2039 * ignore overruns too (for real raw support).
2040 */
2041 if (termios->c_iflag & IGNPAR)
7192f92c 2042 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2043 }
b843aa21 2044 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2045
2046 /* update the per-port timeout */
2047 uart_update_timeout(port, termios->c_cflag, baud);
2048
0ccad870
HS		 2049 /*
2050 * save/disable interrupts. The tty layer will ensure that the
2051 * transmitter is empty if requested by the caller, so there's
2052 * no need to wait for it here.
2053 */
b843aa21
RB		 2054 imr = UART_GET_IMR(port);
2055 UART_PUT_IDR(port, -1);
1e6c9c28
AV		 2056
2057 /* disable receiver and transmitter */
7192f92c 2058 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28 2059
1cf6e8fc 2060 /* mode */
13bd3e6f
RRD		 2061 if (port->rs485.flags & SER_RS485_ENABLED) {
2062 if ((port->rs485.delay_rts_after_send) > 0)
2063 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send);
e8faff73 2064 mode |= ATMEL_US_USMODE_RS485;
1cf6e8fc
CP		 2065 } else if (termios->c_cflag & CRTSCTS) {
2066 /* RS232 with hardware handshake (RTS/CTS) */
2067 mode |= ATMEL_US_USMODE_HWHS;
2068 } else {
2069 /* RS232 without hadware handshake */
2070 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2071 }
2072
1cf6e8fc 2073 /* set the mode, clock divisor, parity, stop bits and data size */
1e6c9c28
AV		 2074 UART_PUT_MR(port, mode);
2075
1cf6e8fc
CP		 2076 /*
2077 * when switching the mode, set the RTS line state according to the
2078 * new mode, otherwise keep the former state
2079 */
2080 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2081 unsigned int rts_state;
2082
2083 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2084 /* let the hardware control the RTS line */
2085 rts_state = ATMEL_US_RTSDIS;
2086 } else {
2087 /* force RTS line to low level */
2088 rts_state = ATMEL_US_RTSEN;
2089 }
2090
2091 UART_PUT_CR(port, rts_state);
2092 }
2093
1e6c9c28
AV		 2094 /* set the baud rate */
2095 UART_PUT_BRGR(port, quot);
7192f92c
HS		 2096 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2097 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2098
2099 /* restore interrupts */
2100 UART_PUT_IER(port, imr);
2101
2102 /* CTS flow-control and modem-status interrupts */
2103 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2104 atmel_enable_ms(port);
2105 else
2106 atmel_disable_ms(port);
1e6c9c28
AV		 2107
2108 spin_unlock_irqrestore(&port->lock, flags);
2109}
2110
732a84a0 2111static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2112{
732a84a0 2113 if (termios->c_line == N_PPS) {
42bd7a4f 2114 port->flags |= UPF_HARDPPS_CD;
d41510ce 2115 spin_lock_irq(&port->lock);
42bd7a4f 2116 atmel_enable_ms(port);
d41510ce 2117 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2118 } else {
2119 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2120 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2121 spin_lock_irq(&port->lock);
2122 atmel_disable_ms(port);
2123 spin_unlock_irq(&port->lock);
2124 }
42bd7a4f
VP		 2125 }
2126}
2127
1e6c9c28
AV		 2128/*
2129 * Return string describing the specified port
2130 */
7192f92c 2131static const char *atmel_type(struct uart_port *port)
1e6c9c28 2132{
9ab4f88b 2133 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2134}
2135
2136/*
2137 * Release the memory region(s) being used by 'port'.
2138 */
7192f92c 2139static void atmel_release_port(struct uart_port *port)
1e6c9c28 2140{
afefc415
AV		 2141 struct platform_device *pdev = to_platform_device(port->dev);
2142 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2143
2144 release_mem_region(port->mapbase, size);
2145
2146 if (port->flags & UPF_IOREMAP) {
2147 iounmap(port->membase);
2148 port->membase = NULL;
2149 }
1e6c9c28
AV		 2150}
2151
2152/*
2153 * Request the memory region(s) being used by 'port'.
2154 */
7192f92c 2155static int atmel_request_port(struct uart_port *port)
1e6c9c28 2156{
afefc415
AV		 2157 struct platform_device *pdev = to_platform_device(port->dev);
2158 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2159
7192f92c 2160 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2161 return -EBUSY;
2162
2163 if (port->flags & UPF_IOREMAP) {
2164 port->membase = ioremap(port->mapbase, size);
2165 if (port->membase == NULL) {
2166 release_mem_region(port->mapbase, size);
2167 return -ENOMEM;
2168 }
2169 }
1e6c9c28 2170
afefc415 2171 return 0;
1e6c9c28
AV		 2172}
2173
2174/*
2175 * Configure/autoconfigure the port.
2176 */
7192f92c 2177static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2178{
2179 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2180 port->type = PORT_ATMEL;
7192f92c 2181 atmel_request_port(port);
1e6c9c28
AV		 2182 }
2183}
2184
2185/*
2186 * Verify the new serial_struct (for TIOCSSERIAL).
2187 */
7192f92c 2188static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2189{
2190 int ret = 0;
9ab4f88b 2191 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2192 ret = -EINVAL;
2193 if (port->irq != ser->irq)
2194 ret = -EINVAL;
2195 if (ser->io_type != SERIAL_IO_MEM)
2196 ret = -EINVAL;
2197 if (port->uartclk / 16 != ser->baud_base)
2198 ret = -EINVAL;
2199 if ((void *)port->mapbase != ser->iomem_base)
2200 ret = -EINVAL;
2201 if (port->iobase != ser->port)
2202 ret = -EINVAL;
2203 if (ser->hub6 != 0)
2204 ret = -EINVAL;
2205 return ret;
2206}
2207
8fe2d541
AT		 2208#ifdef CONFIG_CONSOLE_POLL
2209static int atmel_poll_get_char(struct uart_port *port)
2210{
2211 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
2212 cpu_relax();
2213
2214 return UART_GET_CHAR(port);
2215}
2216
2217static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2218{
2219 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2220 cpu_relax();
2221
2222 UART_PUT_CHAR(port, ch);
2223}
2224#endif
2225
7192f92c
HS		 2226static struct uart_ops atmel_pops = {
2227 .tx_empty = atmel_tx_empty,
2228 .set_mctrl = atmel_set_mctrl,
2229 .get_mctrl = atmel_get_mctrl,
2230 .stop_tx = atmel_stop_tx,
2231 .start_tx = atmel_start_tx,
2232 .stop_rx = atmel_stop_rx,
2233 .enable_ms = atmel_enable_ms,
2234 .break_ctl = atmel_break_ctl,
2235 .startup = atmel_startup,
2236 .shutdown = atmel_shutdown,
9afd561a 2237 .flush_buffer = atmel_flush_buffer,
7192f92c 2238 .set_termios = atmel_set_termios,
42bd7a4f 2239 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2240 .type = atmel_type,
2241 .release_port = atmel_release_port,
2242 .request_port = atmel_request_port,
2243 .config_port = atmel_config_port,
2244 .verify_port = atmel_verify_port,
2245 .pm = atmel_serial_pm,
8fe2d541
AT		 2246#ifdef CONFIG_CONSOLE_POLL
2247 .poll_get_char = atmel_poll_get_char,
2248 .poll_put_char = atmel_poll_put_char,
2249#endif
1e6c9c28
AV		 2250};
2251
afefc415
AV		 2252/*
2253 * Configure the port from the platform device resource info.
2254 */
91f8c2d8 2255static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2256 struct platform_device *pdev)
1e6c9c28 2257{
91f8c2d8 2258 int ret;
7192f92c 2259 struct uart_port *port = &atmel_port->uart;
574de559 2260 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
afefc415 2261
4a1e8888
LZ		 2262 atmel_init_property(atmel_port, pdev);
2263 atmel_set_ops(port);
afefc415 2264
13bd3e6f 2265 atmel_init_rs485(port, pdev);
a930e528 2266
e8faff73
CS		 2267 port->iotype = UPIO_MEM;
2268 port->flags = UPF_BOOT_AUTOCONF;
2269 port->ops = &atmel_pops;
2270 port->fifosize = 1;
e8faff73 2271 port->dev = &pdev->dev;
afefc415
AV		 2272 port->mapbase = pdev->resource[0].start;
2273 port->irq = pdev->resource[1].start;
13bd3e6f 2274 port->rs485_config = atmel_config_rs485;
afefc415 2275
1ecc26bd
RB		 2276 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2277 (unsigned long)port);
1e125786 2278 tasklet_disable(&atmel_port->tasklet);
1ecc26bd
RB		 2279
2280 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2281
5fbe46b6 2282 if (pdata && pdata->regs) {
75d35213 2283 /* Already mapped by setup code */
1acfc7ec 2284 port->membase = pdata->regs;
588edbf3 2285 } else {
afefc415
AV		 2286 port->flags |= UPF_IOREMAP;
2287 port->membase = NULL;
2288 }
1e6c9c28 2289
b843aa21
RB		 2290 /* for console, the clock could already be configured */
2291 if (!atmel_port->clk) {
7192f92c 2292 atmel_port->clk = clk_get(&pdev->dev, "usart");
91f8c2d8
BB		 2293 if (IS_ERR(atmel_port->clk)) {
2294 ret = PTR_ERR(atmel_port->clk);
2295 atmel_port->clk = NULL;
2296 return ret;
2297 }
2298 ret = clk_prepare_enable(atmel_port->clk);
2299 if (ret) {
2300 clk_put(atmel_port->clk);
2301 atmel_port->clk = NULL;
2302 return ret;
2303 }
7192f92c 2304 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2305 clk_disable_unprepare(atmel_port->clk);
06a7f058 2306 /* only enable clock when USART is in use */
afefc415 2307 }
a6670615 2308
e8faff73 2309 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
13bd3e6f 2310 if (port->rs485.flags & SER_RS485_ENABLED)
e8faff73 2311 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2312 else if (atmel_use_pdc_tx(port)) {
a6670615 2313 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2314 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2315 } else {
2316 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2317 }
91f8c2d8
BB		 2318
2319 return 0;
1e6c9c28
AV		 2320}
2321
69f6a27b
JCPV		 2322struct platform_device *atmel_default_console_device; /* the serial console device */
2323
749c4e60 2324#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2325static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2326{
7192f92c 2327 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 2328 cpu_relax();
d358788f
RK		 2329 UART_PUT_CHAR(port, ch);
2330}
1e6c9c28
AV		 2331
2332/*
2333 * Interrupts are disabled on entering
2334 */
7192f92c 2335static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2336{
7192f92c 2337 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2338 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2339 unsigned int status, imr;
39d4c922 2340 unsigned int pdc_tx;
1e6c9c28
AV		 2341
2342 /*
b843aa21 2343 * First, save IMR and then disable interrupts
1e6c9c28 2344 */
b843aa21 2345 imr = UART_GET_IMR(port);
e8faff73 2346 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2347
39d4c922
MP		 2348 /* Store PDC transmit status and disable it */
2349 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2350 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2351
7192f92c 2352 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2353
2354 /*
b843aa21
RB		 2355 * Finally, wait for transmitter to become empty
2356 * and restore IMR
1e6c9c28
AV		 2357 */
2358 do {
2359 status = UART_GET_CSR(port);
7192f92c 2360 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2361
2362 /* Restore PDC transmit status */
2363 if (pdc_tx)
2364 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2365
b843aa21
RB		 2366 /* set interrupts back the way they were */
2367 UART_PUT_IER(port, imr);
1e6c9c28
AV		 2368}
2369
2370/*
b843aa21
RB		 2371 * If the port was already initialised (eg, by a boot loader),
2372 * try to determine the current setup.
1e6c9c28 2373 */
b843aa21
RB		 2374static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2375 int *parity, int *bits)
1e6c9c28
AV		 2376{
2377 unsigned int mr, quot;
2378
1c0fd82f
HS		 2379 /*
2380 * If the baud rate generator isn't running, the port wasn't
2381 * initialized by the boot loader.
2382 */
9c81c5c9 2383 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1c0fd82f
HS		 2384 if (!quot)
2385 return;
1e6c9c28 2386
7192f92c
HS		 2387 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2388 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2389 *bits = 8;
2390 else
2391 *bits = 7;
2392
7192f92c
HS		 2393 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2394 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2395 *parity = 'e';
7192f92c 2396 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2397 *parity = 'o';
2398
4d5e392c
HS		 2399 /*
2400 * The serial core only rounds down when matching this to a
2401 * supported baud rate. Make sure we don't end up slightly
2402 * lower than one of those, as it would make us fall through
2403 * to a much lower baud rate than we really want.
2404 */
4d5e392c 2405 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2406}
2407
7192f92c 2408static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2409{
91f8c2d8 2410 int ret;
7192f92c 2411 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV		 2412 int baud = 115200;
2413 int bits = 8;
2414 int parity = 'n';
2415 int flow = 'n';
2416
b843aa21
RB		 2417 if (port->membase == NULL) {
2418 /* Port not initialized yet - delay setup */
afefc415 2419 return -ENODEV;
b843aa21 2420 }
1e6c9c28 2421
91f8c2d8
BB		 2422 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2423 if (ret)
2424 return ret;
06a7f058 2425
b843aa21 2426 UART_PUT_IDR(port, -1);
7192f92c
HS		 2427 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2428 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2429
2430 if (options)
2431 uart_parse_options(options, &baud, &parity, &bits, &flow);
2432 else
7192f92c 2433 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2434
2435 return uart_set_options(port, co, baud, parity, bits, flow);
2436}
2437
7192f92c 2438static struct uart_driver atmel_uart;
1e6c9c28 2439
7192f92c
HS		 2440static struct console atmel_console = {
2441 .name = ATMEL_DEVICENAME,
2442 .write = atmel_console_write,
1e6c9c28 2443 .device = uart_console_device,
7192f92c 2444 .setup = atmel_console_setup,
1e6c9c28
AV		 2445 .flags = CON_PRINTBUFFER,
2446 .index = -1,
7192f92c 2447 .data = &atmel_uart,
1e6c9c28
AV		 2448};
2449
06a7f058 2450#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2451
afefc415
AV		 2452/*
2453 * Early console initialization (before VM subsystem initialized).
2454 */
7192f92c 2455static int __init atmel_console_init(void)
1e6c9c28 2456{
91f8c2d8 2457 int ret;
73e2798b 2458 if (atmel_default_console_device) {
0d0a3cc1 2459 struct atmel_uart_data *pdata =
574de559 2460 dev_get_platdata(&atmel_default_console_device->dev);
efb8d21b 2461 int id = pdata->num;
4cbf9f48
NF		 2462 struct atmel_uart_port *port = &atmel_ports[id];
2463
4cbf9f48
NF		 2464 port->backup_imr = 0;
2465 port->uart.line = id;
0d0a3cc1 2466
4cbf9f48 2467 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
91f8c2d8
BB		 2468 ret = atmel_init_port(port, atmel_default_console_device);
2469 if (ret)
2470 return ret;
7192f92c 2471 register_console(&atmel_console);
afefc415 2472 }
1e6c9c28 2473
1e6c9c28
AV		 2474 return 0;
2475}
b843aa21 2476
7192f92c 2477console_initcall(atmel_console_init);
1e6c9c28 2478
afefc415
AV		 2479/*
2480 * Late console initialization.
2481 */
7192f92c 2482static int __init atmel_late_console_init(void)
afefc415 2483{
b843aa21
RB		 2484 if (atmel_default_console_device
2485 && !(atmel_console.flags & CON_ENABLED))
7192f92c 2486 register_console(&atmel_console);
afefc415
AV		 2487
2488 return 0;
2489}
b843aa21 2490
7192f92c 2491core_initcall(atmel_late_console_init);
afefc415 2492
dfa7f343
HS		 2493static inline bool atmel_is_console_port(struct uart_port *port)
2494{
2495 return port->cons && port->cons->index == port->line;
2496}
2497
1e6c9c28 2498#else
7192f92c 2499#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2500
2501static inline bool atmel_is_console_port(struct uart_port *port)
2502{
2503 return false;
2504}
1e6c9c28
AV		 2505#endif
2506
7192f92c 2507static struct uart_driver atmel_uart = {
b843aa21
RB		 2508 .owner = THIS_MODULE,
2509 .driver_name = "atmel_serial",
2510 .dev_name = ATMEL_DEVICENAME,
2511 .major = SERIAL_ATMEL_MAJOR,
2512 .minor = MINOR_START,
2513 .nr = ATMEL_MAX_UART,
2514 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2515};
2516
afefc415 2517#ifdef CONFIG_PM
f826caa4
HS		 2518static bool atmel_serial_clk_will_stop(void)
2519{
2520#ifdef CONFIG_ARCH_AT91
2521 return at91_suspend_entering_slow_clock();
2522#else
2523 return false;
2524#endif
2525}
2526
b843aa21
RB		 2527static int atmel_serial_suspend(struct platform_device *pdev,
2528 pm_message_t state)
1e6c9c28 2529{
afefc415 2530 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2531 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2532
e1c609ef
HS		 2533 if (atmel_is_console_port(port) && console_suspend_enabled) {
2534 /* Drain the TX shifter */
2535 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2536 cpu_relax();
2537 }
2538
f05596db
AS		 2539 /* we can not wake up if we're running on slow clock */
2540 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2c7af5ba
BB		 2541 if (atmel_serial_clk_will_stop()) {
2542 unsigned long flags;
2543
2544 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2545 atmel_port->suspended = true;
2546 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
f05596db 2547 device_set_wakeup_enable(&pdev->dev, 0);
2c7af5ba 2548 }
f05596db
AS		 2549
2550 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2551
afefc415
AV		 2552 return 0;
2553}
1e6c9c28 2554
7192f92c 2555static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2556{
2557 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2558 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2559 unsigned long flags;
2560
2561 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2562 if (atmel_port->pending) {
2563 atmel_handle_receive(port, atmel_port->pending);
2564 atmel_handle_status(port, atmel_port->pending,
2565 atmel_port->pending_status);
2566 atmel_handle_transmit(port, atmel_port->pending);
2567 atmel_port->pending = 0;
2568 }
2569 atmel_port->suspended = false;
2570 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2571
f05596db
AS		 2572 uart_resume_port(&atmel_uart, port);
2573 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2574
2575 return 0;
2576}
afefc415 2577#else
7192f92c
HS		 2578#define atmel_serial_suspend NULL
2579#define atmel_serial_resume NULL
afefc415 2580#endif
1e6c9c28 2581
e0b0baad
RG		 2582static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2583{
ab5e4e41
RG		 2584 enum mctrl_gpio_idx i;
2585 struct gpio_desc *gpiod;
2586
e0b0baad 2587 p->gpios = mctrl_gpio_init(dev, 0);
722ccf41
UKK		 2588 if (IS_ERR(p->gpios))
2589 return PTR_ERR(p->gpios);
e0b0baad 2590
ab5e4e41
RG		 2591 for (i = 0; i < UART_GPIO_MAX; i++) {
2592 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2593 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2594 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2595 else
2596 p->gpio_irq[i] = -EINVAL;
2597 }
2598
e0b0baad
RG		 2599 return 0;
2600}
2601
9671f099 2602static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2603{
7192f92c 2604 struct atmel_uart_port *port;
5fbe46b6 2605 struct device_node *np = pdev->dev.of_node;
574de559 2606 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1ecc26bd 2607 void *data;
4cbf9f48 2608 int ret = -ENODEV;
bd737f87 2609 bool rs485_enabled;
1e6c9c28 2610
9d09daf8 2611 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2612
5fbe46b6
NF		 2613 if (np)
2614 ret = of_alias_get_id(np, "serial");
2615 else
2616 if (pdata)
2617 ret = pdata->num;
4cbf9f48
NF		 2618
2619 if (ret < 0)
5fbe46b6 2620 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2621 * auto-enumerate it */
503bded9 2622 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2623
503bded9 2624 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2625 ret = -ENODEV;
2626 goto err;
2627 }
2628
503bded9 2629 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2630 /* port already in use */
2631 ret = -EBUSY;
2632 goto err;
2633 }
2634
2635 port = &atmel_ports[ret];
f05596db 2636 port->backup_imr = 0;
4cbf9f48 2637 port->uart.line = ret;
e0b0baad 2638
2c7af5ba
BB		 2639 spin_lock_init(&port->lock_suspended);
2640
e0b0baad 2641 ret = atmel_init_gpios(port, &pdev->dev);
722ccf41
UKK		 2642 if (ret < 0) {
2643 dev_err(&pdev->dev, "Failed to initialize GPIOs.");
2644 goto err;
2645 }
f05596db 2646
91f8c2d8
BB		 2647 ret = atmel_init_port(port, pdev);
2648 if (ret)
6fbb9bdf 2649 goto err_clear_bit;
1e6c9c28 2650
64e22ebe 2651 if (!atmel_use_pdc_rx(&port->uart)) {
a6670615 2652 ret = -ENOMEM;
6433471d
HS		 2653 data = kmalloc(sizeof(struct atmel_uart_char)
2654 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC		 2655 if (!data)
2656 goto err_alloc_ring;
2657 port->rx_ring.buf = data;
2658 }
1ecc26bd 2659
bd737f87
RRD		 2660 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED;
2661
7192f92c 2662 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS		 2663 if (ret)
2664 goto err_add_port;
2665
8da14b5f 2666#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
06a7f058
DB		 2667 if (atmel_is_console_port(&port->uart)
2668 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2669 /*
2670 * The serial core enabled the clock for us, so undo
91f8c2d8 2671 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2672 */
91f8c2d8 2673 clk_disable_unprepare(port->clk);
06a7f058 2674 }
8da14b5f 2675#endif
06a7f058 2676
dfa7f343
HS		 2677 device_init_wakeup(&pdev->dev, 1);
2678 platform_set_drvdata(pdev, port);
2679
d4f64187
CP		 2680 /*
2681 * The peripheral clock has been disabled by atmel_init_port():
2682 * enable it before accessing I/O registers
2683 */
2684 clk_prepare_enable(port->clk);
2685
bd737f87 2686 if (rs485_enabled) {
5dfbd1d7
CS		 2687 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2688 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2689 }
2690
055560b0
ES		 2691 /*
2692 * Get port name of usart or uart
2693 */
892db58b 2694 atmel_get_ip_name(&port->uart);
055560b0 2695
d4f64187
CP		 2696 /*
2697 * The peripheral clock can now safely be disabled till the port
2698 * is used
2699 */
2700 clk_disable_unprepare(port->clk);
2701
dfa7f343
HS		 2702 return 0;
2703
2704err_add_port:
1ecc26bd
RB		 2705 kfree(port->rx_ring.buf);
2706 port->rx_ring.buf = NULL;
2707err_alloc_ring:
dfa7f343 2708 if (!atmel_is_console_port(&port->uart)) {
dfa7f343
HS		 2709 clk_put(port->clk);
2710 port->clk = NULL;
afefc415 2711 }
6fbb9bdf
CP		 2712err_clear_bit:
2713 clear_bit(port->uart.line, atmel_ports_in_use);
4cbf9f48 2714err:
afefc415
AV		 2715 return ret;
2716}
2717
ae8d8a14 2718static int atmel_serial_remove(struct platform_device *pdev)
afefc415
AV		 2719{
2720 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2721 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415
AV		 2722 int ret = 0;
2723
f50c995f
MR		 2724 tasklet_kill(&atmel_port->tasklet);
2725
afefc415 2726 device_init_wakeup(&pdev->dev, 0);
afefc415 2727
dfa7f343
HS		 2728 ret = uart_remove_one_port(&atmel_uart, port);
2729
1ecc26bd
RB		 2730 kfree(atmel_port->rx_ring.buf);
2731
dfa7f343
HS		 2732 /* "port" is allocated statically, so we shouldn't free it */
2733
503bded9 2734 clear_bit(port->line, atmel_ports_in_use);
4cbf9f48 2735
dfa7f343 2736 clk_put(atmel_port->clk);
afefc415
AV		 2737
2738 return ret;
2739}
2740
7192f92c
HS		 2741static struct platform_driver atmel_serial_driver = {
2742 .probe = atmel_serial_probe,
2d47b716 2743 .remove = atmel_serial_remove,
7192f92c
HS		 2744 .suspend = atmel_serial_suspend,
2745 .resume = atmel_serial_resume,
afefc415 2746 .driver = {
1e8ea802 2747 .name = "atmel_usart",
5fbe46b6 2748 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 2749 },
2750};
2751
7192f92c 2752static int __init atmel_serial_init(void)
afefc415
AV		 2753{
2754 int ret;
2755
7192f92c 2756 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 2757 if (ret)
2758 return ret;
2759
7192f92c 2760 ret = platform_driver_register(&atmel_serial_driver);
afefc415 2761 if (ret)
7192f92c 2762 uart_unregister_driver(&atmel_uart);
afefc415
AV		 2763
2764 return ret;
2765}
2766
7192f92c 2767static void __exit atmel_serial_exit(void)
afefc415 2768{
7192f92c
HS		 2769 platform_driver_unregister(&atmel_serial_driver);
2770 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV		 2771}
2772
7192f92c
HS		 2773module_init(atmel_serial_init);
2774module_exit(atmel_serial_exit);
1e6c9c28
AV		 2775
2776MODULE_AUTHOR("Rick Bronson");
7192f92c 2777MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 2778MODULE_LICENSE("GPL");
e169c139 2779MODULE_ALIAS("platform:atmel_usart");
Linux 6.x block layer and io_uring tree(s)