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tty/serial/amba-pl011: Implement poll_init callback
[linux-2.6-block.git] / drivers / tty / serial / amba-pl011.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
68b65f73 8 * Copyright (C) 2010 ST-Ericsson SA
1da177e4
LT		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
1da177e4
LT		 24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
1da177e4
LT		 31
32#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/module.h>
37#include <linux/ioport.h>
38#include <linux/init.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/device.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/serial.h>
a62c80e5
RK		 46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
f8ce2547 48#include <linux/clk.h>
5a0e3ad6 49#include <linux/slab.h>
68b65f73
RK		 50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
c16d51a3 53#include <linux/delay.h>
258aea76 54#include <linux/types.h>
32614aad
ML		 55#include <linux/of.h>
56#include <linux/of_device.h>
258e0551 57#include <linux/pinctrl/consumer.h>
cb70706c 58#include <linux/sizes.h>
1da177e4
LT		 59
60#include <asm/io.h>
1da177e4
LT		 61
62#define UART_NR 14
63
64#define SERIAL_AMBA_MAJOR 204
65#define SERIAL_AMBA_MINOR 64
66#define SERIAL_AMBA_NR UART_NR
67
68#define AMBA_ISR_PASS_LIMIT 256
69
b63d4f0f
RK		 70#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
71#define UART_DUMMY_DR_RX (1 << 16)
1da177e4 72
5926a295
AR		 73/* There is by now at least one vendor with differing details, so handle it */
74struct vendor_data {
75 unsigned int ifls;
76 unsigned int fifosize;
ec489aa8
LW		 77 unsigned int lcrh_tx;
78 unsigned int lcrh_rx;
ac3e3fb4 79 bool oversampling;
38d62436 80 bool dma_threshold;
4fd0690b 81 bool cts_event_workaround;
5926a295
AR		 82};
83
84static struct vendor_data vendor_arm = {
85 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
86 .fifosize = 16,
ec489aa8
LW		 87 .lcrh_tx = UART011_LCRH,
88 .lcrh_rx = UART011_LCRH,
ac3e3fb4 89 .oversampling = false,
38d62436 90 .dma_threshold = false,
4fd0690b 91 .cts_event_workaround = false,
5926a295
AR		 92};
93
94static struct vendor_data vendor_st = {
95 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
96 .fifosize = 64,
ec489aa8
LW		 97 .lcrh_tx = ST_UART011_LCRH_TX,
98 .lcrh_rx = ST_UART011_LCRH_RX,
ac3e3fb4 99 .oversampling = true,
38d62436 100 .dma_threshold = true,
4fd0690b 101 .cts_event_workaround = true,
1da177e4
LT		 102};
103
c16d51a3
SKS		 104static struct uart_amba_port *amba_ports[UART_NR];
105
68b65f73 106/* Deals with DMA transactions */
ead76f32
LW		 107
108struct pl011_sgbuf {
109 struct scatterlist sg;
110 char *buf;
111};
112
113struct pl011_dmarx_data {
114 struct dma_chan *chan;
115 struct completion complete;
116 bool use_buf_b;
117 struct pl011_sgbuf sgbuf_a;
118 struct pl011_sgbuf sgbuf_b;
119 dma_cookie_t cookie;
120 bool running;
121};
122
68b65f73
RK		 123struct pl011_dmatx_data {
124 struct dma_chan *chan;
125 struct scatterlist sg;
126 char *buf;
127 bool queued;
128};
129
c19f12b5
RK		 130/*
131 * We wrap our port structure around the generic uart_port.
132 */
133struct uart_amba_port {
134 struct uart_port port;
135 struct clk *clk;
78d80c5a
LW		 136 /* Two optional pin states - default & sleep */
137 struct pinctrl *pinctrl;
138 struct pinctrl_state *pins_default;
139 struct pinctrl_state *pins_sleep;
c19f12b5 140 const struct vendor_data *vendor;
68b65f73 141 unsigned int dmacr; /* dma control reg */
c19f12b5
RK		 142 unsigned int im; /* interrupt mask */
143 unsigned int old_status;
ffca2b11 144 unsigned int fifosize; /* vendor-specific */
c19f12b5
RK		 145 unsigned int lcrh_tx; /* vendor-specific */
146 unsigned int lcrh_rx; /* vendor-specific */
d8d8ffa4 147 unsigned int old_cr; /* state during shutdown */
c19f12b5
RK		 148 bool autorts;
149 char type[12];
68b65f73
RK		 150#ifdef CONFIG_DMA_ENGINE
151 /* DMA stuff */
ead76f32
LW		 152 bool using_tx_dma;
153 bool using_rx_dma;
154 struct pl011_dmarx_data dmarx;
68b65f73
RK		 155 struct pl011_dmatx_data dmatx;
156#endif
157};
158
29772c4e
LW		 159/*
160 * Reads up to 256 characters from the FIFO or until it's empty and
161 * inserts them into the TTY layer. Returns the number of characters
162 * read from the FIFO.
163 */
164static int pl011_fifo_to_tty(struct uart_amba_port *uap)
165{
166 u16 status, ch;
167 unsigned int flag, max_count = 256;
168 int fifotaken = 0;
169
170 while (max_count--) {
171 status = readw(uap->port.membase + UART01x_FR);
172 if (status & UART01x_FR_RXFE)
173 break;
174
175 /* Take chars from the FIFO and update status */
176 ch = readw(uap->port.membase + UART01x_DR) |
177 UART_DUMMY_DR_RX;
178 flag = TTY_NORMAL;
179 uap->port.icount.rx++;
180 fifotaken++;
181
182 if (unlikely(ch & UART_DR_ERROR)) {
183 if (ch & UART011_DR_BE) {
184 ch &= ~(UART011_DR_FE | UART011_DR_PE);
185 uap->port.icount.brk++;
186 if (uart_handle_break(&uap->port))
187 continue;
188 } else if (ch & UART011_DR_PE)
189 uap->port.icount.parity++;
190 else if (ch & UART011_DR_FE)
191 uap->port.icount.frame++;
192 if (ch & UART011_DR_OE)
193 uap->port.icount.overrun++;
194
195 ch &= uap->port.read_status_mask;
196
197 if (ch & UART011_DR_BE)
198 flag = TTY_BREAK;
199 else if (ch & UART011_DR_PE)
200 flag = TTY_PARITY;
201 else if (ch & UART011_DR_FE)
202 flag = TTY_FRAME;
203 }
204
205 if (uart_handle_sysrq_char(&uap->port, ch & 255))
206 continue;
207
208 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
209 }
210
211 return fifotaken;
212}
213
214
68b65f73
RK		 215/*
216 * All the DMA operation mode stuff goes inside this ifdef.
217 * This assumes that you have a generic DMA device interface,
218 * no custom DMA interfaces are supported.
219 */
220#ifdef CONFIG_DMA_ENGINE
221
222#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
223
ead76f32
LW		 224static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
225 enum dma_data_direction dir)
226{
227 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
228 if (!sg->buf)
229 return -ENOMEM;
230
231 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
232
233 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
234 kfree(sg->buf);
235 return -EINVAL;
236 }
237 return 0;
238}
239
240static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
241 enum dma_data_direction dir)
242{
243 if (sg->buf) {
244 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
245 kfree(sg->buf);
246 }
247}
248
68b65f73
RK		 249static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
250{
251 /* DMA is the sole user of the platform data right now */
252 struct amba_pl011_data *plat = uap->port.dev->platform_data;
253 struct dma_slave_config tx_conf = {
254 .dst_addr = uap->port.mapbase + UART01x_DR,
255 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 256 .direction = DMA_MEM_TO_DEV,
68b65f73 257 .dst_maxburst = uap->fifosize >> 1,
258aea76 258 .device_fc = false,
68b65f73
RK		 259 };
260 struct dma_chan *chan;
261 dma_cap_mask_t mask;
262
263 /* We need platform data */
264 if (!plat || !plat->dma_filter) {
265 dev_info(uap->port.dev, "no DMA platform data\n");
266 return;
267 }
268
ead76f32 269 /* Try to acquire a generic DMA engine slave TX channel */
68b65f73
RK		 270 dma_cap_zero(mask);
271 dma_cap_set(DMA_SLAVE, mask);
272
273 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
274 if (!chan) {
275 dev_err(uap->port.dev, "no TX DMA channel!\n");
276 return;
277 }
278
279 dmaengine_slave_config(chan, &tx_conf);
280 uap->dmatx.chan = chan;
281
282 dev_info(uap->port.dev, "DMA channel TX %s\n",
283 dma_chan_name(uap->dmatx.chan));
ead76f32
LW		 284
285 /* Optionally make use of an RX channel as well */
286 if (plat->dma_rx_param) {
287 struct dma_slave_config rx_conf = {
288 .src_addr = uap->port.mapbase + UART01x_DR,
289 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 290 .direction = DMA_DEV_TO_MEM,
ead76f32 291 .src_maxburst = uap->fifosize >> 1,
258aea76 292 .device_fc = false,
ead76f32
LW		 293 };
294
295 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
296 if (!chan) {
297 dev_err(uap->port.dev, "no RX DMA channel!\n");
298 return;
299 }
300
301 dmaengine_slave_config(chan, &rx_conf);
302 uap->dmarx.chan = chan;
303
304 dev_info(uap->port.dev, "DMA channel RX %s\n",
305 dma_chan_name(uap->dmarx.chan));
306 }
68b65f73
RK		 307}
308
309#ifndef MODULE
310/*
311 * Stack up the UARTs and let the above initcall be done at device
312 * initcall time, because the serial driver is called as an arch
313 * initcall, and at this time the DMA subsystem is not yet registered.
314 * At this point the driver will switch over to using DMA where desired.
315 */
316struct dma_uap {
317 struct list_head node;
318 struct uart_amba_port *uap;
c19f12b5
RK		 319};
320
68b65f73
RK		 321static LIST_HEAD(pl011_dma_uarts);
322
323static int __init pl011_dma_initcall(void)
324{
325 struct list_head *node, *tmp;
326
327 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
328 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
329 pl011_dma_probe_initcall(dmau->uap);
330 list_del(node);
331 kfree(dmau);
332 }
333 return 0;
334}
335
336device_initcall(pl011_dma_initcall);
337
338static void pl011_dma_probe(struct uart_amba_port *uap)
339{
340 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
341 if (dmau) {
342 dmau->uap = uap;
343 list_add_tail(&dmau->node, &pl011_dma_uarts);
344 }
345}
346#else
347static void pl011_dma_probe(struct uart_amba_port *uap)
348{
349 pl011_dma_probe_initcall(uap);
350}
351#endif
352
353static void pl011_dma_remove(struct uart_amba_port *uap)
354{
355 /* TODO: remove the initcall if it has not yet executed */
356 if (uap->dmatx.chan)
357 dma_release_channel(uap->dmatx.chan);
ead76f32
LW		 358 if (uap->dmarx.chan)
359 dma_release_channel(uap->dmarx.chan);
68b65f73
RK		 360}
361
68b65f73
RK		 362/* Forward declare this for the refill routine */
363static int pl011_dma_tx_refill(struct uart_amba_port *uap);
364
365/*
366 * The current DMA TX buffer has been sent.
367 * Try to queue up another DMA buffer.
368 */
369static void pl011_dma_tx_callback(void *data)
370{
371 struct uart_amba_port *uap = data;
372 struct pl011_dmatx_data *dmatx = &uap->dmatx;
373 unsigned long flags;
374 u16 dmacr;
375
376 spin_lock_irqsave(&uap->port.lock, flags);
377 if (uap->dmatx.queued)
378 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
379 DMA_TO_DEVICE);
380
381 dmacr = uap->dmacr;
382 uap->dmacr = dmacr & ~UART011_TXDMAE;
383 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
384
385 /*
386 * If TX DMA was disabled, it means that we've stopped the DMA for
387 * some reason (eg, XOFF received, or we want to send an X-char.)
388 *
389 * Note: we need to be careful here of a potential race between DMA
390 * and the rest of the driver - if the driver disables TX DMA while
391 * a TX buffer completing, we must update the tx queued status to
392 * get further refills (hence we check dmacr).
393 */
394 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
395 uart_circ_empty(&uap->port.state->xmit)) {
396 uap->dmatx.queued = false;
397 spin_unlock_irqrestore(&uap->port.lock, flags);
398 return;
399 }
400
401 if (pl011_dma_tx_refill(uap) <= 0) {
402 /*
403 * We didn't queue a DMA buffer for some reason, but we
404 * have data pending to be sent. Re-enable the TX IRQ.
405 */
406 uap->im |= UART011_TXIM;
407 writew(uap->im, uap->port.membase + UART011_IMSC);
408 }
409 spin_unlock_irqrestore(&uap->port.lock, flags);
410}
411
412/*
413 * Try to refill the TX DMA buffer.
414 * Locking: called with port lock held and IRQs disabled.
415 * Returns:
416 * 1 if we queued up a TX DMA buffer.
417 * 0 if we didn't want to handle this by DMA
418 * <0 on error
419 */
420static int pl011_dma_tx_refill(struct uart_amba_port *uap)
421{
422 struct pl011_dmatx_data *dmatx = &uap->dmatx;
423 struct dma_chan *chan = dmatx->chan;
424 struct dma_device *dma_dev = chan->device;
425 struct dma_async_tx_descriptor *desc;
426 struct circ_buf *xmit = &uap->port.state->xmit;
427 unsigned int count;
428
429 /*
430 * Try to avoid the overhead involved in using DMA if the
431 * transaction fits in the first half of the FIFO, by using
432 * the standard interrupt handling. This ensures that we
433 * issue a uart_write_wakeup() at the appropriate time.
434 */
435 count = uart_circ_chars_pending(xmit);
436 if (count < (uap->fifosize >> 1)) {
437 uap->dmatx.queued = false;
438 return 0;
439 }
440
441 /*
442 * Bodge: don't send the last character by DMA, as this
443 * will prevent XON from notifying us to restart DMA.
444 */
445 count -= 1;
446
447 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
448 if (count > PL011_DMA_BUFFER_SIZE)
449 count = PL011_DMA_BUFFER_SIZE;
450
451 if (xmit->tail < xmit->head)
452 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
453 else {
454 size_t first = UART_XMIT_SIZE - xmit->tail;
455 size_t second = xmit->head;
456
457 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
458 if (second)
459 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
460 }
461
462 dmatx->sg.length = count;
463
464 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
465 uap->dmatx.queued = false;
466 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
467 return -EBUSY;
468 }
469
16052827 470 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
68b65f73
RK		 471 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
472 if (!desc) {
473 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
474 uap->dmatx.queued = false;
475 /*
476 * If DMA cannot be used right now, we complete this
477 * transaction via IRQ and let the TTY layer retry.
478 */
479 dev_dbg(uap->port.dev, "TX DMA busy\n");
480 return -EBUSY;
481 }
482
483 /* Some data to go along to the callback */
484 desc->callback = pl011_dma_tx_callback;
485 desc->callback_param = uap;
486
487 /* All errors should happen at prepare time */
488 dmaengine_submit(desc);
489
490 /* Fire the DMA transaction */
491 dma_dev->device_issue_pending(chan);
492
493 uap->dmacr |= UART011_TXDMAE;
494 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
495 uap->dmatx.queued = true;
496
497 /*
498 * Now we know that DMA will fire, so advance the ring buffer
499 * with the stuff we just dispatched.
500 */
501 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
502 uap->port.icount.tx += count;
503
504 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
505 uart_write_wakeup(&uap->port);
506
507 return 1;
508}
509
510/*
511 * We received a transmit interrupt without a pending X-char but with
512 * pending characters.
513 * Locking: called with port lock held and IRQs disabled.
514 * Returns:
515 * false if we want to use PIO to transmit
516 * true if we queued a DMA buffer
517 */
518static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
519{
ead76f32 520 if (!uap->using_tx_dma)
68b65f73
RK		 521 return false;
522
523 /*
524 * If we already have a TX buffer queued, but received a
525 * TX interrupt, it will be because we've just sent an X-char.
526 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
527 */
528 if (uap->dmatx.queued) {
529 uap->dmacr |= UART011_TXDMAE;
530 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
531 uap->im &= ~UART011_TXIM;
532 writew(uap->im, uap->port.membase + UART011_IMSC);
533 return true;
534 }
535
536 /*
537 * We don't have a TX buffer queued, so try to queue one.
25985edc 538 * If we successfully queued a buffer, mask the TX IRQ.
68b65f73
RK		 539 */
540 if (pl011_dma_tx_refill(uap) > 0) {
541 uap->im &= ~UART011_TXIM;
542 writew(uap->im, uap->port.membase + UART011_IMSC);
543 return true;
544 }
545 return false;
546}
547
548/*
549 * Stop the DMA transmit (eg, due to received XOFF).
550 * Locking: called with port lock held and IRQs disabled.
551 */
552static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
553{
554 if (uap->dmatx.queued) {
555 uap->dmacr &= ~UART011_TXDMAE;
556 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
557 }
558}
559
560/*
561 * Try to start a DMA transmit, or in the case of an XON/OFF
562 * character queued for send, try to get that character out ASAP.
563 * Locking: called with port lock held and IRQs disabled.
564 * Returns:
565 * false if we want the TX IRQ to be enabled
566 * true if we have a buffer queued
567 */
568static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
569{
570 u16 dmacr;
571
ead76f32 572 if (!uap->using_tx_dma)
68b65f73
RK		 573 return false;
574
575 if (!uap->port.x_char) {
576 /* no X-char, try to push chars out in DMA mode */
577 bool ret = true;
578
579 if (!uap->dmatx.queued) {
580 if (pl011_dma_tx_refill(uap) > 0) {
581 uap->im &= ~UART011_TXIM;
582 ret = true;
583 } else {
584 uap->im |= UART011_TXIM;
585 ret = false;
586 }
587 writew(uap->im, uap->port.membase + UART011_IMSC);
588 } else if (!(uap->dmacr & UART011_TXDMAE)) {
589 uap->dmacr |= UART011_TXDMAE;
590 writew(uap->dmacr,
591 uap->port.membase + UART011_DMACR);
592 }
593 return ret;
594 }
595
596 /*
597 * We have an X-char to send. Disable DMA to prevent it loading
598 * the TX fifo, and then see if we can stuff it into the FIFO.
599 */
600 dmacr = uap->dmacr;
601 uap->dmacr &= ~UART011_TXDMAE;
602 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
603
604 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
605 /*
606 * No space in the FIFO, so enable the transmit interrupt
607 * so we know when there is space. Note that once we've
608 * loaded the character, we should just re-enable DMA.
609 */
610 return false;
611 }
612
613 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
614 uap->port.icount.tx++;
615 uap->port.x_char = 0;
616
617 /* Success - restore the DMA state */
618 uap->dmacr = dmacr;
619 writew(dmacr, uap->port.membase + UART011_DMACR);
620
621 return true;
622}
623
624/*
625 * Flush the transmit buffer.
626 * Locking: called with port lock held and IRQs disabled.
627 */
628static void pl011_dma_flush_buffer(struct uart_port *port)
629{
630 struct uart_amba_port *uap = (struct uart_amba_port *)port;
631
ead76f32 632 if (!uap->using_tx_dma)
68b65f73
RK		 633 return;
634
635 /* Avoid deadlock with the DMA engine callback */
636 spin_unlock(&uap->port.lock);
637 dmaengine_terminate_all(uap->dmatx.chan);
638 spin_lock(&uap->port.lock);
639 if (uap->dmatx.queued) {
640 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
641 DMA_TO_DEVICE);
642 uap->dmatx.queued = false;
643 uap->dmacr &= ~UART011_TXDMAE;
644 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
645 }
646}
647
ead76f32
LW		 648static void pl011_dma_rx_callback(void *data);
649
650static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
651{
652 struct dma_chan *rxchan = uap->dmarx.chan;
ead76f32
LW		 653 struct pl011_dmarx_data *dmarx = &uap->dmarx;
654 struct dma_async_tx_descriptor *desc;
655 struct pl011_sgbuf *sgbuf;
656
657 if (!rxchan)
658 return -EIO;
659
660 /* Start the RX DMA job */
661 sgbuf = uap->dmarx.use_buf_b ?
662 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
16052827 663 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
a485df4b 664 DMA_DEV_TO_MEM,
ead76f32
LW		 665 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
666 /*
667 * If the DMA engine is busy and cannot prepare a
668 * channel, no big deal, the driver will fall back
669 * to interrupt mode as a result of this error code.
670 */
671 if (!desc) {
672 uap->dmarx.running = false;
673 dmaengine_terminate_all(rxchan);
674 return -EBUSY;
675 }
676
677 /* Some data to go along to the callback */
678 desc->callback = pl011_dma_rx_callback;
679 desc->callback_param = uap;
680 dmarx->cookie = dmaengine_submit(desc);
681 dma_async_issue_pending(rxchan);
682
683 uap->dmacr |= UART011_RXDMAE;
684 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
685 uap->dmarx.running = true;
686
687 uap->im &= ~UART011_RXIM;
688 writew(uap->im, uap->port.membase + UART011_IMSC);
689
690 return 0;
691}
692
693/*
694 * This is called when either the DMA job is complete, or
695 * the FIFO timeout interrupt occurred. This must be called
696 * with the port spinlock uap->port.lock held.
697 */
698static void pl011_dma_rx_chars(struct uart_amba_port *uap,
699 u32 pending, bool use_buf_b,
700 bool readfifo)
701{
702 struct tty_struct *tty = uap->port.state->port.tty;
703 struct pl011_sgbuf *sgbuf = use_buf_b ?
704 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
705 struct device *dev = uap->dmarx.chan->device->dev;
ead76f32
LW		 706 int dma_count = 0;
707 u32 fifotaken = 0; /* only used for vdbg() */
708
709 /* Pick everything from the DMA first */
710 if (pending) {
711 /* Sync in buffer */
712 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
713
714 /*
715 * First take all chars in the DMA pipe, then look in the FIFO.
716 * Note that tty_insert_flip_buf() tries to take as many chars
717 * as it can.
718 */
719 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
720 sgbuf->buf, pending);
721
722 /* Return buffer to device */
723 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
724
725 uap->port.icount.rx += dma_count;
726 if (dma_count < pending)
727 dev_warn(uap->port.dev,
728 "couldn't insert all characters (TTY is full?)\n");
729 }
730
731 /*
732 * Only continue with trying to read the FIFO if all DMA chars have
733 * been taken first.
734 */
735 if (dma_count == pending && readfifo) {
736 /* Clear any error flags */
737 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
738 uap->port.membase + UART011_ICR);
739
740 /*
741 * If we read all the DMA'd characters, and we had an
29772c4e
LW		 742 * incomplete buffer, that could be due to an rx error, or
743 * maybe we just timed out. Read any pending chars and check
744 * the error status.
745 *
746 * Error conditions will only occur in the FIFO, these will
747 * trigger an immediate interrupt and stop the DMA job, so we
748 * will always find the error in the FIFO, never in the DMA
749 * buffer.
ead76f32 750 */
29772c4e 751 fifotaken = pl011_fifo_to_tty(uap);
ead76f32
LW		 752 }
753
754 spin_unlock(&uap->port.lock);
755 dev_vdbg(uap->port.dev,
756 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
757 dma_count, fifotaken);
758 tty_flip_buffer_push(tty);
759 spin_lock(&uap->port.lock);
760}
761
762static void pl011_dma_rx_irq(struct uart_amba_port *uap)
763{
764 struct pl011_dmarx_data *dmarx = &uap->dmarx;
765 struct dma_chan *rxchan = dmarx->chan;
766 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
767 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
768 size_t pending;
769 struct dma_tx_state state;
770 enum dma_status dmastat;
771
772 /*
773 * Pause the transfer so we can trust the current counter,
774 * do this before we pause the PL011 block, else we may
775 * overflow the FIFO.
776 */
777 if (dmaengine_pause(rxchan))
778 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
779 dmastat = rxchan->device->device_tx_status(rxchan,
780 dmarx->cookie, &state);
781 if (dmastat != DMA_PAUSED)
782 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
783
784 /* Disable RX DMA - incoming data will wait in the FIFO */
785 uap->dmacr &= ~UART011_RXDMAE;
786 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
787 uap->dmarx.running = false;
788
789 pending = sgbuf->sg.length - state.residue;
790 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
791 /* Then we terminate the transfer - we now know our residue */
792 dmaengine_terminate_all(rxchan);
793
794 /*
795 * This will take the chars we have so far and insert
796 * into the framework.
797 */
798 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
799
800 /* Switch buffer & re-trigger DMA job */
801 dmarx->use_buf_b = !dmarx->use_buf_b;
802 if (pl011_dma_rx_trigger_dma(uap)) {
803 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
804 "fall back to interrupt mode\n");
805 uap->im |= UART011_RXIM;
806 writew(uap->im, uap->port.membase + UART011_IMSC);
807 }
808}
809
810static void pl011_dma_rx_callback(void *data)
811{
812 struct uart_amba_port *uap = data;
813 struct pl011_dmarx_data *dmarx = &uap->dmarx;
6dc01aa6 814 struct dma_chan *rxchan = dmarx->chan;
ead76f32 815 bool lastbuf = dmarx->use_buf_b;
6dc01aa6
CM		 816 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
817 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
818 size_t pending;
819 struct dma_tx_state state;
ead76f32
LW		 820 int ret;
821
822 /*
823 * This completion interrupt occurs typically when the
824 * RX buffer is totally stuffed but no timeout has yet
825 * occurred. When that happens, we just want the RX
826 * routine to flush out the secondary DMA buffer while
827 * we immediately trigger the next DMA job.
828 */
829 spin_lock_irq(&uap->port.lock);
6dc01aa6
CM		 830 /*
831 * Rx data can be taken by the UART interrupts during
832 * the DMA irq handler. So we check the residue here.
833 */
834 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
835 pending = sgbuf->sg.length - state.residue;
836 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
837 /* Then we terminate the transfer - we now know our residue */
838 dmaengine_terminate_all(rxchan);
839
ead76f32
LW		 840 uap->dmarx.running = false;
841 dmarx->use_buf_b = !lastbuf;
842 ret = pl011_dma_rx_trigger_dma(uap);
843
6dc01aa6 844 pl011_dma_rx_chars(uap, pending, lastbuf, false);
ead76f32
LW		 845 spin_unlock_irq(&uap->port.lock);
846 /*
847 * Do this check after we picked the DMA chars so we don't
848 * get some IRQ immediately from RX.
849 */
850 if (ret) {
851 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
852 "fall back to interrupt mode\n");
853 uap->im |= UART011_RXIM;
854 writew(uap->im, uap->port.membase + UART011_IMSC);
855 }
856}
857
858/*
859 * Stop accepting received characters, when we're shutting down or
860 * suspending this port.
861 * Locking: called with port lock held and IRQs disabled.
862 */
863static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
864{
865 /* FIXME. Just disable the DMA enable */
866 uap->dmacr &= ~UART011_RXDMAE;
867 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
868}
68b65f73
RK		 869
870static void pl011_dma_startup(struct uart_amba_port *uap)
871{
ead76f32
LW		 872 int ret;
873
68b65f73
RK		 874 if (!uap->dmatx.chan)
875 return;
876
877 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
878 if (!uap->dmatx.buf) {
879 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
880 uap->port.fifosize = uap->fifosize;
881 return;
882 }
883
884 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
885
886 /* The DMA buffer is now the FIFO the TTY subsystem can use */
887 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
ead76f32
LW		 888 uap->using_tx_dma = true;
889
890 if (!uap->dmarx.chan)
891 goto skip_rx;
892
893 /* Allocate and map DMA RX buffers */
894 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
895 DMA_FROM_DEVICE);
896 if (ret) {
897 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
898 "RX buffer A", ret);
899 goto skip_rx;
900 }
68b65f73 901
ead76f32
LW		 902 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
903 DMA_FROM_DEVICE);
904 if (ret) {
905 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
906 "RX buffer B", ret);
907 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
908 DMA_FROM_DEVICE);
909 goto skip_rx;
910 }
911
912 uap->using_rx_dma = true;
68b65f73 913
ead76f32 914skip_rx:
68b65f73
RK		 915 /* Turn on DMA error (RX/TX will be enabled on demand) */
916 uap->dmacr |= UART011_DMAONERR;
917 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
38d62436
RK		 918
919 /*
920 * ST Micro variants has some specific dma burst threshold
921 * compensation. Set this to 16 bytes, so burst will only
922 * be issued above/below 16 bytes.
923 */
924 if (uap->vendor->dma_threshold)
925 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
926 uap->port.membase + ST_UART011_DMAWM);
ead76f32
LW		 927
928 if (uap->using_rx_dma) {
929 if (pl011_dma_rx_trigger_dma(uap))
930 dev_dbg(uap->port.dev, "could not trigger initial "
931 "RX DMA job, fall back to interrupt mode\n");
932 }
68b65f73
RK		 933}
934
935static void pl011_dma_shutdown(struct uart_amba_port *uap)
936{
ead76f32 937 if (!(uap->using_tx_dma || uap->using_rx_dma))
68b65f73
RK		 938 return;
939
940 /* Disable RX and TX DMA */
941 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
942 barrier();
943
944 spin_lock_irq(&uap->port.lock);
945 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
946 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
947 spin_unlock_irq(&uap->port.lock);
948
ead76f32
LW		 949 if (uap->using_tx_dma) {
950 /* In theory, this should already be done by pl011_dma_flush_buffer */
951 dmaengine_terminate_all(uap->dmatx.chan);
952 if (uap->dmatx.queued) {
953 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
954 DMA_TO_DEVICE);
955 uap->dmatx.queued = false;
956 }
957
958 kfree(uap->dmatx.buf);
959 uap->using_tx_dma = false;
68b65f73
RK		 960 }
961
ead76f32
LW		 962 if (uap->using_rx_dma) {
963 dmaengine_terminate_all(uap->dmarx.chan);
964 /* Clean up the RX DMA */
965 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
966 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
967 uap->using_rx_dma = false;
968 }
969}
68b65f73 970
ead76f32
LW		 971static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
972{
973 return uap->using_rx_dma;
68b65f73
RK		 974}
975
ead76f32
LW		 976static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
977{
978 return uap->using_rx_dma && uap->dmarx.running;
979}
980
981
68b65f73
RK		 982#else
983/* Blank functions if the DMA engine is not available */
984static inline void pl011_dma_probe(struct uart_amba_port *uap)
985{
986}
987
988static inline void pl011_dma_remove(struct uart_amba_port *uap)
989{
990}
991
992static inline void pl011_dma_startup(struct uart_amba_port *uap)
993{
994}
995
996static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
997{
998}
999
1000static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1001{
1002 return false;
1003}
1004
1005static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1006{
1007}
1008
1009static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1010{
1011 return false;
1012}
1013
ead76f32
LW		 1014static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1015{
1016}
1017
1018static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1019{
1020}
1021
1022static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1023{
1024 return -EIO;
1025}
1026
1027static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1028{
1029 return false;
1030}
1031
1032static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1033{
1034 return false;
1035}
1036
68b65f73
RK		 1037#define pl011_dma_flush_buffer NULL
1038#endif
1039
b129a8cc 1040static void pl011_stop_tx(struct uart_port *port)
1da177e4
LT		 1041{
1042 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1043
1044 uap->im &= ~UART011_TXIM;
1045 writew(uap->im, uap->port.membase + UART011_IMSC);
68b65f73 1046 pl011_dma_tx_stop(uap);
1da177e4
LT		 1047}
1048
b129a8cc 1049static void pl011_start_tx(struct uart_port *port)
1da177e4
LT		 1050{
1051 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1052
68b65f73
RK		 1053 if (!pl011_dma_tx_start(uap)) {
1054 uap->im |= UART011_TXIM;
1055 writew(uap->im, uap->port.membase + UART011_IMSC);
1056 }
1da177e4
LT		 1057}
1058
1059static void pl011_stop_rx(struct uart_port *port)
1060{
1061 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1062
1063 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1064 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1065 writew(uap->im, uap->port.membase + UART011_IMSC);
ead76f32
LW		 1066
1067 pl011_dma_rx_stop(uap);
1da177e4
LT		 1068}
1069
1070static void pl011_enable_ms(struct uart_port *port)
1071{
1072 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1073
1074 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1075 writew(uap->im, uap->port.membase + UART011_IMSC);
1076}
1077
7d12e780 1078static void pl011_rx_chars(struct uart_amba_port *uap)
1da177e4 1079{
ebd2c8f6 1080 struct tty_struct *tty = uap->port.state->port.tty;
1da177e4 1081
29772c4e 1082 pl011_fifo_to_tty(uap);
1da177e4 1083
2389b272 1084 spin_unlock(&uap->port.lock);
1da177e4 1085 tty_flip_buffer_push(tty);
ead76f32
LW		 1086 /*
1087 * If we were temporarily out of DMA mode for a while,
1088 * attempt to switch back to DMA mode again.
1089 */
1090 if (pl011_dma_rx_available(uap)) {
1091 if (pl011_dma_rx_trigger_dma(uap)) {
1092 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1093 "fall back to interrupt mode again\n");
1094 uap->im |= UART011_RXIM;
1095 } else
1096 uap->im &= ~UART011_RXIM;
1097 writew(uap->im, uap->port.membase + UART011_IMSC);
1098 }
2389b272 1099 spin_lock(&uap->port.lock);
1da177e4
LT		 1100}
1101
1102static void pl011_tx_chars(struct uart_amba_port *uap)
1103{
ebd2c8f6 1104 struct circ_buf *xmit = &uap->port.state->xmit;
1da177e4
LT		 1105 int count;
1106
1107 if (uap->port.x_char) {
1108 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1109 uap->port.icount.tx++;
1110 uap->port.x_char = 0;
1111 return;
1112 }
1113 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 1114 pl011_stop_tx(&uap->port);
1da177e4
LT		 1115 return;
1116 }
1117
68b65f73
RK		 1118 /* If we are using DMA mode, try to send some characters. */
1119 if (pl011_dma_tx_irq(uap))
1120 return;
1121
ffca2b11 1122 count = uap->fifosize >> 1;
1da177e4
LT		 1123 do {
1124 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1125 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1126 uap->port.icount.tx++;
1127 if (uart_circ_empty(xmit))
1128 break;
1129 } while (--count > 0);
1130
1131 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1132 uart_write_wakeup(&uap->port);
1133
1134 if (uart_circ_empty(xmit))
b129a8cc 1135 pl011_stop_tx(&uap->port);
1da177e4
LT		 1136}
1137
1138static void pl011_modem_status(struct uart_amba_port *uap)
1139{
1140 unsigned int status, delta;
1141
1142 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1143
1144 delta = status ^ uap->old_status;
1145 uap->old_status = status;
1146
1147 if (!delta)
1148 return;
1149
1150 if (delta & UART01x_FR_DCD)
1151 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1152
1153 if (delta & UART01x_FR_DSR)
1154 uap->port.icount.dsr++;
1155
1156 if (delta & UART01x_FR_CTS)
1157 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1158
bdc04e31 1159 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 1160}
1161
7d12e780 1162static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 1163{
1164 struct uart_amba_port *uap = dev_id;
963cc981 1165 unsigned long flags;
1da177e4
LT		 1166 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1167 int handled = 0;
4fd0690b 1168 unsigned int dummy_read;
1da177e4 1169
963cc981 1170 spin_lock_irqsave(&uap->port.lock, flags);
1da177e4
LT		 1171
1172 status = readw(uap->port.membase + UART011_MIS);
1173 if (status) {
1174 do {
4fd0690b
R		 1175 if (uap->vendor->cts_event_workaround) {
1176 /* workaround to make sure that all bits are unlocked.. */
1177 writew(0x00, uap->port.membase + UART011_ICR);
1178
1179 /*
1180 * WA: introduce 26ns(1 uart clk) delay before W1C;
1181 * single apb access will incur 2 pclk(133.12Mhz) delay,
1182 * so add 2 dummy reads
1183 */
1184 dummy_read = readw(uap->port.membase + UART011_ICR);
1185 dummy_read = readw(uap->port.membase + UART011_ICR);
1186 }
1187
1da177e4
LT		 1188 writew(status & ~(UART011_TXIS|UART011_RTIS|
1189 UART011_RXIS),
1190 uap->port.membase + UART011_ICR);
1191
ead76f32
LW		 1192 if (status & (UART011_RTIS|UART011_RXIS)) {
1193 if (pl011_dma_rx_running(uap))
1194 pl011_dma_rx_irq(uap);
1195 else
1196 pl011_rx_chars(uap);
1197 }
1da177e4
LT		 1198 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1199 UART011_CTSMIS|UART011_RIMIS))
1200 pl011_modem_status(uap);
1201 if (status & UART011_TXIS)
1202 pl011_tx_chars(uap);
1203
4fd0690b 1204 if (pass_counter-- == 0)
1da177e4
LT		 1205 break;
1206
1207 status = readw(uap->port.membase + UART011_MIS);
1208 } while (status != 0);
1209 handled = 1;
1210 }
1211
963cc981 1212 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 1213
1214 return IRQ_RETVAL(handled);
1215}
1216
e643f87f 1217static unsigned int pl011_tx_empty(struct uart_port *port)
1da177e4
LT		 1218{
1219 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1220 unsigned int status = readw(uap->port.membase + UART01x_FR);
1221 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1222}
1223
e643f87f 1224static unsigned int pl011_get_mctrl(struct uart_port *port)
1da177e4
LT		 1225{
1226 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1227 unsigned int result = 0;
1228 unsigned int status = readw(uap->port.membase + UART01x_FR);
1229
5159f407 1230#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 1231 if (status & uartbit) \
1232 result |= tiocmbit
1233
5159f407
JS		 1234 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1235 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1236 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1237 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1238#undef TIOCMBIT
1da177e4
LT		 1239 return result;
1240}
1241
1242static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1243{
1244 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1245 unsigned int cr;
1246
1247 cr = readw(uap->port.membase + UART011_CR);
1248
5159f407 1249#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 1250 if (mctrl & tiocmbit) \
1251 cr |= uartbit; \
1252 else \
1253 cr &= ~uartbit
1254
5159f407
JS		 1255 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1256 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1257 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1258 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1259 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f
RV		 1260
1261 if (uap->autorts) {
1262 /* We need to disable auto-RTS if we want to turn RTS off */
1263 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1264 }
5159f407 1265#undef TIOCMBIT
1da177e4
LT		 1266
1267 writew(cr, uap->port.membase + UART011_CR);
1268}
1269
1270static void pl011_break_ctl(struct uart_port *port, int break_state)
1271{
1272 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1273 unsigned long flags;
1274 unsigned int lcr_h;
1275
1276 spin_lock_irqsave(&uap->port.lock, flags);
ec489aa8 1277 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 1278 if (break_state == -1)
1279 lcr_h |= UART01x_LCRH_BRK;
1280 else
1281 lcr_h &= ~UART01x_LCRH_BRK;
ec489aa8 1282 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 1283 spin_unlock_irqrestore(&uap->port.lock, flags);
1284}
1285
84b5ae15 1286#ifdef CONFIG_CONSOLE_POLL
e643f87f 1287static int pl011_get_poll_char(struct uart_port *port)
84b5ae15
JW		 1288{
1289 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1290 unsigned int status;
1291
f5316b4a
JW		 1292 status = readw(uap->port.membase + UART01x_FR);
1293 if (status & UART01x_FR_RXFE)
1294 return NO_POLL_CHAR;
84b5ae15
JW		 1295
1296 return readw(uap->port.membase + UART01x_DR);
1297}
1298
e643f87f 1299static void pl011_put_poll_char(struct uart_port *port,
84b5ae15
JW		 1300 unsigned char ch)
1301{
1302 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1303
1304 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1305 barrier();
1306
1307 writew(ch, uap->port.membase + UART01x_DR);
1308}
1309
1310#endif /* CONFIG_CONSOLE_POLL */
1311
b3564c2c 1312static int pl011_hwinit(struct uart_port *port)
1da177e4
LT		 1313{
1314 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 1315 int retval;
1316
78d80c5a
LW		 1317 /* Optionaly enable pins to be muxed in and configured */
1318 if (!IS_ERR(uap->pins_default)) {
1319 retval = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1320 if (retval)
1321 dev_err(port->dev,
1322 "could not set default pins\n");
1323 }
1324
1da177e4
LT		 1325 /*
1326 * Try to enable the clock producer.
1327 */
1c4c4394 1328 retval = clk_prepare_enable(uap->clk);
1da177e4 1329 if (retval)
1c4c4394 1330 goto out;
1da177e4
LT		 1331
1332 uap->port.uartclk = clk_get_rate(uap->clk);
1333
9b96fbac
LW		 1334 /* Clear pending error and receive interrupts */
1335 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1336 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1337
b3564c2c
AV		 1338 /*
1339 * Save interrupts enable mask, and enable RX interrupts in case if
1340 * the interrupt is used for NMI entry.
1341 */
1342 uap->im = readw(uap->port.membase + UART011_IMSC);
1343 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
1344
1345 if (uap->port.dev->platform_data) {
1346 struct amba_pl011_data *plat;
1347
1348 plat = uap->port.dev->platform_data;
1349 if (plat->init)
1350 plat->init();
1351 }
1352 return 0;
1353 out:
1354 return retval;
1355}
1356
1357static int pl011_startup(struct uart_port *port)
1358{
1359 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1360 unsigned int cr;
1361 int retval;
1362
1363 retval = pl011_hwinit(port);
1364 if (retval)
1365 goto clk_dis;
1366
1367 writew(uap->im, uap->port.membase + UART011_IMSC);
1368
1da177e4
LT		 1369 /*
1370 * Allocate the IRQ
1371 */
1372 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1373 if (retval)
1374 goto clk_dis;
1375
c19f12b5 1376 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1da177e4
LT		 1377
1378 /*
1379 * Provoke TX FIFO interrupt into asserting.
1380 */
1381 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1382 writew(cr, uap->port.membase + UART011_CR);
1383 writew(0, uap->port.membase + UART011_FBRD);
1384 writew(1, uap->port.membase + UART011_IBRD);
ec489aa8
LW		 1385 writew(0, uap->port.membase + uap->lcrh_rx);
1386 if (uap->lcrh_tx != uap->lcrh_rx) {
1387 int i;
1388 /*
1389 * Wait 10 PCLKs before writing LCRH_TX register,
1390 * to get this delay write read only register 10 times
1391 */
1392 for (i = 0; i < 10; ++i)
1393 writew(0xff, uap->port.membase + UART011_MIS);
1394 writew(0, uap->port.membase + uap->lcrh_tx);
1395 }
1da177e4
LT		 1396 writew(0, uap->port.membase + UART01x_DR);
1397 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1398 barrier();
1399
d8d8ffa4
SKS		 1400 /* restore RTS and DTR */
1401 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1402 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1da177e4
LT		 1403 writew(cr, uap->port.membase + UART011_CR);
1404
1405 /*
1406 * initialise the old status of the modem signals
1407 */
1408 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1409
68b65f73
RK		 1410 /* Startup DMA */
1411 pl011_dma_startup(uap);
1412
1da177e4 1413 /*
ead76f32
LW		 1414 * Finally, enable interrupts, only timeouts when using DMA
1415 * if initial RX DMA job failed, start in interrupt mode
1416 * as well.
1da177e4
LT		 1417 */
1418 spin_lock_irq(&uap->port.lock);
9b96fbac
LW		 1419 /* Clear out any spuriously appearing RX interrupts */
1420 writew(UART011_RTIS | UART011_RXIS,
1421 uap->port.membase + UART011_ICR);
ead76f32
LW		 1422 uap->im = UART011_RTIM;
1423 if (!pl011_dma_rx_running(uap))
1424 uap->im |= UART011_RXIM;
1da177e4
LT		 1425 writew(uap->im, uap->port.membase + UART011_IMSC);
1426 spin_unlock_irq(&uap->port.lock);
1427
1428 return 0;
1429
1430 clk_dis:
1c4c4394 1431 clk_disable_unprepare(uap->clk);
1da177e4
LT		 1432 return retval;
1433}
1434
ec489aa8
LW		 1435static void pl011_shutdown_channel(struct uart_amba_port *uap,
1436 unsigned int lcrh)
1437{
1438 unsigned long val;
1439
1440 val = readw(uap->port.membase + lcrh);
1441 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1442 writew(val, uap->port.membase + lcrh);
1443}
1444
1da177e4
LT		 1445static void pl011_shutdown(struct uart_port *port)
1446{
1447 struct uart_amba_port *uap = (struct uart_amba_port *)port;
d8d8ffa4 1448 unsigned int cr;
78d80c5a 1449 int retval;
1da177e4
LT		 1450
1451 /*
1452 * disable all interrupts
1453 */
1454 spin_lock_irq(&uap->port.lock);
1455 uap->im = 0;
1456 writew(uap->im, uap->port.membase + UART011_IMSC);
1457 writew(0xffff, uap->port.membase + UART011_ICR);
1458 spin_unlock_irq(&uap->port.lock);
1459
68b65f73
RK		 1460 pl011_dma_shutdown(uap);
1461
1da177e4
LT		 1462 /*
1463 * Free the interrupt
1464 */
1465 free_irq(uap->port.irq, uap);
1466
1467 /*
1468 * disable the port
d8d8ffa4
SKS		 1469 * disable the port. It should not disable RTS and DTR.
1470 * Also RTS and DTR state should be preserved to restore
1471 * it during startup().
1da177e4 1472 */
3b43816f 1473 uap->autorts = false;
d8d8ffa4
SKS		 1474 cr = readw(uap->port.membase + UART011_CR);
1475 uap->old_cr = cr;
1476 cr &= UART011_CR_RTS | UART011_CR_DTR;
1477 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1478 writew(cr, uap->port.membase + UART011_CR);
1da177e4
LT		 1479
1480 /*
1481 * disable break condition and fifos
1482 */
ec489aa8
LW		 1483 pl011_shutdown_channel(uap, uap->lcrh_rx);
1484 if (uap->lcrh_rx != uap->lcrh_tx)
1485 pl011_shutdown_channel(uap, uap->lcrh_tx);
1da177e4
LT		 1486
1487 /*
1488 * Shut down the clock producer
1489 */
1c4c4394 1490 clk_disable_unprepare(uap->clk);
78d80c5a
LW		 1491 /* Optionally let pins go into sleep states */
1492 if (!IS_ERR(uap->pins_sleep)) {
1493 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep);
1494 if (retval)
1495 dev_err(port->dev,
1496 "could not set pins to sleep state\n");
1497 }
1498
c16d51a3
SKS		 1499
1500 if (uap->port.dev->platform_data) {
1501 struct amba_pl011_data *plat;
1502
1503 plat = uap->port.dev->platform_data;
1504 if (plat->exit)
1505 plat->exit();
1506 }
1507
1da177e4
LT		 1508}
1509
1510static void
606d099c
AC		 1511pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1512 struct ktermios *old)
1da177e4 1513{
3b43816f 1514 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 1515 unsigned int lcr_h, old_cr;
1516 unsigned long flags;
c19f12b5
RK		 1517 unsigned int baud, quot, clkdiv;
1518
1519 if (uap->vendor->oversampling)
1520 clkdiv = 8;
1521 else
1522 clkdiv = 16;
1da177e4
LT		 1523
1524 /*
1525 * Ask the core to calculate the divisor for us.
1526 */
ac3e3fb4 1527 baud = uart_get_baud_rate(port, termios, old, 0,
c19f12b5 1528 port->uartclk / clkdiv);
ac3e3fb4
LW		 1529
1530 if (baud > port->uartclk/16)
1531 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1532 else
1533 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 1534
1535 switch (termios->c_cflag & CSIZE) {
1536 case CS5:
1537 lcr_h = UART01x_LCRH_WLEN_5;
1538 break;
1539 case CS6:
1540 lcr_h = UART01x_LCRH_WLEN_6;
1541 break;
1542 case CS7:
1543 lcr_h = UART01x_LCRH_WLEN_7;
1544 break;
1545 default: // CS8
1546 lcr_h = UART01x_LCRH_WLEN_8;
1547 break;
1548 }
1549 if (termios->c_cflag & CSTOPB)
1550 lcr_h |= UART01x_LCRH_STP2;
1551 if (termios->c_cflag & PARENB) {
1552 lcr_h |= UART01x_LCRH_PEN;
1553 if (!(termios->c_cflag & PARODD))
1554 lcr_h |= UART01x_LCRH_EPS;
1555 }
ffca2b11 1556 if (uap->fifosize > 1)
1da177e4
LT		 1557 lcr_h |= UART01x_LCRH_FEN;
1558
1559 spin_lock_irqsave(&port->lock, flags);
1560
1561 /*
1562 * Update the per-port timeout.
1563 */
1564 uart_update_timeout(port, termios->c_cflag, baud);
1565
b63d4f0f 1566 port->read_status_mask = UART011_DR_OE | 255;
1da177e4 1567 if (termios->c_iflag & INPCK)
b63d4f0f 1568 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1da177e4 1569 if (termios->c_iflag & (BRKINT | PARMRK))
b63d4f0f 1570 port->read_status_mask |= UART011_DR_BE;
1da177e4
LT		 1571
1572 /*
1573 * Characters to ignore
1574 */
1575 port->ignore_status_mask = 0;
1576 if (termios->c_iflag & IGNPAR)
b63d4f0f 1577 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1da177e4 1578 if (termios->c_iflag & IGNBRK) {
b63d4f0f 1579 port->ignore_status_mask |= UART011_DR_BE;
1da177e4
LT		 1580 /*
1581 * If we're ignoring parity and break indicators,
1582 * ignore overruns too (for real raw support).
1583 */
1584 if (termios->c_iflag & IGNPAR)
b63d4f0f 1585 port->ignore_status_mask |= UART011_DR_OE;
1da177e4
LT		 1586 }
1587
1588 /*
1589 * Ignore all characters if CREAD is not set.
1590 */
1591 if ((termios->c_cflag & CREAD) == 0)
b63d4f0f 1592 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1da177e4
LT		 1593
1594 if (UART_ENABLE_MS(port, termios->c_cflag))
1595 pl011_enable_ms(port);
1596
1597 /* first, disable everything */
1598 old_cr = readw(port->membase + UART011_CR);
1599 writew(0, port->membase + UART011_CR);
1600
3b43816f
RV		 1601 if (termios->c_cflag & CRTSCTS) {
1602 if (old_cr & UART011_CR_RTS)
1603 old_cr |= UART011_CR_RTSEN;
1604
1605 old_cr |= UART011_CR_CTSEN;
1606 uap->autorts = true;
1607 } else {
1608 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1609 uap->autorts = false;
1610 }
1611
c19f12b5
RK		 1612 if (uap->vendor->oversampling) {
1613 if (baud > port->uartclk / 16)
ac3e3fb4
LW		 1614 old_cr |= ST_UART011_CR_OVSFACT;
1615 else
1616 old_cr &= ~ST_UART011_CR_OVSFACT;
1617 }
1618
c5dd553b
LW		 1619 /*
1620 * Workaround for the ST Micro oversampling variants to
1621 * increase the bitrate slightly, by lowering the divisor,
1622 * to avoid delayed sampling of start bit at high speeds,
1623 * else we see data corruption.
1624 */
1625 if (uap->vendor->oversampling) {
1626 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1627 quot -= 1;
1628 else if ((baud > 3250000) && (quot > 2))
1629 quot -= 2;
1630 }
1da177e4
LT		 1631 /* Set baud rate */
1632 writew(quot & 0x3f, port->membase + UART011_FBRD);
1633 writew(quot >> 6, port->membase + UART011_IBRD);
1634
1635 /*
1636 * ----------v----------v----------v----------v-----
c5dd553b
LW		 1637 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1638 * UART011_FBRD & UART011_IBRD.
1da177e4
LT		 1639 * ----------^----------^----------^----------^-----
1640 */
ec489aa8
LW		 1641 writew(lcr_h, port->membase + uap->lcrh_rx);
1642 if (uap->lcrh_rx != uap->lcrh_tx) {
1643 int i;
1644 /*
1645 * Wait 10 PCLKs before writing LCRH_TX register,
1646 * to get this delay write read only register 10 times
1647 */
1648 for (i = 0; i < 10; ++i)
1649 writew(0xff, uap->port.membase + UART011_MIS);
1650 writew(lcr_h, port->membase + uap->lcrh_tx);
1651 }
1da177e4
LT		 1652 writew(old_cr, port->membase + UART011_CR);
1653
1654 spin_unlock_irqrestore(&port->lock, flags);
1655}
1656
1657static const char *pl011_type(struct uart_port *port)
1658{
e8a7ba86
RK		 1659 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1660 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 1661}
1662
1663/*
1664 * Release the memory region(s) being used by 'port'
1665 */
e643f87f 1666static void pl011_release_port(struct uart_port *port)
1da177e4
LT		 1667{
1668 release_mem_region(port->mapbase, SZ_4K);
1669}
1670
1671/*
1672 * Request the memory region(s) being used by 'port'
1673 */
e643f87f 1674static int pl011_request_port(struct uart_port *port)
1da177e4
LT		 1675{
1676 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1677 != NULL ? 0 : -EBUSY;
1678}
1679
1680/*
1681 * Configure/autoconfigure the port.
1682 */
e643f87f 1683static void pl011_config_port(struct uart_port *port, int flags)
1da177e4
LT		 1684{
1685 if (flags & UART_CONFIG_TYPE) {
1686 port->type = PORT_AMBA;
e643f87f 1687 pl011_request_port(port);
1da177e4
LT		 1688 }
1689}
1690
1691/*
1692 * verify the new serial_struct (for TIOCSSERIAL).
1693 */
e643f87f 1694static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4
LT		 1695{
1696 int ret = 0;
1697 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1698 ret = -EINVAL;
a62c4133 1699 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 1700 ret = -EINVAL;
1701 if (ser->baud_base < 9600)
1702 ret = -EINVAL;
1703 return ret;
1704}
1705
1706static struct uart_ops amba_pl011_pops = {
e643f87f 1707 .tx_empty = pl011_tx_empty,
1da177e4 1708 .set_mctrl = pl011_set_mctrl,
e643f87f 1709 .get_mctrl = pl011_get_mctrl,
1da177e4
LT		 1710 .stop_tx = pl011_stop_tx,
1711 .start_tx = pl011_start_tx,
1712 .stop_rx = pl011_stop_rx,
1713 .enable_ms = pl011_enable_ms,
1714 .break_ctl = pl011_break_ctl,
1715 .startup = pl011_startup,
1716 .shutdown = pl011_shutdown,
68b65f73 1717 .flush_buffer = pl011_dma_flush_buffer,
1da177e4
LT		 1718 .set_termios = pl011_set_termios,
1719 .type = pl011_type,
e643f87f
LW		 1720 .release_port = pl011_release_port,
1721 .request_port = pl011_request_port,
1722 .config_port = pl011_config_port,
1723 .verify_port = pl011_verify_port,
84b5ae15 1724#ifdef CONFIG_CONSOLE_POLL
b3564c2c 1725 .poll_init = pl011_hwinit,
e643f87f
LW		 1726 .poll_get_char = pl011_get_poll_char,
1727 .poll_put_char = pl011_put_poll_char,
84b5ae15 1728#endif
1da177e4
LT		 1729};
1730
1731static struct uart_amba_port *amba_ports[UART_NR];
1732
1733#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1734
d358788f 1735static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 1736{
d358788f 1737 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4 1738
d358788f
RK		 1739 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1740 barrier();
1da177e4
LT		 1741 writew(ch, uap->port.membase + UART01x_DR);
1742}
1743
1744static void
1745pl011_console_write(struct console *co, const char *s, unsigned int count)
1746{
1747 struct uart_amba_port *uap = amba_ports[co->index];
1748 unsigned int status, old_cr, new_cr;
ef605fdb
RV		 1749 unsigned long flags;
1750 int locked = 1;
1da177e4
LT		 1751
1752 clk_enable(uap->clk);
1753
ef605fdb
RV		 1754 local_irq_save(flags);
1755 if (uap->port.sysrq)
1756 locked = 0;
1757 else if (oops_in_progress)
1758 locked = spin_trylock(&uap->port.lock);
1759 else
1760 spin_lock(&uap->port.lock);
1761
1da177e4
LT		 1762 /*
1763 * First save the CR then disable the interrupts
1764 */
1765 old_cr = readw(uap->port.membase + UART011_CR);
1766 new_cr = old_cr & ~UART011_CR_CTSEN;
1767 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1768 writew(new_cr, uap->port.membase + UART011_CR);
1769
d358788f 1770 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 1771
1772 /*
1773 * Finally, wait for transmitter to become empty
1774 * and restore the TCR
1775 */
1776 do {
1777 status = readw(uap->port.membase + UART01x_FR);
1778 } while (status & UART01x_FR_BUSY);
1779 writew(old_cr, uap->port.membase + UART011_CR);
1780
ef605fdb
RV		 1781 if (locked)
1782 spin_unlock(&uap->port.lock);
1783 local_irq_restore(flags);
1784
1da177e4
LT		 1785 clk_disable(uap->clk);
1786}
1787
1788static void __init
1789pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1790 int *parity, int *bits)
1791{
1792 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1793 unsigned int lcr_h, ibrd, fbrd;
1794
ec489aa8 1795 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 1796
1797 *parity = 'n';
1798 if (lcr_h & UART01x_LCRH_PEN) {
1799 if (lcr_h & UART01x_LCRH_EPS)
1800 *parity = 'e';
1801 else
1802 *parity = 'o';
1803 }
1804
1805 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1806 *bits = 7;
1807 else
1808 *bits = 8;
1809
1810 ibrd = readw(uap->port.membase + UART011_IBRD);
1811 fbrd = readw(uap->port.membase + UART011_FBRD);
1812
1813 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4 1814
c19f12b5 1815 if (uap->vendor->oversampling) {
ac3e3fb4
LW		 1816 if (readw(uap->port.membase + UART011_CR)
1817 & ST_UART011_CR_OVSFACT)
1818 *baud *= 2;
1819 }
1da177e4
LT		 1820 }
1821}
1822
1823static int __init pl011_console_setup(struct console *co, char *options)
1824{
1825 struct uart_amba_port *uap;
1826 int baud = 38400;
1827 int bits = 8;
1828 int parity = 'n';
1829 int flow = 'n';
4b4851c6 1830 int ret;
1da177e4
LT		 1831
1832 /*
1833 * Check whether an invalid uart number has been specified, and
1834 * if so, search for the first available port that does have
1835 * console support.
1836 */
1837 if (co->index >= UART_NR)
1838 co->index = 0;
1839 uap = amba_ports[co->index];
d28122a5
RK		 1840 if (!uap)
1841 return -ENODEV;
1da177e4 1842
78d80c5a
LW		 1843 /* Allow pins to be muxed in and configured */
1844 if (!IS_ERR(uap->pins_default)) {
1845 ret = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1846 if (ret)
1847 dev_err(uap->port.dev,
1848 "could not set default pins\n");
1849 }
1850
4b4851c6
RK		 1851 ret = clk_prepare(uap->clk);
1852 if (ret)
1853 return ret;
1854
c16d51a3
SKS		 1855 if (uap->port.dev->platform_data) {
1856 struct amba_pl011_data *plat;
1857
1858 plat = uap->port.dev->platform_data;
1859 if (plat->init)
1860 plat->init();
1861 }
1862
1da177e4
LT		 1863 uap->port.uartclk = clk_get_rate(uap->clk);
1864
1865 if (options)
1866 uart_parse_options(options, &baud, &parity, &bits, &flow);
1867 else
1868 pl011_console_get_options(uap, &baud, &parity, &bits);
1869
1870 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1871}
1872
2d93486c 1873static struct uart_driver amba_reg;
1da177e4
LT		 1874static struct console amba_console = {
1875 .name = "ttyAMA",
1876 .write = pl011_console_write,
1877 .device = uart_console_device,
1878 .setup = pl011_console_setup,
1879 .flags = CON_PRINTBUFFER,
1880 .index = -1,
1881 .data = &amba_reg,
1882};
1883
1884#define AMBA_CONSOLE (&amba_console)
1885#else
1886#define AMBA_CONSOLE NULL
1887#endif
1888
1889static struct uart_driver amba_reg = {
1890 .owner = THIS_MODULE,
1891 .driver_name = "ttyAMA",
1892 .dev_name = "ttyAMA",
1893 .major = SERIAL_AMBA_MAJOR,
1894 .minor = SERIAL_AMBA_MINOR,
1895 .nr = UART_NR,
1896 .cons = AMBA_CONSOLE,
1897};
1898
32614aad
ML		 1899static int pl011_probe_dt_alias(int index, struct device *dev)
1900{
1901 struct device_node *np;
1902 static bool seen_dev_with_alias = false;
1903 static bool seen_dev_without_alias = false;
1904 int ret = index;
1905
1906 if (!IS_ENABLED(CONFIG_OF))
1907 return ret;
1908
1909 np = dev->of_node;
1910 if (!np)
1911 return ret;
1912
1913 ret = of_alias_get_id(np, "serial");
1914 if (IS_ERR_VALUE(ret)) {
1915 seen_dev_without_alias = true;
1916 ret = index;
1917 } else {
1918 seen_dev_with_alias = true;
1919 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
1920 dev_warn(dev, "requested serial port %d not available.\n", ret);
1921 ret = index;
1922 }
1923 }
1924
1925 if (seen_dev_with_alias && seen_dev_without_alias)
1926 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
1927
1928 return ret;
1929}
1930
aa25afad 1931static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1da177e4
LT		 1932{
1933 struct uart_amba_port *uap;
5926a295 1934 struct vendor_data *vendor = id->data;
1da177e4
LT		 1935 void __iomem *base;
1936 int i, ret;
1937
1938 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1939 if (amba_ports[i] == NULL)
1940 break;
1941
1942 if (i == ARRAY_SIZE(amba_ports)) {
1943 ret = -EBUSY;
1944 goto out;
1945 }
1946
dd00cc48 1947 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1da177e4
LT		 1948 if (uap == NULL) {
1949 ret = -ENOMEM;
1950 goto out;
1951 }
1952
32614aad
ML		 1953 i = pl011_probe_dt_alias(i, &dev->dev);
1954
dc890c2d 1955 base = ioremap(dev->res.start, resource_size(&dev->res));
1da177e4
LT		 1956 if (!base) {
1957 ret = -ENOMEM;
1958 goto free;
1959 }
1960
78d80c5a
LW		 1961 uap->pinctrl = devm_pinctrl_get(&dev->dev);
1962 if (IS_ERR(uap->pinctrl)) {
1963 ret = PTR_ERR(uap->pinctrl);
258e0551
SG		 1964 goto unmap;
1965 }
78d80c5a
LW		 1966 uap->pins_default = pinctrl_lookup_state(uap->pinctrl,
1967 PINCTRL_STATE_DEFAULT);
1968 if (IS_ERR(uap->pins_default))
1969 dev_err(&dev->dev, "could not get default pinstate\n");
1970
1971 uap->pins_sleep = pinctrl_lookup_state(uap->pinctrl,
1972 PINCTRL_STATE_SLEEP);
1973 if (IS_ERR(uap->pins_sleep))
1974 dev_dbg(&dev->dev, "could not get sleep pinstate\n");
258e0551 1975
ee569c43 1976 uap->clk = clk_get(&dev->dev, NULL);
1da177e4
LT		 1977 if (IS_ERR(uap->clk)) {
1978 ret = PTR_ERR(uap->clk);
1979 goto unmap;
1980 }
1981
c19f12b5 1982 uap->vendor = vendor;
ec489aa8
LW		 1983 uap->lcrh_rx = vendor->lcrh_rx;
1984 uap->lcrh_tx = vendor->lcrh_tx;
d8d8ffa4 1985 uap->old_cr = 0;
ffca2b11 1986 uap->fifosize = vendor->fifosize;
1da177e4
LT		 1987 uap->port.dev = &dev->dev;
1988 uap->port.mapbase = dev->res.start;
1989 uap->port.membase = base;
1990 uap->port.iotype = UPIO_MEM;
1991 uap->port.irq = dev->irq[0];
ffca2b11 1992 uap->port.fifosize = uap->fifosize;
1da177e4
LT		 1993 uap->port.ops = &amba_pl011_pops;
1994 uap->port.flags = UPF_BOOT_AUTOCONF;
1995 uap->port.line = i;
68b65f73 1996 pl011_dma_probe(uap);
1da177e4 1997
c3d8b76f
LW		 1998 /* Ensure interrupts from this UART are masked and cleared */
1999 writew(0, uap->port.membase + UART011_IMSC);
2000 writew(0xffff, uap->port.membase + UART011_ICR);
2001
e8a7ba86
RK		 2002 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2003
1da177e4
LT		 2004 amba_ports[i] = uap;
2005
2006 amba_set_drvdata(dev, uap);
2007 ret = uart_add_one_port(&amba_reg, &uap->port);
2008 if (ret) {
2009 amba_set_drvdata(dev, NULL);
2010 amba_ports[i] = NULL;
68b65f73 2011 pl011_dma_remove(uap);
1da177e4
LT		 2012 clk_put(uap->clk);
2013 unmap:
2014 iounmap(base);
2015 free:
2016 kfree(uap);
2017 }
2018 out:
2019 return ret;
2020}
2021
2022static int pl011_remove(struct amba_device *dev)
2023{
2024 struct uart_amba_port *uap = amba_get_drvdata(dev);
2025 int i;
2026
2027 amba_set_drvdata(dev, NULL);
2028
2029 uart_remove_one_port(&amba_reg, &uap->port);
2030
2031 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2032 if (amba_ports[i] == uap)
2033 amba_ports[i] = NULL;
2034
68b65f73 2035 pl011_dma_remove(uap);
1da177e4 2036 iounmap(uap->port.membase);
1da177e4
LT		 2037 clk_put(uap->clk);
2038 kfree(uap);
2039 return 0;
2040}
2041
b736b89f
LC		 2042#ifdef CONFIG_PM
2043static int pl011_suspend(struct amba_device *dev, pm_message_t state)
2044{
2045 struct uart_amba_port *uap = amba_get_drvdata(dev);
2046
2047 if (!uap)
2048 return -EINVAL;
2049
2050 return uart_suspend_port(&amba_reg, &uap->port);
2051}
2052
2053static int pl011_resume(struct amba_device *dev)
2054{
2055 struct uart_amba_port *uap = amba_get_drvdata(dev);
2056
2057 if (!uap)
2058 return -EINVAL;
2059
2060 return uart_resume_port(&amba_reg, &uap->port);
2061}
2062#endif
2063
2c39c9e1 2064static struct amba_id pl011_ids[] = {
1da177e4
LT		 2065 {
2066 .id = 0x00041011,
2067 .mask = 0x000fffff,
5926a295
AR		 2068 .data = &vendor_arm,
2069 },
2070 {
2071 .id = 0x00380802,
2072 .mask = 0x00ffffff,
2073 .data = &vendor_st,
1da177e4
LT		 2074 },
2075 { 0, 0 },
2076};
2077
60f7a33b
DM		 2078MODULE_DEVICE_TABLE(amba, pl011_ids);
2079
1da177e4
LT		 2080static struct amba_driver pl011_driver = {
2081 .drv = {
2082 .name = "uart-pl011",
2083 },
2084 .id_table = pl011_ids,
2085 .probe = pl011_probe,
2086 .remove = pl011_remove,
b736b89f
LC		 2087#ifdef CONFIG_PM
2088 .suspend = pl011_suspend,
2089 .resume = pl011_resume,
2090#endif
1da177e4
LT		 2091};
2092
2093static int __init pl011_init(void)
2094{
2095 int ret;
2096 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2097
2098 ret = uart_register_driver(&amba_reg);
2099 if (ret == 0) {
2100 ret = amba_driver_register(&pl011_driver);
2101 if (ret)
2102 uart_unregister_driver(&amba_reg);
2103 }
2104 return ret;
2105}
2106
2107static void __exit pl011_exit(void)
2108{
2109 amba_driver_unregister(&pl011_driver);
2110 uart_unregister_driver(&amba_reg);
2111}
2112
4dd9e742
AR		 2113/*
2114 * While this can be a module, if builtin it's most likely the console
2115 * So let's leave module_exit but move module_init to an earlier place
2116 */
2117arch_initcall(pl011_init);
1da177e4
LT		 2118module_exit(pl011_exit);
2119
2120MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2121MODULE_DESCRIPTION("ARM AMBA serial port driver");
2122MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)