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tty/serial: Fix break handling for PORT_TEGRA
[linux-2.6-block.git] / drivers / tty / serial / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <linux/8250_pci.h>
22#include <linux/bitops.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28
29#undef SERIAL_DEBUG_PCI
30
1da177e4
LT		 31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
42 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
05caac58 45 struct uart_port *, int);
1da177e4
LT		 46 void (*exit)(struct pci_dev *dev);
47};
48
49#define PCI_NUM_BAR_RESOURCES 6
50
51struct serial_private {
70db3d91 52 struct pci_dev *dev;
1da177e4
LT		 53 unsigned int nr;
54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
55 struct pci_serial_quirk *quirk;
56 int line[0];
57};
58
59static void moan_device(const char *str, struct pci_dev *dev)
60{
ad361c98
JP		 61 printk(KERN_WARNING
62 "%s: %s\n"
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
69}
70
71static int
70db3d91 72setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 73 int bar, int offset, int regshift)
74{
70db3d91 75 struct pci_dev *dev = priv->dev;
1da177e4
LT		 76 unsigned long base, len;
77
78 if (bar >= PCI_NUM_BAR_RESOURCES)
79 return -EINVAL;
80
72ce9a83
RK		 81 base = pci_resource_start(dev, bar);
82
1da177e4 83 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 84 len = pci_resource_len(dev, bar);
85
86 if (!priv->remapped_bar[bar])
6f441fe9 87 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 88 if (!priv->remapped_bar[bar])
89 return -ENOMEM;
90
91 port->iotype = UPIO_MEM;
72ce9a83 92 port->iobase = 0;
1da177e4
LT		 93 port->mapbase = base + offset;
94 port->membase = priv->remapped_bar[bar] + offset;
95 port->regshift = regshift;
96 } else {
1da177e4 97 port->iotype = UPIO_PORT;
72ce9a83
RK		 98 port->iobase = base + offset;
99 port->mapbase = 0;
100 port->membase = NULL;
101 port->regshift = 0;
1da177e4
LT		 102 }
103 return 0;
104}
105
02c9b5cf
KJ		 106/*
107 * ADDI-DATA GmbH communication cards <info@addi-data.com>
108 */
109static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 110 const struct pciserial_board *board,
02c9b5cf
KJ		 111 struct uart_port *port, int idx)
112{
113 unsigned int bar = 0, offset = board->first_offset;
114 bar = FL_GET_BASE(board->flags);
115
116 if (idx < 2) {
117 offset += idx * board->uart_offset;
118 } else if ((idx >= 2) && (idx < 4)) {
119 bar += 1;
120 offset += ((idx - 2) * board->uart_offset);
121 } else if ((idx >= 4) && (idx < 6)) {
122 bar += 2;
123 offset += ((idx - 4) * board->uart_offset);
124 } else if (idx >= 6) {
125 bar += 3;
126 offset += ((idx - 6) * board->uart_offset);
127 }
128
129 return setup_port(priv, port, bar, offset, board->reg_shift);
130}
131
1da177e4
LT		 132/*
133 * AFAVLAB uses a different mixture of BARs and offsets
134 * Not that ugly ;) -- HW
135 */
136static int
975a1a7d 137afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 138 struct uart_port *port, int idx)
139{
140 unsigned int bar, offset = board->first_offset;
5756ee99 141
1da177e4
LT		 142 bar = FL_GET_BASE(board->flags);
143 if (idx < 4)
144 bar += idx;
145 else {
146 bar = 4;
147 offset += (idx - 4) * board->uart_offset;
148 }
149
70db3d91 150 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 151}
152
153/*
154 * HP's Remote Management Console. The Diva chip came in several
155 * different versions. N-class, L2000 and A500 have two Diva chips, each
156 * with 3 UARTs (the third UART on the second chip is unused). Superdome
157 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
158 * one Diva chip, but it has been expanded to 5 UARTs.
159 */
61a116ef 160static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 161{
162 int rc = 0;
163
164 switch (dev->subsystem_device) {
165 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
166 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
167 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
168 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
169 rc = 3;
170 break;
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
172 rc = 2;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175 rc = 4;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 178 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 179 rc = 1;
180 break;
181 }
182
183 return rc;
184}
185
186/*
187 * HP's Diva chip puts the 4th/5th serial port further out, and
188 * some serial ports are supposed to be hidden on certain models.
189 */
190static int
975a1a7d
RK		 191pci_hp_diva_setup(struct serial_private *priv,
192 const struct pciserial_board *board,
193 struct uart_port *port, int idx)
1da177e4
LT		 194{
195 unsigned int offset = board->first_offset;
196 unsigned int bar = FL_GET_BASE(board->flags);
197
70db3d91 198 switch (priv->dev->subsystem_device) {
1da177e4
LT		 199 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
200 if (idx == 3)
201 idx++;
202 break;
203 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
204 if (idx > 0)
205 idx++;
206 if (idx > 2)
207 idx++;
208 break;
209 }
210 if (idx > 2)
211 offset = 0x18;
212
213 offset += idx * board->uart_offset;
214
70db3d91 215 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 216}
217
218/*
219 * Added for EKF Intel i960 serial boards
220 */
61a116ef 221static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 222{
223 unsigned long oldval;
224
225 if (!(dev->subsystem_device & 0x1000))
226 return -ENODEV;
227
228 /* is firmware started? */
5756ee99
AC		 229 pci_read_config_dword(dev, 0x44, (void *)&oldval);
230 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 231 printk(KERN_DEBUG "Local i960 firmware missing");
232 return -ENODEV;
233 }
234 return 0;
235}
236
237/*
238 * Some PCI serial cards using the PLX 9050 PCI interface chip require
239 * that the card interrupt be explicitly enabled or disabled. This
240 * seems to be mainly needed on card using the PLX which also use I/O
241 * mapped memory.
242 */
61a116ef 243static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 244{
245 u8 irq_config;
246 void __iomem *p;
247
248 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
249 moan_device("no memory in bar 0", dev);
250 return 0;
251 }
252
253 irq_config = 0x41;
add7b58e 254 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 255 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 256 irq_config = 0x43;
5756ee99 257
1da177e4 258 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 259 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 260 /*
261 * As the megawolf cards have the int pins active
262 * high, and have 2 UART chips, both ints must be
263 * enabled on the 9050. Also, the UARTS are set in
264 * 16450 mode by default, so we have to enable the
265 * 16C950 'enhanced' mode so that we can use the
266 * deep FIFOs
267 */
268 irq_config = 0x5b;
1da177e4
LT		 269 /*
270 * enable/disable interrupts
271 */
6f441fe9 272 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 273 if (p == NULL)
274 return -ENOMEM;
275 writel(irq_config, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282
283 return 0;
284}
285
286static void __devexit pci_plx9050_exit(struct pci_dev *dev)
287{
288 u8 __iomem *p;
289
290 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
291 return;
292
293 /*
294 * disable interrupts
295 */
6f441fe9 296 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 297 if (p != NULL) {
298 writel(0, p + 0x4c);
299
300 /*
301 * Read the register back to ensure that it took effect.
302 */
303 readl(p + 0x4c);
304 iounmap(p);
305 }
306}
307
04bf7e74
WP		 308#define NI8420_INT_ENABLE_REG 0x38
309#define NI8420_INT_ENABLE_BIT 0x2000
310
311static void __devexit pci_ni8420_exit(struct pci_dev *dev)
312{
313 void __iomem *p;
314 unsigned long base, len;
315 unsigned int bar = 0;
316
317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
318 moan_device("no memory in bar", dev);
319 return;
320 }
321
322 base = pci_resource_start(dev, bar);
323 len = pci_resource_len(dev, bar);
324 p = ioremap_nocache(base, len);
325 if (p == NULL)
326 return;
327
328 /* Disable the CPU Interrupt */
329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330 p + NI8420_INT_ENABLE_REG);
331 iounmap(p);
332}
333
334
46a0fac9
SB		 335/* MITE registers */
336#define MITE_IOWBSR1 0xc4
337#define MITE_IOWCR1 0xf4
338#define MITE_LCIMR1 0x08
339#define MITE_LCIMR2 0x10
340
341#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342
343static void __devexit pci_ni8430_exit(struct pci_dev *dev)
344{
345 void __iomem *p;
346 unsigned long base, len;
347 unsigned int bar = 0;
348
349 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
350 moan_device("no memory in bar", dev);
351 return;
352 }
353
354 base = pci_resource_start(dev, bar);
355 len = pci_resource_len(dev, bar);
356 p = ioremap_nocache(base, len);
357 if (p == NULL)
358 return;
359
360 /* Disable the CPU Interrupt */
361 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
362 iounmap(p);
363}
364
1da177e4
LT		 365/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
366static int
975a1a7d 367sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 368 struct uart_port *port, int idx)
369{
370 unsigned int bar, offset = board->first_offset;
371
372 bar = 0;
373
374 if (idx < 4) {
375 /* first four channels map to 0, 0x100, 0x200, 0x300 */
376 offset += idx * board->uart_offset;
377 } else if (idx < 8) {
378 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
379 offset += idx * board->uart_offset + 0xC00;
380 } else /* we have only 8 ports on PMC-OCTALPRO */
381 return 1;
382
70db3d91 383 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 384}
385
386/*
387* This does initialization for PMC OCTALPRO cards:
388* maps the device memory, resets the UARTs (needed, bc
389* if the module is removed and inserted again, the card
390* is in the sleep mode) and enables global interrupt.
391*/
392
393/* global control register offset for SBS PMC-OctalPro */
394#define OCT_REG_CR_OFF 0x500
395
61a116ef 396static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 397{
398 u8 __iomem *p;
399
24ed3aba 400 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 401
402 if (p == NULL)
403 return -ENOMEM;
404 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 405 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 406 udelay(50);
5756ee99 407 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 408
409 /* Set bit-2 (INTENABLE) of Control Register */
410 writeb(0x4, p + OCT_REG_CR_OFF);
411 iounmap(p);
412
413 return 0;
414}
415
416/*
417 * Disables the global interrupt of PMC-OctalPro
418 */
419
420static void __devexit sbs_exit(struct pci_dev *dev)
421{
422 u8 __iomem *p;
423
24ed3aba 424 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 425 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
426 if (p != NULL)
1da177e4 427 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 428 iounmap(p);
429}
430
431/*
432 * SIIG serial cards have an PCI interface chip which also controls
433 * the UART clocking frequency. Each UART can be clocked independently
25985edc 434 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 435 * are stored in the EEPROM chip. It can cause problems because this
436 * version of serial driver doesn't support differently clocked UART's
437 * on single PCI card. To prevent this, initialization functions set
438 * high frequency clocking for all UART's on given card. It is safe (I
439 * hope) because it doesn't touch EEPROM settings to prevent conflicts
440 * with other OSes (like M$ DOS).
441 *
442 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 443 *
1da177e4
LT		 444 * There is two family of SIIG serial cards with different PCI
445 * interface chip and different configuration methods:
446 * - 10x cards have control registers in IO and/or memory space;
447 * - 20x cards have control registers in standard PCI configuration space.
448 *
67d74b87
RK		 449 * Note: all 10x cards have PCI device ids 0x10..
450 * all 20x cards have PCI device ids 0x20..
451 *
fbc0dc0d
AP		 452 * There are also Quartet Serial cards which use Oxford Semiconductor
453 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
454 *
1da177e4
LT		 455 * Note: some SIIG cards are probed by the parport_serial object.
456 */
457
458#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
459#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
460
461static int pci_siig10x_init(struct pci_dev *dev)
462{
463 u16 data;
464 void __iomem *p;
465
466 switch (dev->device & 0xfff8) {
467 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
468 data = 0xffdf;
469 break;
470 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
471 data = 0xf7ff;
472 break;
473 default: /* 1S1P, 4S */
474 data = 0xfffb;
475 break;
476 }
477
6f441fe9 478 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 479 if (p == NULL)
480 return -ENOMEM;
481
482 writew(readw(p + 0x28) & data, p + 0x28);
483 readw(p + 0x28);
484 iounmap(p);
485 return 0;
486}
487
488#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
489#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
490
491static int pci_siig20x_init(struct pci_dev *dev)
492{
493 u8 data;
494
495 /* Change clock frequency for the first UART. */
496 pci_read_config_byte(dev, 0x6f, &data);
497 pci_write_config_byte(dev, 0x6f, data & 0xef);
498
499 /* If this card has 2 UART, we have to do the same with second UART. */
500 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
501 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
502 pci_read_config_byte(dev, 0x73, &data);
503 pci_write_config_byte(dev, 0x73, data & 0xef);
504 }
505 return 0;
506}
507
67d74b87
RK		 508static int pci_siig_init(struct pci_dev *dev)
509{
510 unsigned int type = dev->device & 0xff00;
511
512 if (type == 0x1000)
513 return pci_siig10x_init(dev);
514 else if (type == 0x2000)
515 return pci_siig20x_init(dev);
516
517 moan_device("Unknown SIIG card", dev);
518 return -ENODEV;
519}
520
3ec9c594 521static int pci_siig_setup(struct serial_private *priv,
975a1a7d 522 const struct pciserial_board *board,
3ec9c594
AP		 523 struct uart_port *port, int idx)
524{
525 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
526
527 if (idx > 3) {
528 bar = 4;
529 offset = (idx - 4) * 8;
530 }
531
532 return setup_port(priv, port, bar, offset, 0);
533}
534
1da177e4
LT		 535/*
536 * Timedia has an explosion of boards, and to avoid the PCI table from
537 * growing *huge*, we use this function to collapse some 70 entries
538 * in the PCI table into one, for sanity's and compactness's sake.
539 */
e9422e09 540static const unsigned short timedia_single_port[] = {
1da177e4
LT		 541 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
542};
543
e9422e09 544static const unsigned short timedia_dual_port[] = {
1da177e4 545 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 546 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
547 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 548 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
549 0xD079, 0
550};
551
e9422e09 552static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 553 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
554 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 555 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
556 0xB157, 0
557};
558
e9422e09 559static const unsigned short timedia_eight_port[] = {
5756ee99 560 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 561 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
562};
563
cb3592be 564static const struct timedia_struct {
1da177e4 565 int num;
e9422e09 566 const unsigned short *ids;
1da177e4
LT		 567} timedia_data[] = {
568 { 1, timedia_single_port },
569 { 2, timedia_dual_port },
570 { 4, timedia_quad_port },
e9422e09 571 { 8, timedia_eight_port }
1da177e4
LT		 572};
573
61a116ef 574static int pci_timedia_init(struct pci_dev *dev)
1da177e4 575{
e9422e09 576 const unsigned short *ids;
1da177e4
LT		 577 int i, j;
578
e9422e09 579 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 580 ids = timedia_data[i].ids;
581 for (j = 0; ids[j]; j++)
582 if (dev->subsystem_device == ids[j])
583 return timedia_data[i].num;
584 }
585 return 0;
586}
587
588/*
589 * Timedia/SUNIX uses a mixture of BARs and offsets
590 * Ugh, this is ugly as all hell --- TYT
591 */
592static int
975a1a7d
RK		 593pci_timedia_setup(struct serial_private *priv,
594 const struct pciserial_board *board,
1da177e4
LT		 595 struct uart_port *port, int idx)
596{
597 unsigned int bar = 0, offset = board->first_offset;
598
599 switch (idx) {
600 case 0:
601 bar = 0;
602 break;
603 case 1:
604 offset = board->uart_offset;
605 bar = 0;
606 break;
607 case 2:
608 bar = 1;
609 break;
610 case 3:
611 offset = board->uart_offset;
c2cd6d3c 612 /* FALLTHROUGH */
1da177e4
LT		 613 case 4: /* BAR 2 */
614 case 5: /* BAR 3 */
615 case 6: /* BAR 4 */
616 case 7: /* BAR 5 */
617 bar = idx - 2;
618 }
619
70db3d91 620 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 621}
622
623/*
624 * Some Titan cards are also a little weird
625 */
626static int
70db3d91 627titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 628 const struct pciserial_board *board,
1da177e4
LT		 629 struct uart_port *port, int idx)
630{
631 unsigned int bar, offset = board->first_offset;
632
633 switch (idx) {
634 case 0:
635 bar = 1;
636 break;
637 case 1:
638 bar = 2;
639 break;
640 default:
641 bar = 4;
642 offset = (idx - 2) * board->uart_offset;
643 }
644
70db3d91 645 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 646}
647
61a116ef 648static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 649{
650 msleep(100);
651 return 0;
652}
653
04bf7e74
WP		 654static int pci_ni8420_init(struct pci_dev *dev)
655{
656 void __iomem *p;
657 unsigned long base, len;
658 unsigned int bar = 0;
659
660 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
661 moan_device("no memory in bar", dev);
662 return 0;
663 }
664
665 base = pci_resource_start(dev, bar);
666 len = pci_resource_len(dev, bar);
667 p = ioremap_nocache(base, len);
668 if (p == NULL)
669 return -ENOMEM;
670
671 /* Enable CPU Interrupt */
672 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
673 p + NI8420_INT_ENABLE_REG);
674
675 iounmap(p);
676 return 0;
677}
678
46a0fac9
SB		 679#define MITE_IOWBSR1_WSIZE 0xa
680#define MITE_IOWBSR1_WIN_OFFSET 0x800
681#define MITE_IOWBSR1_WENAB (1 << 7)
682#define MITE_LCIMR1_IO_IE_0 (1 << 24)
683#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
684#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
685
686static int pci_ni8430_init(struct pci_dev *dev)
687{
688 void __iomem *p;
689 unsigned long base, len;
690 u32 device_window;
691 unsigned int bar = 0;
692
693 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
694 moan_device("no memory in bar", dev);
695 return 0;
696 }
697
698 base = pci_resource_start(dev, bar);
699 len = pci_resource_len(dev, bar);
700 p = ioremap_nocache(base, len);
701 if (p == NULL)
702 return -ENOMEM;
703
704 /* Set device window address and size in BAR0 */
705 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
706 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
707 writel(device_window, p + MITE_IOWBSR1);
708
709 /* Set window access to go to RAMSEL IO address space */
710 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
711 p + MITE_IOWCR1);
712
713 /* Enable IO Bus Interrupt 0 */
714 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
715
716 /* Enable CPU Interrupt */
717 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
718
719 iounmap(p);
720 return 0;
721}
722
723/* UART Port Control Register */
724#define NI8430_PORTCON 0x0f
725#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
726
727static int
bf538fe4
AC		 728pci_ni8430_setup(struct serial_private *priv,
729 const struct pciserial_board *board,
46a0fac9
SB		 730 struct uart_port *port, int idx)
731{
732 void __iomem *p;
733 unsigned long base, len;
734 unsigned int bar, offset = board->first_offset;
735
736 if (idx >= board->num_ports)
737 return 1;
738
739 bar = FL_GET_BASE(board->flags);
740 offset += idx * board->uart_offset;
741
742 base = pci_resource_start(priv->dev, bar);
743 len = pci_resource_len(priv->dev, bar);
744 p = ioremap_nocache(base, len);
745
746 /* enable the transciever */
747 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
748 p + offset + NI8430_PORTCON);
749
750 iounmap(p);
751
752 return setup_port(priv, port, bar, offset, board->reg_shift);
753}
754
755
61a116ef 756static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 757{
758 /* subdevice 0x00PS means <P> parallel, <S> serial */
759 unsigned int num_serial = dev->subsystem_device & 0xf;
760
ac6ec5b1
IS		 761 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
762 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 763 return 0;
25cf9bc1
JS		 764 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
765 dev->subsystem_device == 0x0299)
766 return 0;
767
1da177e4
LT		 768 if (num_serial == 0)
769 return -ENODEV;
770 return num_serial;
771}
772
84f8c6fc 773/*
84f8c6fc
NV		 774 * These chips are available with optionally one parallel port and up to
775 * two serial ports. Unfortunately they all have the same product id.
776 *
777 * Basic configuration is done over a region of 32 I/O ports. The base
778 * ioport is called INTA or INTC, depending on docs/other drivers.
779 *
780 * The region of the 32 I/O ports is configured in POSIO0R...
781 */
782
783/* registers */
784#define ITE_887x_MISCR 0x9c
785#define ITE_887x_INTCBAR 0x78
786#define ITE_887x_UARTBAR 0x7c
787#define ITE_887x_PS0BAR 0x10
788#define ITE_887x_POSIO0 0x60
789
790/* I/O space size */
791#define ITE_887x_IOSIZE 32
792/* I/O space size (bits 26-24; 8 bytes = 011b) */
793#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
794/* I/O space size (bits 26-24; 32 bytes = 101b) */
795#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
796/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
797#define ITE_887x_POSIO_SPEED (3 << 29)
798/* enable IO_Space bit */
799#define ITE_887x_POSIO_ENABLE (1 << 31)
800
f79abb82 801static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 802{
803 /* inta_addr are the configuration addresses of the ITE */
804 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
805 0x200, 0x280, 0 };
806 int ret, i, type;
807 struct resource *iobase = NULL;
808 u32 miscr, uartbar, ioport;
809
810 /* search for the base-ioport */
811 i = 0;
812 while (inta_addr[i] && iobase == NULL) {
813 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
814 "ite887x");
815 if (iobase != NULL) {
816 /* write POSIO0R - speed | size | ioport */
817 pci_write_config_dword(dev, ITE_887x_POSIO0,
818 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
819 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
820 /* write INTCBAR - ioport */
5756ee99
AC		 821 pci_write_config_dword(dev, ITE_887x_INTCBAR,
822 inta_addr[i]);
84f8c6fc
NV		 823 ret = inb(inta_addr[i]);
824 if (ret != 0xff) {
825 /* ioport connected */
826 break;
827 }
828 release_region(iobase->start, ITE_887x_IOSIZE);
829 iobase = NULL;
830 }
831 i++;
832 }
833
834 if (!inta_addr[i]) {
835 printk(KERN_ERR "ite887x: could not find iobase\n");
836 return -ENODEV;
837 }
838
839 /* start of undocumented type checking (see parport_pc.c) */
840 type = inb(iobase->start + 0x18) & 0x0f;
841
842 switch (type) {
843 case 0x2: /* ITE8871 (1P) */
844 case 0xa: /* ITE8875 (1P) */
845 ret = 0;
846 break;
847 case 0xe: /* ITE8872 (2S1P) */
848 ret = 2;
849 break;
850 case 0x6: /* ITE8873 (1S) */
851 ret = 1;
852 break;
853 case 0x8: /* ITE8874 (2S) */
854 ret = 2;
855 break;
856 default:
857 moan_device("Unknown ITE887x", dev);
858 ret = -ENODEV;
859 }
860
861 /* configure all serial ports */
862 for (i = 0; i < ret; i++) {
863 /* read the I/O port from the device */
864 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
865 &ioport);
866 ioport &= 0x0000FF00; /* the actual base address */
867 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
868 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
869 ITE_887x_POSIO_IOSIZE_8 | ioport);
870
871 /* write the ioport to the UARTBAR */
872 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
873 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
874 uartbar |= (ioport << (16 * i)); /* set the ioport */
875 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
876
877 /* get current config */
878 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
879 /* disable interrupts (UARTx_Routing[3:0]) */
880 miscr &= ~(0xf << (12 - 4 * i));
881 /* activate the UART (UARTx_En) */
882 miscr |= 1 << (23 - i);
883 /* write new config with activated UART */
884 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
885 }
886
887 if (ret <= 0) {
888 /* the device has no UARTs if we get here */
889 release_region(iobase->start, ITE_887x_IOSIZE);
890 }
891
892 return ret;
893}
894
895static void __devexit pci_ite887x_exit(struct pci_dev *dev)
896{
897 u32 ioport;
898 /* the ioport is bit 0-15 in POSIO0R */
899 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
900 ioport &= 0xffff;
901 release_region(ioport, ITE_887x_IOSIZE);
902}
903
9f2a036a
RK		 904/*
905 * Oxford Semiconductor Inc.
906 * Check that device is part of the Tornado range of devices, then determine
907 * the number of ports available on the device.
908 */
909static int pci_oxsemi_tornado_init(struct pci_dev *dev)
910{
911 u8 __iomem *p;
912 unsigned long deviceID;
913 unsigned int number_uarts = 0;
914
915 /* OxSemi Tornado devices are all 0xCxxx */
916 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
917 (dev->device & 0xF000) != 0xC000)
918 return 0;
919
920 p = pci_iomap(dev, 0, 5);
921 if (p == NULL)
922 return -ENOMEM;
923
924 deviceID = ioread32(p);
925 /* Tornado device */
926 if (deviceID == 0x07000200) {
927 number_uarts = ioread8(p + 4);
928 printk(KERN_DEBUG
929 "%d ports detected on Oxford PCI Express device\n",
930 number_uarts);
931 }
932 pci_iounmap(dev, p);
933 return number_uarts;
934}
935
1da177e4 936static int
975a1a7d
RK		 937pci_default_setup(struct serial_private *priv,
938 const struct pciserial_board *board,
1da177e4
LT		 939 struct uart_port *port, int idx)
940{
941 unsigned int bar, offset = board->first_offset, maxnr;
942
943 bar = FL_GET_BASE(board->flags);
944 if (board->flags & FL_BASE_BARS)
945 bar += idx;
946 else
947 offset += idx * board->uart_offset;
948
2427ddd8
GKH		 949 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
950 (board->reg_shift + 3);
1da177e4
LT		 951
952 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
953 return 1;
5756ee99 954
70db3d91 955 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 956}
957
095e24b0
DB		 958static int
959ce4100_serial_setup(struct serial_private *priv,
960 const struct pciserial_board *board,
961 struct uart_port *port, int idx)
962{
963 int ret;
964
965 ret = setup_port(priv, port, 0, 0, board->reg_shift);
966 port->iotype = UPIO_MEM32;
967 port->type = PORT_XSCALE;
968 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
969 port->regshift = 2;
970
971 return ret;
972}
973
b6adea33
MCC		 974static int skip_tx_en_setup(struct serial_private *priv,
975 const struct pciserial_board *board,
976 struct uart_port *port, int idx)
977{
978 port->flags |= UPF_NO_TXEN_TEST;
979 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
980 "[%04x:%04x] subsystem [%04x:%04x]\n",
981 priv->dev->vendor,
982 priv->dev->device,
983 priv->dev->subsystem_vendor,
984 priv->dev->subsystem_device);
985
986 return pci_default_setup(priv, board, port, idx);
987}
988
1da177e4
LT		 989/* This should be in linux/pci_ids.h */
990#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
991#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
992#define PCI_DEVICE_ID_OCTPRO 0x0001
993#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
994#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
995#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
996#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48 997#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 998#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 999#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1000#define PCI_DEVICE_ID_TITAN_200I 0x8028
1001#define PCI_DEVICE_ID_TITAN_400I 0x8048
1002#define PCI_DEVICE_ID_TITAN_800I 0x8088
1003#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1004#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1005#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1006#define PCI_DEVICE_ID_TITAN_100E 0xA010
1007#define PCI_DEVICE_ID_TITAN_200E 0xA012
1008#define PCI_DEVICE_ID_TITAN_400E 0xA013
1009#define PCI_DEVICE_ID_TITAN_800E 0xA014
1010#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1011#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
e847003f 1012#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1013#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1da177e4 1014
b76c5a07
CB		 1015/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1016#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1017
1da177e4
LT		 1018/*
1019 * Master list of serial port init/setup/exit quirks.
1020 * This does not describe the general nature of the port.
1021 * (ie, baud base, number and location of ports, etc)
1022 *
1023 * This list is ordered alphabetically by vendor then device.
1024 * Specific entries must come before more generic entries.
1025 */
7a63ce5a 1026static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1027 /*
1028 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1029 */
1030 {
1031 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1032 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1033 .subvendor = PCI_ANY_ID,
1034 .subdevice = PCI_ANY_ID,
1035 .setup = addidata_apci7800_setup,
1036 },
1da177e4 1037 /*
61a116ef 1038 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1039 * It is not clear whether this applies to all products.
1040 */
1041 {
1042 .vendor = PCI_VENDOR_ID_AFAVLAB,
1043 .device = PCI_ANY_ID,
1044 .subvendor = PCI_ANY_ID,
1045 .subdevice = PCI_ANY_ID,
1046 .setup = afavlab_setup,
1047 },
1048 /*
1049 * HP Diva
1050 */
1051 {
1052 .vendor = PCI_VENDOR_ID_HP,
1053 .device = PCI_DEVICE_ID_HP_DIVA,
1054 .subvendor = PCI_ANY_ID,
1055 .subdevice = PCI_ANY_ID,
1056 .init = pci_hp_diva_init,
1057 .setup = pci_hp_diva_setup,
1058 },
1059 /*
1060 * Intel
1061 */
1062 {
1063 .vendor = PCI_VENDOR_ID_INTEL,
1064 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1065 .subvendor = 0xe4bf,
1066 .subdevice = PCI_ANY_ID,
1067 .init = pci_inteli960ni_init,
1068 .setup = pci_default_setup,
1069 },
b6adea33
MCC		 1070 {
1071 .vendor = PCI_VENDOR_ID_INTEL,
1072 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1073 .subvendor = PCI_ANY_ID,
1074 .subdevice = PCI_ANY_ID,
1075 .setup = skip_tx_en_setup,
1076 },
1077 {
1078 .vendor = PCI_VENDOR_ID_INTEL,
1079 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .setup = skip_tx_en_setup,
1083 },
1084 {
1085 .vendor = PCI_VENDOR_ID_INTEL,
1086 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1087 .subvendor = PCI_ANY_ID,
1088 .subdevice = PCI_ANY_ID,
1089 .setup = skip_tx_en_setup,
1090 },
095e24b0
DB		 1091 {
1092 .vendor = PCI_VENDOR_ID_INTEL,
1093 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1094 .subvendor = PCI_ANY_ID,
1095 .subdevice = PCI_ANY_ID,
1096 .setup = ce4100_serial_setup,
1097 },
84f8c6fc
NV		 1098 /*
1099 * ITE
1100 */
1101 {
1102 .vendor = PCI_VENDOR_ID_ITE,
1103 .device = PCI_DEVICE_ID_ITE_8872,
1104 .subvendor = PCI_ANY_ID,
1105 .subdevice = PCI_ANY_ID,
1106 .init = pci_ite887x_init,
1107 .setup = pci_default_setup,
1108 .exit = __devexit_p(pci_ite887x_exit),
1109 },
46a0fac9
SB		 1110 /*
1111 * National Instruments
1112 */
04bf7e74
WP		 1113 {
1114 .vendor = PCI_VENDOR_ID_NI,
1115 .device = PCI_DEVICE_ID_NI_PCI23216,
1116 .subvendor = PCI_ANY_ID,
1117 .subdevice = PCI_ANY_ID,
1118 .init = pci_ni8420_init,
1119 .setup = pci_default_setup,
1120 .exit = __devexit_p(pci_ni8420_exit),
1121 },
1122 {
1123 .vendor = PCI_VENDOR_ID_NI,
1124 .device = PCI_DEVICE_ID_NI_PCI2328,
1125 .subvendor = PCI_ANY_ID,
1126 .subdevice = PCI_ANY_ID,
1127 .init = pci_ni8420_init,
1128 .setup = pci_default_setup,
1129 .exit = __devexit_p(pci_ni8420_exit),
1130 },
1131 {
1132 .vendor = PCI_VENDOR_ID_NI,
1133 .device = PCI_DEVICE_ID_NI_PCI2324,
1134 .subvendor = PCI_ANY_ID,
1135 .subdevice = PCI_ANY_ID,
1136 .init = pci_ni8420_init,
1137 .setup = pci_default_setup,
1138 .exit = __devexit_p(pci_ni8420_exit),
1139 },
1140 {
1141 .vendor = PCI_VENDOR_ID_NI,
1142 .device = PCI_DEVICE_ID_NI_PCI2322,
1143 .subvendor = PCI_ANY_ID,
1144 .subdevice = PCI_ANY_ID,
1145 .init = pci_ni8420_init,
1146 .setup = pci_default_setup,
1147 .exit = __devexit_p(pci_ni8420_exit),
1148 },
1149 {
1150 .vendor = PCI_VENDOR_ID_NI,
1151 .device = PCI_DEVICE_ID_NI_PCI2324I,
1152 .subvendor = PCI_ANY_ID,
1153 .subdevice = PCI_ANY_ID,
1154 .init = pci_ni8420_init,
1155 .setup = pci_default_setup,
1156 .exit = __devexit_p(pci_ni8420_exit),
1157 },
1158 {
1159 .vendor = PCI_VENDOR_ID_NI,
1160 .device = PCI_DEVICE_ID_NI_PCI2322I,
1161 .subvendor = PCI_ANY_ID,
1162 .subdevice = PCI_ANY_ID,
1163 .init = pci_ni8420_init,
1164 .setup = pci_default_setup,
1165 .exit = __devexit_p(pci_ni8420_exit),
1166 },
1167 {
1168 .vendor = PCI_VENDOR_ID_NI,
1169 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .init = pci_ni8420_init,
1173 .setup = pci_default_setup,
1174 .exit = __devexit_p(pci_ni8420_exit),
1175 },
1176 {
1177 .vendor = PCI_VENDOR_ID_NI,
1178 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1179 .subvendor = PCI_ANY_ID,
1180 .subdevice = PCI_ANY_ID,
1181 .init = pci_ni8420_init,
1182 .setup = pci_default_setup,
1183 .exit = __devexit_p(pci_ni8420_exit),
1184 },
1185 {
1186 .vendor = PCI_VENDOR_ID_NI,
1187 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1188 .subvendor = PCI_ANY_ID,
1189 .subdevice = PCI_ANY_ID,
1190 .init = pci_ni8420_init,
1191 .setup = pci_default_setup,
1192 .exit = __devexit_p(pci_ni8420_exit),
1193 },
1194 {
1195 .vendor = PCI_VENDOR_ID_NI,
1196 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1197 .subvendor = PCI_ANY_ID,
1198 .subdevice = PCI_ANY_ID,
1199 .init = pci_ni8420_init,
1200 .setup = pci_default_setup,
1201 .exit = __devexit_p(pci_ni8420_exit),
1202 },
1203 {
1204 .vendor = PCI_VENDOR_ID_NI,
1205 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1206 .subvendor = PCI_ANY_ID,
1207 .subdevice = PCI_ANY_ID,
1208 .init = pci_ni8420_init,
1209 .setup = pci_default_setup,
1210 .exit = __devexit_p(pci_ni8420_exit),
1211 },
1212 {
1213 .vendor = PCI_VENDOR_ID_NI,
1214 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1215 .subvendor = PCI_ANY_ID,
1216 .subdevice = PCI_ANY_ID,
1217 .init = pci_ni8420_init,
1218 .setup = pci_default_setup,
1219 .exit = __devexit_p(pci_ni8420_exit),
1220 },
46a0fac9
SB		 1221 {
1222 .vendor = PCI_VENDOR_ID_NI,
1223 .device = PCI_ANY_ID,
1224 .subvendor = PCI_ANY_ID,
1225 .subdevice = PCI_ANY_ID,
1226 .init = pci_ni8430_init,
1227 .setup = pci_ni8430_setup,
1228 .exit = __devexit_p(pci_ni8430_exit),
1229 },
1da177e4
LT		 1230 /*
1231 * Panacom
1232 */
1233 {
1234 .vendor = PCI_VENDOR_ID_PANACOM,
1235 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1236 .subvendor = PCI_ANY_ID,
1237 .subdevice = PCI_ANY_ID,
1238 .init = pci_plx9050_init,
1239 .setup = pci_default_setup,
1240 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1241 },
1da177e4
LT		 1242 {
1243 .vendor = PCI_VENDOR_ID_PANACOM,
1244 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1245 .subvendor = PCI_ANY_ID,
1246 .subdevice = PCI_ANY_ID,
1247 .init = pci_plx9050_init,
1248 .setup = pci_default_setup,
1249 .exit = __devexit_p(pci_plx9050_exit),
1250 },
1251 /*
1252 * PLX
1253 */
48212008
TH		 1254 {
1255 .vendor = PCI_VENDOR_ID_PLX,
1256 .device = PCI_DEVICE_ID_PLX_9030,
1257 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1258 .subdevice = PCI_ANY_ID,
1259 .setup = pci_default_setup,
1260 },
add7b58e
BH		 1261 {
1262 .vendor = PCI_VENDOR_ID_PLX,
1263 .device = PCI_DEVICE_ID_PLX_9050,
1264 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1265 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1266 .init = pci_plx9050_init,
1267 .setup = pci_default_setup,
1268 .exit = __devexit_p(pci_plx9050_exit),
1269 },
1da177e4
LT		 1270 {
1271 .vendor = PCI_VENDOR_ID_PLX,
1272 .device = PCI_DEVICE_ID_PLX_9050,
1273 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1274 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1275 .init = pci_plx9050_init,
1276 .setup = pci_default_setup,
1277 .exit = __devexit_p(pci_plx9050_exit),
1278 },
b76c5a07
CB		 1279 {
1280 .vendor = PCI_VENDOR_ID_PLX,
1281 .device = PCI_DEVICE_ID_PLX_9050,
1282 .subvendor = PCI_VENDOR_ID_PLX,
1283 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1284 .init = pci_plx9050_init,
1285 .setup = pci_default_setup,
1286 .exit = __devexit_p(pci_plx9050_exit),
1287 },
1da177e4
LT		 1288 {
1289 .vendor = PCI_VENDOR_ID_PLX,
1290 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1291 .subvendor = PCI_VENDOR_ID_PLX,
1292 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1293 .init = pci_plx9050_init,
1294 .setup = pci_default_setup,
1295 .exit = __devexit_p(pci_plx9050_exit),
1296 },
1297 /*
1298 * SBS Technologies, Inc., PMC-OCTALPRO 232
1299 */
1300 {
1301 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1302 .device = PCI_DEVICE_ID_OCTPRO,
1303 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1304 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1305 .init = sbs_init,
1306 .setup = sbs_setup,
1307 .exit = __devexit_p(sbs_exit),
1308 },
1309 /*
1310 * SBS Technologies, Inc., PMC-OCTALPRO 422
1311 */
1312 {
1313 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1314 .device = PCI_DEVICE_ID_OCTPRO,
1315 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1316 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1317 .init = sbs_init,
1318 .setup = sbs_setup,
1319 .exit = __devexit_p(sbs_exit),
1320 },
1321 /*
1322 * SBS Technologies, Inc., P-Octal 232
1323 */
1324 {
1325 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1326 .device = PCI_DEVICE_ID_OCTPRO,
1327 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1328 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1329 .init = sbs_init,
1330 .setup = sbs_setup,
1331 .exit = __devexit_p(sbs_exit),
1332 },
1333 /*
1334 * SBS Technologies, Inc., P-Octal 422
1335 */
1336 {
1337 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1338 .device = PCI_DEVICE_ID_OCTPRO,
1339 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1340 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1341 .init = sbs_init,
1342 .setup = sbs_setup,
1343 .exit = __devexit_p(sbs_exit),
1344 },
1da177e4 1345 /*
61a116ef 1346 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1347 */
1348 {
1349 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1350 .device = PCI_ANY_ID,
1da177e4
LT		 1351 .subvendor = PCI_ANY_ID,
1352 .subdevice = PCI_ANY_ID,
67d74b87 1353 .init = pci_siig_init,
3ec9c594 1354 .setup = pci_siig_setup,
1da177e4
LT		 1355 },
1356 /*
1357 * Titan cards
1358 */
1359 {
1360 .vendor = PCI_VENDOR_ID_TITAN,
1361 .device = PCI_DEVICE_ID_TITAN_400L,
1362 .subvendor = PCI_ANY_ID,
1363 .subdevice = PCI_ANY_ID,
1364 .setup = titan_400l_800l_setup,
1365 },
1366 {
1367 .vendor = PCI_VENDOR_ID_TITAN,
1368 .device = PCI_DEVICE_ID_TITAN_800L,
1369 .subvendor = PCI_ANY_ID,
1370 .subdevice = PCI_ANY_ID,
1371 .setup = titan_400l_800l_setup,
1372 },
1373 /*
1374 * Timedia cards
1375 */
1376 {
1377 .vendor = PCI_VENDOR_ID_TIMEDIA,
1378 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1379 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1380 .subdevice = PCI_ANY_ID,
1381 .init = pci_timedia_init,
1382 .setup = pci_timedia_setup,
1383 },
1384 {
1385 .vendor = PCI_VENDOR_ID_TIMEDIA,
1386 .device = PCI_ANY_ID,
1387 .subvendor = PCI_ANY_ID,
1388 .subdevice = PCI_ANY_ID,
1389 .setup = pci_timedia_setup,
1390 },
1391 /*
1392 * Xircom cards
1393 */
1394 {
1395 .vendor = PCI_VENDOR_ID_XIRCOM,
1396 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1397 .subvendor = PCI_ANY_ID,
1398 .subdevice = PCI_ANY_ID,
1399 .init = pci_xircom_init,
1400 .setup = pci_default_setup,
1401 },
1402 /*
61a116ef 1403 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1404 */
1405 {
1406 .vendor = PCI_VENDOR_ID_NETMOS,
1407 .device = PCI_ANY_ID,
1408 .subvendor = PCI_ANY_ID,
1409 .subdevice = PCI_ANY_ID,
1410 .init = pci_netmos_init,
1411 .setup = pci_default_setup,
1412 },
9f2a036a 1413 /*
aa273ae5 1414 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 1415 */
1416 {
1417 .vendor = PCI_VENDOR_ID_OXSEMI,
1418 .device = PCI_ANY_ID,
1419 .subvendor = PCI_ANY_ID,
1420 .subdevice = PCI_ANY_ID,
1421 .init = pci_oxsemi_tornado_init,
1422 .setup = pci_default_setup,
1423 },
1424 {
1425 .vendor = PCI_VENDOR_ID_MAINPINE,
1426 .device = PCI_ANY_ID,
1427 .subvendor = PCI_ANY_ID,
1428 .subdevice = PCI_ANY_ID,
1429 .init = pci_oxsemi_tornado_init,
1430 .setup = pci_default_setup,
1431 },
aa273ae5
SK		 1432 {
1433 .vendor = PCI_VENDOR_ID_DIGI,
1434 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1435 .subvendor = PCI_SUBVENDOR_ID_IBM,
1436 .subdevice = PCI_ANY_ID,
1437 .init = pci_oxsemi_tornado_init,
1438 .setup = pci_default_setup,
1439 },
1da177e4
LT		 1440 /*
1441 * Default "match everything" terminator entry
1442 */
1443 {
1444 .vendor = PCI_ANY_ID,
1445 .device = PCI_ANY_ID,
1446 .subvendor = PCI_ANY_ID,
1447 .subdevice = PCI_ANY_ID,
1448 .setup = pci_default_setup,
1449 }
1450};
1451
1452static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1453{
1454 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1455}
1456
1457static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1458{
1459 struct pci_serial_quirk *quirk;
1460
1461 for (quirk = pci_serial_quirks; ; quirk++)
1462 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1463 quirk_id_matches(quirk->device, dev->device) &&
1464 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1465 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1466 break;
1da177e4
LT		 1467 return quirk;
1468}
1469
dd68e88c 1470static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1471 const struct pciserial_board *board)
1da177e4
LT		 1472{
1473 if (board->flags & FL_NOIRQ)
1474 return 0;
1475 else
1476 return dev->irq;
1477}
1478
1479/*
1480 * This is the configuration table for all of the PCI serial boards
1481 * which we support. It is directly indexed by the pci_board_num_t enum
1482 * value, which is encoded in the pci_device_id PCI probe table's
1483 * driver_data member.
1484 *
1485 * The makeup of these names are:
26e92861 1486 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1487 *
26e92861
GH		 1488 * bn = PCI BAR number
1489 * bt = Index using PCI BARs
1490 * n = number of serial ports
1491 * baud = baud rate
1492 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1493 *
26e92861 1494 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1495 *
1da177e4
LT		 1496 * Please note: in theory if n = 1, _bt infix should make no difference.
1497 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1498 */
1499enum pci_board_num_t {
1500 pbn_default = 0,
1501
1502 pbn_b0_1_115200,
1503 pbn_b0_2_115200,
1504 pbn_b0_4_115200,
1505 pbn_b0_5_115200,
bf0df636 1506 pbn_b0_8_115200,
1da177e4
LT		 1507
1508 pbn_b0_1_921600,
1509 pbn_b0_2_921600,
1510 pbn_b0_4_921600,
1511
db1de159
DR		 1512 pbn_b0_2_1130000,
1513
fbc0dc0d
AP		 1514 pbn_b0_4_1152000,
1515
26e92861
GH		 1516 pbn_b0_2_1843200,
1517 pbn_b0_4_1843200,
1518
1519 pbn_b0_2_1843200_200,
1520 pbn_b0_4_1843200_200,
1521 pbn_b0_8_1843200_200,
1522
7106b4e3
LH		 1523 pbn_b0_1_4000000,
1524
1da177e4
LT		 1525 pbn_b0_bt_1_115200,
1526 pbn_b0_bt_2_115200,
ac6ec5b1 1527 pbn_b0_bt_4_115200,
1da177e4
LT		 1528 pbn_b0_bt_8_115200,
1529
1530 pbn_b0_bt_1_460800,
1531 pbn_b0_bt_2_460800,
1532 pbn_b0_bt_4_460800,
1533
1534 pbn_b0_bt_1_921600,
1535 pbn_b0_bt_2_921600,
1536 pbn_b0_bt_4_921600,
1537 pbn_b0_bt_8_921600,
1538
1539 pbn_b1_1_115200,
1540 pbn_b1_2_115200,
1541 pbn_b1_4_115200,
1542 pbn_b1_8_115200,
04bf7e74 1543 pbn_b1_16_115200,
1da177e4
LT		 1544
1545 pbn_b1_1_921600,
1546 pbn_b1_2_921600,
1547 pbn_b1_4_921600,
1548 pbn_b1_8_921600,
1549
26e92861
GH		 1550 pbn_b1_2_1250000,
1551
84f8c6fc 1552 pbn_b1_bt_1_115200,
04bf7e74
WP		 1553 pbn_b1_bt_2_115200,
1554 pbn_b1_bt_4_115200,
1555
1da177e4
LT		 1556 pbn_b1_bt_2_921600,
1557
1558 pbn_b1_1_1382400,
1559 pbn_b1_2_1382400,
1560 pbn_b1_4_1382400,
1561 pbn_b1_8_1382400,
1562
1563 pbn_b2_1_115200,
737c1756 1564 pbn_b2_2_115200,
a9cccd34 1565 pbn_b2_4_115200,
1da177e4
LT		 1566 pbn_b2_8_115200,
1567
1568 pbn_b2_1_460800,
1569 pbn_b2_4_460800,
1570 pbn_b2_8_460800,
1571 pbn_b2_16_460800,
1572
1573 pbn_b2_1_921600,
1574 pbn_b2_4_921600,
1575 pbn_b2_8_921600,
1576
e847003f
LB		 1577 pbn_b2_8_1152000,
1578
1da177e4
LT		 1579 pbn_b2_bt_1_115200,
1580 pbn_b2_bt_2_115200,
1581 pbn_b2_bt_4_115200,
1582
1583 pbn_b2_bt_2_921600,
1584 pbn_b2_bt_4_921600,
1585
d9004eb4 1586 pbn_b3_2_115200,
1da177e4
LT		 1587 pbn_b3_4_115200,
1588 pbn_b3_8_115200,
1589
66169ad1
YY		 1590 pbn_b4_bt_2_921600,
1591 pbn_b4_bt_4_921600,
1592 pbn_b4_bt_8_921600,
1593
1da177e4
LT		 1594 /*
1595 * Board-specific versions.
1596 */
1597 pbn_panacom,
1598 pbn_panacom2,
1599 pbn_panacom4,
add7b58e 1600 pbn_exsys_4055,
1da177e4
LT		 1601 pbn_plx_romulus,
1602 pbn_oxsemi,
7106b4e3
LH		 1603 pbn_oxsemi_1_4000000,
1604 pbn_oxsemi_2_4000000,
1605 pbn_oxsemi_4_4000000,
1606 pbn_oxsemi_8_4000000,
1da177e4
LT		 1607 pbn_intel_i960,
1608 pbn_sgi_ioc3,
1da177e4
LT		 1609 pbn_computone_4,
1610 pbn_computone_6,
1611 pbn_computone_8,
1612 pbn_sbsxrsio,
1613 pbn_exar_XR17C152,
1614 pbn_exar_XR17C154,
1615 pbn_exar_XR17C158,
c68d2b15 1616 pbn_exar_ibm_saturn,
aa798505 1617 pbn_pasemi_1682M,
46a0fac9
SB		 1618 pbn_ni8430_2,
1619 pbn_ni8430_4,
1620 pbn_ni8430_8,
1621 pbn_ni8430_16,
1b62cbf2
KJ		 1622 pbn_ADDIDATA_PCIe_1_3906250,
1623 pbn_ADDIDATA_PCIe_2_3906250,
1624 pbn_ADDIDATA_PCIe_4_3906250,
1625 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 1626 pbn_ce4100_1_115200,
1da177e4
LT		 1627};
1628
1629/*
1630 * uart_offset - the space between channels
1631 * reg_shift - describes how the UART registers are mapped
1632 * to PCI memory by the card.
1633 * For example IER register on SBS, Inc. PMC-OctPro is located at
1634 * offset 0x10 from the UART base, while UART_IER is defined as 1
1635 * in include/linux/serial_reg.h,
1636 * see first lines of serial_in() and serial_out() in 8250.c
1637*/
1638
1c7c1fe5 1639static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1640 [pbn_default] = {
1641 .flags = FL_BASE0,
1642 .num_ports = 1,
1643 .base_baud = 115200,
1644 .uart_offset = 8,
1645 },
1646 [pbn_b0_1_115200] = {
1647 .flags = FL_BASE0,
1648 .num_ports = 1,
1649 .base_baud = 115200,
1650 .uart_offset = 8,
1651 },
1652 [pbn_b0_2_115200] = {
1653 .flags = FL_BASE0,
1654 .num_ports = 2,
1655 .base_baud = 115200,
1656 .uart_offset = 8,
1657 },
1658 [pbn_b0_4_115200] = {
1659 .flags = FL_BASE0,
1660 .num_ports = 4,
1661 .base_baud = 115200,
1662 .uart_offset = 8,
1663 },
1664 [pbn_b0_5_115200] = {
1665 .flags = FL_BASE0,
1666 .num_ports = 5,
1667 .base_baud = 115200,
1668 .uart_offset = 8,
1669 },
bf0df636
AC		 1670 [pbn_b0_8_115200] = {
1671 .flags = FL_BASE0,
1672 .num_ports = 8,
1673 .base_baud = 115200,
1674 .uart_offset = 8,
1675 },
1da177e4
LT		 1676 [pbn_b0_1_921600] = {
1677 .flags = FL_BASE0,
1678 .num_ports = 1,
1679 .base_baud = 921600,
1680 .uart_offset = 8,
1681 },
1682 [pbn_b0_2_921600] = {
1683 .flags = FL_BASE0,
1684 .num_ports = 2,
1685 .base_baud = 921600,
1686 .uart_offset = 8,
1687 },
1688 [pbn_b0_4_921600] = {
1689 .flags = FL_BASE0,
1690 .num_ports = 4,
1691 .base_baud = 921600,
1692 .uart_offset = 8,
1693 },
db1de159
DR		 1694
1695 [pbn_b0_2_1130000] = {
1696 .flags = FL_BASE0,
1697 .num_ports = 2,
1698 .base_baud = 1130000,
1699 .uart_offset = 8,
1700 },
1701
fbc0dc0d
AP		 1702 [pbn_b0_4_1152000] = {
1703 .flags = FL_BASE0,
1704 .num_ports = 4,
1705 .base_baud = 1152000,
1706 .uart_offset = 8,
1707 },
1da177e4 1708
26e92861
GH		 1709 [pbn_b0_2_1843200] = {
1710 .flags = FL_BASE0,
1711 .num_ports = 2,
1712 .base_baud = 1843200,
1713 .uart_offset = 8,
1714 },
1715 [pbn_b0_4_1843200] = {
1716 .flags = FL_BASE0,
1717 .num_ports = 4,
1718 .base_baud = 1843200,
1719 .uart_offset = 8,
1720 },
1721
1722 [pbn_b0_2_1843200_200] = {
1723 .flags = FL_BASE0,
1724 .num_ports = 2,
1725 .base_baud = 1843200,
1726 .uart_offset = 0x200,
1727 },
1728 [pbn_b0_4_1843200_200] = {
1729 .flags = FL_BASE0,
1730 .num_ports = 4,
1731 .base_baud = 1843200,
1732 .uart_offset = 0x200,
1733 },
1734 [pbn_b0_8_1843200_200] = {
1735 .flags = FL_BASE0,
1736 .num_ports = 8,
1737 .base_baud = 1843200,
1738 .uart_offset = 0x200,
1739 },
7106b4e3
LH		 1740 [pbn_b0_1_4000000] = {
1741 .flags = FL_BASE0,
1742 .num_ports = 1,
1743 .base_baud = 4000000,
1744 .uart_offset = 8,
1745 },
26e92861 1746
1da177e4
LT		 1747 [pbn_b0_bt_1_115200] = {
1748 .flags = FL_BASE0|FL_BASE_BARS,
1749 .num_ports = 1,
1750 .base_baud = 115200,
1751 .uart_offset = 8,
1752 },
1753 [pbn_b0_bt_2_115200] = {
1754 .flags = FL_BASE0|FL_BASE_BARS,
1755 .num_ports = 2,
1756 .base_baud = 115200,
1757 .uart_offset = 8,
1758 },
ac6ec5b1
IS		 1759 [pbn_b0_bt_4_115200] = {
1760 .flags = FL_BASE0|FL_BASE_BARS,
1761 .num_ports = 4,
1762 .base_baud = 115200,
1763 .uart_offset = 8,
1764 },
1da177e4
LT		 1765 [pbn_b0_bt_8_115200] = {
1766 .flags = FL_BASE0|FL_BASE_BARS,
1767 .num_ports = 8,
1768 .base_baud = 115200,
1769 .uart_offset = 8,
1770 },
1771
1772 [pbn_b0_bt_1_460800] = {
1773 .flags = FL_BASE0|FL_BASE_BARS,
1774 .num_ports = 1,
1775 .base_baud = 460800,
1776 .uart_offset = 8,
1777 },
1778 [pbn_b0_bt_2_460800] = {
1779 .flags = FL_BASE0|FL_BASE_BARS,
1780 .num_ports = 2,
1781 .base_baud = 460800,
1782 .uart_offset = 8,
1783 },
1784 [pbn_b0_bt_4_460800] = {
1785 .flags = FL_BASE0|FL_BASE_BARS,
1786 .num_ports = 4,
1787 .base_baud = 460800,
1788 .uart_offset = 8,
1789 },
1790
1791 [pbn_b0_bt_1_921600] = {
1792 .flags = FL_BASE0|FL_BASE_BARS,
1793 .num_ports = 1,
1794 .base_baud = 921600,
1795 .uart_offset = 8,
1796 },
1797 [pbn_b0_bt_2_921600] = {
1798 .flags = FL_BASE0|FL_BASE_BARS,
1799 .num_ports = 2,
1800 .base_baud = 921600,
1801 .uart_offset = 8,
1802 },
1803 [pbn_b0_bt_4_921600] = {
1804 .flags = FL_BASE0|FL_BASE_BARS,
1805 .num_ports = 4,
1806 .base_baud = 921600,
1807 .uart_offset = 8,
1808 },
1809 [pbn_b0_bt_8_921600] = {
1810 .flags = FL_BASE0|FL_BASE_BARS,
1811 .num_ports = 8,
1812 .base_baud = 921600,
1813 .uart_offset = 8,
1814 },
1815
1816 [pbn_b1_1_115200] = {
1817 .flags = FL_BASE1,
1818 .num_ports = 1,
1819 .base_baud = 115200,
1820 .uart_offset = 8,
1821 },
1822 [pbn_b1_2_115200] = {
1823 .flags = FL_BASE1,
1824 .num_ports = 2,
1825 .base_baud = 115200,
1826 .uart_offset = 8,
1827 },
1828 [pbn_b1_4_115200] = {
1829 .flags = FL_BASE1,
1830 .num_ports = 4,
1831 .base_baud = 115200,
1832 .uart_offset = 8,
1833 },
1834 [pbn_b1_8_115200] = {
1835 .flags = FL_BASE1,
1836 .num_ports = 8,
1837 .base_baud = 115200,
1838 .uart_offset = 8,
1839 },
04bf7e74
WP		 1840 [pbn_b1_16_115200] = {
1841 .flags = FL_BASE1,
1842 .num_ports = 16,
1843 .base_baud = 115200,
1844 .uart_offset = 8,
1845 },
1da177e4
LT		 1846
1847 [pbn_b1_1_921600] = {
1848 .flags = FL_BASE1,
1849 .num_ports = 1,
1850 .base_baud = 921600,
1851 .uart_offset = 8,
1852 },
1853 [pbn_b1_2_921600] = {
1854 .flags = FL_BASE1,
1855 .num_ports = 2,
1856 .base_baud = 921600,
1857 .uart_offset = 8,
1858 },
1859 [pbn_b1_4_921600] = {
1860 .flags = FL_BASE1,
1861 .num_ports = 4,
1862 .base_baud = 921600,
1863 .uart_offset = 8,
1864 },
1865 [pbn_b1_8_921600] = {
1866 .flags = FL_BASE1,
1867 .num_ports = 8,
1868 .base_baud = 921600,
1869 .uart_offset = 8,
1870 },
26e92861
GH		 1871 [pbn_b1_2_1250000] = {
1872 .flags = FL_BASE1,
1873 .num_ports = 2,
1874 .base_baud = 1250000,
1875 .uart_offset = 8,
1876 },
1da177e4 1877
84f8c6fc
NV		 1878 [pbn_b1_bt_1_115200] = {
1879 .flags = FL_BASE1|FL_BASE_BARS,
1880 .num_ports = 1,
1881 .base_baud = 115200,
1882 .uart_offset = 8,
1883 },
04bf7e74
WP		 1884 [pbn_b1_bt_2_115200] = {
1885 .flags = FL_BASE1|FL_BASE_BARS,
1886 .num_ports = 2,
1887 .base_baud = 115200,
1888 .uart_offset = 8,
1889 },
1890 [pbn_b1_bt_4_115200] = {
1891 .flags = FL_BASE1|FL_BASE_BARS,
1892 .num_ports = 4,
1893 .base_baud = 115200,
1894 .uart_offset = 8,
1895 },
84f8c6fc 1896
1da177e4
LT		 1897 [pbn_b1_bt_2_921600] = {
1898 .flags = FL_BASE1|FL_BASE_BARS,
1899 .num_ports = 2,
1900 .base_baud = 921600,
1901 .uart_offset = 8,
1902 },
1903
1904 [pbn_b1_1_1382400] = {
1905 .flags = FL_BASE1,
1906 .num_ports = 1,
1907 .base_baud = 1382400,
1908 .uart_offset = 8,
1909 },
1910 [pbn_b1_2_1382400] = {
1911 .flags = FL_BASE1,
1912 .num_ports = 2,
1913 .base_baud = 1382400,
1914 .uart_offset = 8,
1915 },
1916 [pbn_b1_4_1382400] = {
1917 .flags = FL_BASE1,
1918 .num_ports = 4,
1919 .base_baud = 1382400,
1920 .uart_offset = 8,
1921 },
1922 [pbn_b1_8_1382400] = {
1923 .flags = FL_BASE1,
1924 .num_ports = 8,
1925 .base_baud = 1382400,
1926 .uart_offset = 8,
1927 },
1928
1929 [pbn_b2_1_115200] = {
1930 .flags = FL_BASE2,
1931 .num_ports = 1,
1932 .base_baud = 115200,
1933 .uart_offset = 8,
1934 },
737c1756
PH		 1935 [pbn_b2_2_115200] = {
1936 .flags = FL_BASE2,
1937 .num_ports = 2,
1938 .base_baud = 115200,
1939 .uart_offset = 8,
1940 },
a9cccd34
MF		 1941 [pbn_b2_4_115200] = {
1942 .flags = FL_BASE2,
1943 .num_ports = 4,
1944 .base_baud = 115200,
1945 .uart_offset = 8,
1946 },
1da177e4
LT		 1947 [pbn_b2_8_115200] = {
1948 .flags = FL_BASE2,
1949 .num_ports = 8,
1950 .base_baud = 115200,
1951 .uart_offset = 8,
1952 },
1953
1954 [pbn_b2_1_460800] = {
1955 .flags = FL_BASE2,
1956 .num_ports = 1,
1957 .base_baud = 460800,
1958 .uart_offset = 8,
1959 },
1960 [pbn_b2_4_460800] = {
1961 .flags = FL_BASE2,
1962 .num_ports = 4,
1963 .base_baud = 460800,
1964 .uart_offset = 8,
1965 },
1966 [pbn_b2_8_460800] = {
1967 .flags = FL_BASE2,
1968 .num_ports = 8,
1969 .base_baud = 460800,
1970 .uart_offset = 8,
1971 },
1972 [pbn_b2_16_460800] = {
1973 .flags = FL_BASE2,
1974 .num_ports = 16,
1975 .base_baud = 460800,
1976 .uart_offset = 8,
1977 },
1978
1979 [pbn_b2_1_921600] = {
1980 .flags = FL_BASE2,
1981 .num_ports = 1,
1982 .base_baud = 921600,
1983 .uart_offset = 8,
1984 },
1985 [pbn_b2_4_921600] = {
1986 .flags = FL_BASE2,
1987 .num_ports = 4,
1988 .base_baud = 921600,
1989 .uart_offset = 8,
1990 },
1991 [pbn_b2_8_921600] = {
1992 .flags = FL_BASE2,
1993 .num_ports = 8,
1994 .base_baud = 921600,
1995 .uart_offset = 8,
1996 },
1997
e847003f
LB		 1998 [pbn_b2_8_1152000] = {
1999 .flags = FL_BASE2,
2000 .num_ports = 8,
2001 .base_baud = 1152000,
2002 .uart_offset = 8,
2003 },
2004
1da177e4
LT		 2005 [pbn_b2_bt_1_115200] = {
2006 .flags = FL_BASE2|FL_BASE_BARS,
2007 .num_ports = 1,
2008 .base_baud = 115200,
2009 .uart_offset = 8,
2010 },
2011 [pbn_b2_bt_2_115200] = {
2012 .flags = FL_BASE2|FL_BASE_BARS,
2013 .num_ports = 2,
2014 .base_baud = 115200,
2015 .uart_offset = 8,
2016 },
2017 [pbn_b2_bt_4_115200] = {
2018 .flags = FL_BASE2|FL_BASE_BARS,
2019 .num_ports = 4,
2020 .base_baud = 115200,
2021 .uart_offset = 8,
2022 },
2023
2024 [pbn_b2_bt_2_921600] = {
2025 .flags = FL_BASE2|FL_BASE_BARS,
2026 .num_ports = 2,
2027 .base_baud = 921600,
2028 .uart_offset = 8,
2029 },
2030 [pbn_b2_bt_4_921600] = {
2031 .flags = FL_BASE2|FL_BASE_BARS,
2032 .num_ports = 4,
2033 .base_baud = 921600,
2034 .uart_offset = 8,
2035 },
2036
d9004eb4
ABL		 2037 [pbn_b3_2_115200] = {
2038 .flags = FL_BASE3,
2039 .num_ports = 2,
2040 .base_baud = 115200,
2041 .uart_offset = 8,
2042 },
1da177e4
LT		 2043 [pbn_b3_4_115200] = {
2044 .flags = FL_BASE3,
2045 .num_ports = 4,
2046 .base_baud = 115200,
2047 .uart_offset = 8,
2048 },
2049 [pbn_b3_8_115200] = {
2050 .flags = FL_BASE3,
2051 .num_ports = 8,
2052 .base_baud = 115200,
2053 .uart_offset = 8,
2054 },
2055
66169ad1
YY		 2056 [pbn_b4_bt_2_921600] = {
2057 .flags = FL_BASE4,
2058 .num_ports = 2,
2059 .base_baud = 921600,
2060 .uart_offset = 8,
2061 },
2062 [pbn_b4_bt_4_921600] = {
2063 .flags = FL_BASE4,
2064 .num_ports = 4,
2065 .base_baud = 921600,
2066 .uart_offset = 8,
2067 },
2068 [pbn_b4_bt_8_921600] = {
2069 .flags = FL_BASE4,
2070 .num_ports = 8,
2071 .base_baud = 921600,
2072 .uart_offset = 8,
2073 },
2074
1da177e4
LT		 2075 /*
2076 * Entries following this are board-specific.
2077 */
2078
2079 /*
2080 * Panacom - IOMEM
2081 */
2082 [pbn_panacom] = {
2083 .flags = FL_BASE2,
2084 .num_ports = 2,
2085 .base_baud = 921600,
2086 .uart_offset = 0x400,
2087 .reg_shift = 7,
2088 },
2089 [pbn_panacom2] = {
2090 .flags = FL_BASE2|FL_BASE_BARS,
2091 .num_ports = 2,
2092 .base_baud = 921600,
2093 .uart_offset = 0x400,
2094 .reg_shift = 7,
2095 },
2096 [pbn_panacom4] = {
2097 .flags = FL_BASE2|FL_BASE_BARS,
2098 .num_ports = 4,
2099 .base_baud = 921600,
2100 .uart_offset = 0x400,
2101 .reg_shift = 7,
2102 },
2103
add7b58e
BH		 2104 [pbn_exsys_4055] = {
2105 .flags = FL_BASE2,
2106 .num_ports = 4,
2107 .base_baud = 115200,
2108 .uart_offset = 8,
2109 },
2110
1da177e4
LT		 2111 /* I think this entry is broken - the first_offset looks wrong --rmk */
2112 [pbn_plx_romulus] = {
2113 .flags = FL_BASE2,
2114 .num_ports = 4,
2115 .base_baud = 921600,
2116 .uart_offset = 8 << 2,
2117 .reg_shift = 2,
2118 .first_offset = 0x03,
2119 },
2120
2121 /*
2122 * This board uses the size of PCI Base region 0 to
2123 * signal now many ports are available
2124 */
2125 [pbn_oxsemi] = {
2126 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2127 .num_ports = 32,
2128 .base_baud = 115200,
2129 .uart_offset = 8,
2130 },
7106b4e3
LH		 2131 [pbn_oxsemi_1_4000000] = {
2132 .flags = FL_BASE0,
2133 .num_ports = 1,
2134 .base_baud = 4000000,
2135 .uart_offset = 0x200,
2136 .first_offset = 0x1000,
2137 },
2138 [pbn_oxsemi_2_4000000] = {
2139 .flags = FL_BASE0,
2140 .num_ports = 2,
2141 .base_baud = 4000000,
2142 .uart_offset = 0x200,
2143 .first_offset = 0x1000,
2144 },
2145 [pbn_oxsemi_4_4000000] = {
2146 .flags = FL_BASE0,
2147 .num_ports = 4,
2148 .base_baud = 4000000,
2149 .uart_offset = 0x200,
2150 .first_offset = 0x1000,
2151 },
2152 [pbn_oxsemi_8_4000000] = {
2153 .flags = FL_BASE0,
2154 .num_ports = 8,
2155 .base_baud = 4000000,
2156 .uart_offset = 0x200,
2157 .first_offset = 0x1000,
2158 },
2159
1da177e4
LT		 2160
2161 /*
2162 * EKF addition for i960 Boards form EKF with serial port.
2163 * Max 256 ports.
2164 */
2165 [pbn_intel_i960] = {
2166 .flags = FL_BASE0,
2167 .num_ports = 32,
2168 .base_baud = 921600,
2169 .uart_offset = 8 << 2,
2170 .reg_shift = 2,
2171 .first_offset = 0x10000,
2172 },
2173 [pbn_sgi_ioc3] = {
2174 .flags = FL_BASE0|FL_NOIRQ,
2175 .num_ports = 1,
2176 .base_baud = 458333,
2177 .uart_offset = 8,
2178 .reg_shift = 0,
2179 .first_offset = 0x20178,
2180 },
2181
1da177e4
LT		 2182 /*
2183 * Computone - uses IOMEM.
2184 */
2185 [pbn_computone_4] = {
2186 .flags = FL_BASE0,
2187 .num_ports = 4,
2188 .base_baud = 921600,
2189 .uart_offset = 0x40,
2190 .reg_shift = 2,
2191 .first_offset = 0x200,
2192 },
2193 [pbn_computone_6] = {
2194 .flags = FL_BASE0,
2195 .num_ports = 6,
2196 .base_baud = 921600,
2197 .uart_offset = 0x40,
2198 .reg_shift = 2,
2199 .first_offset = 0x200,
2200 },
2201 [pbn_computone_8] = {
2202 .flags = FL_BASE0,
2203 .num_ports = 8,
2204 .base_baud = 921600,
2205 .uart_offset = 0x40,
2206 .reg_shift = 2,
2207 .first_offset = 0x200,
2208 },
2209 [pbn_sbsxrsio] = {
2210 .flags = FL_BASE0,
2211 .num_ports = 8,
2212 .base_baud = 460800,
2213 .uart_offset = 256,
2214 .reg_shift = 4,
2215 },
2216 /*
2217 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2218 * Only basic 16550A support.
2219 * XR17C15[24] are not tested, but they should work.
2220 */
2221 [pbn_exar_XR17C152] = {
2222 .flags = FL_BASE0,
2223 .num_ports = 2,
2224 .base_baud = 921600,
2225 .uart_offset = 0x200,
2226 },
2227 [pbn_exar_XR17C154] = {
2228 .flags = FL_BASE0,
2229 .num_ports = 4,
2230 .base_baud = 921600,
2231 .uart_offset = 0x200,
2232 },
2233 [pbn_exar_XR17C158] = {
2234 .flags = FL_BASE0,
2235 .num_ports = 8,
2236 .base_baud = 921600,
2237 .uart_offset = 0x200,
2238 },
c68d2b15
BH		 2239 [pbn_exar_ibm_saturn] = {
2240 .flags = FL_BASE0,
2241 .num_ports = 1,
2242 .base_baud = 921600,
2243 .uart_offset = 0x200,
2244 },
2245
aa798505
OJ		 2246 /*
2247 * PA Semi PWRficient PA6T-1682M on-chip UART
2248 */
2249 [pbn_pasemi_1682M] = {
2250 .flags = FL_BASE0,
2251 .num_ports = 1,
2252 .base_baud = 8333333,
2253 },
46a0fac9
SB		 2254 /*
2255 * National Instruments 843x
2256 */
2257 [pbn_ni8430_16] = {
2258 .flags = FL_BASE0,
2259 .num_ports = 16,
2260 .base_baud = 3686400,
2261 .uart_offset = 0x10,
2262 .first_offset = 0x800,
2263 },
2264 [pbn_ni8430_8] = {
2265 .flags = FL_BASE0,
2266 .num_ports = 8,
2267 .base_baud = 3686400,
2268 .uart_offset = 0x10,
2269 .first_offset = 0x800,
2270 },
2271 [pbn_ni8430_4] = {
2272 .flags = FL_BASE0,
2273 .num_ports = 4,
2274 .base_baud = 3686400,
2275 .uart_offset = 0x10,
2276 .first_offset = 0x800,
2277 },
2278 [pbn_ni8430_2] = {
2279 .flags = FL_BASE0,
2280 .num_ports = 2,
2281 .base_baud = 3686400,
2282 .uart_offset = 0x10,
2283 .first_offset = 0x800,
2284 },
1b62cbf2
KJ		 2285 /*
2286 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2287 */
2288 [pbn_ADDIDATA_PCIe_1_3906250] = {
2289 .flags = FL_BASE0,
2290 .num_ports = 1,
2291 .base_baud = 3906250,
2292 .uart_offset = 0x200,
2293 .first_offset = 0x1000,
2294 },
2295 [pbn_ADDIDATA_PCIe_2_3906250] = {
2296 .flags = FL_BASE0,
2297 .num_ports = 2,
2298 .base_baud = 3906250,
2299 .uart_offset = 0x200,
2300 .first_offset = 0x1000,
2301 },
2302 [pbn_ADDIDATA_PCIe_4_3906250] = {
2303 .flags = FL_BASE0,
2304 .num_ports = 4,
2305 .base_baud = 3906250,
2306 .uart_offset = 0x200,
2307 .first_offset = 0x1000,
2308 },
2309 [pbn_ADDIDATA_PCIe_8_3906250] = {
2310 .flags = FL_BASE0,
2311 .num_ports = 8,
2312 .base_baud = 3906250,
2313 .uart_offset = 0x200,
2314 .first_offset = 0x1000,
2315 },
095e24b0
DB		 2316 [pbn_ce4100_1_115200] = {
2317 .flags = FL_BASE0,
2318 .num_ports = 1,
2319 .base_baud = 921600,
2320 .reg_shift = 2,
2321 },
1da177e4
LT		 2322};
2323
436bbd43 2324static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2325 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 2326 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2327 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
436bbd43
CS		 2328};
2329
1da177e4
LT		 2330/*
2331 * Given a complete unknown PCI device, try to use some heuristics to
2332 * guess what the configuration might be, based on the pitiful PCI
2333 * serial specs. Returns 0 on success, 1 on failure.
2334 */
2335static int __devinit
1c7c1fe5 2336serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2337{
436bbd43 2338 const struct pci_device_id *blacklist;
1da177e4 2339 int num_iomem, num_port, first_port = -1, i;
5756ee99 2340
1da177e4
LT		 2341 /*
2342 * If it is not a communications device or the programming
2343 * interface is greater than 6, give up.
2344 *
2345 * (Should we try to make guesses for multiport serial devices
5756ee99 2346 * later?)
1da177e4
LT		 2347 */
2348 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2349 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2350 (dev->class & 0xff) > 6)
2351 return -ENODEV;
2352
436bbd43
CS		 2353 /*
2354 * Do not access blacklisted devices that are known not to
2355 * feature serial ports.
2356 */
2357 for (blacklist = softmodem_blacklist;
2358 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2359 blacklist++) {
2360 if (dev->vendor == blacklist->vendor &&
2361 dev->device == blacklist->device)
2362 return -ENODEV;
2363 }
2364
1da177e4
LT		 2365 num_iomem = num_port = 0;
2366 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2367 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2368 num_port++;
2369 if (first_port == -1)
2370 first_port = i;
2371 }
2372 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2373 num_iomem++;
2374 }
2375
2376 /*
2377 * If there is 1 or 0 iomem regions, and exactly one port,
2378 * use it. We guess the number of ports based on the IO
2379 * region size.
2380 */
2381 if (num_iomem <= 1 && num_port == 1) {
2382 board->flags = first_port;
2383 board->num_ports = pci_resource_len(dev, first_port) / 8;
2384 return 0;
2385 }
2386
2387 /*
2388 * Now guess if we've got a board which indexes by BARs.
2389 * Each IO BAR should be 8 bytes, and they should follow
2390 * consecutively.
2391 */
2392 first_port = -1;
2393 num_port = 0;
2394 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2395 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2396 pci_resource_len(dev, i) == 8 &&
2397 (first_port == -1 || (first_port + num_port) == i)) {
2398 num_port++;
2399 if (first_port == -1)
2400 first_port = i;
2401 }
2402 }
2403
2404 if (num_port > 1) {
2405 board->flags = first_port | FL_BASE_BARS;
2406 board->num_ports = num_port;
2407 return 0;
2408 }
2409
2410 return -ENODEV;
2411}
2412
2413static inline int
975a1a7d
RK		 2414serial_pci_matches(const struct pciserial_board *board,
2415 const struct pciserial_board *guessed)
1da177e4
LT		 2416{
2417 return
2418 board->num_ports == guessed->num_ports &&
2419 board->base_baud == guessed->base_baud &&
2420 board->uart_offset == guessed->uart_offset &&
2421 board->reg_shift == guessed->reg_shift &&
2422 board->first_offset == guessed->first_offset;
2423}
2424
241fc436 2425struct serial_private *
975a1a7d 2426pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2427{
72ce9a83 2428 struct uart_port serial_port;
1da177e4 2429 struct serial_private *priv;
1da177e4
LT		 2430 struct pci_serial_quirk *quirk;
2431 int rc, nr_ports, i;
2432
1da177e4
LT		 2433 nr_ports = board->num_ports;
2434
2435 /*
2436 * Find an init and setup quirks.
2437 */
2438 quirk = find_quirk(dev);
2439
2440 /*
2441 * Run the new-style initialization function.
2442 * The initialization function returns:
2443 * <0 - error
2444 * 0 - use board->num_ports
2445 * >0 - number of ports
2446 */
2447 if (quirk->init) {
2448 rc = quirk->init(dev);
241fc436
RK		 2449 if (rc < 0) {
2450 priv = ERR_PTR(rc);
2451 goto err_out;
2452 }
1da177e4
LT		 2453 if (rc)
2454 nr_ports = rc;
2455 }
2456
8f31bb39 2457 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2458 sizeof(unsigned int) * nr_ports,
2459 GFP_KERNEL);
2460 if (!priv) {
241fc436
RK		 2461 priv = ERR_PTR(-ENOMEM);
2462 goto err_deinit;
1da177e4
LT		 2463 }
2464
70db3d91 2465 priv->dev = dev;
1da177e4 2466 priv->quirk = quirk;
1da177e4 2467
72ce9a83
RK		 2468 memset(&serial_port, 0, sizeof(struct uart_port));
2469 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2470 serial_port.uartclk = board->base_baud * 16;
2471 serial_port.irq = get_pci_irq(dev, board);
2472 serial_port.dev = &dev->dev;
2473
1da177e4 2474 for (i = 0; i < nr_ports; i++) {
70db3d91 2475 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 2476 break;
72ce9a83 2477
1da177e4 2478#ifdef SERIAL_DEBUG_PCI
80647b95 2479 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
1da177e4
LT		 2480 serial_port.iobase, serial_port.irq, serial_port.iotype);
2481#endif
5756ee99 2482
1da177e4
LT		 2483 priv->line[i] = serial8250_register_port(&serial_port);
2484 if (priv->line[i] < 0) {
2485 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2486 break;
2487 }
2488 }
1da177e4 2489 priv->nr = i;
241fc436 2490 return priv;
1da177e4 2491
5756ee99 2492err_deinit:
1da177e4
LT		 2493 if (quirk->exit)
2494 quirk->exit(dev);
5756ee99 2495err_out:
241fc436 2496 return priv;
1da177e4 2497}
241fc436 2498EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2499
241fc436 2500void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2501{
056a8763
RK		 2502 struct pci_serial_quirk *quirk;
2503 int i;
1da177e4 2504
056a8763
RK		 2505 for (i = 0; i < priv->nr; i++)
2506 serial8250_unregister_port(priv->line[i]);
1da177e4 2507
056a8763
RK		 2508 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2509 if (priv->remapped_bar[i])
2510 iounmap(priv->remapped_bar[i]);
2511 priv->remapped_bar[i] = NULL;
2512 }
1da177e4 2513
056a8763
RK		 2514 /*
2515 * Find the exit quirks.
2516 */
241fc436 2517 quirk = find_quirk(priv->dev);
056a8763 2518 if (quirk->exit)
241fc436
RK		 2519 quirk->exit(priv->dev);
2520
2521 kfree(priv);
2522}
2523EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2524
2525void pciserial_suspend_ports(struct serial_private *priv)
2526{
2527 int i;
2528
2529 for (i = 0; i < priv->nr; i++)
2530 if (priv->line[i] >= 0)
2531 serial8250_suspend_port(priv->line[i]);
2532}
2533EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2534
2535void pciserial_resume_ports(struct serial_private *priv)
2536{
2537 int i;
2538
2539 /*
2540 * Ensure that the board is correctly configured.
2541 */
2542 if (priv->quirk->init)
2543 priv->quirk->init(priv->dev);
2544
2545 for (i = 0; i < priv->nr; i++)
2546 if (priv->line[i] >= 0)
2547 serial8250_resume_port(priv->line[i]);
2548}
2549EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2550
2551/*
2552 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2553 * to the arrangement of serial ports on a PCI card.
2554 */
2555static int __devinit
2556pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2557{
2558 struct serial_private *priv;
975a1a7d
RK		 2559 const struct pciserial_board *board;
2560 struct pciserial_board tmp;
241fc436
RK		 2561 int rc;
2562
2563 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2564 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2565 ent->driver_data);
2566 return -EINVAL;
2567 }
2568
2569 board = &pci_boards[ent->driver_data];
2570
2571 rc = pci_enable_device(dev);
2572 if (rc)
2573 return rc;
2574
2575 if (ent->driver_data == pbn_default) {
2576 /*
2577 * Use a copy of the pci_board entry for this;
2578 * avoid changing entries in the table.
2579 */
2580 memcpy(&tmp, board, sizeof(struct pciserial_board));
2581 board = &tmp;
2582
2583 /*
2584 * We matched one of our class entries. Try to
2585 * determine the parameters of this board.
2586 */
975a1a7d 2587 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2588 if (rc)
2589 goto disable;
2590 } else {
2591 /*
2592 * We matched an explicit entry. If we are able to
2593 * detect this boards settings with our heuristic,
2594 * then we no longer need this entry.
2595 */
2596 memcpy(&tmp, &pci_boards[pbn_default],
2597 sizeof(struct pciserial_board));
2598 rc = serial_pci_guess_board(dev, &tmp);
2599 if (rc == 0 && serial_pci_matches(board, &tmp))
2600 moan_device("Redundant entry in serial pci_table.",
2601 dev);
2602 }
2603
2604 priv = pciserial_init_ports(dev, board);
2605 if (!IS_ERR(priv)) {
2606 pci_set_drvdata(dev, priv);
2607 return 0;
2608 }
2609
2610 rc = PTR_ERR(priv);
1da177e4 2611
241fc436 2612 disable:
056a8763 2613 pci_disable_device(dev);
241fc436
RK		 2614 return rc;
2615}
1da177e4 2616
241fc436
RK		 2617static void __devexit pciserial_remove_one(struct pci_dev *dev)
2618{
2619 struct serial_private *priv = pci_get_drvdata(dev);
2620
2621 pci_set_drvdata(dev, NULL);
2622
2623 pciserial_remove_ports(priv);
2624
2625 pci_disable_device(dev);
1da177e4
LT		 2626}
2627
1d5e7996 2628#ifdef CONFIG_PM
1da177e4
LT		 2629static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2630{
2631 struct serial_private *priv = pci_get_drvdata(dev);
2632
241fc436
RK		 2633 if (priv)
2634 pciserial_suspend_ports(priv);
1da177e4 2635
1da177e4
LT		 2636 pci_save_state(dev);
2637 pci_set_power_state(dev, pci_choose_state(dev, state));
2638 return 0;
2639}
2640
2641static int pciserial_resume_one(struct pci_dev *dev)
2642{
ccb9d59e 2643 int err;
1da177e4
LT		 2644 struct serial_private *priv = pci_get_drvdata(dev);
2645
2646 pci_set_power_state(dev, PCI_D0);
2647 pci_restore_state(dev);
2648
2649 if (priv) {
1da177e4
LT		 2650 /*
2651 * The device may have been disabled. Re-enable it.
2652 */
ccb9d59e 2653 err = pci_enable_device(dev);
40836c48 2654 /* FIXME: We cannot simply error out here */
ccb9d59e 2655 if (err)
40836c48 2656 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2657 pciserial_resume_ports(priv);
1da177e4
LT		 2658 }
2659 return 0;
2660}
1d5e7996 2661#endif
1da177e4
LT		 2662
2663static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2664 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2665 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2666 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2667 pbn_b2_8_921600 },
1da177e4
LT		 2668 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2669 PCI_SUBVENDOR_ID_CONNECT_TECH,
2670 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2671 pbn_b1_8_1382400 },
2672 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2673 PCI_SUBVENDOR_ID_CONNECT_TECH,
2674 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2675 pbn_b1_4_1382400 },
2676 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2677 PCI_SUBVENDOR_ID_CONNECT_TECH,
2678 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2679 pbn_b1_2_1382400 },
2680 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2681 PCI_SUBVENDOR_ID_CONNECT_TECH,
2682 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2683 pbn_b1_8_1382400 },
2684 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2685 PCI_SUBVENDOR_ID_CONNECT_TECH,
2686 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2687 pbn_b1_4_1382400 },
2688 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2689 PCI_SUBVENDOR_ID_CONNECT_TECH,
2690 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2691 pbn_b1_2_1382400 },
2692 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2693 PCI_SUBVENDOR_ID_CONNECT_TECH,
2694 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2695 pbn_b1_8_921600 },
2696 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2697 PCI_SUBVENDOR_ID_CONNECT_TECH,
2698 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2699 pbn_b1_8_921600 },
2700 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2701 PCI_SUBVENDOR_ID_CONNECT_TECH,
2702 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2703 pbn_b1_4_921600 },
2704 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2705 PCI_SUBVENDOR_ID_CONNECT_TECH,
2706 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2707 pbn_b1_4_921600 },
2708 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2709 PCI_SUBVENDOR_ID_CONNECT_TECH,
2710 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2711 pbn_b1_2_921600 },
2712 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2713 PCI_SUBVENDOR_ID_CONNECT_TECH,
2714 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2715 pbn_b1_8_921600 },
2716 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2717 PCI_SUBVENDOR_ID_CONNECT_TECH,
2718 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2719 pbn_b1_8_921600 },
2720 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2721 PCI_SUBVENDOR_ID_CONNECT_TECH,
2722 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2723 pbn_b1_4_921600 },
26e92861
GH		 2724 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2725 PCI_SUBVENDOR_ID_CONNECT_TECH,
2726 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2727 pbn_b1_2_1250000 },
2728 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2729 PCI_SUBVENDOR_ID_CONNECT_TECH,
2730 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2731 pbn_b0_2_1843200 },
2732 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2733 PCI_SUBVENDOR_ID_CONNECT_TECH,
2734 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2735 pbn_b0_4_1843200 },
85d1494e
YY		 2736 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2737 PCI_VENDOR_ID_AFAVLAB,
2738 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2739 pbn_b0_4_1152000 },
26e92861
GH		 2740 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2741 PCI_SUBVENDOR_ID_CONNECT_TECH,
2742 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2743 pbn_b0_2_1843200_200 },
2744 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2745 PCI_SUBVENDOR_ID_CONNECT_TECH,
2746 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2747 pbn_b0_4_1843200_200 },
2748 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2749 PCI_SUBVENDOR_ID_CONNECT_TECH,
2750 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2751 pbn_b0_8_1843200_200 },
2752 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2753 PCI_SUBVENDOR_ID_CONNECT_TECH,
2754 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2755 pbn_b0_2_1843200_200 },
2756 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2757 PCI_SUBVENDOR_ID_CONNECT_TECH,
2758 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2759 pbn_b0_4_1843200_200 },
2760 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2761 PCI_SUBVENDOR_ID_CONNECT_TECH,
2762 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2763 pbn_b0_8_1843200_200 },
2764 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2765 PCI_SUBVENDOR_ID_CONNECT_TECH,
2766 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2767 pbn_b0_2_1843200_200 },
2768 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2769 PCI_SUBVENDOR_ID_CONNECT_TECH,
2770 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2771 pbn_b0_4_1843200_200 },
2772 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2773 PCI_SUBVENDOR_ID_CONNECT_TECH,
2774 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2775 pbn_b0_8_1843200_200 },
2776 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2777 PCI_SUBVENDOR_ID_CONNECT_TECH,
2778 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2779 pbn_b0_2_1843200_200 },
2780 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2781 PCI_SUBVENDOR_ID_CONNECT_TECH,
2782 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2783 pbn_b0_4_1843200_200 },
2784 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2785 PCI_SUBVENDOR_ID_CONNECT_TECH,
2786 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2787 pbn_b0_8_1843200_200 },
c68d2b15
BH		 2788 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2789 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2790 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 2791
2792 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2794 pbn_b2_bt_1_115200 },
2795 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 2796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2797 pbn_b2_bt_2_115200 },
2798 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2800 pbn_b2_bt_4_115200 },
2801 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 2802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2803 pbn_b2_bt_2_115200 },
2804 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2806 pbn_b2_bt_4_115200 },
2807 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 2808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2809 pbn_b2_8_115200 },
e65f0f82
FL		 2810 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2812 pbn_b2_8_460800 },
1da177e4
LT		 2813 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2815 pbn_b2_8_115200 },
2816
2817 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2819 pbn_b2_bt_2_115200 },
2820 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2822 pbn_b2_bt_2_921600 },
2823 /*
2824 * VScom SPCOM800, from sl@s.pl
2825 */
5756ee99
AC		 2826 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2828 pbn_b2_8_921600 },
2829 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 2830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2831 pbn_b2_4_921600 },
b76c5a07
CB		 2832 /* Unknown card - subdevice 0x1584 */
2833 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2834 PCI_VENDOR_ID_PLX,
2835 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2836 pbn_b0_4_115200 },
1da177e4
LT		 2837 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2838 PCI_SUBVENDOR_ID_KEYSPAN,
2839 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2840 pbn_panacom },
2841 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2843 pbn_panacom4 },
2844 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2846 pbn_panacom2 },
a9cccd34
MF		 2847 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2848 PCI_VENDOR_ID_ESDGMBH,
2849 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2850 pbn_b2_4_115200 },
1da177e4
LT		 2851 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2852 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2853 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 2854 pbn_b2_4_460800 },
2855 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2856 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2857 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 2858 pbn_b2_8_460800 },
2859 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2860 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2861 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 2862 pbn_b2_16_460800 },
2863 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2864 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2865 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 2866 pbn_b2_16_460800 },
2867 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2868 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2869 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 2870 pbn_b2_4_460800 },
2871 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2872 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2873 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 2874 pbn_b2_8_460800 },
add7b58e
BH		 2875 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2876 PCI_SUBVENDOR_ID_EXSYS,
2877 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2878 pbn_exsys_4055 },
1da177e4
LT		 2879 /*
2880 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2881 * (Exoray@isys.ca)
2882 */
2883 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2884 0x10b5, 0x106a, 0, 0,
2885 pbn_plx_romulus },
2886 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2888 pbn_b1_4_115200 },
2889 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2891 pbn_b1_2_115200 },
2892 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2894 pbn_b1_8_115200 },
2895 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897 pbn_b1_8_115200 },
2898 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2899 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2900 0, 0,
1da177e4 2901 pbn_b0_4_921600 },
fbc0dc0d 2902 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2903 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2904 0, 0,
fbc0dc0d 2905 pbn_b0_4_1152000 },
c9bd9d01
MP		 2906 { PCI_VENDOR_ID_OXSEMI, 0x9505,
2907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2908 pbn_b0_bt_2_921600 },
db1de159
DR		 2909
2910 /*
2911 * The below card is a little controversial since it is the
2912 * subject of a PCI vendor/device ID clash. (See
2913 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2914 * For now just used the hex ID 0x950a.
2915 */
39aced68
NV		 2916 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2917 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2918 pbn_b0_2_115200 },
db1de159
DR		 2919 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2921 pbn_b0_2_1130000 },
70fd8fde
AP		 2922 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2923 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2924 pbn_b0_1_921600 },
1da177e4
LT		 2925 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2927 pbn_b0_4_115200 },
2928 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2930 pbn_b0_bt_2_921600 },
e847003f
LB		 2931 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
2932 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
2933 pbn_b2_8_1152000 },
1da177e4 2934
7106b4e3
LH		 2935 /*
2936 * Oxford Semiconductor Inc. Tornado PCI express device range.
2937 */
2938 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2940 pbn_b0_1_4000000 },
2941 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2943 pbn_b0_1_4000000 },
2944 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2946 pbn_oxsemi_1_4000000 },
2947 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2949 pbn_oxsemi_1_4000000 },
2950 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2952 pbn_b0_1_4000000 },
2953 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2955 pbn_b0_1_4000000 },
2956 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2958 pbn_oxsemi_1_4000000 },
2959 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2961 pbn_oxsemi_1_4000000 },
2962 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2964 pbn_b0_1_4000000 },
2965 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2967 pbn_b0_1_4000000 },
2968 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2970 pbn_b0_1_4000000 },
2971 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2973 pbn_b0_1_4000000 },
2974 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2976 pbn_oxsemi_2_4000000 },
2977 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2979 pbn_oxsemi_2_4000000 },
2980 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2982 pbn_oxsemi_4_4000000 },
2983 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2985 pbn_oxsemi_4_4000000 },
2986 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2988 pbn_oxsemi_8_4000000 },
2989 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2991 pbn_oxsemi_8_4000000 },
2992 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2994 pbn_oxsemi_1_4000000 },
2995 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2997 pbn_oxsemi_1_4000000 },
2998 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3000 pbn_oxsemi_1_4000000 },
3001 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3003 pbn_oxsemi_1_4000000 },
3004 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3006 pbn_oxsemi_1_4000000 },
3007 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3009 pbn_oxsemi_1_4000000 },
3010 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3012 pbn_oxsemi_1_4000000 },
3013 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3015 pbn_oxsemi_1_4000000 },
3016 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3018 pbn_oxsemi_1_4000000 },
3019 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3021 pbn_oxsemi_1_4000000 },
3022 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3024 pbn_oxsemi_1_4000000 },
3025 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3027 pbn_oxsemi_1_4000000 },
3028 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3030 pbn_oxsemi_1_4000000 },
3031 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3033 pbn_oxsemi_1_4000000 },
3034 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3036 pbn_oxsemi_1_4000000 },
3037 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3039 pbn_oxsemi_1_4000000 },
3040 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3042 pbn_oxsemi_1_4000000 },
3043 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3045 pbn_oxsemi_1_4000000 },
3046 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3048 pbn_oxsemi_1_4000000 },
3049 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3051 pbn_oxsemi_1_4000000 },
3052 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3054 pbn_oxsemi_1_4000000 },
3055 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3057 pbn_oxsemi_1_4000000 },
3058 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3060 pbn_oxsemi_1_4000000 },
3061 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3063 pbn_oxsemi_1_4000000 },
3064 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3066 pbn_oxsemi_1_4000000 },
3067 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3069 pbn_oxsemi_1_4000000 },
b80de369
LH		 3070 /*
3071 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3072 */
3073 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3074 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3075 pbn_oxsemi_1_4000000 },
3076 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3077 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3078 pbn_oxsemi_2_4000000 },
3079 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3080 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3081 pbn_oxsemi_4_4000000 },
3082 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3083 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3084 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 3085
3086 /*
3087 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3088 */
3089 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3090 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3091 pbn_oxsemi_2_4000000 },
3092
1da177e4
LT		 3093 /*
3094 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3095 * from skokodyn@yahoo.com
3096 */
3097 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3098 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3099 pbn_sbsxrsio },
3100 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3101 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3102 pbn_sbsxrsio },
3103 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3104 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3105 pbn_sbsxrsio },
3106 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3107 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3108 pbn_sbsxrsio },
3109
3110 /*
3111 * Digitan DS560-558, from jimd@esoft.com
3112 */
3113 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 3114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3115 pbn_b1_1_115200 },
3116
3117 /*
3118 * Titan Electronic cards
3119 * The 400L and 800L have a custom setup quirk.
3120 */
3121 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 3122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3123 pbn_b0_1_921600 },
3124 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 3125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3126 pbn_b0_2_921600 },
3127 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 3128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3129 pbn_b0_4_921600 },
3130 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 3131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3132 pbn_b0_4_921600 },
3133 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3135 pbn_b1_1_921600 },
3136 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3138 pbn_b1_bt_2_921600 },
3139 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3141 pbn_b0_bt_4_921600 },
3142 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3144 pbn_b0_bt_8_921600 },
66169ad1
YY		 3145 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3147 pbn_b4_bt_2_921600 },
3148 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3150 pbn_b4_bt_4_921600 },
3151 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3153 pbn_b4_bt_8_921600 },
3154 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3156 pbn_b0_4_921600 },
3157 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 pbn_b0_4_921600 },
3160 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3162 pbn_b0_4_921600 },
3163 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3165 pbn_oxsemi_1_4000000 },
3166 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3168 pbn_oxsemi_2_4000000 },
3169 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3171 pbn_oxsemi_4_4000000 },
3172 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3174 pbn_oxsemi_8_4000000 },
3175 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3177 pbn_oxsemi_2_4000000 },
3178 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3180 pbn_oxsemi_2_4000000 },
1da177e4
LT		 3181
3182 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3184 pbn_b2_1_460800 },
3185 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3187 pbn_b2_1_460800 },
3188 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3190 pbn_b2_1_460800 },
3191 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3193 pbn_b2_bt_2_921600 },
3194 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3196 pbn_b2_bt_2_921600 },
3197 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3199 pbn_b2_bt_2_921600 },
3200 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3202 pbn_b2_bt_4_921600 },
3203 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3205 pbn_b2_bt_4_921600 },
3206 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 pbn_b2_bt_4_921600 },
3209 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211 pbn_b0_1_921600 },
3212 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214 pbn_b0_1_921600 },
3215 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217 pbn_b0_1_921600 },
3218 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220 pbn_b0_bt_2_921600 },
3221 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223 pbn_b0_bt_2_921600 },
3224 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3226 pbn_b0_bt_2_921600 },
3227 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3229 pbn_b0_bt_4_921600 },
3230 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3232 pbn_b0_bt_4_921600 },
3233 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3235 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3236 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3238 pbn_b0_bt_8_921600 },
3239 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241 pbn_b0_bt_8_921600 },
3242 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244 pbn_b0_bt_8_921600 },
1da177e4
LT		 3245
3246 /*
3247 * Computone devices submitted by Doug McNash dmcnash@computone.com
3248 */
3249 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3250 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3251 0, 0, pbn_computone_4 },
3252 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3253 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3254 0, 0, pbn_computone_8 },
3255 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3256 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3257 0, 0, pbn_computone_6 },
3258
3259 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3261 pbn_oxsemi },
3262 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3263 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3264 pbn_b0_bt_1_921600 },
3265
3266 /*
3267 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3268 */
3269 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 pbn_b0_bt_8_115200 },
3272 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274 pbn_b0_bt_8_115200 },
3275
3276 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278 pbn_b0_bt_2_115200 },
3279 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281 pbn_b0_bt_2_115200 },
3282 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 3285 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287 pbn_b0_bt_2_115200 },
3288 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290 pbn_b0_bt_2_115200 },
1da177e4
LT		 3291 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293 pbn_b0_bt_4_460800 },
3294 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296 pbn_b0_bt_4_460800 },
3297 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299 pbn_b0_bt_2_460800 },
3300 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302 pbn_b0_bt_2_460800 },
3303 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305 pbn_b0_bt_2_460800 },
3306 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3308 pbn_b0_bt_1_115200 },
3309 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311 pbn_b0_bt_1_460800 },
3312
1fb8cacc
RK		 3313 /*
3314 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3315 * Cards are identified by their subsystem vendor IDs, which
3316 * (in hex) match the model number.
3317 *
3318 * Note that JC140x are RS422/485 cards which require ox950
3319 * ACR = 0x10, and as such are not currently fully supported.
3320 */
3321 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3322 0x1204, 0x0004, 0, 0,
3323 pbn_b0_4_921600 },
3324 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3325 0x1208, 0x0004, 0, 0,
3326 pbn_b0_4_921600 },
3327/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3328 0x1402, 0x0002, 0, 0,
3329 pbn_b0_2_921600 }, */
3330/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3331 0x1404, 0x0004, 0, 0,
3332 pbn_b0_4_921600 }, */
3333 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3334 0x1208, 0x0004, 0, 0,
3335 pbn_b0_4_921600 },
3336
2a52fcb5
KY		 3337 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3338 0x1204, 0x0004, 0, 0,
3339 pbn_b0_4_921600 },
3340 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3341 0x1208, 0x0004, 0, 0,
3342 pbn_b0_4_921600 },
3343 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3344 0x1208, 0x0004, 0, 0,
3345 pbn_b0_4_921600 },
1da177e4
LT		 3346 /*
3347 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3348 */
3349 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3351 pbn_b1_1_1382400 },
3352
3353 /*
3354 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3355 */
3356 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3358 pbn_b1_1_1382400 },
3359
3360 /*
3361 * RAStel 2 port modem, gerg@moreton.com.au
3362 */
3363 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3365 pbn_b2_bt_2_115200 },
3366
3367 /*
3368 * EKF addition for i960 Boards form EKF with serial port
3369 */
3370 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3371 0xE4BF, PCI_ANY_ID, 0, 0,
3372 pbn_intel_i960 },
3373
3374 /*
3375 * Xircom Cardbus/Ethernet combos
3376 */
3377 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3379 pbn_b0_1_115200 },
3380 /*
3381 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3382 */
3383 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3385 pbn_b0_1_115200 },
3386
3387 /*
3388 * Untested PCI modems, sent in from various folks...
3389 */
3390
3391 /*
3392 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3393 */
3394 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3395 0x1048, 0x1500, 0, 0,
3396 pbn_b1_1_115200 },
3397
3398 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3399 0xFF00, 0, 0, 0,
3400 pbn_sgi_ioc3 },
3401
3402 /*
3403 * HP Diva card
3404 */
3405 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3406 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3407 pbn_b1_1_115200 },
3408 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410 pbn_b0_5_115200 },
3411 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413 pbn_b2_1_115200 },
3414
d9004eb4
ABL		 3415 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3417 pbn_b3_2_115200 },
1da177e4
LT		 3418 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420 pbn_b3_4_115200 },
3421 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423 pbn_b3_8_115200 },
3424
3425 /*
3426 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3427 */
3428 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3429 PCI_ANY_ID, PCI_ANY_ID,
3430 0,
3431 0, pbn_exar_XR17C152 },
3432 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3433 PCI_ANY_ID, PCI_ANY_ID,
3434 0,
3435 0, pbn_exar_XR17C154 },
3436 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3437 PCI_ANY_ID, PCI_ANY_ID,
3438 0,
3439 0, pbn_exar_XR17C158 },
3440
3441 /*
3442 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3443 */
3444 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446 pbn_b0_1_115200 },
84f8c6fc
NV		 3447 /*
3448 * ITE
3449 */
3450 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3451 PCI_ANY_ID, PCI_ANY_ID,
3452 0, 0,
3453 pbn_b1_bt_1_115200 },
1da177e4 3454
737c1756
PH		 3455 /*
3456 * IntaShield IS-200
3457 */
3458 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3459 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3460 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3461 /*
3462 * IntaShield IS-400
3463 */
3464 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3466 pbn_b2_4_115200 },
48212008
TH		 3467 /*
3468 * Perle PCI-RAS cards
3469 */
3470 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3471 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3472 0, 0, pbn_b2_4_921600 },
3473 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3474 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3475 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3476
3477 /*
3478 * Mainpine series cards: Fairly standard layout but fools
3479 * parts of the autodetect in some cases and uses otherwise
3480 * unmatched communications subclasses in the PCI Express case
3481 */
3482
3483 { /* RockForceDUO */
3484 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3485 PCI_VENDOR_ID_MAINPINE, 0x0200,
3486 0, 0, pbn_b0_2_115200 },
3487 { /* RockForceQUATRO */
3488 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3489 PCI_VENDOR_ID_MAINPINE, 0x0300,
3490 0, 0, pbn_b0_4_115200 },
3491 { /* RockForceDUO+ */
3492 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3493 PCI_VENDOR_ID_MAINPINE, 0x0400,
3494 0, 0, pbn_b0_2_115200 },
3495 { /* RockForceQUATRO+ */
3496 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3497 PCI_VENDOR_ID_MAINPINE, 0x0500,
3498 0, 0, pbn_b0_4_115200 },
3499 { /* RockForce+ */
3500 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3501 PCI_VENDOR_ID_MAINPINE, 0x0600,
3502 0, 0, pbn_b0_2_115200 },
3503 { /* RockForce+ */
3504 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3505 PCI_VENDOR_ID_MAINPINE, 0x0700,
3506 0, 0, pbn_b0_4_115200 },
3507 { /* RockForceOCTO+ */
3508 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3509 PCI_VENDOR_ID_MAINPINE, 0x0800,
3510 0, 0, pbn_b0_8_115200 },
3511 { /* RockForceDUO+ */
3512 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3513 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3514 0, 0, pbn_b0_2_115200 },
3515 { /* RockForceQUARTRO+ */
3516 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3517 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3518 0, 0, pbn_b0_4_115200 },
3519 { /* RockForceOCTO+ */
3520 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3521 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3522 0, 0, pbn_b0_8_115200 },
3523 { /* RockForceD1 */
3524 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3525 PCI_VENDOR_ID_MAINPINE, 0x2000,
3526 0, 0, pbn_b0_1_115200 },
3527 { /* RockForceF1 */
3528 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3529 PCI_VENDOR_ID_MAINPINE, 0x2100,
3530 0, 0, pbn_b0_1_115200 },
3531 { /* RockForceD2 */
3532 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3533 PCI_VENDOR_ID_MAINPINE, 0x2200,
3534 0, 0, pbn_b0_2_115200 },
3535 { /* RockForceF2 */
3536 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3537 PCI_VENDOR_ID_MAINPINE, 0x2300,
3538 0, 0, pbn_b0_2_115200 },
3539 { /* RockForceD4 */
3540 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3541 PCI_VENDOR_ID_MAINPINE, 0x2400,
3542 0, 0, pbn_b0_4_115200 },
3543 { /* RockForceF4 */
3544 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3545 PCI_VENDOR_ID_MAINPINE, 0x2500,
3546 0, 0, pbn_b0_4_115200 },
3547 { /* RockForceD8 */
3548 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3549 PCI_VENDOR_ID_MAINPINE, 0x2600,
3550 0, 0, pbn_b0_8_115200 },
3551 { /* RockForceF8 */
3552 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3553 PCI_VENDOR_ID_MAINPINE, 0x2700,
3554 0, 0, pbn_b0_8_115200 },
3555 { /* IQ Express D1 */
3556 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3557 PCI_VENDOR_ID_MAINPINE, 0x3000,
3558 0, 0, pbn_b0_1_115200 },
3559 { /* IQ Express F1 */
3560 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3561 PCI_VENDOR_ID_MAINPINE, 0x3100,
3562 0, 0, pbn_b0_1_115200 },
3563 { /* IQ Express D2 */
3564 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3565 PCI_VENDOR_ID_MAINPINE, 0x3200,
3566 0, 0, pbn_b0_2_115200 },
3567 { /* IQ Express F2 */
3568 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3569 PCI_VENDOR_ID_MAINPINE, 0x3300,
3570 0, 0, pbn_b0_2_115200 },
3571 { /* IQ Express D4 */
3572 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3573 PCI_VENDOR_ID_MAINPINE, 0x3400,
3574 0, 0, pbn_b0_4_115200 },
3575 { /* IQ Express F4 */
3576 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3577 PCI_VENDOR_ID_MAINPINE, 0x3500,
3578 0, 0, pbn_b0_4_115200 },
3579 { /* IQ Express D8 */
3580 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3581 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3582 0, 0, pbn_b0_8_115200 },
3583 { /* IQ Express F8 */
3584 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3585 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3586 0, 0, pbn_b0_8_115200 },
3587
3588
aa798505
OJ		 3589 /*
3590 * PA Semi PA6T-1682M on-chip UART
3591 */
3592 { PCI_VENDOR_ID_PASEMI, 0xa004,
3593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3594 pbn_pasemi_1682M },
3595
46a0fac9
SB		 3596 /*
3597 * National Instruments
3598 */
04bf7e74
WP		 3599 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601 pbn_b1_16_115200 },
3602 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604 pbn_b1_8_115200 },
3605 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3607 pbn_b1_bt_4_115200 },
3608 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3610 pbn_b1_bt_2_115200 },
3611 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3613 pbn_b1_bt_4_115200 },
3614 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616 pbn_b1_bt_2_115200 },
3617 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3619 pbn_b1_16_115200 },
3620 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3622 pbn_b1_8_115200 },
3623 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3625 pbn_b1_bt_4_115200 },
3626 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3628 pbn_b1_bt_2_115200 },
3629 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3631 pbn_b1_bt_4_115200 },
3632 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3634 pbn_b1_bt_2_115200 },
46a0fac9
SB		 3635 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3637 pbn_ni8430_2 },
3638 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3640 pbn_ni8430_2 },
3641 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3643 pbn_ni8430_4 },
3644 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3646 pbn_ni8430_4 },
3647 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3649 pbn_ni8430_8 },
3650 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3652 pbn_ni8430_8 },
3653 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3655 pbn_ni8430_16 },
3656 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3658 pbn_ni8430_16 },
3659 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3661 pbn_ni8430_2 },
3662 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3664 pbn_ni8430_2 },
3665 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3667 pbn_ni8430_4 },
3668 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3670 pbn_ni8430_4 },
3671
02c9b5cf
KJ		 3672 /*
3673 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3674 */
3675 { PCI_VENDOR_ID_ADDIDATA,
3676 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3677 PCI_ANY_ID,
3678 PCI_ANY_ID,
3679 0,
3680 0,
3681 pbn_b0_4_115200 },
3682
3683 { PCI_VENDOR_ID_ADDIDATA,
3684 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3685 PCI_ANY_ID,
3686 PCI_ANY_ID,
3687 0,
3688 0,
3689 pbn_b0_2_115200 },
3690
3691 { PCI_VENDOR_ID_ADDIDATA,
3692 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3693 PCI_ANY_ID,
3694 PCI_ANY_ID,
3695 0,
3696 0,
3697 pbn_b0_1_115200 },
3698
3699 { PCI_VENDOR_ID_ADDIDATA_OLD,
3700 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3701 PCI_ANY_ID,
3702 PCI_ANY_ID,
3703 0,
3704 0,
3705 pbn_b1_8_115200 },
3706
3707 { PCI_VENDOR_ID_ADDIDATA,
3708 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3709 PCI_ANY_ID,
3710 PCI_ANY_ID,
3711 0,
3712 0,
3713 pbn_b0_4_115200 },
3714
3715 { PCI_VENDOR_ID_ADDIDATA,
3716 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3717 PCI_ANY_ID,
3718 PCI_ANY_ID,
3719 0,
3720 0,
3721 pbn_b0_2_115200 },
3722
3723 { PCI_VENDOR_ID_ADDIDATA,
3724 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3725 PCI_ANY_ID,
3726 PCI_ANY_ID,
3727 0,
3728 0,
3729 pbn_b0_1_115200 },
3730
3731 { PCI_VENDOR_ID_ADDIDATA,
3732 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3733 PCI_ANY_ID,
3734 PCI_ANY_ID,
3735 0,
3736 0,
3737 pbn_b0_4_115200 },
3738
3739 { PCI_VENDOR_ID_ADDIDATA,
3740 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3741 PCI_ANY_ID,
3742 PCI_ANY_ID,
3743 0,
3744 0,
3745 pbn_b0_2_115200 },
3746
3747 { PCI_VENDOR_ID_ADDIDATA,
3748 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3749 PCI_ANY_ID,
3750 PCI_ANY_ID,
3751 0,
3752 0,
3753 pbn_b0_1_115200 },
3754
3755 { PCI_VENDOR_ID_ADDIDATA,
3756 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3757 PCI_ANY_ID,
3758 PCI_ANY_ID,
3759 0,
3760 0,
3761 pbn_b0_8_115200 },
3762
1b62cbf2
KJ		 3763 { PCI_VENDOR_ID_ADDIDATA,
3764 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3765 PCI_ANY_ID,
3766 PCI_ANY_ID,
3767 0,
3768 0,
3769 pbn_ADDIDATA_PCIe_4_3906250 },
3770
3771 { PCI_VENDOR_ID_ADDIDATA,
3772 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3773 PCI_ANY_ID,
3774 PCI_ANY_ID,
3775 0,
3776 0,
3777 pbn_ADDIDATA_PCIe_2_3906250 },
3778
3779 { PCI_VENDOR_ID_ADDIDATA,
3780 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3781 PCI_ANY_ID,
3782 PCI_ANY_ID,
3783 0,
3784 0,
3785 pbn_ADDIDATA_PCIe_1_3906250 },
3786
3787 { PCI_VENDOR_ID_ADDIDATA,
3788 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3789 PCI_ANY_ID,
3790 PCI_ANY_ID,
3791 0,
3792 0,
3793 pbn_ADDIDATA_PCIe_8_3906250 },
3794
25cf9bc1
JS		 3795 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3796 PCI_VENDOR_ID_IBM, 0x0299,
3797 0, 0, pbn_b0_bt_2_115200 },
3798
c4285b47
MB		 3799 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3800 0xA000, 0x1000,
3801 0, 0, pbn_b0_1_115200 },
3802
ac6ec5b1
IS		 3803 /*
3804 * Best Connectivity PCI Multi I/O cards
3805 */
3806
3807 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3808 0xA000, 0x1000,
3809 0, 0, pbn_b0_1_115200 },
3810
3811 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3812 0xA000, 0x3004,
3813 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 3814 /* Intel CE4100 */
3815 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
3816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3817 pbn_ce4100_1_115200 },
3818
ac6ec5b1 3819
1da177e4
LT		 3820 /*
3821 * These entries match devices with class COMMUNICATION_SERIAL,
3822 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3823 */
3824 { PCI_ANY_ID, PCI_ANY_ID,
3825 PCI_ANY_ID, PCI_ANY_ID,
3826 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3827 0xffff00, pbn_default },
3828 { PCI_ANY_ID, PCI_ANY_ID,
3829 PCI_ANY_ID, PCI_ANY_ID,
3830 PCI_CLASS_COMMUNICATION_MODEM << 8,
3831 0xffff00, pbn_default },
3832 { PCI_ANY_ID, PCI_ANY_ID,
3833 PCI_ANY_ID, PCI_ANY_ID,
3834 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3835 0xffff00, pbn_default },
3836 { 0, }
3837};
3838
3839static struct pci_driver serial_pci_driver = {
3840 .name = "serial",
3841 .probe = pciserial_init_one,
3842 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 3843#ifdef CONFIG_PM
1da177e4
LT		 3844 .suspend = pciserial_suspend_one,
3845 .resume = pciserial_resume_one,
1d5e7996 3846#endif
1da177e4
LT		 3847 .id_table = serial_pci_tbl,
3848};
3849
3850static int __init serial8250_pci_init(void)
3851{
3852 return pci_register_driver(&serial_pci_driver);
3853}
3854
3855static void __exit serial8250_pci_exit(void)
3856{
3857 pci_unregister_driver(&serial_pci_driver);
3858}
3859
3860module_init(serial8250_pci_init);
3861module_exit(serial8250_pci_exit);
3862
3863MODULE_LICENSE("GPL");
3864MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3865MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux 6.x block layer and io_uring tree(s)