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ACPI / SRAT: fix SRAT parsing order with both LAPIC and X2APIC present
[linux-2.6-block.git] / drivers / tty / serial / 8250 / 8250_port.c
CommitLineData
b6830f6d
PH		 1/*
2 * Base port operations for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * A note about mapbase / membase
13 *
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
16 */
17
18#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/ioport.h>
25#include <linux/init.h>
26#include <linux/console.h>
27#include <linux/sysrq.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/tty.h>
31#include <linux/ratelimit.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/serial_8250.h>
35#include <linux/nmi.h>
36#include <linux/mutex.h>
37#include <linux/slab.h>
38#include <linux/uaccess.h>
39#include <linux/pm_runtime.h>
e490c914 40#include <linux/timer.h>
b6830f6d
PH		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
47/*
48 * Debugging.
49 */
50#if 0
51#define DEBUG_AUTOCONF(fmt...) printk(fmt)
52#else
53#define DEBUG_AUTOCONF(fmt...) do { } while (0)
54#endif
55
6d7c157f 56#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
b6830f6d
PH		 57
58/*
59 * Here we define the default xmit fifo size used for each type of UART.
60 */
61static const struct serial8250_config uart_config[] = {
62 [PORT_UNKNOWN] = {
63 .name = "unknown",
64 .fifo_size = 1,
65 .tx_loadsz = 1,
66 },
67 [PORT_8250] = {
68 .name = "8250",
69 .fifo_size = 1,
70 .tx_loadsz = 1,
71 },
72 [PORT_16450] = {
73 .name = "16450",
74 .fifo_size = 1,
75 .tx_loadsz = 1,
76 },
77 [PORT_16550] = {
78 .name = "16550",
79 .fifo_size = 1,
80 .tx_loadsz = 1,
81 },
82 [PORT_16550A] = {
83 .name = "16550A",
84 .fifo_size = 16,
85 .tx_loadsz = 16,
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
87 .rxtrig_bytes = {1, 4, 8, 14},
88 .flags = UART_CAP_FIFO,
89 },
90 [PORT_CIRRUS] = {
91 .name = "Cirrus",
92 .fifo_size = 1,
93 .tx_loadsz = 1,
94 },
95 [PORT_16650] = {
96 .name = "ST16650",
97 .fifo_size = 1,
98 .tx_loadsz = 1,
99 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
100 },
101 [PORT_16650V2] = {
102 .name = "ST16650V2",
103 .fifo_size = 32,
104 .tx_loadsz = 16,
105 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
106 UART_FCR_T_TRIG_00,
107 .rxtrig_bytes = {8, 16, 24, 28},
108 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
109 },
110 [PORT_16750] = {
111 .name = "TI16750",
112 .fifo_size = 64,
113 .tx_loadsz = 64,
114 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
115 UART_FCR7_64BYTE,
116 .rxtrig_bytes = {1, 16, 32, 56},
117 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
118 },
119 [PORT_STARTECH] = {
120 .name = "Startech",
121 .fifo_size = 1,
122 .tx_loadsz = 1,
123 },
124 [PORT_16C950] = {
125 .name = "16C950/954",
126 .fifo_size = 128,
127 .tx_loadsz = 128,
128 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
131 },
132 [PORT_16654] = {
133 .name = "ST16654",
134 .fifo_size = 64,
135 .tx_loadsz = 32,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
137 UART_FCR_T_TRIG_10,
138 .rxtrig_bytes = {8, 16, 56, 60},
139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
140 },
141 [PORT_16850] = {
142 .name = "XR16850",
143 .fifo_size = 128,
144 .tx_loadsz = 128,
145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
147 },
148 [PORT_RSA] = {
149 .name = "RSA",
150 .fifo_size = 2048,
151 .tx_loadsz = 2048,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
153 .flags = UART_CAP_FIFO,
154 },
155 [PORT_NS16550A] = {
156 .name = "NS16550A",
157 .fifo_size = 16,
158 .tx_loadsz = 16,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160 .flags = UART_CAP_FIFO | UART_NATSEMI,
161 },
162 [PORT_XSCALE] = {
163 .name = "XScale",
164 .fifo_size = 32,
165 .tx_loadsz = 32,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
168 },
169 [PORT_OCTEON] = {
170 .name = "OCTEON",
171 .fifo_size = 64,
172 .tx_loadsz = 64,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
175 },
176 [PORT_AR7] = {
177 .name = "AR7",
178 .fifo_size = 16,
179 .tx_loadsz = 16,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
181 .flags = UART_CAP_FIFO | UART_CAP_AFE,
182 },
183 [PORT_U6_16550A] = {
184 .name = "U6_16550A",
185 .fifo_size = 64,
186 .tx_loadsz = 64,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
188 .flags = UART_CAP_FIFO | UART_CAP_AFE,
189 },
190 [PORT_TEGRA] = {
191 .name = "Tegra",
192 .fifo_size = 32,
193 .tx_loadsz = 8,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_01,
196 .rxtrig_bytes = {1, 4, 8, 14},
197 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
198 },
199 [PORT_XR17D15X] = {
200 .name = "XR17D15X",
201 .fifo_size = 64,
202 .tx_loadsz = 64,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
205 UART_CAP_SLEEP,
206 },
207 [PORT_XR17V35X] = {
208 .name = "XR17V35X",
209 .fifo_size = 256,
210 .tx_loadsz = 256,
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
212 UART_FCR_T_TRIG_11,
213 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
214 UART_CAP_SLEEP,
215 },
216 [PORT_LPC3220] = {
217 .name = "LPC3220",
218 .fifo_size = 64,
219 .tx_loadsz = 32,
220 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
221 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
222 .flags = UART_CAP_FIFO,
223 },
224 [PORT_BRCM_TRUMANAGE] = {
225 .name = "TruManage",
226 .fifo_size = 1,
227 .tx_loadsz = 1024,
228 .flags = UART_CAP_HFIFO,
229 },
230 [PORT_8250_CIR] = {
231 .name = "CIR port"
232 },
233 [PORT_ALTR_16550_F32] = {
234 .name = "Altera 16550 FIFO32",
235 .fifo_size = 32,
236 .tx_loadsz = 32,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 },
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
242 .fifo_size = 64,
243 .tx_loadsz = 64,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 },
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
249 .fifo_size = 128,
250 .tx_loadsz = 128,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 },
740dc2de
AW		 254 /*
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
258 */
b6830f6d
PH		 259 [PORT_16550A_FSL64] = {
260 .name = "16550A_FSL64",
261 .fifo_size = 64,
262 .tx_loadsz = 63,
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 UART_FCR7_64BYTE,
265 .flags = UART_CAP_FIFO,
266 },
3c5a0357
MR		 267 [PORT_RT2880] = {
268 .name = "Palmchip BK-3103",
269 .fifo_size = 16,
270 .tx_loadsz = 16,
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .rxtrig_bytes = {1, 4, 8, 14},
273 .flags = UART_CAP_FIFO,
274 },
b6830f6d
PH		 275};
276
277/* Uart divisor latch read */
278static int default_serial_dl_read(struct uart_8250_port *up)
279{
280 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
281}
282
283/* Uart divisor latch write */
284static void default_serial_dl_write(struct uart_8250_port *up, int value)
285{
286 serial_out(up, UART_DLL, value & 0xff);
287 serial_out(up, UART_DLM, value >> 8 & 0xff);
288}
289
9b2256c8 290#ifdef CONFIG_SERIAL_8250_RT288X
b6830f6d
PH		 291
292/* Au1x00/RT288x UART hardware has a weird register layout */
293static const s8 au_io_in_map[8] = {
294 0, /* UART_RX */
295 2, /* UART_IER */
296 3, /* UART_IIR */
297 5, /* UART_LCR */
298 6, /* UART_MCR */
299 7, /* UART_LSR */
300 8, /* UART_MSR */
301 -1, /* UART_SCR (unmapped) */
302};
303
304static const s8 au_io_out_map[8] = {
305 1, /* UART_TX */
306 2, /* UART_IER */
307 4, /* UART_FCR */
308 5, /* UART_LCR */
309 6, /* UART_MCR */
310 -1, /* UART_LSR (unmapped) */
311 -1, /* UART_MSR (unmapped) */
312 -1, /* UART_SCR (unmapped) */
313};
314
315static unsigned int au_serial_in(struct uart_port *p, int offset)
316{
317 if (offset >= ARRAY_SIZE(au_io_in_map))
318 return UINT_MAX;
319 offset = au_io_in_map[offset];
320 if (offset < 0)
321 return UINT_MAX;
322 return __raw_readl(p->membase + (offset << p->regshift));
323}
324
325static void au_serial_out(struct uart_port *p, int offset, int value)
326{
327 if (offset >= ARRAY_SIZE(au_io_out_map))
328 return;
329 offset = au_io_out_map[offset];
330 if (offset < 0)
331 return;
332 __raw_writel(value, p->membase + (offset << p->regshift));
333}
334
335/* Au1x00 haven't got a standard divisor latch */
336static int au_serial_dl_read(struct uart_8250_port *up)
337{
338 return __raw_readl(up->port.membase + 0x28);
339}
340
341static void au_serial_dl_write(struct uart_8250_port *up, int value)
342{
343 __raw_writel(value, up->port.membase + 0x28);
344}
345
346#endif
347
348static unsigned int hub6_serial_in(struct uart_port *p, int offset)
349{
350 offset = offset << p->regshift;
351 outb(p->hub6 - 1 + offset, p->iobase);
352 return inb(p->iobase + 1);
353}
354
355static void hub6_serial_out(struct uart_port *p, int offset, int value)
356{
357 offset = offset << p->regshift;
358 outb(p->hub6 - 1 + offset, p->iobase);
359 outb(value, p->iobase + 1);
360}
361
362static unsigned int mem_serial_in(struct uart_port *p, int offset)
363{
364 offset = offset << p->regshift;
365 return readb(p->membase + offset);
366}
367
368static void mem_serial_out(struct uart_port *p, int offset, int value)
369{
370 offset = offset << p->regshift;
371 writeb(value, p->membase + offset);
372}
373
bd94c407
MY		 374static void mem16_serial_out(struct uart_port *p, int offset, int value)
375{
376 offset = offset << p->regshift;
377 writew(value, p->membase + offset);
378}
379
380static unsigned int mem16_serial_in(struct uart_port *p, int offset)
381{
382 offset = offset << p->regshift;
383 return readw(p->membase + offset);
384}
385
b6830f6d
PH		 386static void mem32_serial_out(struct uart_port *p, int offset, int value)
387{
388 offset = offset << p->regshift;
389 writel(value, p->membase + offset);
390}
391
392static unsigned int mem32_serial_in(struct uart_port *p, int offset)
393{
394 offset = offset << p->regshift;
395 return readl(p->membase + offset);
396}
397
398static void mem32be_serial_out(struct uart_port *p, int offset, int value)
399{
400 offset = offset << p->regshift;
401 iowrite32be(value, p->membase + offset);
402}
403
404static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
405{
406 offset = offset << p->regshift;
407 return ioread32be(p->membase + offset);
408}
409
410static unsigned int io_serial_in(struct uart_port *p, int offset)
411{
412 offset = offset << p->regshift;
413 return inb(p->iobase + offset);
414}
415
416static void io_serial_out(struct uart_port *p, int offset, int value)
417{
418 offset = offset << p->regshift;
419 outb(value, p->iobase + offset);
420}
421
422static int serial8250_default_handle_irq(struct uart_port *port);
423static int exar_handle_irq(struct uart_port *port);
424
425static void set_io_from_upio(struct uart_port *p)
426{
427 struct uart_8250_port *up = up_to_u8250p(p);
428
429 up->dl_read = default_serial_dl_read;
430 up->dl_write = default_serial_dl_write;
431
432 switch (p->iotype) {
433 case UPIO_HUB6:
434 p->serial_in = hub6_serial_in;
435 p->serial_out = hub6_serial_out;
436 break;
437
438 case UPIO_MEM:
439 p->serial_in = mem_serial_in;
440 p->serial_out = mem_serial_out;
441 break;
442
bd94c407
MY		 443 case UPIO_MEM16:
444 p->serial_in = mem16_serial_in;
445 p->serial_out = mem16_serial_out;
446 break;
447
b6830f6d
PH		 448 case UPIO_MEM32:
449 p->serial_in = mem32_serial_in;
450 p->serial_out = mem32_serial_out;
451 break;
452
453 case UPIO_MEM32BE:
454 p->serial_in = mem32be_serial_in;
455 p->serial_out = mem32be_serial_out;
456 break;
457
9b2256c8 458#ifdef CONFIG_SERIAL_8250_RT288X
b6830f6d
PH		 459 case UPIO_AU:
460 p->serial_in = au_serial_in;
461 p->serial_out = au_serial_out;
462 up->dl_read = au_serial_dl_read;
463 up->dl_write = au_serial_dl_write;
464 break;
465#endif
466
467 default:
468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
470 break;
471 }
472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
474 p->handle_irq = serial8250_default_handle_irq;
475}
476
477static void
478serial_port_out_sync(struct uart_port *p, int offset, int value)
479{
480 switch (p->iotype) {
481 case UPIO_MEM:
bd94c407 482 case UPIO_MEM16:
b6830f6d
PH		 483 case UPIO_MEM32:
484 case UPIO_MEM32BE:
485 case UPIO_AU:
486 p->serial_out(p, offset, value);
487 p->serial_in(p, UART_LCR); /* safe, no side-effects */
488 break;
489 default:
490 p->serial_out(p, offset, value);
491 }
492}
493
494/*
495 * For the 16C950
496 */
497static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
498{
499 serial_out(up, UART_SCR, offset);
500 serial_out(up, UART_ICR, value);
501}
502
503static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
504{
505 unsigned int value;
506
507 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
508 serial_out(up, UART_SCR, offset);
509 value = serial_in(up, UART_ICR);
510 serial_icr_write(up, UART_ACR, up->acr);
511
512 return value;
513}
514
515/*
516 * FIFO support.
517 */
518static void serial8250_clear_fifos(struct uart_8250_port *p)
519{
520 if (p->capabilities & UART_CAP_FIFO) {
521 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
522 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
523 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
524 serial_out(p, UART_FCR, 0);
525 }
526}
527
e490c914
MK		 528static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
529{
530 unsigned char mcr = serial_in(p, UART_MCR);
531
532 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
533 mcr |= UART_MCR_RTS;
534 else
535 mcr &= ~UART_MCR_RTS;
536 serial_out(p, UART_MCR, mcr);
537}
538
539static void serial8250_em485_handle_start_tx(unsigned long arg);
540static void serial8250_em485_handle_stop_tx(unsigned long arg);
541
b6830f6d
PH		 542void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
543{
544 serial8250_clear_fifos(p);
545 serial_out(p, UART_FCR, p->fcr);
546}
547EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
548
549void serial8250_rpm_get(struct uart_8250_port *p)
550{
551 if (!(p->capabilities & UART_CAP_RPM))
552 return;
553 pm_runtime_get_sync(p->port.dev);
554}
555EXPORT_SYMBOL_GPL(serial8250_rpm_get);
556
557void serial8250_rpm_put(struct uart_8250_port *p)
558{
559 if (!(p->capabilities & UART_CAP_RPM))
560 return;
561 pm_runtime_mark_last_busy(p->port.dev);
562 pm_runtime_put_autosuspend(p->port.dev);
563}
564EXPORT_SYMBOL_GPL(serial8250_rpm_put);
565
e490c914
MK		 566/**
567 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
568 * @p: uart_8250_port port instance
569 *
570 * The function is used to start rs485 software emulating on the
571 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
572 * transmission. The function is idempotent, so it is safe to call it
573 * multiple times.
574 *
575 * The caller MUST enable interrupt on empty shift register before
576 * calling serial8250_em485_init(). This interrupt is not a part of
577 * 8250 standard, but implementation defined.
578 *
579 * The function is supposed to be called from .rs485_config callback
580 * or from any other callback protected with p->port.lock spinlock.
581 *
582 * See also serial8250_em485_destroy()
583 *
584 * Return 0 - success, -errno - otherwise
585 */
586int serial8250_em485_init(struct uart_8250_port *p)
587{
588 if (p->em485 != NULL)
589 return 0;
590
b18a183e 591 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
e490c914
MK		 592 if (p->em485 == NULL)
593 return -ENOMEM;
594
595 setup_timer(&p->em485->stop_tx_timer,
596 serial8250_em485_handle_stop_tx, (unsigned long)p);
597 setup_timer(&p->em485->start_tx_timer,
598 serial8250_em485_handle_start_tx, (unsigned long)p);
599 p->em485->active_timer = NULL;
600
601 serial8250_em485_rts_after_send(p);
602
603 return 0;
604}
605EXPORT_SYMBOL_GPL(serial8250_em485_init);
606
607/**
608 * serial8250_em485_destroy() - put uart_8250_port into normal state
609 * @p: uart_8250_port port instance
610 *
611 * The function is used to stop rs485 software emulating on the
612 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
613 * call it multiple times.
614 *
615 * The function is supposed to be called from .rs485_config callback
616 * or from any other callback protected with p->port.lock spinlock.
617 *
618 * See also serial8250_em485_init()
619 */
620void serial8250_em485_destroy(struct uart_8250_port *p)
621{
622 if (p->em485 == NULL)
623 return;
624
625 del_timer(&p->em485->start_tx_timer);
626 del_timer(&p->em485->stop_tx_timer);
627
628 kfree(p->em485);
629 p->em485 = NULL;
630}
631EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
632
b6830f6d
PH		 633/*
634 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
635 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
636 * empty and the HW can idle again.
637 */
638static void serial8250_rpm_get_tx(struct uart_8250_port *p)
639{
640 unsigned char rpm_active;
641
642 if (!(p->capabilities & UART_CAP_RPM))
643 return;
644
645 rpm_active = xchg(&p->rpm_tx_active, 1);
646 if (rpm_active)
647 return;
648 pm_runtime_get_sync(p->port.dev);
649}
650
651static void serial8250_rpm_put_tx(struct uart_8250_port *p)
652{
653 unsigned char rpm_active;
654
655 if (!(p->capabilities & UART_CAP_RPM))
656 return;
657
658 rpm_active = xchg(&p->rpm_tx_active, 0);
659 if (!rpm_active)
660 return;
661 pm_runtime_mark_last_busy(p->port.dev);
662 pm_runtime_put_autosuspend(p->port.dev);
663}
664
665/*
666 * IER sleep support. UARTs which have EFRs need the "extended
667 * capability" bit enabled. Note that on XR16C850s, we need to
668 * reset LCR to write to IER.
669 */
670static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
671{
672 unsigned char lcr = 0, efr = 0;
673 /*
674 * Exar UARTs have a SLEEP register that enables or disables
675 * each UART to enter sleep mode separately. On the XR17V35x the
676 * register is accessible to each UART at the UART_EXAR_SLEEP
677 * offset but the UART channel may only write to the corresponding
678 * bit.
679 */
680 serial8250_rpm_get(p);
681 if ((p->port.type == PORT_XR17V35X) ||
682 (p->port.type == PORT_XR17D15X)) {
683 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
684 goto out;
685 }
686
687 if (p->capabilities & UART_CAP_SLEEP) {
688 if (p->capabilities & UART_CAP_EFR) {
689 lcr = serial_in(p, UART_LCR);
690 efr = serial_in(p, UART_EFR);
691 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
692 serial_out(p, UART_EFR, UART_EFR_ECB);
693 serial_out(p, UART_LCR, 0);
694 }
695 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
696 if (p->capabilities & UART_CAP_EFR) {
697 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
698 serial_out(p, UART_EFR, efr);
699 serial_out(p, UART_LCR, lcr);
700 }
701 }
702out:
703 serial8250_rpm_put(p);
704}
705
706#ifdef CONFIG_SERIAL_8250_RSA
707/*
708 * Attempts to turn on the RSA FIFO. Returns zero on failure.
709 * We set the port uart clock rate if we succeed.
710 */
711static int __enable_rsa(struct uart_8250_port *up)
712{
713 unsigned char mode;
714 int result;
715
716 mode = serial_in(up, UART_RSA_MSR);
717 result = mode & UART_RSA_MSR_FIFO;
718
719 if (!result) {
720 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
721 mode = serial_in(up, UART_RSA_MSR);
722 result = mode & UART_RSA_MSR_FIFO;
723 }
724
725 if (result)
726 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
727
728 return result;
729}
730
731static void enable_rsa(struct uart_8250_port *up)
732{
733 if (up->port.type == PORT_RSA) {
734 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
735 spin_lock_irq(&up->port.lock);
736 __enable_rsa(up);
737 spin_unlock_irq(&up->port.lock);
738 }
739 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
740 serial_out(up, UART_RSA_FRR, 0);
741 }
742}
743
744/*
745 * Attempts to turn off the RSA FIFO. Returns zero on failure.
746 * It is unknown why interrupts were disabled in here. However,
747 * the caller is expected to preserve this behaviour by grabbing
748 * the spinlock before calling this function.
749 */
750static void disable_rsa(struct uart_8250_port *up)
751{
752 unsigned char mode;
753 int result;
754
755 if (up->port.type == PORT_RSA &&
756 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
757 spin_lock_irq(&up->port.lock);
758
759 mode = serial_in(up, UART_RSA_MSR);
760 result = !(mode & UART_RSA_MSR_FIFO);
761
762 if (!result) {
763 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
764 mode = serial_in(up, UART_RSA_MSR);
765 result = !(mode & UART_RSA_MSR_FIFO);
766 }
767
768 if (result)
769 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
770 spin_unlock_irq(&up->port.lock);
771 }
772}
773#endif /* CONFIG_SERIAL_8250_RSA */
774
775/*
776 * This is a quickie test to see how big the FIFO is.
777 * It doesn't work at all the time, more's the pity.
778 */
779static int size_fifo(struct uart_8250_port *up)
780{
781 unsigned char old_fcr, old_mcr, old_lcr;
782 unsigned short old_dl;
783 int count;
784
785 old_lcr = serial_in(up, UART_LCR);
786 serial_out(up, UART_LCR, 0);
787 old_fcr = serial_in(up, UART_FCR);
788 old_mcr = serial_in(up, UART_MCR);
789 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
790 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
791 serial_out(up, UART_MCR, UART_MCR_LOOP);
792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
793 old_dl = serial_dl_read(up);
794 serial_dl_write(up, 0x0001);
795 serial_out(up, UART_LCR, 0x03);
796 for (count = 0; count < 256; count++)
797 serial_out(up, UART_TX, count);
798 mdelay(20);/* FIXME - schedule_timeout */
799 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
800 (count < 256); count++)
801 serial_in(up, UART_RX);
802 serial_out(up, UART_FCR, old_fcr);
803 serial_out(up, UART_MCR, old_mcr);
804 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
805 serial_dl_write(up, old_dl);
806 serial_out(up, UART_LCR, old_lcr);
807
808 return count;
809}
810
811/*
812 * Read UART ID using the divisor method - set DLL and DLM to zero
813 * and the revision will be in DLL and device type in DLM. We
814 * preserve the device state across this.
815 */
816static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
817{
0b41ce99
SF		 818 unsigned char old_lcr;
819 unsigned int id, old_dl;
b6830f6d
PH		 820
821 old_lcr = serial_in(p, UART_LCR);
822 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
0b41ce99
SF		 823 old_dl = serial_dl_read(p);
824 serial_dl_write(p, 0);
825 id = serial_dl_read(p);
826 serial_dl_write(p, old_dl);
b6830f6d 827
b6830f6d
PH		 828 serial_out(p, UART_LCR, old_lcr);
829
830 return id;
831}
832
833/*
834 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
835 * When this function is called we know it is at least a StarTech
836 * 16650 V2, but it might be one of several StarTech UARTs, or one of
837 * its clones. (We treat the broken original StarTech 16650 V1 as a
838 * 16550, and why not? Startech doesn't seem to even acknowledge its
839 * existence.)
840 *
841 * What evil have men's minds wrought...
842 */
843static void autoconfig_has_efr(struct uart_8250_port *up)
844{
845 unsigned int id1, id2, id3, rev;
846
847 /*
848 * Everything with an EFR has SLEEP
849 */
850 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
851
852 /*
853 * First we check to see if it's an Oxford Semiconductor UART.
854 *
855 * If we have to do this here because some non-National
856 * Semiconductor clone chips lock up if you try writing to the
857 * LSR register (which serial_icr_read does)
858 */
859
860 /*
861 * Check for Oxford Semiconductor 16C950.
862 *
863 * EFR [4] must be set else this test fails.
864 *
865 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
866 * claims that it's needed for 952 dual UART's (which are not
867 * recommended for new designs).
868 */
869 up->acr = 0;
870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
871 serial_out(up, UART_EFR, UART_EFR_ECB);
872 serial_out(up, UART_LCR, 0x00);
873 id1 = serial_icr_read(up, UART_ID1);
874 id2 = serial_icr_read(up, UART_ID2);
875 id3 = serial_icr_read(up, UART_ID3);
876 rev = serial_icr_read(up, UART_REV);
877
878 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
879
880 if (id1 == 0x16 && id2 == 0xC9 &&
881 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
882 up->port.type = PORT_16C950;
883
884 /*
885 * Enable work around for the Oxford Semiconductor 952 rev B
886 * chip which causes it to seriously miscalculate baud rates
887 * when DLL is 0.
888 */
889 if (id3 == 0x52 && rev == 0x01)
890 up->bugs |= UART_BUG_QUOT;
891 return;
892 }
893
894 /*
895 * We check for a XR16C850 by setting DLL and DLM to 0, and then
896 * reading back DLL and DLM. The chip type depends on the DLM
897 * value read back:
898 * 0x10 - XR16C850 and the DLL contains the chip revision.
899 * 0x12 - XR16C2850.
900 * 0x14 - XR16C854.
901 */
902 id1 = autoconfig_read_divisor_id(up);
903 DEBUG_AUTOCONF("850id=%04x ", id1);
904
905 id2 = id1 >> 8;
906 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
907 up->port.type = PORT_16850;
908 return;
909 }
910
911 /*
912 * It wasn't an XR16C850.
913 *
914 * We distinguish between the '654 and the '650 by counting
915 * how many bytes are in the FIFO. I'm using this for now,
916 * since that's the technique that was sent to me in the
917 * serial driver update, but I'm not convinced this works.
918 * I've had problems doing this in the past. -TYT
919 */
920 if (size_fifo(up) == 64)
921 up->port.type = PORT_16654;
922 else
923 up->port.type = PORT_16650V2;
924}
925
926/*
927 * We detected a chip without a FIFO. Only two fall into
928 * this category - the original 8250 and the 16450. The
929 * 16450 has a scratch register (accessible with LCR=0)
930 */
931static void autoconfig_8250(struct uart_8250_port *up)
932{
933 unsigned char scratch, status1, status2;
934
935 up->port.type = PORT_8250;
936
937 scratch = serial_in(up, UART_SCR);
938 serial_out(up, UART_SCR, 0xa5);
939 status1 = serial_in(up, UART_SCR);
940 serial_out(up, UART_SCR, 0x5a);
941 status2 = serial_in(up, UART_SCR);
942 serial_out(up, UART_SCR, scratch);
943
944 if (status1 == 0xa5 && status2 == 0x5a)
945 up->port.type = PORT_16450;
946}
947
948static int broken_efr(struct uart_8250_port *up)
949{
950 /*
951 * Exar ST16C2550 "A2" devices incorrectly detect as
952 * having an EFR, and report an ID of 0x0201. See
953 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
954 */
955 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
956 return 1;
957
958 return 0;
959}
960
961/*
962 * We know that the chip has FIFOs. Does it have an EFR? The
963 * EFR is located in the same register position as the IIR and
964 * we know the top two bits of the IIR are currently set. The
965 * EFR should contain zero. Try to read the EFR.
966 */
967static void autoconfig_16550a(struct uart_8250_port *up)
968{
969 unsigned char status1, status2;
970 unsigned int iersave;
971
972 up->port.type = PORT_16550A;
973 up->capabilities |= UART_CAP_FIFO;
974
975 /*
976 * XR17V35x UARTs have an extra divisor register, DLD
977 * that gets enabled with when DLAB is set which will
978 * cause the device to incorrectly match and assign
979 * port type to PORT_16650. The EFR for this UART is
980 * found at offset 0x09. Instead check the Deice ID (DVID)
981 * register for a 2, 4 or 8 port UART.
982 */
983 if (up->port.flags & UPF_EXAR_EFR) {
984 status1 = serial_in(up, UART_EXAR_DVID);
985 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
986 DEBUG_AUTOCONF("Exar XR17V35x ");
987 up->port.type = PORT_XR17V35X;
988 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
989 UART_CAP_SLEEP;
990
991 return;
992 }
993
994 }
995
996 /*
997 * Check for presence of the EFR when DLAB is set.
998 * Only ST16C650V1 UARTs pass this test.
999 */
1000 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001 if (serial_in(up, UART_EFR) == 0) {
1002 serial_out(up, UART_EFR, 0xA8);
1003 if (serial_in(up, UART_EFR) != 0) {
1004 DEBUG_AUTOCONF("EFRv1 ");
1005 up->port.type = PORT_16650;
1006 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1007 } else {
1008 serial_out(up, UART_LCR, 0);
1009 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1010 UART_FCR7_64BYTE);
1011 status1 = serial_in(up, UART_IIR) >> 5;
1012 serial_out(up, UART_FCR, 0);
1013 serial_out(up, UART_LCR, 0);
1014
1015 if (status1 == 7)
1016 up->port.type = PORT_16550A_FSL64;
1017 else
1018 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1019 }
1020 serial_out(up, UART_EFR, 0);
1021 return;
1022 }
1023
1024 /*
1025 * Maybe it requires 0xbf to be written to the LCR.
1026 * (other ST16C650V2 UARTs, TI16C752A, etc)
1027 */
1028 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1029 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1030 DEBUG_AUTOCONF("EFRv2 ");
1031 autoconfig_has_efr(up);
1032 return;
1033 }
1034
1035 /*
1036 * Check for a National Semiconductor SuperIO chip.
1037 * Attempt to switch to bank 2, read the value of the LOOP bit
1038 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1039 * switch back to bank 2, read it from EXCR1 again and check
1040 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1041 */
1042 serial_out(up, UART_LCR, 0);
1043 status1 = serial_in(up, UART_MCR);
1044 serial_out(up, UART_LCR, 0xE0);
1045 status2 = serial_in(up, 0x02); /* EXCR1 */
1046
1047 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1048 serial_out(up, UART_LCR, 0);
1049 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1050 serial_out(up, UART_LCR, 0xE0);
1051 status2 = serial_in(up, 0x02); /* EXCR1 */
1052 serial_out(up, UART_LCR, 0);
1053 serial_out(up, UART_MCR, status1);
1054
1055 if ((status2 ^ status1) & UART_MCR_LOOP) {
1056 unsigned short quot;
1057
1058 serial_out(up, UART_LCR, 0xE0);
1059
1060 quot = serial_dl_read(up);
1061 quot <<= 3;
1062
1063 if (ns16550a_goto_highspeed(up))
1064 serial_dl_write(up, quot);
1065
1066 serial_out(up, UART_LCR, 0);
1067
1068 up->port.uartclk = 921600*16;
1069 up->port.type = PORT_NS16550A;
1070 up->capabilities |= UART_NATSEMI;
1071 return;
1072 }
1073 }
1074
1075 /*
1076 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1077 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1078 * Try setting it with and without DLAB set. Cheap clones
1079 * set bit 5 without DLAB set.
1080 */
1081 serial_out(up, UART_LCR, 0);
1082 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1083 status1 = serial_in(up, UART_IIR) >> 5;
1084 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1085 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1086 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1087 status2 = serial_in(up, UART_IIR) >> 5;
1088 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1089 serial_out(up, UART_LCR, 0);
1090
1091 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1092
1093 if (status1 == 6 && status2 == 7) {
1094 up->port.type = PORT_16750;
1095 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1096 return;
1097 }
1098
1099 /*
1100 * Try writing and reading the UART_IER_UUE bit (b6).
1101 * If it works, this is probably one of the Xscale platform's
1102 * internal UARTs.
1103 * We're going to explicitly set the UUE bit to 0 before
1104 * trying to write and read a 1 just to make sure it's not
1105 * already a 1 and maybe locked there before we even start start.
1106 */
1107 iersave = serial_in(up, UART_IER);
1108 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1109 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1110 /*
1111 * OK it's in a known zero state, try writing and reading
1112 * without disturbing the current state of the other bits.
1113 */
1114 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1115 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1116 /*
1117 * It's an Xscale.
1118 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1119 */
1120 DEBUG_AUTOCONF("Xscale ");
1121 up->port.type = PORT_XSCALE;
1122 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1123 return;
1124 }
1125 } else {
1126 /*
1127 * If we got here we couldn't force the IER_UUE bit to 0.
1128 * Log it and continue.
1129 */
1130 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1131 }
1132 serial_out(up, UART_IER, iersave);
1133
1134 /*
1135 * Exar uarts have EFR in a weird location
1136 */
1137 if (up->port.flags & UPF_EXAR_EFR) {
1138 DEBUG_AUTOCONF("Exar XR17D15x ");
1139 up->port.type = PORT_XR17D15X;
1140 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1141 UART_CAP_SLEEP;
1142
1143 return;
1144 }
1145
1146 /*
1147 * We distinguish between 16550A and U6 16550A by counting
1148 * how many bytes are in the FIFO.
1149 */
1150 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1151 up->port.type = PORT_U6_16550A;
1152 up->capabilities |= UART_CAP_AFE;
1153 }
1154}
1155
1156/*
1157 * This routine is called by rs_init() to initialize a specific serial
1158 * port. It determines what type of UART chip this serial port is
1159 * using: 8250, 16450, 16550, 16550A. The important question is
1160 * whether or not this UART is a 16550A or not, since this will
1161 * determine whether or not we can use its FIFO features or not.
1162 */
1163static void autoconfig(struct uart_8250_port *up)
1164{
1165 unsigned char status1, scratch, scratch2, scratch3;
1166 unsigned char save_lcr, save_mcr;
1167 struct uart_port *port = &up->port;
1168 unsigned long flags;
1169 unsigned int old_capabilities;
1170
1171 if (!port->iobase && !port->mapbase && !port->membase)
1172 return;
1173
1174 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1175 serial_index(port), port->iobase, port->membase);
1176
1177 /*
1178 * We really do need global IRQs disabled here - we're going to
1179 * be frobbing the chips IRQ enable register to see if it exists.
1180 */
1181 spin_lock_irqsave(&port->lock, flags);
1182
1183 up->capabilities = 0;
1184 up->bugs = 0;
1185
1186 if (!(port->flags & UPF_BUGGY_UART)) {
1187 /*
1188 * Do a simple existence test first; if we fail this,
1189 * there's no point trying anything else.
1190 *
1191 * 0x80 is used as a nonsense port to prevent against
1192 * false positives due to ISA bus float. The
1193 * assumption is that 0x80 is a non-existent port;
1194 * which should be safe since include/asm/io.h also
1195 * makes this assumption.
1196 *
1197 * Note: this is safe as long as MCR bit 4 is clear
1198 * and the device is in "PC" mode.
1199 */
1200 scratch = serial_in(up, UART_IER);
1201 serial_out(up, UART_IER, 0);
1202#ifdef __i386__
1203 outb(0xff, 0x080);
1204#endif
1205 /*
1206 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1207 * 16C754B) allow only to modify them if an EFR bit is set.
1208 */
1209 scratch2 = serial_in(up, UART_IER) & 0x0f;
1210 serial_out(up, UART_IER, 0x0F);
1211#ifdef __i386__
1212 outb(0, 0x080);
1213#endif
1214 scratch3 = serial_in(up, UART_IER) & 0x0f;
1215 serial_out(up, UART_IER, scratch);
1216 if (scratch2 != 0 || scratch3 != 0x0F) {
1217 /*
1218 * We failed; there's nothing here
1219 */
1220 spin_unlock_irqrestore(&port->lock, flags);
1221 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1222 scratch2, scratch3);
1223 goto out;
1224 }
1225 }
1226
1227 save_mcr = serial_in(up, UART_MCR);
1228 save_lcr = serial_in(up, UART_LCR);
1229
1230 /*
1231 * Check to see if a UART is really there. Certain broken
1232 * internal modems based on the Rockwell chipset fail this
1233 * test, because they apparently don't implement the loopback
1234 * test mode. So this test is skipped on the COM 1 through
1235 * COM 4 ports. This *should* be safe, since no board
1236 * manufacturer would be stupid enough to design a board
1237 * that conflicts with COM 1-4 --- we hope!
1238 */
1239 if (!(port->flags & UPF_SKIP_TEST)) {
1240 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1241 status1 = serial_in(up, UART_MSR) & 0xF0;
1242 serial_out(up, UART_MCR, save_mcr);
1243 if (status1 != 0x90) {
1244 spin_unlock_irqrestore(&port->lock, flags);
1245 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1246 status1);
1247 goto out;
1248 }
1249 }
1250
1251 /*
1252 * We're pretty sure there's a port here. Lets find out what
1253 * type of port it is. The IIR top two bits allows us to find
1254 * out if it's 8250 or 16450, 16550, 16550A or later. This
1255 * determines what we test for next.
1256 *
1257 * We also initialise the EFR (if any) to zero for later. The
1258 * EFR occupies the same register location as the FCR and IIR.
1259 */
1260 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1261 serial_out(up, UART_EFR, 0);
1262 serial_out(up, UART_LCR, 0);
1263
1264 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1265 scratch = serial_in(up, UART_IIR) >> 6;
1266
1267 switch (scratch) {
1268 case 0:
1269 autoconfig_8250(up);
1270 break;
1271 case 1:
1272 port->type = PORT_UNKNOWN;
1273 break;
1274 case 2:
1275 port->type = PORT_16550;
1276 break;
1277 case 3:
1278 autoconfig_16550a(up);
1279 break;
1280 }
1281
1282#ifdef CONFIG_SERIAL_8250_RSA
1283 /*
1284 * Only probe for RSA ports if we got the region.
1285 */
1286 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1287 __enable_rsa(up))
1288 port->type = PORT_RSA;
1289#endif
1290
1291 serial_out(up, UART_LCR, save_lcr);
1292
1293 port->fifosize = uart_config[up->port.type].fifo_size;
1294 old_capabilities = up->capabilities;
1295 up->capabilities = uart_config[port->type].flags;
1296 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1297
1298 if (port->type == PORT_UNKNOWN)
1299 goto out_lock;
1300
1301 /*
1302 * Reset the UART.
1303 */
1304#ifdef CONFIG_SERIAL_8250_RSA
1305 if (port->type == PORT_RSA)
1306 serial_out(up, UART_RSA_FRR, 0);
1307#endif
1308 serial_out(up, UART_MCR, save_mcr);
1309 serial8250_clear_fifos(up);
1310 serial_in(up, UART_RX);
1311 if (up->capabilities & UART_CAP_UUE)
1312 serial_out(up, UART_IER, UART_IER_UUE);
1313 else
1314 serial_out(up, UART_IER, 0);
1315
1316out_lock:
1317 spin_unlock_irqrestore(&port->lock, flags);
1318 if (up->capabilities != old_capabilities) {
9f59fbf0 1319 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
b6830f6d
PH		 1320 serial_index(port), old_capabilities,
1321 up->capabilities);
1322 }
1323out:
1324 DEBUG_AUTOCONF("iir=%d ", scratch);
1325 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1326}
1327
1328static void autoconfig_irq(struct uart_8250_port *up)
1329{
1330 struct uart_port *port = &up->port;
1331 unsigned char save_mcr, save_ier;
1332 unsigned char save_ICP = 0;
1333 unsigned int ICP = 0;
1334 unsigned long irqs;
1335 int irq;
1336
1337 if (port->flags & UPF_FOURPORT) {
1338 ICP = (port->iobase & 0xfe0) | 0x1f;
1339 save_ICP = inb_p(ICP);
1340 outb_p(0x80, ICP);
1341 inb_p(ICP);
1342 }
1343
9a23a1d1
TK		 1344 if (uart_console(port))
1345 console_lock();
1346
b6830f6d
PH		 1347 /* forget possible initially masked and pending IRQ */
1348 probe_irq_off(probe_irq_on());
1349 save_mcr = serial_in(up, UART_MCR);
1350 save_ier = serial_in(up, UART_IER);
1351 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1352
1353 irqs = probe_irq_on();
1354 serial_out(up, UART_MCR, 0);
1355 udelay(10);
1356 if (port->flags & UPF_FOURPORT) {
1357 serial_out(up, UART_MCR,
1358 UART_MCR_DTR | UART_MCR_RTS);
1359 } else {
1360 serial_out(up, UART_MCR,
1361 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1362 }
1363 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1364 serial_in(up, UART_LSR);
1365 serial_in(up, UART_RX);
1366 serial_in(up, UART_IIR);
1367 serial_in(up, UART_MSR);
1368 serial_out(up, UART_TX, 0xFF);
1369 udelay(20);
1370 irq = probe_irq_off(irqs);
1371
1372 serial_out(up, UART_MCR, save_mcr);
1373 serial_out(up, UART_IER, save_ier);
1374
1375 if (port->flags & UPF_FOURPORT)
1376 outb_p(save_ICP, ICP);
1377
9a23a1d1
TK		 1378 if (uart_console(port))
1379 console_unlock();
1380
b6830f6d
PH		 1381 port->irq = (irq > 0) ? irq : 0;
1382}
1383
a07a70bc
MK		 1384static void serial8250_stop_rx(struct uart_port *port)
1385{
1386 struct uart_8250_port *up = up_to_u8250p(port);
1387
1388 serial8250_rpm_get(up);
1389
1390 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1391 up->port.read_status_mask &= ~UART_LSR_DR;
1392 serial_port_out(port, UART_IER, up->ier);
1393
1394 serial8250_rpm_put(up);
1395}
1396
e490c914
MK		 1397static void __do_stop_tx_rs485(struct uart_8250_port *p)
1398{
1399 if (!p->em485)
1400 return;
1401
1402 serial8250_em485_rts_after_send(p);
1403 /*
1404 * Empty the RX FIFO, we are not interested in anything
1405 * received during the half-duplex transmission.
1406 */
1407 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX))
1408 serial8250_clear_fifos(p);
1409}
1410
1411static void serial8250_em485_handle_stop_tx(unsigned long arg)
1412{
1413 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1414 struct uart_8250_em485 *em485 = p->em485;
1415 unsigned long flags;
1416
1417 spin_lock_irqsave(&p->port.lock, flags);
1418 if (em485 &&
1419 em485->active_timer == &em485->stop_tx_timer) {
1420 __do_stop_tx_rs485(p);
1421 em485->active_timer = NULL;
1422 }
1423 spin_unlock_irqrestore(&p->port.lock, flags);
1424}
1425
1426static void __stop_tx_rs485(struct uart_8250_port *p)
1427{
1428 struct uart_8250_em485 *em485 = p->em485;
1429
1430 if (!em485)
1431 return;
1432
1433 /*
1434 * __do_stop_tx_rs485 is going to set RTS according to config
1435 * AND flush RX FIFO if required.
1436 */
1437 if (p->port.rs485.delay_rts_after_send > 0) {
1438 em485->active_timer = &em485->stop_tx_timer;
1439 mod_timer(&em485->stop_tx_timer, jiffies +
1440 p->port.rs485.delay_rts_after_send * HZ / 1000);
1441 } else {
1442 __do_stop_tx_rs485(p);
1443 }
1444}
1445
1446static inline void __do_stop_tx(struct uart_8250_port *p)
b6830f6d
PH		 1447{
1448 if (p->ier & UART_IER_THRI) {
1449 p->ier &= ~UART_IER_THRI;
1450 serial_out(p, UART_IER, p->ier);
1451 serial8250_rpm_put_tx(p);
1452 }
1453}
1454
e490c914
MK		 1455static inline void __stop_tx(struct uart_8250_port *p)
1456{
1457 struct uart_8250_em485 *em485 = p->em485;
1458
1459 if (em485) {
1460 unsigned char lsr = serial_in(p, UART_LSR);
1461 /*
1462 * To provide required timeing and allow FIFO transfer,
1463 * __stop_tx_rs485 must be called only when both FIFO and
1464 * shift register are empty. It is for device driver to enable
1465 * interrupt on TEMT.
1466 */
1467 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1468 return;
1469
1470 del_timer(&em485->start_tx_timer);
1471 em485->active_timer = NULL;
1472 }
1473 __do_stop_tx(p);
1474 __stop_tx_rs485(p);
1475}
1476
b6830f6d
PH		 1477static void serial8250_stop_tx(struct uart_port *port)
1478{
1479 struct uart_8250_port *up = up_to_u8250p(port);
1480
1481 serial8250_rpm_get(up);
1482 __stop_tx(up);
1483
1484 /*
1485 * We really want to stop the transmitter from sending.
1486 */
1487 if (port->type == PORT_16C950) {
1488 up->acr |= UART_ACR_TXDIS;
1489 serial_icr_write(up, UART_ACR, up->acr);
1490 }
1491 serial8250_rpm_put(up);
1492}
1493
e490c914 1494static inline void __start_tx(struct uart_port *port)
b6830f6d
PH		 1495{
1496 struct uart_8250_port *up = up_to_u8250p(port);
1497
b6830f6d
PH		 1498 if (up->dma && !up->dma->tx_dma(up))
1499 return;
1500
1501 if (!(up->ier & UART_IER_THRI)) {
1502 up->ier |= UART_IER_THRI;
1503 serial_port_out(port, UART_IER, up->ier);
1504
1505 if (up->bugs & UART_BUG_TXEN) {
1506 unsigned char lsr;
1a33e342 1507
b6830f6d
PH		 1508 lsr = serial_in(up, UART_LSR);
1509 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1510 if (lsr & UART_LSR_THRE)
1511 serial8250_tx_chars(up);
1512 }
1513 }
1514
1515 /*
1516 * Re-enable the transmitter if we disabled it.
1517 */
1518 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1519 up->acr &= ~UART_ACR_TXDIS;
1520 serial_icr_write(up, UART_ACR, up->acr);
1521 }
1522}
1523
e490c914
MK		 1524static inline void start_tx_rs485(struct uart_port *port)
1525{
1526 struct uart_8250_port *up = up_to_u8250p(port);
1527 struct uart_8250_em485 *em485 = up->em485;
1528 unsigned char mcr;
1529
1530 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1531 serial8250_stop_rx(&up->port);
1532
1533 del_timer(&em485->stop_tx_timer);
1534 em485->active_timer = NULL;
1535
1536 mcr = serial_in(up, UART_MCR);
1537 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1538 !!(mcr & UART_MCR_RTS)) {
1539 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1540 mcr |= UART_MCR_RTS;
1541 else
1542 mcr &= ~UART_MCR_RTS;
1543 serial_out(up, UART_MCR, mcr);
1544
1545 if (up->port.rs485.delay_rts_before_send > 0) {
1546 em485->active_timer = &em485->start_tx_timer;
1547 mod_timer(&em485->start_tx_timer, jiffies +
1548 up->port.rs485.delay_rts_before_send * HZ / 1000);
1549 return;
1550 }
1551 }
1552
1553 __start_tx(port);
1554}
1555
1556static void serial8250_em485_handle_start_tx(unsigned long arg)
1557{
1558 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1559 struct uart_8250_em485 *em485 = p->em485;
1560 unsigned long flags;
1561
1562 spin_lock_irqsave(&p->port.lock, flags);
1563 if (em485 &&
1564 em485->active_timer == &em485->start_tx_timer) {
1565 __start_tx(&p->port);
1566 em485->active_timer = NULL;
1567 }
1568 spin_unlock_irqrestore(&p->port.lock, flags);
1569}
1570
1571static void serial8250_start_tx(struct uart_port *port)
1572{
1573 struct uart_8250_port *up = up_to_u8250p(port);
1574 struct uart_8250_em485 *em485 = up->em485;
1575
1576 serial8250_rpm_get_tx(up);
1577
1578 if (em485 &&
1579 em485->active_timer == &em485->start_tx_timer)
1580 return;
1581
1582 if (em485)
1583 start_tx_rs485(port);
1584 else
1585 __start_tx(port);
1586}
1587
b6830f6d
PH		 1588static void serial8250_throttle(struct uart_port *port)
1589{
1590 port->throttle(port);
1591}
1592
1593static void serial8250_unthrottle(struct uart_port *port)
1594{
1595 port->unthrottle(port);
1596}
1597
b6830f6d
PH		 1598static void serial8250_disable_ms(struct uart_port *port)
1599{
013e3586 1600 struct uart_8250_port *up = up_to_u8250p(port);
b6830f6d
PH		 1601
1602 /* no MSR capabilities */
1603 if (up->bugs & UART_BUG_NOMSR)
1604 return;
1605
1606 up->ier &= ~UART_IER_MSI;
1607 serial_port_out(port, UART_IER, up->ier);
1608}
1609
1610static void serial8250_enable_ms(struct uart_port *port)
1611{
1612 struct uart_8250_port *up = up_to_u8250p(port);
1613
1614 /* no MSR capabilities */
1615 if (up->bugs & UART_BUG_NOMSR)
1616 return;
1617
1618 up->ier |= UART_IER_MSI;
1619
1620 serial8250_rpm_get(up);
1621 serial_port_out(port, UART_IER, up->ier);
1622 serial8250_rpm_put(up);
1623}
1624
3f6b3ce0
PH		 1625static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1626{
1627 struct uart_port *port = &up->port;
1628 unsigned char ch;
1629 char flag = TTY_NORMAL;
1630
1631 if (likely(lsr & UART_LSR_DR))
1632 ch = serial_in(up, UART_RX);
1633 else
1634 /*
1635 * Intel 82571 has a Serial Over Lan device that will
1636 * set UART_LSR_BI without setting UART_LSR_DR when
1637 * it receives a break. To avoid reading from the
1638 * receive buffer without UART_LSR_DR bit set, we
1639 * just force the read character to be 0
1640 */
1641 ch = 0;
1642
1643 port->icount.rx++;
1644
1645 lsr |= up->lsr_saved_flags;
1646 up->lsr_saved_flags = 0;
1647
1648 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1649 if (lsr & UART_LSR_BI) {
1650 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1651 port->icount.brk++;
1652 /*
1653 * We do the SysRQ and SAK checking
1654 * here because otherwise the break
1655 * may get masked by ignore_status_mask
1656 * or read_status_mask.
1657 */
1658 if (uart_handle_break(port))
1659 return;
1660 } else if (lsr & UART_LSR_PE)
1661 port->icount.parity++;
1662 else if (lsr & UART_LSR_FE)
1663 port->icount.frame++;
1664 if (lsr & UART_LSR_OE)
1665 port->icount.overrun++;
1666
1667 /*
1668 * Mask off conditions which should be ignored.
1669 */
1670 lsr &= port->read_status_mask;
1671
1672 if (lsr & UART_LSR_BI) {
1673 DEBUG_INTR("handling break....");
1674 flag = TTY_BREAK;
1675 } else if (lsr & UART_LSR_PE)
1676 flag = TTY_PARITY;
1677 else if (lsr & UART_LSR_FE)
1678 flag = TTY_FRAME;
1679 }
1680 if (uart_handle_sysrq_char(port, ch))
1681 return;
1682
1683 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1684}
1685
b6830f6d
PH		 1686/*
1687 * serial8250_rx_chars: processes according to the passed in LSR
1688 * value, and returns the remaining LSR bits not handled
1689 * by this Rx routine.
1690 */
d22f8f10 1691unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
b6830f6d
PH		 1692{
1693 struct uart_port *port = &up->port;
b6830f6d 1694 int max_count = 256;
b6830f6d
PH		 1695
1696 do {
3f6b3ce0 1697 serial8250_read_char(up, lsr);
d22f8f10
PH		 1698 if (--max_count == 0)
1699 break;
b6830f6d 1700 lsr = serial_in(up, UART_LSR);
d22f8f10 1701 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
6a597a38 1702
b6830f6d 1703 tty_flip_buffer_push(&port->state->port);
b6830f6d
PH		 1704 return lsr;
1705}
1706EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1707
1708void serial8250_tx_chars(struct uart_8250_port *up)
1709{
1710 struct uart_port *port = &up->port;
1711 struct circ_buf *xmit = &port->state->xmit;
1712 int count;
1713
1714 if (port->x_char) {
1715 serial_out(up, UART_TX, port->x_char);
1716 port->icount.tx++;
1717 port->x_char = 0;
1718 return;
1719 }
1720 if (uart_tx_stopped(port)) {
1721 serial8250_stop_tx(port);
1722 return;
1723 }
1724 if (uart_circ_empty(xmit)) {
1725 __stop_tx(up);
1726 return;
1727 }
1728
1729 count = up->tx_loadsz;
1730 do {
1731 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1732 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1733 port->icount.tx++;
1734 if (uart_circ_empty(xmit))
1735 break;
cee10c8c
PH		 1736 if ((up->capabilities & UART_CAP_HFIFO) &&
1737 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1738 break;
b6830f6d
PH		 1739 } while (--count > 0);
1740
1741 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1742 uart_write_wakeup(port);
1743
1744 DEBUG_INTR("THRE...");
1745
1746 /*
1747 * With RPM enabled, we have to wait until the FIFO is empty before the
1748 * HW can go idle. So we get here once again with empty FIFO and disable
1749 * the interrupt and RPM in __stop_tx()
1750 */
1751 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1752 __stop_tx(up);
1753}
1754EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1755
1756/* Caller holds uart port lock */
1757unsigned int serial8250_modem_status(struct uart_8250_port *up)
1758{
1759 struct uart_port *port = &up->port;
1760 unsigned int status = serial_in(up, UART_MSR);
1761
1762 status |= up->msr_saved_flags;
1763 up->msr_saved_flags = 0;
1764 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1765 port->state != NULL) {
1766 if (status & UART_MSR_TERI)
1767 port->icount.rng++;
1768 if (status & UART_MSR_DDSR)
1769 port->icount.dsr++;
1770 if (status & UART_MSR_DDCD)
1771 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1772 if (status & UART_MSR_DCTS)
1773 uart_handle_cts_change(port, status & UART_MSR_CTS);
1774
1775 wake_up_interruptible(&port->state->port.delta_msr_wait);
1776 }
1777
1778 return status;
1779}
1780EXPORT_SYMBOL_GPL(serial8250_modem_status);
1781
1782/*
1783 * This handles the interrupt from one port.
1784 */
1785int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1786{
1787 unsigned char status;
1788 unsigned long flags;
1789 struct uart_8250_port *up = up_to_u8250p(port);
1790 int dma_err = 0;
1791
1792 if (iir & UART_IIR_NO_INT)
1793 return 0;
1794
1795 spin_lock_irqsave(&port->lock, flags);
1796
1797 status = serial_port_in(port, UART_LSR);
1798
1799 DEBUG_INTR("status = %x...", status);
1800
1801 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1802 if (up->dma)
1803 dma_err = up->dma->rx_dma(up, iir);
1804
1805 if (!up->dma || dma_err)
1806 status = serial8250_rx_chars(up, status);
1807 }
1808 serial8250_modem_status(up);
1809 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1810 (status & UART_LSR_THRE))
1811 serial8250_tx_chars(up);
1812
1813 spin_unlock_irqrestore(&port->lock, flags);
1814 return 1;
1815}
1816EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1817
1818static int serial8250_default_handle_irq(struct uart_port *port)
1819{
1820 struct uart_8250_port *up = up_to_u8250p(port);
1821 unsigned int iir;
1822 int ret;
1823
1824 serial8250_rpm_get(up);
1825
1826 iir = serial_port_in(port, UART_IIR);
1827 ret = serial8250_handle_irq(port, iir);
1828
1829 serial8250_rpm_put(up);
1830 return ret;
1831}
1832
1833/*
1834 * These Exar UARTs have an extra interrupt indicator that could
1835 * fire for a few unimplemented interrupts. One of which is a
1836 * wakeup event when coming out of sleep. Put this here just
1837 * to be on the safe side that these interrupts don't go unhandled.
1838 */
1839static int exar_handle_irq(struct uart_port *port)
1840{
1841 unsigned char int0, int1, int2, int3;
1842 unsigned int iir = serial_port_in(port, UART_IIR);
1843 int ret;
1844
1845 ret = serial8250_handle_irq(port, iir);
1846
1847 if ((port->type == PORT_XR17V35X) ||
1848 (port->type == PORT_XR17D15X)) {
1849 int0 = serial_port_in(port, 0x80);
1850 int1 = serial_port_in(port, 0x81);
1851 int2 = serial_port_in(port, 0x82);
1852 int3 = serial_port_in(port, 0x83);
1853 }
1854
1855 return ret;
1856}
1857
1858static unsigned int serial8250_tx_empty(struct uart_port *port)
1859{
1860 struct uart_8250_port *up = up_to_u8250p(port);
1861 unsigned long flags;
1862 unsigned int lsr;
1863
1864 serial8250_rpm_get(up);
1865
1866 spin_lock_irqsave(&port->lock, flags);
1867 lsr = serial_port_in(port, UART_LSR);
1868 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1869 spin_unlock_irqrestore(&port->lock, flags);
1870
1871 serial8250_rpm_put(up);
1872
1873 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1874}
1875
1876static unsigned int serial8250_get_mctrl(struct uart_port *port)
1877{
1878 struct uart_8250_port *up = up_to_u8250p(port);
1879 unsigned int status;
1880 unsigned int ret;
1881
1882 serial8250_rpm_get(up);
1883 status = serial8250_modem_status(up);
1884 serial8250_rpm_put(up);
1885
1886 ret = 0;
1887 if (status & UART_MSR_DCD)
1888 ret |= TIOCM_CAR;
1889 if (status & UART_MSR_RI)
1890 ret |= TIOCM_RNG;
1891 if (status & UART_MSR_DSR)
1892 ret |= TIOCM_DSR;
1893 if (status & UART_MSR_CTS)
1894 ret |= TIOCM_CTS;
1895 return ret;
1896}
1897
1898void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1899{
1900 struct uart_8250_port *up = up_to_u8250p(port);
1901 unsigned char mcr = 0;
1902
1903 if (mctrl & TIOCM_RTS)
1904 mcr |= UART_MCR_RTS;
1905 if (mctrl & TIOCM_DTR)
1906 mcr |= UART_MCR_DTR;
1907 if (mctrl & TIOCM_OUT1)
1908 mcr |= UART_MCR_OUT1;
1909 if (mctrl & TIOCM_OUT2)
1910 mcr |= UART_MCR_OUT2;
1911 if (mctrl & TIOCM_LOOP)
1912 mcr |= UART_MCR_LOOP;
1913
1914 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1915
1916 serial_port_out(port, UART_MCR, mcr);
1917}
1918EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1919
1920static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1921{
1922 if (port->set_mctrl)
1923 port->set_mctrl(port, mctrl);
1924 else
1925 serial8250_do_set_mctrl(port, mctrl);
1926}
1927
1928static void serial8250_break_ctl(struct uart_port *port, int break_state)
1929{
1930 struct uart_8250_port *up = up_to_u8250p(port);
1931 unsigned long flags;
1932
1933 serial8250_rpm_get(up);
1934 spin_lock_irqsave(&port->lock, flags);
1935 if (break_state == -1)
1936 up->lcr |= UART_LCR_SBC;
1937 else
1938 up->lcr &= ~UART_LCR_SBC;
1939 serial_port_out(port, UART_LCR, up->lcr);
1940 spin_unlock_irqrestore(&port->lock, flags);
1941 serial8250_rpm_put(up);
1942}
1943
1944/*
1945 * Wait for transmitter & holding register to empty
1946 */
1947static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1948{
1949 unsigned int status, tmout = 10000;
1950
1951 /* Wait up to 10ms for the character(s) to be sent. */
1952 for (;;) {
1953 status = serial_in(up, UART_LSR);
1954
1955 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1956
1957 if ((status & bits) == bits)
1958 break;
1959 if (--tmout == 0)
1960 break;
1961 udelay(1);
1962 }
1963
1964 /* Wait up to 1s for flow control if necessary */
1965 if (up->port.flags & UPF_CONS_FLOW) {
1966 unsigned int tmout;
1a33e342 1967
b6830f6d
PH		 1968 for (tmout = 1000000; tmout; tmout--) {
1969 unsigned int msr = serial_in(up, UART_MSR);
1970 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1971 if (msr & UART_MSR_CTS)
1972 break;
1973 udelay(1);
1974 touch_nmi_watchdog();
1975 }
1976 }
1977}
1978
1979#ifdef CONFIG_CONSOLE_POLL
1980/*
1981 * Console polling routines for writing and reading from the uart while
1982 * in an interrupt or debug context.
1983 */
1984
1985static int serial8250_get_poll_char(struct uart_port *port)
1986{
1987 struct uart_8250_port *up = up_to_u8250p(port);
1988 unsigned char lsr;
1989 int status;
1990
1991 serial8250_rpm_get(up);
1992
1993 lsr = serial_port_in(port, UART_LSR);
1994
1995 if (!(lsr & UART_LSR_DR)) {
1996 status = NO_POLL_CHAR;
1997 goto out;
1998 }
1999
2000 status = serial_port_in(port, UART_RX);
2001out:
2002 serial8250_rpm_put(up);
2003 return status;
2004}
2005
2006
2007static void serial8250_put_poll_char(struct uart_port *port,
2008 unsigned char c)
2009{
2010 unsigned int ier;
2011 struct uart_8250_port *up = up_to_u8250p(port);
2012
2013 serial8250_rpm_get(up);
2014 /*
2015 * First save the IER then disable the interrupts
2016 */
2017 ier = serial_port_in(port, UART_IER);
2018 if (up->capabilities & UART_CAP_UUE)
2019 serial_port_out(port, UART_IER, UART_IER_UUE);
2020 else
2021 serial_port_out(port, UART_IER, 0);
2022
2023 wait_for_xmitr(up, BOTH_EMPTY);
2024 /*
2025 * Send the character out.
2026 */
2027 serial_port_out(port, UART_TX, c);
2028
2029 /*
2030 * Finally, wait for transmitter to become empty
2031 * and restore the IER
2032 */
2033 wait_for_xmitr(up, BOTH_EMPTY);
2034 serial_port_out(port, UART_IER, ier);
2035 serial8250_rpm_put(up);
2036}
2037
2038#endif /* CONFIG_CONSOLE_POLL */
2039
2040int serial8250_do_startup(struct uart_port *port)
2041{
2042 struct uart_8250_port *up = up_to_u8250p(port);
2043 unsigned long flags;
2044 unsigned char lsr, iir;
2045 int retval;
2046
b6830f6d
PH		 2047 if (!port->fifosize)
2048 port->fifosize = uart_config[port->type].fifo_size;
2049 if (!up->tx_loadsz)
2050 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2051 if (!up->capabilities)
2052 up->capabilities = uart_config[port->type].flags;
2053 up->mcr = 0;
2054
2055 if (port->iotype != up->cur_iotype)
2056 set_io_from_upio(port);
2057
2058 serial8250_rpm_get(up);
2059 if (port->type == PORT_16C950) {
2060 /* Wake up and initialize UART */
2061 up->acr = 0;
2062 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2063 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2064 serial_port_out(port, UART_IER, 0);
2065 serial_port_out(port, UART_LCR, 0);
2066 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2067 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2068 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2069 serial_port_out(port, UART_LCR, 0);
2070 }
2071
2072#ifdef CONFIG_SERIAL_8250_RSA
2073 /*
2074 * If this is an RSA port, see if we can kick it up to the
2075 * higher speed clock.
2076 */
2077 enable_rsa(up);
2078#endif
da891641
JR		 2079
2080 if (port->type == PORT_XR17V35X) {
2081 /*
2082 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2083 * MCR [7:5] and MSR [7:0]
2084 */
2085 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2086
2087 /*
2088 * Make sure all interrups are masked until initialization is
2089 * complete and the FIFOs are cleared
2090 */
2091 serial_port_out(port, UART_IER, 0);
2092 }
2093
b6830f6d
PH		 2094 /*
2095 * Clear the FIFO buffers and disable them.
2096 * (they will be reenabled in set_termios())
2097 */
2098 serial8250_clear_fifos(up);
2099
2100 /*
2101 * Clear the interrupt registers.
2102 */
2103 serial_port_in(port, UART_LSR);
2104 serial_port_in(port, UART_RX);
2105 serial_port_in(port, UART_IIR);
2106 serial_port_in(port, UART_MSR);
2107
2108 /*
2109 * At this point, there's no way the LSR could still be 0xff;
2110 * if it is, then bail out, because there's likely no UART
2111 * here.
2112 */
2113 if (!(port->flags & UPF_BUGGY_UART) &&
2114 (serial_port_in(port, UART_LSR) == 0xff)) {
2115 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2116 serial_index(port));
2117 retval = -ENODEV;
2118 goto out;
2119 }
2120
2121 /*
2122 * For a XR16C850, we need to set the trigger levels
2123 */
2124 if (port->type == PORT_16850) {
2125 unsigned char fctr;
2126
2127 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2128
2129 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2130 serial_port_out(port, UART_FCTR,
2131 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2132 serial_port_out(port, UART_TRG, UART_TRG_96);
2133 serial_port_out(port, UART_FCTR,
2134 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2135 serial_port_out(port, UART_TRG, UART_TRG_96);
2136
2137 serial_port_out(port, UART_LCR, 0);
2138 }
2139
2140 if (port->irq) {
2141 unsigned char iir1;
2142 /*
2143 * Test for UARTs that do not reassert THRE when the
2144 * transmitter is idle and the interrupt has already
2145 * been cleared. Real 16550s should always reassert
2146 * this interrupt whenever the transmitter is idle and
2147 * the interrupt is enabled. Delays are necessary to
2148 * allow register changes to become visible.
2149 */
2150 spin_lock_irqsave(&port->lock, flags);
2151 if (up->port.irqflags & IRQF_SHARED)
2152 disable_irq_nosync(port->irq);
2153
2154 wait_for_xmitr(up, UART_LSR_THRE);
2155 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2156 udelay(1); /* allow THRE to set */
2157 iir1 = serial_port_in(port, UART_IIR);
2158 serial_port_out(port, UART_IER, 0);
2159 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2160 udelay(1); /* allow a working UART time to re-assert THRE */
2161 iir = serial_port_in(port, UART_IIR);
2162 serial_port_out(port, UART_IER, 0);
2163
2164 if (port->irqflags & IRQF_SHARED)
2165 enable_irq(port->irq);
2166 spin_unlock_irqrestore(&port->lock, flags);
2167
2168 /*
2169 * If the interrupt is not reasserted, or we otherwise
2170 * don't trust the iir, setup a timer to kick the UART
2171 * on a regular basis.
2172 */
2173 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2174 up->port.flags & UPF_BUG_THRE) {
2175 up->bugs |= UART_BUG_THRE;
2176 }
2177 }
2178
2179 retval = up->ops->setup_irq(up);
2180 if (retval)
2181 goto out;
2182
2183 /*
2184 * Now, initialize the UART
2185 */
2186 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2187
2188 spin_lock_irqsave(&port->lock, flags);
2189 if (up->port.flags & UPF_FOURPORT) {
2190 if (!up->port.irq)
2191 up->port.mctrl |= TIOCM_OUT1;
2192 } else
2193 /*
2194 * Most PC uarts need OUT2 raised to enable interrupts.
2195 */
2196 if (port->irq)
2197 up->port.mctrl |= TIOCM_OUT2;
2198
2199 serial8250_set_mctrl(port, port->mctrl);
2200
740dc2de
AW		 2201 /*
2202 * Serial over Lan (SoL) hack:
2203 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2204 * used for Serial Over Lan. Those chips take a longer time than a
2205 * normal serial device to signalize that a transmission data was
2206 * queued. Due to that, the above test generally fails. One solution
2207 * would be to delay the reading of iir. However, this is not
2208 * reliable, since the timeout is variable. So, let's just don't
2209 * test if we receive TX irq. This way, we'll never enable
2210 * UART_BUG_TXEN.
b6830f6d
PH		 2211 */
2212 if (up->port.flags & UPF_NO_TXEN_TEST)
2213 goto dont_test_tx_en;
2214
2215 /*
740dc2de
AW		 2216 * Do a quick test to see if we receive an interrupt when we enable
2217 * the TX irq.
b6830f6d
PH		 2218 */
2219 serial_port_out(port, UART_IER, UART_IER_THRI);
2220 lsr = serial_port_in(port, UART_LSR);
2221 iir = serial_port_in(port, UART_IIR);
2222 serial_port_out(port, UART_IER, 0);
2223
2224 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2225 if (!(up->bugs & UART_BUG_TXEN)) {
2226 up->bugs |= UART_BUG_TXEN;
2227 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2228 serial_index(port));
2229 }
2230 } else {
2231 up->bugs &= ~UART_BUG_TXEN;
2232 }
2233
2234dont_test_tx_en:
2235 spin_unlock_irqrestore(&port->lock, flags);
2236
2237 /*
2238 * Clear the interrupt registers again for luck, and clear the
2239 * saved flags to avoid getting false values from polling
2240 * routines or the previous session.
2241 */
2242 serial_port_in(port, UART_LSR);
2243 serial_port_in(port, UART_RX);
2244 serial_port_in(port, UART_IIR);
2245 serial_port_in(port, UART_MSR);
2246 up->lsr_saved_flags = 0;
2247 up->msr_saved_flags = 0;
2248
2249 /*
2250 * Request DMA channels for both RX and TX.
2251 */
2252 if (up->dma) {
2253 retval = serial8250_request_dma(up);
2254 if (retval) {
2255 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2256 serial_index(port));
2257 up->dma = NULL;
2258 }
2259 }
2260
2261 /*
ee3ad90b
PH		 2262 * Set the IER shadow for rx interrupts but defer actual interrupt
2263 * enable until after the FIFOs are enabled; otherwise, an already-
2264 * active sender can swamp the interrupt handler with "too much work".
b6830f6d
PH		 2265 */
2266 up->ier = UART_IER_RLSI | UART_IER_RDI;
b6830f6d
PH		 2267
2268 if (port->flags & UPF_FOURPORT) {
2269 unsigned int icp;
2270 /*
2271 * Enable interrupts on the AST Fourport board
2272 */
2273 icp = (port->iobase & 0xfe0) | 0x01f;
2274 outb_p(0x80, icp);
2275 inb_p(icp);
2276 }
2277 retval = 0;
2278out:
2279 serial8250_rpm_put(up);
2280 return retval;
2281}
2282EXPORT_SYMBOL_GPL(serial8250_do_startup);
2283
2284static int serial8250_startup(struct uart_port *port)
2285{
2286 if (port->startup)
2287 return port->startup(port);
2288 return serial8250_do_startup(port);
2289}
2290
2291void serial8250_do_shutdown(struct uart_port *port)
2292{
2293 struct uart_8250_port *up = up_to_u8250p(port);
2294 unsigned long flags;
2295
2296 serial8250_rpm_get(up);
2297 /*
2298 * Disable interrupts from this port
2299 */
611e0d83 2300 spin_lock_irqsave(&port->lock, flags);
b6830f6d
PH		 2301 up->ier = 0;
2302 serial_port_out(port, UART_IER, 0);
611e0d83
PH		 2303 spin_unlock_irqrestore(&port->lock, flags);
2304
2305 synchronize_irq(port->irq);
b6830f6d
PH		 2306
2307 if (up->dma)
2308 serial8250_release_dma(up);
2309
2310 spin_lock_irqsave(&port->lock, flags);
2311 if (port->flags & UPF_FOURPORT) {
2312 /* reset interrupts on the AST Fourport board */
2313 inb((port->iobase & 0xfe0) | 0x1f);
2314 port->mctrl |= TIOCM_OUT1;
2315 } else
2316 port->mctrl &= ~TIOCM_OUT2;
2317
2318 serial8250_set_mctrl(port, port->mctrl);
2319 spin_unlock_irqrestore(&port->lock, flags);
2320
2321 /*
2322 * Disable break condition and FIFOs
2323 */
2324 serial_port_out(port, UART_LCR,
2325 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2326 serial8250_clear_fifos(up);
2327
2328#ifdef CONFIG_SERIAL_8250_RSA
2329 /*
2330 * Reset the RSA board back to 115kbps compat mode.
2331 */
2332 disable_rsa(up);
2333#endif
2334
2335 /*
2336 * Read data port to reset things, and then unlink from
2337 * the IRQ chain.
2338 */
2339 serial_port_in(port, UART_RX);
2340 serial8250_rpm_put(up);
2341
2342 up->ops->release_irq(up);
2343}
2344EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2345
2346static void serial8250_shutdown(struct uart_port *port)
2347{
2348 if (port->shutdown)
2349 port->shutdown(port);
2350 else
2351 serial8250_do_shutdown(port);
2352}
2353
2354/*
2355 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2356 * Calculate divisor with extra 4-bit fractional portion
2357 */
2358static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2359 unsigned int baud,
2360 unsigned int *frac)
2361{
2362 struct uart_port *port = &up->port;
2363 unsigned int quot_16;
2364
2365 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2366 *frac = quot_16 & 0x0f;
2367
2368 return quot_16 >> 4;
2369}
2370
2371static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2372 unsigned int baud,
2373 unsigned int *frac)
2374{
2375 struct uart_port *port = &up->port;
2376 unsigned int quot;
2377
2378 /*
2379 * Handle magic divisors for baud rates above baud_base on
2380 * SMSC SuperIO chips.
2381 *
2382 */
2383 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2384 baud == (port->uartclk/4))
2385 quot = 0x8001;
2386 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2387 baud == (port->uartclk/8))
2388 quot = 0x8002;
2389 else if (up->port.type == PORT_XR17V35X)
2390 quot = xr17v35x_get_divisor(up, baud, frac);
2391 else
2392 quot = uart_get_divisor(port, baud);
2393
2394 /*
2395 * Oxford Semi 952 rev B workaround
2396 */
2397 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2398 quot++;
2399
2400 return quot;
2401}
2402
2403static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2404 tcflag_t c_cflag)
2405{
2406 unsigned char cval;
2407
2408 switch (c_cflag & CSIZE) {
2409 case CS5:
2410 cval = UART_LCR_WLEN5;
2411 break;
2412 case CS6:
2413 cval = UART_LCR_WLEN6;
2414 break;
2415 case CS7:
2416 cval = UART_LCR_WLEN7;
2417 break;
2418 default:
2419 case CS8:
2420 cval = UART_LCR_WLEN8;
2421 break;
2422 }
2423
2424 if (c_cflag & CSTOPB)
2425 cval |= UART_LCR_STOP;
2426 if (c_cflag & PARENB) {
2427 cval |= UART_LCR_PARITY;
2428 if (up->bugs & UART_BUG_PARITY)
2429 up->fifo_bug = true;
2430 }
2431 if (!(c_cflag & PARODD))
2432 cval |= UART_LCR_EPAR;
2433#ifdef CMSPAR
2434 if (c_cflag & CMSPAR)
2435 cval |= UART_LCR_SPAR;
2436#endif
2437
2438 return cval;
2439}
2440
2441static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2442 unsigned int quot, unsigned int quot_frac)
2443{
2444 struct uart_8250_port *up = up_to_u8250p(port);
2445
2446 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2447 if (is_omap1510_8250(up)) {
2448 if (baud == 115200) {
2449 quot = 1;
2450 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2451 } else
2452 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2453 }
2454
2455 /*
2456 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2457 * otherwise just set DLAB
2458 */
2459 if (up->capabilities & UART_NATSEMI)
2460 serial_port_out(port, UART_LCR, 0xe0);
2461 else
2462 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2463
2464 serial_dl_write(up, quot);
2465
2466 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2467 if (up->port.type == PORT_XR17V35X)
2468 serial_port_out(port, 0x2, quot_frac);
2469}
2470
b3d67936
AW		 2471static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2472 struct ktermios *termios,
2473 struct ktermios *old)
4f56f3fd
JH		 2474{
2475 unsigned int tolerance = port->uartclk / 100;
2476
2477 /*
2478 * Ask the core to calculate the divisor for us.
2479 * Allow 1% tolerance at the upper limit so uart clks marginally
2480 * slower than nominal still match standard baud rates without
2481 * causing transmission errors.
2482 */
2483 return uart_get_baud_rate(port, termios, old,
2484 port->uartclk / 16 / 0xffff,
2485 (port->uartclk + tolerance) / 16);
2486}
2487
b6830f6d
PH		 2488void
2489serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
6d7c157f 2490 struct ktermios *old)
b6830f6d
PH		 2491{
2492 struct uart_8250_port *up = up_to_u8250p(port);
2493 unsigned char cval;
2494 unsigned long flags;
2495 unsigned int baud, quot, frac = 0;
2496
2497 cval = serial8250_compute_lcr(up, termios->c_cflag);
2498
4f56f3fd 2499 baud = serial8250_get_baud_rate(port, termios, old);
b6830f6d
PH		 2500 quot = serial8250_get_divisor(up, baud, &frac);
2501
2502 /*
2503 * Ok, we're now changing the port state. Do it with
2504 * interrupts disabled.
2505 */
2506 serial8250_rpm_get(up);
2507 spin_lock_irqsave(&port->lock, flags);
2508
2509 up->lcr = cval; /* Save computed LCR */
2510
2511 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2512 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2513 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2514 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2515 up->fcr |= UART_FCR_TRIGGER_1;
2516 }
2517 }
2518
2519 /*
2520 * MCR-based auto flow control. When AFE is enabled, RTS will be
2521 * deasserted when the receive FIFO contains more characters than
2522 * the trigger, or the MCR RTS bit is cleared. In the case where
2523 * the remote UART is not using CTS auto flow control, we must
2524 * have sufficient FIFO entries for the latency of the remote
2525 * UART to respond. IOW, at least 32 bytes of FIFO.
2526 */
2527 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2528 up->mcr &= ~UART_MCR_AFE;
2529 if (termios->c_cflag & CRTSCTS)
2530 up->mcr |= UART_MCR_AFE;
2531 }
2532
2533 /*
2534 * Update the per-port timeout.
2535 */
2536 uart_update_timeout(port, termios->c_cflag, baud);
2537
2538 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2539 if (termios->c_iflag & INPCK)
2540 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2541 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2542 port->read_status_mask |= UART_LSR_BI;
2543
2544 /*
2545 * Characteres to ignore
2546 */
2547 port->ignore_status_mask = 0;
2548 if (termios->c_iflag & IGNPAR)
2549 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2550 if (termios->c_iflag & IGNBRK) {
2551 port->ignore_status_mask |= UART_LSR_BI;
2552 /*
2553 * If we're ignoring parity and break indicators,
2554 * ignore overruns too (for real raw support).
2555 */
2556 if (termios->c_iflag & IGNPAR)
2557 port->ignore_status_mask |= UART_LSR_OE;
2558 }
2559
2560 /*
2561 * ignore all characters if CREAD is not set
2562 */
2563 if ((termios->c_cflag & CREAD) == 0)
2564 port->ignore_status_mask |= UART_LSR_DR;
2565
2566 /*
2567 * CTS flow control flag and modem status interrupts
2568 */
2569 up->ier &= ~UART_IER_MSI;
2570 if (!(up->bugs & UART_BUG_NOMSR) &&
2571 UART_ENABLE_MS(&up->port, termios->c_cflag))
2572 up->ier |= UART_IER_MSI;
2573 if (up->capabilities & UART_CAP_UUE)
2574 up->ier |= UART_IER_UUE;
2575 if (up->capabilities & UART_CAP_RTOIE)
2576 up->ier |= UART_IER_RTOIE;
2577
2578 serial_port_out(port, UART_IER, up->ier);
2579
2580 if (up->capabilities & UART_CAP_EFR) {
2581 unsigned char efr = 0;
2582 /*
2583 * TI16C752/Startech hardware flow control. FIXME:
2584 * - TI16C752 requires control thresholds to be set.
2585 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2586 */
2587 if (termios->c_cflag & CRTSCTS)
2588 efr |= UART_EFR_CTS;
2589
2590 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2591 if (port->flags & UPF_EXAR_EFR)
2592 serial_port_out(port, UART_XR_EFR, efr);
2593 else
2594 serial_port_out(port, UART_EFR, efr);
2595 }
2596
2597 serial8250_set_divisor(port, baud, quot, frac);
2598
2599 /*
2600 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2601 * is written without DLAB set, this mode will be disabled.
2602 */
2603 if (port->type == PORT_16750)
2604 serial_port_out(port, UART_FCR, up->fcr);
2605
2606 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2607 if (port->type != PORT_16750) {
2608 /* emulated UARTs (Lucent Venus 167x) need two steps */
2609 if (up->fcr & UART_FCR_ENABLE_FIFO)
2610 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2611 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2612 }
2613 serial8250_set_mctrl(port, port->mctrl);
2614 spin_unlock_irqrestore(&port->lock, flags);
2615 serial8250_rpm_put(up);
2616
2617 /* Don't rewrite B0 */
2618 if (tty_termios_baud_rate(termios))
2619 tty_termios_encode_baud_rate(termios, baud, baud);
2620}
2621EXPORT_SYMBOL(serial8250_do_set_termios);
2622
2623static void
2624serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2625 struct ktermios *old)
2626{
2627 if (port->set_termios)
2628 port->set_termios(port, termios, old);
2629 else
2630 serial8250_do_set_termios(port, termios, old);
2631}
2632
2633static void
2634serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2635{
2636 if (termios->c_line == N_PPS) {
2637 port->flags |= UPF_HARDPPS_CD;
2638 spin_lock_irq(&port->lock);
2639 serial8250_enable_ms(port);
2640 spin_unlock_irq(&port->lock);
2641 } else {
2642 port->flags &= ~UPF_HARDPPS_CD;
2643 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2644 spin_lock_irq(&port->lock);
2645 serial8250_disable_ms(port);
2646 spin_unlock_irq(&port->lock);
2647 }
2648 }
2649}
2650
2651
2652void serial8250_do_pm(struct uart_port *port, unsigned int state,
2653 unsigned int oldstate)
2654{
2655 struct uart_8250_port *p = up_to_u8250p(port);
2656
2657 serial8250_set_sleep(p, state != 0);
2658}
2659EXPORT_SYMBOL(serial8250_do_pm);
2660
2661static void
2662serial8250_pm(struct uart_port *port, unsigned int state,
2663 unsigned int oldstate)
2664{
2665 if (port->pm)
2666 port->pm(port, state, oldstate);
2667 else
2668 serial8250_do_pm(port, state, oldstate);
2669}
2670
2671static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2672{
2673 if (pt->port.mapsize)
2674 return pt->port.mapsize;
2675 if (pt->port.iotype == UPIO_AU) {
2676 if (pt->port.type == PORT_RT2880)
2677 return 0x100;
2678 return 0x1000;
2679 }
2680 if (is_omap1_8250(pt))
2681 return 0x16 << pt->port.regshift;
2682
2683 return 8 << pt->port.regshift;
2684}
2685
2686/*
2687 * Resource handling.
2688 */
2689static int serial8250_request_std_resource(struct uart_8250_port *up)
2690{
2691 unsigned int size = serial8250_port_size(up);
2692 struct uart_port *port = &up->port;
2693 int ret = 0;
2694
2695 switch (port->iotype) {
2696 case UPIO_AU:
2697 case UPIO_TSI:
2698 case UPIO_MEM32:
2699 case UPIO_MEM32BE:
bd94c407 2700 case UPIO_MEM16:
b6830f6d
PH		 2701 case UPIO_MEM:
2702 if (!port->mapbase)
2703 break;
2704
2705 if (!request_mem_region(port->mapbase, size, "serial")) {
2706 ret = -EBUSY;
2707 break;
2708 }
2709
2710 if (port->flags & UPF_IOREMAP) {
2711 port->membase = ioremap_nocache(port->mapbase, size);
2712 if (!port->membase) {
2713 release_mem_region(port->mapbase, size);
2714 ret = -ENOMEM;
2715 }
2716 }
2717 break;
2718
2719 case UPIO_HUB6:
2720 case UPIO_PORT:
2721 if (!request_region(port->iobase, size, "serial"))
2722 ret = -EBUSY;
2723 break;
2724 }
2725 return ret;
2726}
2727
2728static void serial8250_release_std_resource(struct uart_8250_port *up)
2729{
2730 unsigned int size = serial8250_port_size(up);
2731 struct uart_port *port = &up->port;
2732
2733 switch (port->iotype) {
2734 case UPIO_AU:
2735 case UPIO_TSI:
2736 case UPIO_MEM32:
2737 case UPIO_MEM32BE:
bd94c407 2738 case UPIO_MEM16:
b6830f6d
PH		 2739 case UPIO_MEM:
2740 if (!port->mapbase)
2741 break;
2742
2743 if (port->flags & UPF_IOREMAP) {
2744 iounmap(port->membase);
2745 port->membase = NULL;
2746 }
2747
2748 release_mem_region(port->mapbase, size);
2749 break;
2750
2751 case UPIO_HUB6:
2752 case UPIO_PORT:
2753 release_region(port->iobase, size);
2754 break;
2755 }
2756}
2757
2758static void serial8250_release_port(struct uart_port *port)
2759{
2760 struct uart_8250_port *up = up_to_u8250p(port);
2761
2762 serial8250_release_std_resource(up);
2763}
2764
2765static int serial8250_request_port(struct uart_port *port)
2766{
2767 struct uart_8250_port *up = up_to_u8250p(port);
b6830f6d 2768
e4fda3a0 2769 return serial8250_request_std_resource(up);
b6830f6d
PH		 2770}
2771
2772static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2773{
2774 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2775 unsigned char bytes;
2776
2777 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2778
2779 return bytes ? bytes : -EOPNOTSUPP;
2780}
2781
2782static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2783{
2784 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2785 int i;
2786
2787 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2788 return -EOPNOTSUPP;
2789
2790 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2791 if (bytes < conf_type->rxtrig_bytes[i])
2792 /* Use the nearest lower value */
2793 return (--i) << UART_FCR_R_TRIG_SHIFT;
2794 }
2795
2796 return UART_FCR_R_TRIG_11;
2797}
2798
2799static int do_get_rxtrig(struct tty_port *port)
2800{
2801 struct uart_state *state = container_of(port, struct uart_state, port);
2802 struct uart_port *uport = state->uart_port;
013e3586 2803 struct uart_8250_port *up = up_to_u8250p(uport);
b6830f6d
PH		 2804
2805 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2806 return -EINVAL;
2807
2808 return fcr_get_rxtrig_bytes(up);
2809}
2810
2811static int do_serial8250_get_rxtrig(struct tty_port *port)
2812{
2813 int rxtrig_bytes;
2814
2815 mutex_lock(&port->mutex);
2816 rxtrig_bytes = do_get_rxtrig(port);
2817 mutex_unlock(&port->mutex);
2818
2819 return rxtrig_bytes;
2820}
2821
2822static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2823 struct device_attribute *attr, char *buf)
2824{
2825 struct tty_port *port = dev_get_drvdata(dev);
2826 int rxtrig_bytes;
2827
2828 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2829 if (rxtrig_bytes < 0)
2830 return rxtrig_bytes;
2831
2832 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2833}
2834
2835static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2836{
2837 struct uart_state *state = container_of(port, struct uart_state, port);
2838 struct uart_port *uport = state->uart_port;
013e3586 2839 struct uart_8250_port *up = up_to_u8250p(uport);
b6830f6d
PH		 2840 int rxtrig;
2841
2842 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2843 up->fifo_bug)
2844 return -EINVAL;
2845
2846 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2847 if (rxtrig < 0)
2848 return rxtrig;
2849
2850 serial8250_clear_fifos(up);
2851 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2852 up->fcr |= (unsigned char)rxtrig;
2853 serial_out(up, UART_FCR, up->fcr);
2854 return 0;
2855}
2856
2857static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2858{
2859 int ret;
2860
2861 mutex_lock(&port->mutex);
2862 ret = do_set_rxtrig(port, bytes);
2863 mutex_unlock(&port->mutex);
2864
2865 return ret;
2866}
2867
2868static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2869 struct device_attribute *attr, const char *buf, size_t count)
2870{
2871 struct tty_port *port = dev_get_drvdata(dev);
2872 unsigned char bytes;
2873 int ret;
2874
2875 if (!count)
2876 return -EINVAL;
2877
2878 ret = kstrtou8(buf, 10, &bytes);
2879 if (ret < 0)
2880 return ret;
2881
2882 ret = do_serial8250_set_rxtrig(port, bytes);
2883 if (ret < 0)
2884 return ret;
2885
2886 return count;
2887}
2888
2889static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2890 serial8250_get_attr_rx_trig_bytes,
2891 serial8250_set_attr_rx_trig_bytes);
2892
2893static struct attribute *serial8250_dev_attrs[] = {
2894 &dev_attr_rx_trig_bytes.attr,
2895 NULL,
2896 };
2897
2898static struct attribute_group serial8250_dev_attr_group = {
2899 .attrs = serial8250_dev_attrs,
2900 };
2901
2902static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2903{
2904 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2905
2906 if (conf_type->rxtrig_bytes[0])
2907 up->port.attr_group = &serial8250_dev_attr_group;
2908}
2909
2910static void serial8250_config_port(struct uart_port *port, int flags)
2911{
2912 struct uart_8250_port *up = up_to_u8250p(port);
2913 int ret;
2914
b6830f6d
PH		 2915 /*
2916 * Find the region that we can probe for. This in turn
2917 * tells us whether we can probe for the type of port.
2918 */
2919 ret = serial8250_request_std_resource(up);
2920 if (ret < 0)
2921 return;
2922
2923 if (port->iotype != up->cur_iotype)
2924 set_io_from_upio(port);
2925
2926 if (flags & UART_CONFIG_TYPE)
2927 autoconfig(up);
2928
2929 /* if access method is AU, it is a 16550 with a quirk */
2930 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2931 up->bugs |= UART_BUG_NOMSR;
2932
2933 /* HW bugs may trigger IRQ while IIR == NO_INT */
2934 if (port->type == PORT_TEGRA)
2935 up->bugs |= UART_BUG_NOMSR;
2936
2937 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2938 autoconfig_irq(up);
2939
2940 if (port->type == PORT_UNKNOWN)
2941 serial8250_release_std_resource(up);
2942
2943 /* Fixme: probably not the best place for this */
2944 if ((port->type == PORT_XR17V35X) ||
2945 (port->type == PORT_XR17D15X))
2946 port->handle_irq = exar_handle_irq;
2947
2948 register_dev_spec_attr_grp(up);
2949 up->fcr = uart_config[up->port.type].fcr;
2950}
2951
2952static int
2953serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2954{
2955 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2956 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2957 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2958 ser->type == PORT_STARTECH)
2959 return -EINVAL;
2960 return 0;
2961}
2962
cee10c8c 2963static const char *serial8250_type(struct uart_port *port)
b6830f6d
PH		 2964{
2965 int type = port->type;
2966
2967 if (type >= ARRAY_SIZE(uart_config))
2968 type = 0;
2969 return uart_config[type].name;
2970}
2971
2972static const struct uart_ops serial8250_pops = {
2973 .tx_empty = serial8250_tx_empty,
2974 .set_mctrl = serial8250_set_mctrl,
2975 .get_mctrl = serial8250_get_mctrl,
2976 .stop_tx = serial8250_stop_tx,
2977 .start_tx = serial8250_start_tx,
2978 .throttle = serial8250_throttle,
2979 .unthrottle = serial8250_unthrottle,
2980 .stop_rx = serial8250_stop_rx,
2981 .enable_ms = serial8250_enable_ms,
2982 .break_ctl = serial8250_break_ctl,
2983 .startup = serial8250_startup,
2984 .shutdown = serial8250_shutdown,
2985 .set_termios = serial8250_set_termios,
2986 .set_ldisc = serial8250_set_ldisc,
2987 .pm = serial8250_pm,
2988 .type = serial8250_type,
2989 .release_port = serial8250_release_port,
2990 .request_port = serial8250_request_port,
2991 .config_port = serial8250_config_port,
2992 .verify_port = serial8250_verify_port,
2993#ifdef CONFIG_CONSOLE_POLL
2994 .poll_get_char = serial8250_get_poll_char,
2995 .poll_put_char = serial8250_put_poll_char,
2996#endif
2997};
2998
2999void serial8250_init_port(struct uart_8250_port *up)
3000{
3001 struct uart_port *port = &up->port;
3002
3003 spin_lock_init(&port->lock);
3004 port->ops = &serial8250_pops;
3005
3006 up->cur_iotype = 0xFF;
3007}
3008EXPORT_SYMBOL_GPL(serial8250_init_port);
3009
3010void serial8250_set_defaults(struct uart_8250_port *up)
3011{
3012 struct uart_port *port = &up->port;
3013
3014 if (up->port.flags & UPF_FIXED_TYPE) {
3015 unsigned int type = up->port.type;
3016
3017 if (!up->port.fifosize)
3018 up->port.fifosize = uart_config[type].fifo_size;
3019 if (!up->tx_loadsz)
3020 up->tx_loadsz = uart_config[type].tx_loadsz;
3021 if (!up->capabilities)
3022 up->capabilities = uart_config[type].flags;
3023 }
3024
3025 set_io_from_upio(port);
3026
3027 /* default dma handlers */
3028 if (up->dma) {
3029 if (!up->dma->tx_dma)
3030 up->dma->tx_dma = serial8250_tx_dma;
3031 if (!up->dma->rx_dma)
3032 up->dma->rx_dma = serial8250_rx_dma;
3033 }
3034}
3035EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3036
3037#ifdef CONFIG_SERIAL_8250_CONSOLE
3038
3039static void serial8250_console_putchar(struct uart_port *port, int ch)
3040{
3041 struct uart_8250_port *up = up_to_u8250p(port);
3042
3043 wait_for_xmitr(up, UART_LSR_THRE);
3044 serial_port_out(port, UART_TX, ch);
3045}
3046
10791233
PH		 3047/*
3048 * Restore serial console when h/w power-off detected
3049 */
3050static void serial8250_console_restore(struct uart_8250_port *up)
3051{
3052 struct uart_port *port = &up->port;
3053 struct ktermios termios;
3054 unsigned int baud, quot, frac = 0;
3055
3056 termios.c_cflag = port->cons->cflag;
3057 if (port->state->port.tty && termios.c_cflag == 0)
3058 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3059
3060 baud = serial8250_get_baud_rate(port, &termios, NULL);
3061 quot = serial8250_get_divisor(up, baud, &frac);
3062
3063 serial8250_set_divisor(port, baud, quot, frac);
3064 serial_port_out(port, UART_LCR, up->lcr);
3065 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
3066}
3067
b6830f6d
PH		 3068/*
3069 * Print a string to the serial port trying not to disturb
3070 * any possible real use of the port...
3071 *
3072 * The console_lock must be held when we get here.
3073 */
3074void serial8250_console_write(struct uart_8250_port *up, const char *s,
3075 unsigned int count)
3076{
3077 struct uart_port *port = &up->port;
3078 unsigned long flags;
3079 unsigned int ier;
3080 int locked = 1;
3081
3082 touch_nmi_watchdog();
3083
3084 serial8250_rpm_get(up);
3085
3086 if (port->sysrq)
3087 locked = 0;
3088 else if (oops_in_progress)
3089 locked = spin_trylock_irqsave(&port->lock, flags);
3090 else
3091 spin_lock_irqsave(&port->lock, flags);
3092
3093 /*
3094 * First save the IER then disable the interrupts
3095 */
3096 ier = serial_port_in(port, UART_IER);
3097
3098 if (up->capabilities & UART_CAP_UUE)
3099 serial_port_out(port, UART_IER, UART_IER_UUE);
3100 else
3101 serial_port_out(port, UART_IER, 0);
3102
3103 /* check scratch reg to see if port powered off during system sleep */
3104 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
10791233 3105 serial8250_console_restore(up);
b6830f6d
PH		 3106 up->canary = 0;
3107 }
3108
3109 uart_console_write(port, s, count, serial8250_console_putchar);
3110
3111 /*
3112 * Finally, wait for transmitter to become empty
3113 * and restore the IER
3114 */
3115 wait_for_xmitr(up, BOTH_EMPTY);
3116 serial_port_out(port, UART_IER, ier);
3117
3118 /*
3119 * The receive handling will happen properly because the
3120 * receive ready bit will still be set; it is not cleared
3121 * on read. However, modem control will not, we must
3122 * call it if we have saved something in the saved flags
3123 * while processing with interrupts off.
3124 */
3125 if (up->msr_saved_flags)
3126 serial8250_modem_status(up);
3127
3128 if (locked)
3129 spin_unlock_irqrestore(&port->lock, flags);
3130 serial8250_rpm_put(up);
3131}
3132
3133static unsigned int probe_baud(struct uart_port *port)
3134{
3135 unsigned char lcr, dll, dlm;
3136 unsigned int quot;
3137
3138 lcr = serial_port_in(port, UART_LCR);
3139 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3140 dll = serial_port_in(port, UART_DLL);
3141 dlm = serial_port_in(port, UART_DLM);
3142 serial_port_out(port, UART_LCR, lcr);
3143
3144 quot = (dlm << 8) | dll;
3145 return (port->uartclk / 16) / quot;
3146}
3147
3148int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3149{
3150 int baud = 9600;
3151 int bits = 8;
3152 int parity = 'n';
3153 int flow = 'n';
3154
3155 if (!port->iobase && !port->membase)
3156 return -ENODEV;
3157
3158 if (options)
3159 uart_parse_options(options, &baud, &parity, &bits, &flow);
3160 else if (probe)
3161 baud = probe_baud(port);
3162
3163 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3164}
3165
3166#endif /* CONFIG_SERIAL_8250_CONSOLE */
f7a7651f
JM		 3167
3168MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)