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earlycon: 8250: Document kernel command line options
[linux-2.6-block.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
21947ba6 24#include <linux/rational.h>
1da177e4
LT		 25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
9a1870ce
AS		 29#include <linux/dmaengine.h>
30#include <linux/platform_data/dma-dw.h>
f549e94e 31#include <linux/platform_data/dma-hsu.h>
9a1870ce 32
1da177e4
LT		 33#include "8250.h"
34
1da177e4
LT		 35/*
36 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
5bf8f501 46 int (*probe)(struct pci_dev *dev);
1da177e4 47 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 48 int (*setup)(struct serial_private *,
49 const struct pciserial_board *,
2655a2c7 50 struct uart_8250_port *, int);
1da177e4
LT		 51 void (*exit)(struct pci_dev *dev);
52};
53
54#define PCI_NUM_BAR_RESOURCES 6
55
56struct serial_private {
70db3d91 57 struct pci_dev *dev;
1da177e4
LT		 58 unsigned int nr;
59 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
60 struct pci_serial_quirk *quirk;
61 int line[0];
62};
63
7808edcd 64static int pci_default_setup(struct serial_private*,
2655a2c7 65 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 66
1da177e4
LT		 67static void moan_device(const char *str, struct pci_dev *dev)
68{
af8c5b8d 69 dev_err(&dev->dev,
ad361c98
JP		 70 "%s: %s\n"
71 "Please send the output of lspci -vv, this\n"
72 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
73 "manufacturer and name of serial board or\n"
f2e0ea86 74 "modem board to <linux-serial@vger.kernel.org>.\n",
1da177e4
LT		 75 pci_name(dev), str, dev->vendor, dev->device,
76 dev->subsystem_vendor, dev->subsystem_device);
77}
78
79static int
2655a2c7 80setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 81 int bar, int offset, int regshift)
82{
70db3d91 83 struct pci_dev *dev = priv->dev;
1da177e4
LT		 84
85 if (bar >= PCI_NUM_BAR_RESOURCES)
86 return -EINVAL;
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4 89 if (!priv->remapped_bar[bar])
398a9db6 90 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
1da177e4
LT		 91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
2655a2c7
AC		 94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
398a9db6 96 port->port.mapbase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
1da177e4 99 } else {
2655a2c7 100 port->port.iotype = UPIO_PORT;
398a9db6 101 port->port.iobase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
02c9b5cf
KJ		 109/*
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 113 const struct pciserial_board *board,
2655a2c7 114 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 115{
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133}
134
1da177e4
LT		 135/*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139static int
975a1a7d 140afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 141 struct uart_8250_port *port, int idx)
1da177e4
LT		 142{
143 unsigned int bar, offset = board->first_offset;
5756ee99 144
1da177e4
LT		 145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
70db3d91 153 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 154}
155
156/*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
61a116ef 163static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 164{
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 182 rc = 1;
183 break;
184 }
185
186 return rc;
187}
188
189/*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193static int
975a1a7d
RK		 194pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
2655a2c7 196 struct uart_8250_port *port, int idx)
1da177e4
LT		 197{
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
70db3d91 201 switch (priv->dev->subsystem_device) {
1da177e4
LT		 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
70db3d91 218 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 219}
220
221/*
222 * Added for EKF Intel i960 serial boards
223 */
61a116ef 224static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4 225{
0a0d412a 226 u32 oldval;
1da177e4
LT		 227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
0a0d412a 232 pci_read_config_dword(dev, 0x44, &oldval);
5756ee99 233 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 235 return -ENODEV;
236 }
237 return 0;
238}
239
240/*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
61a116ef 246static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 247{
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
add7b58e 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 259 irq_config = 0x43;
5756ee99 260
1da177e4 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
1da177e4
LT		 272 /*
273 * enable/disable interrupts
274 */
6f441fe9 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287}
288
ae8d8a14 289static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 290{
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
6f441fe9 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309}
310
04bf7e74
WP		 311#define NI8420_INT_ENABLE_REG 0x38
312#define NI8420_INT_ENABLE_BIT 0x2000
313
ae8d8a14 314static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 315{
316 void __iomem *p;
04bf7e74
WP		 317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
398a9db6 324 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 325 if (p == NULL)
326 return;
327
328 /* Disable the CPU Interrupt */
329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330 p + NI8420_INT_ENABLE_REG);
331 iounmap(p);
332}
333
334
46a0fac9
SB		 335/* MITE registers */
336#define MITE_IOWBSR1 0xc4
337#define MITE_IOWCR1 0xf4
338#define MITE_LCIMR1 0x08
339#define MITE_LCIMR2 0x10
340
341#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342
ae8d8a14 343static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 344{
345 void __iomem *p;
46a0fac9
SB		 346 unsigned int bar = 0;
347
348 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
349 moan_device("no memory in bar", dev);
350 return;
351 }
352
398a9db6 353 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 354 if (p == NULL)
355 return;
356
357 /* Disable the CPU Interrupt */
358 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
359 iounmap(p);
360}
361
1da177e4
LT		 362/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363static int
975a1a7d 364sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 365 struct uart_8250_port *port, int idx)
1da177e4
LT		 366{
367 unsigned int bar, offset = board->first_offset;
368
369 bar = 0;
370
371 if (idx < 4) {
372 /* first four channels map to 0, 0x100, 0x200, 0x300 */
373 offset += idx * board->uart_offset;
374 } else if (idx < 8) {
375 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
376 offset += idx * board->uart_offset + 0xC00;
377 } else /* we have only 8 ports on PMC-OCTALPRO */
378 return 1;
379
70db3d91 380 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 381}
382
383/*
384* This does initialization for PMC OCTALPRO cards:
385* maps the device memory, resets the UARTs (needed, bc
386* if the module is removed and inserted again, the card
387* is in the sleep mode) and enables global interrupt.
388*/
389
390/* global control register offset for SBS PMC-OctalPro */
391#define OCT_REG_CR_OFF 0x500
392
61a116ef 393static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 394{
395 u8 __iomem *p;
396
24ed3aba 397 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 398
399 if (p == NULL)
400 return -ENOMEM;
401 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 402 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 403 udelay(50);
5756ee99 404 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 405
406 /* Set bit-2 (INTENABLE) of Control Register */
407 writeb(0x4, p + OCT_REG_CR_OFF);
408 iounmap(p);
409
410 return 0;
411}
412
413/*
414 * Disables the global interrupt of PMC-OctalPro
415 */
416
ae8d8a14 417static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 418{
419 u8 __iomem *p;
420
24ed3aba 421 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 422 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 if (p != NULL)
1da177e4 424 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 425 iounmap(p);
426}
427
428/*
429 * SIIG serial cards have an PCI interface chip which also controls
430 * the UART clocking frequency. Each UART can be clocked independently
25985edc 431 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 432 * are stored in the EEPROM chip. It can cause problems because this
433 * version of serial driver doesn't support differently clocked UART's
434 * on single PCI card. To prevent this, initialization functions set
435 * high frequency clocking for all UART's on given card. It is safe (I
436 * hope) because it doesn't touch EEPROM settings to prevent conflicts
437 * with other OSes (like M$ DOS).
438 *
439 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 440 *
1da177e4
LT		 441 * There is two family of SIIG serial cards with different PCI
442 * interface chip and different configuration methods:
443 * - 10x cards have control registers in IO and/or memory space;
444 * - 20x cards have control registers in standard PCI configuration space.
445 *
67d74b87
RK		 446 * Note: all 10x cards have PCI device ids 0x10..
447 * all 20x cards have PCI device ids 0x20..
448 *
fbc0dc0d
AP		 449 * There are also Quartet Serial cards which use Oxford Semiconductor
450 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 *
1da177e4
LT		 452 * Note: some SIIG cards are probed by the parport_serial object.
453 */
454
455#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
456#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457
458static int pci_siig10x_init(struct pci_dev *dev)
459{
460 u16 data;
461 void __iomem *p;
462
463 switch (dev->device & 0xfff8) {
464 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
465 data = 0xffdf;
466 break;
467 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
468 data = 0xf7ff;
469 break;
470 default: /* 1S1P, 4S */
471 data = 0xfffb;
472 break;
473 }
474
6f441fe9 475 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 476 if (p == NULL)
477 return -ENOMEM;
478
479 writew(readw(p + 0x28) & data, p + 0x28);
480 readw(p + 0x28);
481 iounmap(p);
482 return 0;
483}
484
485#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
486#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487
488static int pci_siig20x_init(struct pci_dev *dev)
489{
490 u8 data;
491
492 /* Change clock frequency for the first UART. */
493 pci_read_config_byte(dev, 0x6f, &data);
494 pci_write_config_byte(dev, 0x6f, data & 0xef);
495
496 /* If this card has 2 UART, we have to do the same with second UART. */
497 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
498 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
499 pci_read_config_byte(dev, 0x73, &data);
500 pci_write_config_byte(dev, 0x73, data & 0xef);
501 }
502 return 0;
503}
504
67d74b87
RK		 505static int pci_siig_init(struct pci_dev *dev)
506{
507 unsigned int type = dev->device & 0xff00;
508
509 if (type == 0x1000)
510 return pci_siig10x_init(dev);
511 else if (type == 0x2000)
512 return pci_siig20x_init(dev);
513
514 moan_device("Unknown SIIG card", dev);
515 return -ENODEV;
516}
517
3ec9c594 518static int pci_siig_setup(struct serial_private *priv,
975a1a7d 519 const struct pciserial_board *board,
2655a2c7 520 struct uart_8250_port *port, int idx)
3ec9c594
AP		 521{
522 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
523
524 if (idx > 3) {
525 bar = 4;
526 offset = (idx - 4) * 8;
527 }
528
529 return setup_port(priv, port, bar, offset, 0);
530}
531
1da177e4
LT		 532/*
533 * Timedia has an explosion of boards, and to avoid the PCI table from
534 * growing *huge*, we use this function to collapse some 70 entries
535 * in the PCI table into one, for sanity's and compactness's sake.
536 */
e9422e09 537static const unsigned short timedia_single_port[] = {
1da177e4
LT		 538 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
539};
540
e9422e09 541static const unsigned short timedia_dual_port[] = {
1da177e4 542 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 543 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
544 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 545 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
546 0xD079, 0
547};
548
e9422e09 549static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 550 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
551 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 552 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
553 0xB157, 0
554};
555
e9422e09 556static const unsigned short timedia_eight_port[] = {
5756ee99 557 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 558 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
559};
560
cb3592be 561static const struct timedia_struct {
1da177e4 562 int num;
e9422e09 563 const unsigned short *ids;
1da177e4
LT		 564} timedia_data[] = {
565 { 1, timedia_single_port },
566 { 2, timedia_dual_port },
567 { 4, timedia_quad_port },
e9422e09 568 { 8, timedia_eight_port }
1da177e4
LT		 569};
570
b9b24558
FB		 571/*
572 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
573 * listing them individually, this driver merely grabs them all with
574 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
575 * and should be left free to be claimed by parport_serial instead.
576 */
577static int pci_timedia_probe(struct pci_dev *dev)
578{
579 /*
580 * Check the third digit of the subdevice ID
581 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 */
583 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 dev_info(&dev->dev,
585 "ignoring Timedia subdevice %04x for parport_serial\n",
586 dev->subsystem_device);
587 return -ENODEV;
588 }
589
590 return 0;
591}
592
61a116ef 593static int pci_timedia_init(struct pci_dev *dev)
1da177e4 594{
e9422e09 595 const unsigned short *ids;
1da177e4
LT		 596 int i, j;
597
e9422e09 598 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 599 ids = timedia_data[i].ids;
600 for (j = 0; ids[j]; j++)
601 if (dev->subsystem_device == ids[j])
602 return timedia_data[i].num;
603 }
604 return 0;
605}
606
607/*
608 * Timedia/SUNIX uses a mixture of BARs and offsets
609 * Ugh, this is ugly as all hell --- TYT
610 */
611static int
975a1a7d
RK		 612pci_timedia_setup(struct serial_private *priv,
613 const struct pciserial_board *board,
2655a2c7 614 struct uart_8250_port *port, int idx)
1da177e4
LT		 615{
616 unsigned int bar = 0, offset = board->first_offset;
617
618 switch (idx) {
619 case 0:
620 bar = 0;
621 break;
622 case 1:
623 offset = board->uart_offset;
624 bar = 0;
625 break;
626 case 2:
627 bar = 1;
628 break;
629 case 3:
630 offset = board->uart_offset;
c2cd6d3c 631 /* FALLTHROUGH */
1da177e4
LT		 632 case 4: /* BAR 2 */
633 case 5: /* BAR 3 */
634 case 6: /* BAR 4 */
635 case 7: /* BAR 5 */
636 bar = idx - 2;
637 }
638
70db3d91 639 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 640}
641
642/*
643 * Some Titan cards are also a little weird
644 */
645static int
70db3d91 646titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 647 const struct pciserial_board *board,
2655a2c7 648 struct uart_8250_port *port, int idx)
1da177e4
LT		 649{
650 unsigned int bar, offset = board->first_offset;
651
652 switch (idx) {
653 case 0:
654 bar = 1;
655 break;
656 case 1:
657 bar = 2;
658 break;
659 default:
660 bar = 4;
661 offset = (idx - 2) * board->uart_offset;
662 }
663
70db3d91 664 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 665}
666
61a116ef 667static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 668{
669 msleep(100);
670 return 0;
671}
672
04bf7e74
WP		 673static int pci_ni8420_init(struct pci_dev *dev)
674{
675 void __iomem *p;
04bf7e74
WP		 676 unsigned int bar = 0;
677
678 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
679 moan_device("no memory in bar", dev);
680 return 0;
681 }
682
398a9db6 683 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 684 if (p == NULL)
685 return -ENOMEM;
686
687 /* Enable CPU Interrupt */
688 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
689 p + NI8420_INT_ENABLE_REG);
690
691 iounmap(p);
692 return 0;
693}
694
46a0fac9
SB		 695#define MITE_IOWBSR1_WSIZE 0xa
696#define MITE_IOWBSR1_WIN_OFFSET 0x800
697#define MITE_IOWBSR1_WENAB (1 << 7)
698#define MITE_LCIMR1_IO_IE_0 (1 << 24)
699#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
700#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701
702static int pci_ni8430_init(struct pci_dev *dev)
703{
704 void __iomem *p;
398a9db6 705 struct pci_bus_region region;
46a0fac9
SB		 706 u32 device_window;
707 unsigned int bar = 0;
708
709 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
710 moan_device("no memory in bar", dev);
711 return 0;
712 }
713
398a9db6 714 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 715 if (p == NULL)
716 return -ENOMEM;
717
398a9db6
AS		 718 /*
719 * Set device window address and size in BAR0, while acknowledging that
720 * the resource structure may contain a translated address that differs
721 * from the address the device responds to.
722 */
723 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
724 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
46a0fac9
SB		 725 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
726 writel(device_window, p + MITE_IOWBSR1);
727
728 /* Set window access to go to RAMSEL IO address space */
729 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
730 p + MITE_IOWCR1);
731
732 /* Enable IO Bus Interrupt 0 */
733 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734
735 /* Enable CPU Interrupt */
736 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
737
738 iounmap(p);
739 return 0;
740}
741
742/* UART Port Control Register */
743#define NI8430_PORTCON 0x0f
744#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
745
746static int
bf538fe4
AC		 747pci_ni8430_setup(struct serial_private *priv,
748 const struct pciserial_board *board,
2655a2c7 749 struct uart_8250_port *port, int idx)
46a0fac9 750{
398a9db6 751 struct pci_dev *dev = priv->dev;
46a0fac9 752 void __iomem *p;
46a0fac9
SB		 753 unsigned int bar, offset = board->first_offset;
754
755 if (idx >= board->num_ports)
756 return 1;
757
758 bar = FL_GET_BASE(board->flags);
759 offset += idx * board->uart_offset;
760
398a9db6 761 p = pci_ioremap_bar(dev, bar);
5d14bba9
AS		 762 if (!p)
763 return -ENOMEM;
46a0fac9 764
7c9d440e 765 /* enable the transceiver */
46a0fac9
SB		 766 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
767 p + offset + NI8430_PORTCON);
768
769 iounmap(p);
770
771 return setup_port(priv, port, bar, offset, board->reg_shift);
772}
773
7808edcd
NG		 774static int pci_netmos_9900_setup(struct serial_private *priv,
775 const struct pciserial_board *board,
2655a2c7 776 struct uart_8250_port *port, int idx)
7808edcd
NG		 777{
778 unsigned int bar;
779
333c085e
DES		 780 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
781 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
7808edcd
NG		 782 /* netmos apparently orders BARs by datasheet layout, so serial
783 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
784 */
785 bar = 3 * idx;
786
787 return setup_port(priv, port, bar, 0, board->reg_shift);
788 } else {
789 return pci_default_setup(priv, board, port, idx);
790 }
791}
792
793/* the 99xx series comes with a range of device IDs and a variety
794 * of capabilities:
795 *
796 * 9900 has varying capabilities and can cascade to sub-controllers
797 * (cascading should be purely internal)
798 * 9904 is hardwired with 4 serial ports
799 * 9912 and 9922 are hardwired with 2 serial ports
800 */
801static int pci_netmos_9900_numports(struct pci_dev *dev)
802{
803 unsigned int c = dev->class;
804 unsigned int pi;
805 unsigned short sub_serports;
806
807 pi = (c & 0xff);
808
809 if (pi == 2) {
810 return 1;
811 } else if ((pi == 0) &&
812 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
813 /* two possibilities: 0x30ps encodes number of parallel and
814 * serial ports, or 0x1000 indicates *something*. This is not
815 * immediately obvious, since the 2s1p+4s configuration seems
816 * to offer all functionality on functions 0..2, while still
817 * advertising the same function 3 as the 4s+2s1p config.
818 */
819 sub_serports = dev->subsystem_device & 0xf;
820 if (sub_serports > 0) {
821 return sub_serports;
822 } else {
af8c5b8d 823 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 824 return 0;
825 }
826 }
827
828 moan_device("unknown NetMos/Mostech program interface", dev);
829 return 0;
830}
46a0fac9 831
61a116ef 832static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 833{
834 /* subdevice 0x00PS means <P> parallel, <S> serial */
835 unsigned int num_serial = dev->subsystem_device & 0xf;
836
ac6ec5b1
IS		 837 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
838 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 839 return 0;
7808edcd 840
25cf9bc1
JS		 841 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
842 dev->subsystem_device == 0x0299)
843 return 0;
844
7808edcd
NG		 845 switch (dev->device) { /* FALLTHROUGH on all */
846 case PCI_DEVICE_ID_NETMOS_9904:
847 case PCI_DEVICE_ID_NETMOS_9912:
848 case PCI_DEVICE_ID_NETMOS_9922:
849 case PCI_DEVICE_ID_NETMOS_9900:
850 num_serial = pci_netmos_9900_numports(dev);
851 break;
852
853 default:
854 if (num_serial == 0 ) {
855 moan_device("unknown NetMos/Mostech device", dev);
856 }
857 }
858
1da177e4
LT		 859 if (num_serial == 0)
860 return -ENODEV;
7808edcd 861
1da177e4
LT		 862 return num_serial;
863}
864
84f8c6fc 865/*
84f8c6fc
NV		 866 * These chips are available with optionally one parallel port and up to
867 * two serial ports. Unfortunately they all have the same product id.
868 *
869 * Basic configuration is done over a region of 32 I/O ports. The base
870 * ioport is called INTA or INTC, depending on docs/other drivers.
871 *
872 * The region of the 32 I/O ports is configured in POSIO0R...
873 */
874
875/* registers */
876#define ITE_887x_MISCR 0x9c
877#define ITE_887x_INTCBAR 0x78
878#define ITE_887x_UARTBAR 0x7c
879#define ITE_887x_PS0BAR 0x10
880#define ITE_887x_POSIO0 0x60
881
882/* I/O space size */
883#define ITE_887x_IOSIZE 32
884/* I/O space size (bits 26-24; 8 bytes = 011b) */
885#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
886/* I/O space size (bits 26-24; 32 bytes = 101b) */
887#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
888/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
889#define ITE_887x_POSIO_SPEED (3 << 29)
890/* enable IO_Space bit */
891#define ITE_887x_POSIO_ENABLE (1 << 31)
892
f79abb82 893static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 894{
895 /* inta_addr are the configuration addresses of the ITE */
896 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
897 0x200, 0x280, 0 };
898 int ret, i, type;
899 struct resource *iobase = NULL;
900 u32 miscr, uartbar, ioport;
901
902 /* search for the base-ioport */
903 i = 0;
904 while (inta_addr[i] && iobase == NULL) {
905 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 "ite887x");
907 if (iobase != NULL) {
908 /* write POSIO0R - speed | size | ioport */
909 pci_write_config_dword(dev, ITE_887x_POSIO0,
910 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
911 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
912 /* write INTCBAR - ioport */
5756ee99
AC		 913 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 inta_addr[i]);
84f8c6fc
NV		 915 ret = inb(inta_addr[i]);
916 if (ret != 0xff) {
917 /* ioport connected */
918 break;
919 }
920 release_region(iobase->start, ITE_887x_IOSIZE);
921 iobase = NULL;
922 }
923 i++;
924 }
925
926 if (!inta_addr[i]) {
af8c5b8d 927 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 928 return -ENODEV;
929 }
930
931 /* start of undocumented type checking (see parport_pc.c) */
932 type = inb(iobase->start + 0x18) & 0x0f;
933
934 switch (type) {
935 case 0x2: /* ITE8871 (1P) */
936 case 0xa: /* ITE8875 (1P) */
937 ret = 0;
938 break;
939 case 0xe: /* ITE8872 (2S1P) */
940 ret = 2;
941 break;
942 case 0x6: /* ITE8873 (1S) */
943 ret = 1;
944 break;
945 case 0x8: /* ITE8874 (2S) */
946 ret = 2;
947 break;
948 default:
949 moan_device("Unknown ITE887x", dev);
950 ret = -ENODEV;
951 }
952
953 /* configure all serial ports */
954 for (i = 0; i < ret; i++) {
955 /* read the I/O port from the device */
956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 &ioport);
958 ioport &= 0x0000FF00; /* the actual base address */
959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961 ITE_887x_POSIO_IOSIZE_8 | ioport);
962
963 /* write the ioport to the UARTBAR */
964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
966 uartbar |= (ioport << (16 * i)); /* set the ioport */
967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968
969 /* get current config */
970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971 /* disable interrupts (UARTx_Routing[3:0]) */
972 miscr &= ~(0xf << (12 - 4 * i));
973 /* activate the UART (UARTx_En) */
974 miscr |= 1 << (23 - i);
975 /* write new config with activated UART */
976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
977 }
978
979 if (ret <= 0) {
980 /* the device has no UARTs if we get here */
981 release_region(iobase->start, ITE_887x_IOSIZE);
982 }
983
984 return ret;
985}
986
ae8d8a14 987static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 988{
989 u32 ioport;
990 /* the ioport is bit 0-15 in POSIO0R */
991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 ioport &= 0xffff;
993 release_region(ioport, ITE_887x_IOSIZE);
994}
995
1bc8cde4
MS		 996/*
997 * EndRun Technologies.
998 * Determine the number of ports available on the device.
999 */
1000#define PCI_VENDOR_ID_ENDRUN 0x7401
1001#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002
1003static int pci_endrun_init(struct pci_dev *dev)
1004{
1005 u8 __iomem *p;
1006 unsigned long deviceID;
1007 unsigned int number_uarts = 0;
1008
1009 /* EndRun device is all 0xexxx */
1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011 (dev->device & 0xf000) != 0xe000)
1012 return 0;
1013
1014 p = pci_iomap(dev, 0, 5);
1015 if (p == NULL)
1016 return -ENOMEM;
1017
1018 deviceID = ioread32(p);
1019 /* EndRun device */
1020 if (deviceID == 0x07000200) {
1021 number_uarts = ioread8(p + 4);
1022 dev_dbg(&dev->dev,
1023 "%d ports detected on EndRun PCI Express device\n",
1024 number_uarts);
1025 }
1026 pci_iounmap(dev, p);
1027 return number_uarts;
1028}
1029
9f2a036a
RK		 1030/*
1031 * Oxford Semiconductor Inc.
1032 * Check that device is part of the Tornado range of devices, then determine
1033 * the number of ports available on the device.
1034 */
1035static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036{
1037 u8 __iomem *p;
1038 unsigned long deviceID;
1039 unsigned int number_uarts = 0;
1040
1041 /* OxSemi Tornado devices are all 0xCxxx */
1042 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043 (dev->device & 0xF000) != 0xC000)
1044 return 0;
1045
1046 p = pci_iomap(dev, 0, 5);
1047 if (p == NULL)
1048 return -ENOMEM;
1049
1050 deviceID = ioread32(p);
1051 /* Tornado device */
1052 if (deviceID == 0x07000200) {
1053 number_uarts = ioread8(p + 4);
af8c5b8d 1054 dev_dbg(&dev->dev,
9f2a036a 1055 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1056 number_uarts);
9f2a036a
RK		 1057 }
1058 pci_iounmap(dev, p);
1059 return number_uarts;
1060}
1061
eb26dfe8
AC		 1062static int pci_asix_setup(struct serial_private *priv,
1063 const struct pciserial_board *board,
1064 struct uart_8250_port *port, int idx)
1065{
1066 port->bugs |= UART_BUG_PARITY;
1067 return pci_default_setup(priv, board, port, idx);
1068}
1069
55c7c0fd
AC		 1070/* Quatech devices have their own extra interface features */
1071
1072struct quatech_feature {
1073 u16 devid;
1074 bool amcc;
1075};
1076
1077#define QPCR_TEST_FOR1 0x3F
1078#define QPCR_TEST_GET1 0x00
1079#define QPCR_TEST_FOR2 0x40
1080#define QPCR_TEST_GET2 0x40
1081#define QPCR_TEST_FOR3 0x80
1082#define QPCR_TEST_GET3 0x40
1083#define QPCR_TEST_FOR4 0xC0
1084#define QPCR_TEST_GET4 0x80
1085
1086#define QOPR_CLOCK_X1 0x0000
1087#define QOPR_CLOCK_X2 0x0001
1088#define QOPR_CLOCK_X4 0x0002
1089#define QOPR_CLOCK_X8 0x0003
1090#define QOPR_CLOCK_RATE_MASK 0x0003
1091
1092
1093static struct quatech_feature quatech_cards[] = {
1094 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1098 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1100 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1103 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1105 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113 { 0, }
1114};
1115
1116static int pci_quatech_amcc(u16 devid)
1117{
1118 struct quatech_feature *qf = &quatech_cards[0];
1119 while (qf->devid) {
1120 if (qf->devid == devid)
1121 return qf->amcc;
1122 qf++;
1123 }
1124 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125 return 0;
1126};
1127
1128static int pci_quatech_rqopr(struct uart_8250_port *port)
1129{
1130 unsigned long base = port->port.iobase;
1131 u8 LCR, val;
1132
1133 LCR = inb(base + UART_LCR);
1134 outb(0xBF, base + UART_LCR);
1135 val = inb(base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137 return val;
1138}
1139
1140static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141{
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(qopr, base + UART_SCR);
1149 outb(LCR, base + UART_LCR);
1150}
1151
1152static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153{
1154 unsigned long base = port->port.iobase;
1155 u8 LCR, val, qmcr;
1156
1157 LCR = inb(base + UART_LCR);
1158 outb(0xBF, base + UART_LCR);
1159 val = inb(base + UART_SCR);
1160 outb(val | 0x10, base + UART_SCR);
1161 qmcr = inb(base + UART_MCR);
1162 outb(val, base + UART_SCR);
1163 outb(LCR, base + UART_LCR);
1164
1165 return qmcr;
1166}
1167
1168static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169{
1170 unsigned long base = port->port.iobase;
1171 u8 LCR, val;
1172
1173 LCR = inb(base + UART_LCR);
1174 outb(0xBF, base + UART_LCR);
1175 val = inb(base + UART_SCR);
1176 outb(val | 0x10, base + UART_SCR);
1177 outb(qmcr, base + UART_MCR);
1178 outb(val, base + UART_SCR);
1179 outb(LCR, base + UART_LCR);
1180}
1181
1182static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183{
1184 unsigned long base = port->port.iobase;
1185 u8 LCR, val;
1186
1187 LCR = inb(base + UART_LCR);
1188 outb(0xBF, base + UART_LCR);
1189 val = inb(base + UART_SCR);
1190 if (val & 0x20) {
1191 outb(0x80, UART_LCR);
1192 if (!(inb(UART_SCR) & 0x20)) {
1193 outb(LCR, base + UART_LCR);
1194 return 1;
1195 }
1196 }
1197 return 0;
1198}
1199
1200static int pci_quatech_test(struct uart_8250_port *port)
1201{
1202 u8 reg;
1203 u8 qopr = pci_quatech_rqopr(port);
1204 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205 reg = pci_quatech_rqopr(port) & 0xC0;
1206 if (reg != QPCR_TEST_GET1)
1207 return -EINVAL;
1208 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209 reg = pci_quatech_rqopr(port) & 0xC0;
1210 if (reg != QPCR_TEST_GET2)
1211 return -EINVAL;
1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213 reg = pci_quatech_rqopr(port) & 0xC0;
1214 if (reg != QPCR_TEST_GET3)
1215 return -EINVAL;
1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217 reg = pci_quatech_rqopr(port) & 0xC0;
1218 if (reg != QPCR_TEST_GET4)
1219 return -EINVAL;
1220
1221 pci_quatech_wqopr(port, qopr);
1222 return 0;
1223}
1224
1225static int pci_quatech_clock(struct uart_8250_port *port)
1226{
1227 u8 qopr, reg, set;
1228 unsigned long clock;
1229
1230 if (pci_quatech_test(port) < 0)
1231 return 1843200;
1232
1233 qopr = pci_quatech_rqopr(port);
1234
1235 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236 reg = pci_quatech_rqopr(port);
1237 if (reg & QOPR_CLOCK_X8) {
1238 clock = 1843200;
1239 goto out;
1240 }
1241 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242 reg = pci_quatech_rqopr(port);
1243 if (!(reg & QOPR_CLOCK_X8)) {
1244 clock = 1843200;
1245 goto out;
1246 }
1247 reg &= QOPR_CLOCK_X8;
1248 if (reg == QOPR_CLOCK_X2) {
1249 clock = 3685400;
1250 set = QOPR_CLOCK_X2;
1251 } else if (reg == QOPR_CLOCK_X4) {
1252 clock = 7372800;
1253 set = QOPR_CLOCK_X4;
1254 } else if (reg == QOPR_CLOCK_X8) {
1255 clock = 14745600;
1256 set = QOPR_CLOCK_X8;
1257 } else {
1258 clock = 1843200;
1259 set = QOPR_CLOCK_X1;
1260 }
1261 qopr &= ~QOPR_CLOCK_RATE_MASK;
1262 qopr |= set;
1263
1264out:
1265 pci_quatech_wqopr(port, qopr);
1266 return clock;
1267}
1268
1269static int pci_quatech_rs422(struct uart_8250_port *port)
1270{
1271 u8 qmcr;
1272 int rs422 = 0;
1273
1274 if (!pci_quatech_has_qmcr(port))
1275 return 0;
1276 qmcr = pci_quatech_rqmcr(port);
1277 pci_quatech_wqmcr(port, 0xFF);
1278 if (pci_quatech_rqmcr(port))
1279 rs422 = 1;
1280 pci_quatech_wqmcr(port, qmcr);
1281 return rs422;
1282}
1283
1284static int pci_quatech_init(struct pci_dev *dev)
1285{
1286 if (pci_quatech_amcc(dev->device)) {
1287 unsigned long base = pci_resource_start(dev, 0);
1288 if (base) {
1289 u32 tmp;
9c5320f8 1290 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1291 tmp = inl(base + 0x3c);
1292 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1293 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1294 }
1295 }
1296 return 0;
1297}
1298
1299static int pci_quatech_setup(struct serial_private *priv,
1300 const struct pciserial_board *board,
1301 struct uart_8250_port *port, int idx)
1302{
1303 /* Needed by pci_quatech calls below */
1304 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305 /* Set up the clocking */
1306 port->port.uartclk = pci_quatech_clock(port);
1307 /* For now just warn about RS422 */
1308 if (pci_quatech_rs422(port))
1309 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310 return pci_default_setup(priv, board, port, idx);
1311}
1312
d73dfc6a 1313static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1314{
1315}
1316
eb26dfe8 1317static int pci_default_setup(struct serial_private *priv,
975a1a7d 1318 const struct pciserial_board *board,
2655a2c7 1319 struct uart_8250_port *port, int idx)
1da177e4
LT		 1320{
1321 unsigned int bar, offset = board->first_offset, maxnr;
1322
1323 bar = FL_GET_BASE(board->flags);
1324 if (board->flags & FL_BASE_BARS)
1325 bar += idx;
1326 else
1327 offset += idx * board->uart_offset;
1328
2427ddd8
GKH		 1329 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330 (board->reg_shift + 3);
1da177e4
LT		 1331
1332 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333 return 1;
5756ee99 1334
70db3d91 1335 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1336}
1337
94341475
AB		 1338static int pci_pericom_setup(struct serial_private *priv,
1339 const struct pciserial_board *board,
1340 struct uart_8250_port *port, int idx)
1341{
1342 unsigned int bar, offset = board->first_offset, maxnr;
1343
1344 bar = FL_GET_BASE(board->flags);
1345 if (board->flags & FL_BASE_BARS)
1346 bar += idx;
1347 else
1348 offset += idx * board->uart_offset;
1349
1350 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351 (board->reg_shift + 3);
1352
1353 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 return 1;
1355
1356 port->port.uartclk = 14745600;
1357
1358 return setup_port(priv, port, bar, offset, board->reg_shift);
1359}
1360
095e24b0
DB		 1361static int
1362ce4100_serial_setup(struct serial_private *priv,
1363 const struct pciserial_board *board,
2655a2c7 1364 struct uart_8250_port *port, int idx)
095e24b0
DB		 1365{
1366 int ret;
1367
08ec212c 1368 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1369 port->port.iotype = UPIO_MEM32;
1370 port->port.type = PORT_XSCALE;
1371 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372 port->port.regshift = 2;
095e24b0
DB		 1373
1374 return ret;
1375}
1376
b15e5691
HK		 1377#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1378#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1379
29897087
AC		 1380#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1381#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1382
b15e5691
HK		 1383#define BYT_PRV_CLK 0x800
1384#define BYT_PRV_CLK_EN (1 << 0)
1385#define BYT_PRV_CLK_M_VAL_SHIFT 1
1386#define BYT_PRV_CLK_N_VAL_SHIFT 16
1387#define BYT_PRV_CLK_UPDATE (1 << 31)
1388
b15e5691
HK		 1389#define BYT_TX_OVF_INT 0x820
1390#define BYT_TX_OVF_INT_MASK (1 << 1)
1391
1392static void
1393byt_set_termios(struct uart_port *p, struct ktermios *termios,
1394 struct ktermios *old)
1395{
1396 unsigned int baud = tty_termios_baud_rate(termios);
21947ba6
AS		 1397 unsigned long fref = 100000000, fuart = baud * 16;
1398 unsigned long w = BIT(15) - 1;
1399 unsigned long m, n;
b15e5691
HK		 1400 u32 reg;
1401
21947ba6
AS		 1402 /* Get Fuart closer to Fref */
1403 fuart *= rounddown_pow_of_two(fref / fuart);
1404
50825c57
AS		 1405 /*
1406 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1407 * dividers must be adjusted.
1408 *
1409 * uartclk = (m / n) * 100 MHz, where m <= n
1410 */
21947ba6
AS		 1411 rational_best_approximation(fuart, fref, w, w, &m, &n);
1412 p->uartclk = fuart;
b15e5691
HK		 1413
1414 /* Reset the clock */
1415 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1416 writel(reg, p->membase + BYT_PRV_CLK);
1417 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1418 writel(reg, p->membase + BYT_PRV_CLK);
1419
b15e5691
HK		 1420 serial8250_do_set_termios(p, termios, old);
1421}
1422
1423static bool byt_dma_filter(struct dma_chan *chan, void *param)
1424{
9a1870ce
AS		 1425 struct dw_dma_slave *dws = param;
1426
1427 if (dws->dma_dev != chan->device->dev)
1428 return false;
1429
1430 chan->private = dws;
1431 return true;
b15e5691
HK		 1432}
1433
1434static int
1435byt_serial_setup(struct serial_private *priv,
1436 const struct pciserial_board *board,
1437 struct uart_8250_port *port, int idx)
1438{
9a1870ce
AS		 1439 struct pci_dev *pdev = priv->dev;
1440 struct device *dev = port->port.dev;
b15e5691 1441 struct uart_8250_dma *dma;
9a1870ce
AS		 1442 struct dw_dma_slave *tx_param, *rx_param;
1443 struct pci_dev *dma_dev;
b15e5691
HK		 1444 int ret;
1445
9a1870ce 1446 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
b15e5691
HK		 1447 if (!dma)
1448 return -ENOMEM;
1449
9a1870ce
AS		 1450 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1451 if (!tx_param)
1452 return -ENOMEM;
1453
1454 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1455 if (!rx_param)
1456 return -ENOMEM;
1457
1458 switch (pdev->device) {
b15e5691 1459 case PCI_DEVICE_ID_INTEL_BYT_UART1:
29897087 1460 case PCI_DEVICE_ID_INTEL_BSW_UART1:
9a1870ce
AS		 1461 rx_param->src_id = 3;
1462 tx_param->dst_id = 2;
b15e5691
HK		 1463 break;
1464 case PCI_DEVICE_ID_INTEL_BYT_UART2:
29897087 1465 case PCI_DEVICE_ID_INTEL_BSW_UART2:
9a1870ce
AS		 1466 rx_param->src_id = 5;
1467 tx_param->dst_id = 4;
b15e5691
HK		 1468 break;
1469 default:
1470 return -EINVAL;
1471 }
1472
9a1870ce
AS		 1473 rx_param->src_master = 1;
1474 rx_param->dst_master = 0;
1475
b15e5691
HK		 1476 dma->rxconf.src_maxburst = 16;
1477
9a1870ce
AS		 1478 tx_param->src_master = 1;
1479 tx_param->dst_master = 0;
1480
b15e5691
HK		 1481 dma->txconf.dst_maxburst = 16;
1482
9a1870ce
AS		 1483 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1484 rx_param->dma_dev = &dma_dev->dev;
1485 tx_param->dma_dev = &dma_dev->dev;
1486
b15e5691 1487 dma->fn = byt_dma_filter;
9a1870ce
AS		 1488 dma->rx_param = rx_param;
1489 dma->tx_param = tx_param;
b15e5691
HK		 1490
1491 ret = pci_default_setup(priv, board, port, idx);
1492 port->port.iotype = UPIO_MEM;
1493 port->port.type = PORT_16550A;
1494 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1495 port->port.set_termios = byt_set_termios;
1496 port->port.fifosize = 64;
1497 port->tx_loadsz = 64;
1498 port->dma = dma;
1499 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1500
1501 /* Disable Tx counter interrupts */
1502 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1503
1504 return ret;
1505}
1506
f549e94e
AS		 1507#define INTEL_MID_UART_PS 0x30
1508#define INTEL_MID_UART_MUL 0x34
c1a67b48 1509#define INTEL_MID_UART_DIV 0x38
f549e94e 1510
c1a67b48
AS		 1511static void intel_mid_set_termios(struct uart_port *p,
1512 struct ktermios *termios,
1513 struct ktermios *old,
1514 unsigned long fref)
f549e94e
AS		 1515{
1516 unsigned int baud = tty_termios_baud_rate(termios);
c1a67b48
AS		 1517 unsigned short ps = 16;
1518 unsigned long fuart = baud * ps;
1519 unsigned long w = BIT(24) - 1;
1520 unsigned long mul, div;
1521
1522 if (fref < fuart) {
1523 /* Find prescaler value that satisfies Fuart < Fref */
1524 if (fref > baud)
1525 ps = fref / baud; /* baud rate too high */
1526 else
1527 ps = 1; /* PLL case */
1528 fuart = baud * ps;
1529 } else {
1530 /* Get Fuart closer to Fref */
1531 fuart *= rounddown_pow_of_two(fref / fuart);
f549e94e
AS		 1532 }
1533
c1a67b48
AS		 1534 rational_best_approximation(fuart, fref, w, w, &mul, &div);
1535 p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */
1536
f549e94e
AS		 1537 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
1538 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
c1a67b48 1539 writel(div, p->membase + INTEL_MID_UART_DIV);
f549e94e
AS		 1540
1541 serial8250_do_set_termios(p, termios, old);
1542}
90b9aacf
AS		 1543
1544static void intel_mid_set_termios_38_4M(struct uart_port *p,
1545 struct ktermios *termios,
1546 struct ktermios *old)
1547{
1548 intel_mid_set_termios(p, termios, old, 38400000);
1549}
1550
c1a67b48
AS		 1551static void intel_mid_set_termios_50M(struct uart_port *p,
1552 struct ktermios *termios,
1553 struct ktermios *old)
1554{
1555 /*
1556 * The uart clk is 50Mhz, and the baud rate come from:
1557 * baud = 50M * MUL / (DIV * PS * DLAB)
1558 */
1559 intel_mid_set_termios(p, termios, old, 50000000);
1560}
f549e94e
AS		 1561
1562static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
1563{
1564 struct hsu_dma_slave *s = param;
1565
1566 if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
1567 return false;
1568
1569 chan->private = s;
1570 return true;
1571}
1572
1573static int intel_mid_serial_setup(struct serial_private *priv,
1574 const struct pciserial_board *board,
1575 struct uart_8250_port *port, int idx,
1576 int index, struct pci_dev *dma_dev)
1577{
1578 struct device *dev = port->port.dev;
1579 struct uart_8250_dma *dma;
1580 struct hsu_dma_slave *tx_param, *rx_param;
1581
1582 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1583 if (!dma)
1584 return -ENOMEM;
1585
1586 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1587 if (!tx_param)
1588 return -ENOMEM;
1589
1590 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1591 if (!rx_param)
1592 return -ENOMEM;
1593
1594 rx_param->chan_id = index * 2 + 1;
1595 tx_param->chan_id = index * 2;
1596
1597 dma->rxconf.src_maxburst = 64;
1598 dma->txconf.dst_maxburst = 64;
1599
1600 rx_param->dma_dev = &dma_dev->dev;
1601 tx_param->dma_dev = &dma_dev->dev;
1602
1603 dma->fn = intel_mid_dma_filter;
1604 dma->rx_param = rx_param;
1605 dma->tx_param = tx_param;
1606
1607 port->port.type = PORT_16750;
1608 port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
1609 port->dma = dma;
1610
1611 return pci_default_setup(priv, board, port, idx);
1612}
1613
1614#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
1615#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
1616#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
1617
1618static int pnw_serial_setup(struct serial_private *priv,
1619 const struct pciserial_board *board,
1620 struct uart_8250_port *port, int idx)
1621{
1622 struct pci_dev *pdev = priv->dev;
1623 struct pci_dev *dma_dev;
1624 int index;
1625
1626 switch (pdev->device) {
1627 case PCI_DEVICE_ID_INTEL_PNW_UART1:
1628 index = 0;
1629 break;
1630 case PCI_DEVICE_ID_INTEL_PNW_UART2:
1631 index = 1;
1632 break;
1633 case PCI_DEVICE_ID_INTEL_PNW_UART3:
1634 index = 2;
1635 break;
1636 default:
1637 return -EINVAL;
1638 }
1639
1640 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
1641
1642 port->port.set_termios = intel_mid_set_termios_50M;
1643
1644 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1645}
1646
90b9aacf
AS		 1647#define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
1648
1649static int tng_serial_setup(struct serial_private *priv,
1650 const struct pciserial_board *board,
1651 struct uart_8250_port *port, int idx)
1652{
1653 struct pci_dev *pdev = priv->dev;
1654 struct pci_dev *dma_dev;
1655 int index = PCI_FUNC(pdev->devfn);
1656
1657 /* Currently no support for HSU port0 */
1658 if (index-- == 0)
1659 return -ENODEV;
1660
1661 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
1662
1663 port->port.set_termios = intel_mid_set_termios_38_4M;
1664
1665 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1666}
1667
d9a0fbfd
AP		 1668static int
1669pci_omegapci_setup(struct serial_private *priv,
1798ca13 1670 const struct pciserial_board *board,
2655a2c7 1671 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1672{
1673 return setup_port(priv, port, 2, idx * 8, 0);
1674}
1675
ebebd49a
SH		 1676static int
1677pci_brcm_trumanage_setup(struct serial_private *priv,
1678 const struct pciserial_board *board,
1679 struct uart_8250_port *port, int idx)
1680{
1681 int ret = pci_default_setup(priv, board, port, idx);
1682
1683 port->port.type = PORT_BRCM_TRUMANAGE;
1684 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1685 return ret;
1686}
1687
2c62a3c8
GKH		 1688static int pci_fintek_setup(struct serial_private *priv,
1689 const struct pciserial_board *board,
1690 struct uart_8250_port *port, int idx)
1691{
1692 struct pci_dev *pdev = priv->dev;
2c62a3c8 1693 unsigned long iobase;
2c62a3c8 1694 u8 config_base;
cb8ee9f0 1695 u32 bar_data[3];
2c62a3c8
GKH		 1696
1697 /*
cb8ee9f0 1698 * Find each UARTs offset in PCI configuraion space
2c62a3c8
GKH		 1699 */
1700 switch (idx) {
cb8ee9f0
PH		 1701 case 0:
1702 config_base = 0x40;
1703 break;
1704 case 1:
1705 config_base = 0x48;
1706 break;
1707 case 2:
1708 config_base = 0x50;
1709 break;
1710 case 3:
1711 config_base = 0x58;
1712 break;
1713 case 4:
1714 config_base = 0x60;
1715 break;
1716 case 5:
1717 config_base = 0x68;
1718 break;
1719 case 6:
1720 config_base = 0x70;
1721 break;
1722 case 7:
1723 config_base = 0x78;
1724 break;
1725 case 8:
1726 config_base = 0x80;
1727 break;
1728 case 9:
1729 config_base = 0x88;
1730 break;
1731 case 10:
1732 config_base = 0x90;
1733 break;
1734 case 11:
1735 config_base = 0x98;
1736 break;
2c62a3c8
GKH		 1737 default:
1738 /* Unknown number of ports, get out of here */
1739 return -EINVAL;
1740 }
1741
cb8ee9f0
PH		 1742 /* Get the io address dispatch from the BIOS */
1743 pci_read_config_dword(pdev, 0x24, &bar_data[0]);
1744 pci_read_config_dword(pdev, 0x20, &bar_data[1]);
1745 pci_read_config_dword(pdev, 0x1c, &bar_data[2]);
1746
1747 /* Calculate Real IO Port */
1748 iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8;
1749
77002c6f
PH		 1750 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx config_base=0x%2x\n",
1751 __func__, idx, iobase, config_base);
2c62a3c8
GKH		 1752
1753 /* Enable UART I/O port */
1754 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1755
1756 /* Select 128-byte FIFO and 8x FIFO threshold */
1757 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1758
1759 /* LSB UART */
1760 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1761
1762 /* MSB UART */
1763 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1764
1765 /* irq number, this usually fails, but the spec says to do it anyway. */
1766 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1767
1768 port->port.iotype = UPIO_PORT;
1769 port->port.iobase = iobase;
1770 port->port.mapbase = 0;
1771 port->port.membase = NULL;
1772 port->port.regshift = 0;
1773
1774 return 0;
1775}
1776
b6adea33
MCC		 1777static int skip_tx_en_setup(struct serial_private *priv,
1778 const struct pciserial_board *board,
2655a2c7 1779 struct uart_8250_port *port, int idx)
b6adea33 1780{
2655a2c7 1781 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1782 dev_dbg(&priv->dev->dev,
1783 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1784 priv->dev->vendor, priv->dev->device,
1785 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1786
1787 return pci_default_setup(priv, board, port, idx);
1788}
1789
0ad372b9
SM		 1790static void kt_handle_break(struct uart_port *p)
1791{
b1261c86 1792 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1793 /*
1794 * On receipt of a BI, serial device in Intel ME (Intel
1795 * management engine) needs to have its fifos cleared for sane
1796 * SOL (Serial Over Lan) output.
1797 */
1798 serial8250_clear_and_reinit_fifos(up);
1799}
1800
1801static unsigned int kt_serial_in(struct uart_port *p, int offset)
1802{
b1261c86 1803 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1804 unsigned int val;
1805
1806 /*
1807 * When the Intel ME (management engine) gets reset its serial
1808 * port registers could return 0 momentarily. Functions like
1809 * serial8250_console_write, read and save the IER, perform
1810 * some operation and then restore it. In order to avoid
1811 * setting IER register inadvertently to 0, if the value read
1812 * is 0, double check with ier value in uart_8250_port and use
1813 * that instead. up->ier should be the same value as what is
1814 * currently configured.
1815 */
1816 val = inb(p->iobase + offset);
1817 if (offset == UART_IER) {
1818 if (val == 0)
1819 val = up->ier;
1820 }
1821 return val;
1822}
1823
bc02d15a
DW		 1824static int kt_serial_setup(struct serial_private *priv,
1825 const struct pciserial_board *board,
2655a2c7 1826 struct uart_8250_port *port, int idx)
bc02d15a 1827{
2655a2c7
AC		 1828 port->port.flags |= UPF_BUG_THRE;
1829 port->port.serial_in = kt_serial_in;
1830 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1831 return skip_tx_en_setup(priv, board, port, idx);
1832}
1833
eb7073db
TM		 1834static int pci_eg20t_init(struct pci_dev *dev)
1835{
1836#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1837 return -ENODEV;
1838#else
1839 return 0;
1840#endif
1841}
1842
06315348
SH		 1843static int
1844pci_xr17c154_setup(struct serial_private *priv,
1845 const struct pciserial_board *board,
2655a2c7 1846 struct uart_8250_port *port, int idx)
06315348 1847{
2655a2c7 1848 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1849 return pci_default_setup(priv, board, port, idx);
1850}
1851
dc96efb7
MS		 1852static int
1853pci_xr17v35x_setup(struct serial_private *priv,
1854 const struct pciserial_board *board,
1855 struct uart_8250_port *port, int idx)
1856{
1857 u8 __iomem *p;
1858
1859 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1860 if (p == NULL)
1861 return -ENOMEM;
dc96efb7
MS		 1862
1863 port->port.flags |= UPF_EXAR_EFR;
1864
1865 /*
1866 * Setup Multipurpose Input/Output pins.
1867 */
1868 if (idx == 0) {
1869 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1870 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1871 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1872 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1873 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1874 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1875 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1876 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1877 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1878 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1879 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1880 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1881 }
f965b9c4
MS		 1882 writeb(0x00, p + UART_EXAR_8XMODE);
1883 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1884 writeb(128, p + UART_EXAR_TXTRG);
1885 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1886 iounmap(p);
1887
1888 return pci_default_setup(priv, board, port, idx);
1889}
1890
14faa8cc
MS		 1891#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1892#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1893#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1894#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1895
1896static int
1897pci_fastcom335_setup(struct serial_private *priv,
1898 const struct pciserial_board *board,
1899 struct uart_8250_port *port, int idx)
1900{
1901 u8 __iomem *p;
1902
1903 p = pci_ioremap_bar(priv->dev, 0);
1904 if (p == NULL)
1905 return -ENOMEM;
1906
1907 port->port.flags |= UPF_EXAR_EFR;
1908
1909 /*
1910 * Setup Multipurpose Input/Output pins.
1911 */
1912 if (idx == 0) {
1913 switch (priv->dev->device) {
1914 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1915 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1916 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1917 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1918 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1919 break;
1920 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1921 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1922 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1923 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1924 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1925 break;
1926 }
1927 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1928 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1929 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1930 }
1931 writeb(0x00, p + UART_EXAR_8XMODE);
1932 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1933 writeb(32, p + UART_EXAR_TXTRG);
1934 writeb(32, p + UART_EXAR_RXTRG);
1935 iounmap(p);
1936
1937 return pci_default_setup(priv, board, port, idx);
1938}
1939
6971c635
GA		 1940static int
1941pci_wch_ch353_setup(struct serial_private *priv,
1942 const struct pciserial_board *board,
1943 struct uart_8250_port *port, int idx)
1944{
1945 port->port.flags |= UPF_FIXED_TYPE;
1946 port->port.type = PORT_16550A;
06315348
SH		 1947 return pci_default_setup(priv, board, port, idx);
1948}
1949
2fdd8c8c 1950static int
72a3c0e4 1951pci_wch_ch38x_setup(struct serial_private *priv,
2fdd8c8c
SP		 1952 const struct pciserial_board *board,
1953 struct uart_8250_port *port, int idx)
1954{
1955 port->port.flags |= UPF_FIXED_TYPE;
1956 port->port.type = PORT_16850;
1957 return pci_default_setup(priv, board, port, idx);
1958}
1959
1da177e4
LT		 1960#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1961#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1962#define PCI_DEVICE_ID_OCTPRO 0x0001
1963#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1964#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1965#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1966#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1967#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1968#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1969#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1970#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1971#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
0c6d774c
TW		 1972#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1973#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
66169ad1
YY		 1974#define PCI_DEVICE_ID_TITAN_200I 0x8028
1975#define PCI_DEVICE_ID_TITAN_400I 0x8048
1976#define PCI_DEVICE_ID_TITAN_800I 0x8088
1977#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1978#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1979#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1980#define PCI_DEVICE_ID_TITAN_100E 0xA010
1981#define PCI_DEVICE_ID_TITAN_200E 0xA012
1982#define PCI_DEVICE_ID_TITAN_400E 0xA013
1983#define PCI_DEVICE_ID_TITAN_800E 0xA014
1984#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1985#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 1986#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 1987#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1988#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1989#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1990#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1991#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1992#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1993#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1994#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1995#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1996#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1997#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1998#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
feb58142 1999#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
27788c5f 2000#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 2001#define PCI_VENDOR_ID_AGESTAR 0x5372
2002#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 2003#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 2004#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
2005#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 2006#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 2007#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 2008#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1ede7dcc 2009#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
14faa8cc 2010
abd7baca
SC		 2011#define PCI_VENDOR_ID_SUNIX 0x1fd4
2012#define PCI_DEVICE_ID_SUNIX_1999 0x1999
2013
2fdd8c8c
SP		 2014#define PCIE_VENDOR_ID_WCH 0x1c00
2015#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
72a3c0e4 2016#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1da177e4 2017
b76c5a07
CB		 2018/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2019#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 2020#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 2021
1da177e4
LT		 2022/*
2023 * Master list of serial port init/setup/exit quirks.
2024 * This does not describe the general nature of the port.
2025 * (ie, baud base, number and location of ports, etc)
2026 *
2027 * This list is ordered alphabetically by vendor then device.
2028 * Specific entries must come before more generic entries.
2029 */
7a63ce5a 2030static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 2031 /*
2032 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2033 */
2034 {
086231f7 2035 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 2036 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 2037 .subvendor = PCI_ANY_ID,
2038 .subdevice = PCI_ANY_ID,
2039 .setup = addidata_apci7800_setup,
2040 },
1da177e4 2041 /*
61a116ef 2042 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 2043 * It is not clear whether this applies to all products.
2044 */
2045 {
2046 .vendor = PCI_VENDOR_ID_AFAVLAB,
2047 .device = PCI_ANY_ID,
2048 .subvendor = PCI_ANY_ID,
2049 .subdevice = PCI_ANY_ID,
2050 .setup = afavlab_setup,
2051 },
2052 /*
2053 * HP Diva
2054 */
2055 {
2056 .vendor = PCI_VENDOR_ID_HP,
2057 .device = PCI_DEVICE_ID_HP_DIVA,
2058 .subvendor = PCI_ANY_ID,
2059 .subdevice = PCI_ANY_ID,
2060 .init = pci_hp_diva_init,
2061 .setup = pci_hp_diva_setup,
2062 },
2063 /*
2064 * Intel
2065 */
2066 {
2067 .vendor = PCI_VENDOR_ID_INTEL,
2068 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2069 .subvendor = 0xe4bf,
2070 .subdevice = PCI_ANY_ID,
2071 .init = pci_inteli960ni_init,
2072 .setup = pci_default_setup,
2073 },
b6adea33
MCC		 2074 {
2075 .vendor = PCI_VENDOR_ID_INTEL,
2076 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2077 .subvendor = PCI_ANY_ID,
2078 .subdevice = PCI_ANY_ID,
2079 .setup = skip_tx_en_setup,
2080 },
2081 {
2082 .vendor = PCI_VENDOR_ID_INTEL,
2083 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2084 .subvendor = PCI_ANY_ID,
2085 .subdevice = PCI_ANY_ID,
2086 .setup = skip_tx_en_setup,
2087 },
2088 {
2089 .vendor = PCI_VENDOR_ID_INTEL,
2090 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2091 .subvendor = PCI_ANY_ID,
2092 .subdevice = PCI_ANY_ID,
2093 .setup = skip_tx_en_setup,
2094 },
095e24b0
DB		 2095 {
2096 .vendor = PCI_VENDOR_ID_INTEL,
2097 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2098 .subvendor = PCI_ANY_ID,
2099 .subdevice = PCI_ANY_ID,
2100 .setup = ce4100_serial_setup,
2101 },
bc02d15a
DW		 2102 {
2103 .vendor = PCI_VENDOR_ID_INTEL,
2104 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2105 .subvendor = PCI_ANY_ID,
2106 .subdevice = PCI_ANY_ID,
2107 .setup = kt_serial_setup,
2108 },
b15e5691
HK		 2109 {
2110 .vendor = PCI_VENDOR_ID_INTEL,
2111 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2112 .subvendor = PCI_ANY_ID,
2113 .subdevice = PCI_ANY_ID,
2114 .setup = byt_serial_setup,
2115 },
2116 {
2117 .vendor = PCI_VENDOR_ID_INTEL,
2118 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2119 .subvendor = PCI_ANY_ID,
2120 .subdevice = PCI_ANY_ID,
2121 .setup = byt_serial_setup,
2122 },
f549e94e
AS		 2123 {
2124 .vendor = PCI_VENDOR_ID_INTEL,
2125 .device = PCI_DEVICE_ID_INTEL_PNW_UART1,
2126 .subvendor = PCI_ANY_ID,
2127 .subdevice = PCI_ANY_ID,
2128 .setup = pnw_serial_setup,
2129 },
2130 {
2131 .vendor = PCI_VENDOR_ID_INTEL,
2132 .device = PCI_DEVICE_ID_INTEL_PNW_UART2,
2133 .subvendor = PCI_ANY_ID,
2134 .subdevice = PCI_ANY_ID,
2135 .setup = pnw_serial_setup,
2136 },
2137 {
2138 .vendor = PCI_VENDOR_ID_INTEL,
2139 .device = PCI_DEVICE_ID_INTEL_PNW_UART3,
2140 .subvendor = PCI_ANY_ID,
2141 .subdevice = PCI_ANY_ID,
2142 .setup = pnw_serial_setup,
2143 },
90b9aacf
AS		 2144 {
2145 .vendor = PCI_VENDOR_ID_INTEL,
2146 .device = PCI_DEVICE_ID_INTEL_TNG_UART,
2147 .subvendor = PCI_ANY_ID,
2148 .subdevice = PCI_ANY_ID,
2149 .setup = tng_serial_setup,
2150 },
29897087
AC		 2151 {
2152 .vendor = PCI_VENDOR_ID_INTEL,
2153 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2154 .subvendor = PCI_ANY_ID,
2155 .subdevice = PCI_ANY_ID,
2156 .setup = byt_serial_setup,
2157 },
2158 {
2159 .vendor = PCI_VENDOR_ID_INTEL,
2160 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2161 .subvendor = PCI_ANY_ID,
2162 .subdevice = PCI_ANY_ID,
2163 .setup = byt_serial_setup,
2164 },
84f8c6fc
NV		 2165 /*
2166 * ITE
2167 */
2168 {
2169 .vendor = PCI_VENDOR_ID_ITE,
2170 .device = PCI_DEVICE_ID_ITE_8872,
2171 .subvendor = PCI_ANY_ID,
2172 .subdevice = PCI_ANY_ID,
2173 .init = pci_ite887x_init,
2174 .setup = pci_default_setup,
2d47b716 2175 .exit = pci_ite887x_exit,
84f8c6fc 2176 },
46a0fac9
SB		 2177 /*
2178 * National Instruments
2179 */
04bf7e74
WP		 2180 {
2181 .vendor = PCI_VENDOR_ID_NI,
2182 .device = PCI_DEVICE_ID_NI_PCI23216,
2183 .subvendor = PCI_ANY_ID,
2184 .subdevice = PCI_ANY_ID,
2185 .init = pci_ni8420_init,
2186 .setup = pci_default_setup,
2d47b716 2187 .exit = pci_ni8420_exit,
04bf7e74
WP		 2188 },
2189 {
2190 .vendor = PCI_VENDOR_ID_NI,
2191 .device = PCI_DEVICE_ID_NI_PCI2328,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .init = pci_ni8420_init,
2195 .setup = pci_default_setup,
2d47b716 2196 .exit = pci_ni8420_exit,
04bf7e74
WP		 2197 },
2198 {
2199 .vendor = PCI_VENDOR_ID_NI,
2200 .device = PCI_DEVICE_ID_NI_PCI2324,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .init = pci_ni8420_init,
2204 .setup = pci_default_setup,
2d47b716 2205 .exit = pci_ni8420_exit,
04bf7e74
WP		 2206 },
2207 {
2208 .vendor = PCI_VENDOR_ID_NI,
2209 .device = PCI_DEVICE_ID_NI_PCI2322,
2210 .subvendor = PCI_ANY_ID,
2211 .subdevice = PCI_ANY_ID,
2212 .init = pci_ni8420_init,
2213 .setup = pci_default_setup,
2d47b716 2214 .exit = pci_ni8420_exit,
04bf7e74
WP		 2215 },
2216 {
2217 .vendor = PCI_VENDOR_ID_NI,
2218 .device = PCI_DEVICE_ID_NI_PCI2324I,
2219 .subvendor = PCI_ANY_ID,
2220 .subdevice = PCI_ANY_ID,
2221 .init = pci_ni8420_init,
2222 .setup = pci_default_setup,
2d47b716 2223 .exit = pci_ni8420_exit,
04bf7e74
WP		 2224 },
2225 {
2226 .vendor = PCI_VENDOR_ID_NI,
2227 .device = PCI_DEVICE_ID_NI_PCI2322I,
2228 .subvendor = PCI_ANY_ID,
2229 .subdevice = PCI_ANY_ID,
2230 .init = pci_ni8420_init,
2231 .setup = pci_default_setup,
2d47b716 2232 .exit = pci_ni8420_exit,
04bf7e74
WP		 2233 },
2234 {
2235 .vendor = PCI_VENDOR_ID_NI,
2236 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2237 .subvendor = PCI_ANY_ID,
2238 .subdevice = PCI_ANY_ID,
2239 .init = pci_ni8420_init,
2240 .setup = pci_default_setup,
2d47b716 2241 .exit = pci_ni8420_exit,
04bf7e74
WP		 2242 },
2243 {
2244 .vendor = PCI_VENDOR_ID_NI,
2245 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .init = pci_ni8420_init,
2249 .setup = pci_default_setup,
2d47b716 2250 .exit = pci_ni8420_exit,
04bf7e74
WP		 2251 },
2252 {
2253 .vendor = PCI_VENDOR_ID_NI,
2254 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .init = pci_ni8420_init,
2258 .setup = pci_default_setup,
2d47b716 2259 .exit = pci_ni8420_exit,
04bf7e74
WP		 2260 },
2261 {
2262 .vendor = PCI_VENDOR_ID_NI,
2263 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .init = pci_ni8420_init,
2267 .setup = pci_default_setup,
2d47b716 2268 .exit = pci_ni8420_exit,
04bf7e74
WP		 2269 },
2270 {
2271 .vendor = PCI_VENDOR_ID_NI,
2272 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2273 .subvendor = PCI_ANY_ID,
2274 .subdevice = PCI_ANY_ID,
2275 .init = pci_ni8420_init,
2276 .setup = pci_default_setup,
2d47b716 2277 .exit = pci_ni8420_exit,
04bf7e74
WP		 2278 },
2279 {
2280 .vendor = PCI_VENDOR_ID_NI,
2281 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2282 .subvendor = PCI_ANY_ID,
2283 .subdevice = PCI_ANY_ID,
2284 .init = pci_ni8420_init,
2285 .setup = pci_default_setup,
2d47b716 2286 .exit = pci_ni8420_exit,
04bf7e74 2287 },
46a0fac9
SB		 2288 {
2289 .vendor = PCI_VENDOR_ID_NI,
2290 .device = PCI_ANY_ID,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .init = pci_ni8430_init,
2294 .setup = pci_ni8430_setup,
2d47b716 2295 .exit = pci_ni8430_exit,
46a0fac9 2296 },
55c7c0fd
AC		 2297 /* Quatech */
2298 {
2299 .vendor = PCI_VENDOR_ID_QUATECH,
2300 .device = PCI_ANY_ID,
2301 .subvendor = PCI_ANY_ID,
2302 .subdevice = PCI_ANY_ID,
2303 .init = pci_quatech_init,
2304 .setup = pci_quatech_setup,
d73dfc6a 2305 .exit = pci_quatech_exit,
55c7c0fd 2306 },
1da177e4
LT		 2307 /*
2308 * Panacom
2309 */
2310 {
2311 .vendor = PCI_VENDOR_ID_PANACOM,
2312 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2313 .subvendor = PCI_ANY_ID,
2314 .subdevice = PCI_ANY_ID,
2315 .init = pci_plx9050_init,
2316 .setup = pci_default_setup,
2d47b716 2317 .exit = pci_plx9050_exit,
5756ee99 2318 },
1da177e4
LT		 2319 {
2320 .vendor = PCI_VENDOR_ID_PANACOM,
2321 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2322 .subvendor = PCI_ANY_ID,
2323 .subdevice = PCI_ANY_ID,
2324 .init = pci_plx9050_init,
2325 .setup = pci_default_setup,
2d47b716 2326 .exit = pci_plx9050_exit,
1da177e4 2327 },
94341475
AB		 2328 /*
2329 * Pericom
2330 */
2331 {
2332 .vendor = 0x12d8,
2333 .device = 0x7952,
2334 .subvendor = PCI_ANY_ID,
2335 .subdevice = PCI_ANY_ID,
2336 .setup = pci_pericom_setup,
2337 },
2338 {
2339 .vendor = 0x12d8,
2340 .device = 0x7954,
2341 .subvendor = PCI_ANY_ID,
2342 .subdevice = PCI_ANY_ID,
2343 .setup = pci_pericom_setup,
2344 },
2345 {
2346 .vendor = 0x12d8,
2347 .device = 0x7958,
2348 .subvendor = PCI_ANY_ID,
2349 .subdevice = PCI_ANY_ID,
2350 .setup = pci_pericom_setup,
2351 },
2352
1da177e4
LT		 2353 /*
2354 * PLX
2355 */
add7b58e
BH		 2356 {
2357 .vendor = PCI_VENDOR_ID_PLX,
2358 .device = PCI_DEVICE_ID_PLX_9050,
2359 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2360 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2361 .init = pci_plx9050_init,
2362 .setup = pci_default_setup,
2d47b716 2363 .exit = pci_plx9050_exit,
add7b58e 2364 },
1da177e4
LT		 2365 {
2366 .vendor = PCI_VENDOR_ID_PLX,
2367 .device = PCI_DEVICE_ID_PLX_9050,
2368 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2369 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2370 .init = pci_plx9050_init,
2371 .setup = pci_default_setup,
2d47b716 2372 .exit = pci_plx9050_exit,
1da177e4
LT		 2373 },
2374 {
2375 .vendor = PCI_VENDOR_ID_PLX,
2376 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2377 .subvendor = PCI_VENDOR_ID_PLX,
2378 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2379 .init = pci_plx9050_init,
2380 .setup = pci_default_setup,
2d47b716 2381 .exit = pci_plx9050_exit,
1da177e4
LT		 2382 },
2383 /*
2384 * SBS Technologies, Inc., PMC-OCTALPRO 232
2385 */
2386 {
2387 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2388 .device = PCI_DEVICE_ID_OCTPRO,
2389 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2390 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2391 .init = sbs_init,
2392 .setup = sbs_setup,
2d47b716 2393 .exit = sbs_exit,
1da177e4
LT		 2394 },
2395 /*
2396 * SBS Technologies, Inc., PMC-OCTALPRO 422
2397 */
2398 {
2399 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2400 .device = PCI_DEVICE_ID_OCTPRO,
2401 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2402 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2403 .init = sbs_init,
2404 .setup = sbs_setup,
2d47b716 2405 .exit = sbs_exit,
1da177e4
LT		 2406 },
2407 /*
2408 * SBS Technologies, Inc., P-Octal 232
2409 */
2410 {
2411 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2412 .device = PCI_DEVICE_ID_OCTPRO,
2413 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2414 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2415 .init = sbs_init,
2416 .setup = sbs_setup,
2d47b716 2417 .exit = sbs_exit,
1da177e4
LT		 2418 },
2419 /*
2420 * SBS Technologies, Inc., P-Octal 422
2421 */
2422 {
2423 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2424 .device = PCI_DEVICE_ID_OCTPRO,
2425 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2426 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2427 .init = sbs_init,
2428 .setup = sbs_setup,
2d47b716 2429 .exit = sbs_exit,
1da177e4 2430 },
1da177e4 2431 /*
61a116ef 2432 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2433 */
2434 {
2435 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2436 .device = PCI_ANY_ID,
1da177e4
LT		 2437 .subvendor = PCI_ANY_ID,
2438 .subdevice = PCI_ANY_ID,
67d74b87 2439 .init = pci_siig_init,
3ec9c594 2440 .setup = pci_siig_setup,
1da177e4
LT		 2441 },
2442 /*
2443 * Titan cards
2444 */
2445 {
2446 .vendor = PCI_VENDOR_ID_TITAN,
2447 .device = PCI_DEVICE_ID_TITAN_400L,
2448 .subvendor = PCI_ANY_ID,
2449 .subdevice = PCI_ANY_ID,
2450 .setup = titan_400l_800l_setup,
2451 },
2452 {
2453 .vendor = PCI_VENDOR_ID_TITAN,
2454 .device = PCI_DEVICE_ID_TITAN_800L,
2455 .subvendor = PCI_ANY_ID,
2456 .subdevice = PCI_ANY_ID,
2457 .setup = titan_400l_800l_setup,
2458 },
2459 /*
2460 * Timedia cards
2461 */
2462 {
2463 .vendor = PCI_VENDOR_ID_TIMEDIA,
2464 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2465 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2466 .subdevice = PCI_ANY_ID,
b9b24558 2467 .probe = pci_timedia_probe,
1da177e4
LT		 2468 .init = pci_timedia_init,
2469 .setup = pci_timedia_setup,
2470 },
2471 {
2472 .vendor = PCI_VENDOR_ID_TIMEDIA,
2473 .device = PCI_ANY_ID,
2474 .subvendor = PCI_ANY_ID,
2475 .subdevice = PCI_ANY_ID,
2476 .setup = pci_timedia_setup,
2477 },
abd7baca
SC		 2478 /*
2479 * SUNIX (Timedia) cards
2480 * Do not "probe" for these cards as there is at least one combination
2481 * card that should be handled by parport_pc that doesn't match the
2482 * rule in pci_timedia_probe.
2483 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2484 * There are some boards with part number SER5037AL that report
2485 * subdevice ID 0x0002.
2486 */
2487 {
2488 .vendor = PCI_VENDOR_ID_SUNIX,
2489 .device = PCI_DEVICE_ID_SUNIX_1999,
2490 .subvendor = PCI_VENDOR_ID_SUNIX,
2491 .subdevice = PCI_ANY_ID,
2492 .init = pci_timedia_init,
2493 .setup = pci_timedia_setup,
2494 },
06315348
SH		 2495 /*
2496 * Exar cards
2497 */
2498 {
2499 .vendor = PCI_VENDOR_ID_EXAR,
2500 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2501 .subvendor = PCI_ANY_ID,
2502 .subdevice = PCI_ANY_ID,
2503 .setup = pci_xr17c154_setup,
2504 },
2505 {
2506 .vendor = PCI_VENDOR_ID_EXAR,
2507 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2508 .subvendor = PCI_ANY_ID,
2509 .subdevice = PCI_ANY_ID,
2510 .setup = pci_xr17c154_setup,
2511 },
2512 {
2513 .vendor = PCI_VENDOR_ID_EXAR,
2514 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2515 .subvendor = PCI_ANY_ID,
2516 .subdevice = PCI_ANY_ID,
2517 .setup = pci_xr17c154_setup,
2518 },
dc96efb7
MS		 2519 {
2520 .vendor = PCI_VENDOR_ID_EXAR,
2521 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2522 .subvendor = PCI_ANY_ID,
2523 .subdevice = PCI_ANY_ID,
2524 .setup = pci_xr17v35x_setup,
2525 },
2526 {
2527 .vendor = PCI_VENDOR_ID_EXAR,
2528 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2529 .subvendor = PCI_ANY_ID,
2530 .subdevice = PCI_ANY_ID,
2531 .setup = pci_xr17v35x_setup,
2532 },
2533 {
2534 .vendor = PCI_VENDOR_ID_EXAR,
2535 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2536 .subvendor = PCI_ANY_ID,
2537 .subdevice = PCI_ANY_ID,
2538 .setup = pci_xr17v35x_setup,
2539 },
1da177e4
LT		 2540 /*
2541 * Xircom cards
2542 */
2543 {
2544 .vendor = PCI_VENDOR_ID_XIRCOM,
2545 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2546 .subvendor = PCI_ANY_ID,
2547 .subdevice = PCI_ANY_ID,
2548 .init = pci_xircom_init,
2549 .setup = pci_default_setup,
2550 },
2551 /*
61a116ef 2552 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2553 */
2554 {
2555 .vendor = PCI_VENDOR_ID_NETMOS,
2556 .device = PCI_ANY_ID,
2557 .subvendor = PCI_ANY_ID,
2558 .subdevice = PCI_ANY_ID,
2559 .init = pci_netmos_init,
7808edcd 2560 .setup = pci_netmos_9900_setup,
1da177e4 2561 },
1bc8cde4
MS		 2562 /*
2563 * EndRun Technologies
2564 */
2565 {
2566 .vendor = PCI_VENDOR_ID_ENDRUN,
2567 .device = PCI_ANY_ID,
2568 .subvendor = PCI_ANY_ID,
2569 .subdevice = PCI_ANY_ID,
2570 .init = pci_endrun_init,
2571 .setup = pci_default_setup,
2572 },
9f2a036a 2573 /*
aa273ae5 2574 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2575 */
2576 {
2577 .vendor = PCI_VENDOR_ID_OXSEMI,
2578 .device = PCI_ANY_ID,
2579 .subvendor = PCI_ANY_ID,
2580 .subdevice = PCI_ANY_ID,
2581 .init = pci_oxsemi_tornado_init,
2582 .setup = pci_default_setup,
2583 },
2584 {
2585 .vendor = PCI_VENDOR_ID_MAINPINE,
2586 .device = PCI_ANY_ID,
2587 .subvendor = PCI_ANY_ID,
2588 .subdevice = PCI_ANY_ID,
2589 .init = pci_oxsemi_tornado_init,
2590 .setup = pci_default_setup,
2591 },
aa273ae5
SK		 2592 {
2593 .vendor = PCI_VENDOR_ID_DIGI,
2594 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2595 .subvendor = PCI_SUBVENDOR_ID_IBM,
2596 .subdevice = PCI_ANY_ID,
2597 .init = pci_oxsemi_tornado_init,
2598 .setup = pci_default_setup,
2599 },
eb7073db
TM		 2600 {
2601 .vendor = PCI_VENDOR_ID_INTEL,
2602 .device = 0x8811,
aaa10eb1
AP		 2603 .subvendor = PCI_ANY_ID,
2604 .subdevice = PCI_ANY_ID,
eb7073db 2605 .init = pci_eg20t_init,
64d91cfa 2606 .setup = pci_default_setup,
eb7073db
TM		 2607 },
2608 {
2609 .vendor = PCI_VENDOR_ID_INTEL,
2610 .device = 0x8812,
aaa10eb1
AP		 2611 .subvendor = PCI_ANY_ID,
2612 .subdevice = PCI_ANY_ID,
eb7073db 2613 .init = pci_eg20t_init,
64d91cfa 2614 .setup = pci_default_setup,
eb7073db
TM		 2615 },
2616 {
2617 .vendor = PCI_VENDOR_ID_INTEL,
2618 .device = 0x8813,
aaa10eb1
AP		 2619 .subvendor = PCI_ANY_ID,
2620 .subdevice = PCI_ANY_ID,
eb7073db 2621 .init = pci_eg20t_init,
64d91cfa 2622 .setup = pci_default_setup,
eb7073db
TM		 2623 },
2624 {
2625 .vendor = PCI_VENDOR_ID_INTEL,
2626 .device = 0x8814,
aaa10eb1
AP		 2627 .subvendor = PCI_ANY_ID,
2628 .subdevice = PCI_ANY_ID,
eb7073db 2629 .init = pci_eg20t_init,
64d91cfa 2630 .setup = pci_default_setup,
eb7073db
TM		 2631 },
2632 {
2633 .vendor = 0x10DB,
2634 .device = 0x8027,
aaa10eb1
AP		 2635 .subvendor = PCI_ANY_ID,
2636 .subdevice = PCI_ANY_ID,
eb7073db 2637 .init = pci_eg20t_init,
64d91cfa 2638 .setup = pci_default_setup,
eb7073db
TM		 2639 },
2640 {
2641 .vendor = 0x10DB,
2642 .device = 0x8028,
aaa10eb1
AP		 2643 .subvendor = PCI_ANY_ID,
2644 .subdevice = PCI_ANY_ID,
eb7073db 2645 .init = pci_eg20t_init,
64d91cfa 2646 .setup = pci_default_setup,
eb7073db
TM		 2647 },
2648 {
2649 .vendor = 0x10DB,
2650 .device = 0x8029,
aaa10eb1
AP		 2651 .subvendor = PCI_ANY_ID,
2652 .subdevice = PCI_ANY_ID,
eb7073db 2653 .init = pci_eg20t_init,
64d91cfa 2654 .setup = pci_default_setup,
eb7073db
TM		 2655 },
2656 {
2657 .vendor = 0x10DB,
2658 .device = 0x800C,
aaa10eb1
AP		 2659 .subvendor = PCI_ANY_ID,
2660 .subdevice = PCI_ANY_ID,
eb7073db 2661 .init = pci_eg20t_init,
64d91cfa 2662 .setup = pci_default_setup,
eb7073db
TM		 2663 },
2664 {
2665 .vendor = 0x10DB,
2666 .device = 0x800D,
aaa10eb1
AP		 2667 .subvendor = PCI_ANY_ID,
2668 .subdevice = PCI_ANY_ID,
eb7073db 2669 .init = pci_eg20t_init,
64d91cfa 2670 .setup = pci_default_setup,
eb7073db 2671 },
d9a0fbfd
AP		 2672 /*
2673 * Cronyx Omega PCI (PLX-chip based)
2674 */
2675 {
2676 .vendor = PCI_VENDOR_ID_PLX,
2677 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2678 .subvendor = PCI_ANY_ID,
2679 .subdevice = PCI_ANY_ID,
2680 .setup = pci_omegapci_setup,
eb26dfe8 2681 },
feb58142
EG		 2682 /* WCH CH353 1S1P card (16550 clone) */
2683 {
2684 .vendor = PCI_VENDOR_ID_WCH,
2685 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2686 .subvendor = PCI_ANY_ID,
2687 .subdevice = PCI_ANY_ID,
2688 .setup = pci_wch_ch353_setup,
2689 },
6971c635
GA		 2690 /* WCH CH353 2S1P card (16550 clone) */
2691 {
27788c5f
AC		 2692 .vendor = PCI_VENDOR_ID_WCH,
2693 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2694 .subvendor = PCI_ANY_ID,
2695 .subdevice = PCI_ANY_ID,
2696 .setup = pci_wch_ch353_setup,
2697 },
2698 /* WCH CH353 4S card (16550 clone) */
2699 {
2700 .vendor = PCI_VENDOR_ID_WCH,
2701 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2702 .subvendor = PCI_ANY_ID,
2703 .subdevice = PCI_ANY_ID,
2704 .setup = pci_wch_ch353_setup,
2705 },
2706 /* WCH CH353 2S1PF card (16550 clone) */
2707 {
2708 .vendor = PCI_VENDOR_ID_WCH,
2709 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2710 .subvendor = PCI_ANY_ID,
2711 .subdevice = PCI_ANY_ID,
6971c635
GA		 2712 .setup = pci_wch_ch353_setup,
2713 },
8b5c913f
WY		 2714 /* WCH CH352 2S card (16550 clone) */
2715 {
2716 .vendor = PCI_VENDOR_ID_WCH,
2717 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2718 .subvendor = PCI_ANY_ID,
2719 .subdevice = PCI_ANY_ID,
2720 .setup = pci_wch_ch353_setup,
2721 },
72a3c0e4 2722 /* WCH CH382 2S1P card (16850 clone) */
2fdd8c8c
SP		 2723 {
2724 .vendor = PCIE_VENDOR_ID_WCH,
2725 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2726 .subvendor = PCI_ANY_ID,
2727 .subdevice = PCI_ANY_ID,
72a3c0e4
SP		 2728 .setup = pci_wch_ch38x_setup,
2729 },
2730 /* WCH CH384 4S card (16850 clone) */
2731 {
2732 .vendor = PCIE_VENDOR_ID_WCH,
2733 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2734 .subvendor = PCI_ANY_ID,
2735 .subdevice = PCI_ANY_ID,
2736 .setup = pci_wch_ch38x_setup,
2fdd8c8c 2737 },
eb26dfe8
AC		 2738 /*
2739 * ASIX devices with FIFO bug
2740 */
2741 {
2742 .vendor = PCI_VENDOR_ID_ASIX,
2743 .device = PCI_ANY_ID,
2744 .subvendor = PCI_ANY_ID,
2745 .subdevice = PCI_ANY_ID,
2746 .setup = pci_asix_setup,
2747 },
14faa8cc
MS		 2748 /*
2749 * Commtech, Inc. Fastcom adapters
2750 *
2751 */
2752 {
2753 .vendor = PCI_VENDOR_ID_COMMTECH,
2754 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2755 .subvendor = PCI_ANY_ID,
2756 .subdevice = PCI_ANY_ID,
2757 .setup = pci_fastcom335_setup,
2758 },
2759 {
2760 .vendor = PCI_VENDOR_ID_COMMTECH,
2761 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2762 .subvendor = PCI_ANY_ID,
2763 .subdevice = PCI_ANY_ID,
2764 .setup = pci_fastcom335_setup,
2765 },
2766 {
2767 .vendor = PCI_VENDOR_ID_COMMTECH,
2768 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2769 .subvendor = PCI_ANY_ID,
2770 .subdevice = PCI_ANY_ID,
2771 .setup = pci_fastcom335_setup,
2772 },
2773 {
2774 .vendor = PCI_VENDOR_ID_COMMTECH,
2775 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2776 .subvendor = PCI_ANY_ID,
2777 .subdevice = PCI_ANY_ID,
2778 .setup = pci_fastcom335_setup,
2779 },
2780 {
2781 .vendor = PCI_VENDOR_ID_COMMTECH,
2782 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2783 .subvendor = PCI_ANY_ID,
2784 .subdevice = PCI_ANY_ID,
2785 .setup = pci_xr17v35x_setup,
2786 },
2787 {
2788 .vendor = PCI_VENDOR_ID_COMMTECH,
2789 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2790 .subvendor = PCI_ANY_ID,
2791 .subdevice = PCI_ANY_ID,
2792 .setup = pci_xr17v35x_setup,
2793 },
2794 {
2795 .vendor = PCI_VENDOR_ID_COMMTECH,
2796 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2797 .subvendor = PCI_ANY_ID,
2798 .subdevice = PCI_ANY_ID,
2799 .setup = pci_xr17v35x_setup,
2800 },
ebebd49a
SH		 2801 /*
2802 * Broadcom TruManage (NetXtreme)
2803 */
2804 {
2805 .vendor = PCI_VENDOR_ID_BROADCOM,
2806 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2807 .subvendor = PCI_ANY_ID,
2808 .subdevice = PCI_ANY_ID,
2809 .setup = pci_brcm_trumanage_setup,
2810 },
2c62a3c8
GKH		 2811 {
2812 .vendor = 0x1c29,
2813 .device = 0x1104,
2814 .subvendor = PCI_ANY_ID,
2815 .subdevice = PCI_ANY_ID,
2816 .setup = pci_fintek_setup,
2817 },
2818 {
2819 .vendor = 0x1c29,
2820 .device = 0x1108,
2821 .subvendor = PCI_ANY_ID,
2822 .subdevice = PCI_ANY_ID,
2823 .setup = pci_fintek_setup,
2824 },
2825 {
2826 .vendor = 0x1c29,
2827 .device = 0x1112,
2828 .subvendor = PCI_ANY_ID,
2829 .subdevice = PCI_ANY_ID,
2830 .setup = pci_fintek_setup,
2831 },
ebebd49a 2832
1da177e4
LT		 2833 /*
2834 * Default "match everything" terminator entry
2835 */
2836 {
2837 .vendor = PCI_ANY_ID,
2838 .device = PCI_ANY_ID,
2839 .subvendor = PCI_ANY_ID,
2840 .subdevice = PCI_ANY_ID,
2841 .setup = pci_default_setup,
2842 }
2843};
2844
2845static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2846{
2847 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2848}
2849
2850static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2851{
2852 struct pci_serial_quirk *quirk;
2853
2854 for (quirk = pci_serial_quirks; ; quirk++)
2855 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2856 quirk_id_matches(quirk->device, dev->device) &&
2857 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2858 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2859 break;
1da177e4
LT		 2860 return quirk;
2861}
2862
dd68e88c 2863static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2864 const struct pciserial_board *board)
1da177e4
LT		 2865{
2866 if (board->flags & FL_NOIRQ)
2867 return 0;
2868 else
2869 return dev->irq;
2870}
2871
2872/*
2873 * This is the configuration table for all of the PCI serial boards
2874 * which we support. It is directly indexed by the pci_board_num_t enum
2875 * value, which is encoded in the pci_device_id PCI probe table's
2876 * driver_data member.
2877 *
2878 * The makeup of these names are:
26e92861 2879 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2880 *
26e92861
GH		 2881 * bn = PCI BAR number
2882 * bt = Index using PCI BARs
2883 * n = number of serial ports
2884 * baud = baud rate
2885 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2886 *
26e92861 2887 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2888 *
1da177e4
LT		 2889 * Please note: in theory if n = 1, _bt infix should make no difference.
2890 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2891 */
2892enum pci_board_num_t {
2893 pbn_default = 0,
2894
2895 pbn_b0_1_115200,
2896 pbn_b0_2_115200,
2897 pbn_b0_4_115200,
2898 pbn_b0_5_115200,
bf0df636 2899 pbn_b0_8_115200,
1da177e4
LT		 2900
2901 pbn_b0_1_921600,
2902 pbn_b0_2_921600,
2903 pbn_b0_4_921600,
2904
db1de159
DR		 2905 pbn_b0_2_1130000,
2906
fbc0dc0d
AP		 2907 pbn_b0_4_1152000,
2908
14faa8cc
MS		 2909 pbn_b0_2_1152000_200,
2910 pbn_b0_4_1152000_200,
2911 pbn_b0_8_1152000_200,
2912
26e92861
GH		 2913 pbn_b0_2_1843200,
2914 pbn_b0_4_1843200,
2915
2916 pbn_b0_2_1843200_200,
2917 pbn_b0_4_1843200_200,
2918 pbn_b0_8_1843200_200,
2919
7106b4e3
LH		 2920 pbn_b0_1_4000000,
2921
1da177e4
LT		 2922 pbn_b0_bt_1_115200,
2923 pbn_b0_bt_2_115200,
ac6ec5b1 2924 pbn_b0_bt_4_115200,
1da177e4
LT		 2925 pbn_b0_bt_8_115200,
2926
2927 pbn_b0_bt_1_460800,
2928 pbn_b0_bt_2_460800,
2929 pbn_b0_bt_4_460800,
2930
2931 pbn_b0_bt_1_921600,
2932 pbn_b0_bt_2_921600,
2933 pbn_b0_bt_4_921600,
2934 pbn_b0_bt_8_921600,
2935
2936 pbn_b1_1_115200,
2937 pbn_b1_2_115200,
2938 pbn_b1_4_115200,
2939 pbn_b1_8_115200,
04bf7e74 2940 pbn_b1_16_115200,
1da177e4
LT		 2941
2942 pbn_b1_1_921600,
2943 pbn_b1_2_921600,
2944 pbn_b1_4_921600,
2945 pbn_b1_8_921600,
2946
26e92861
GH		 2947 pbn_b1_2_1250000,
2948
84f8c6fc 2949 pbn_b1_bt_1_115200,
04bf7e74
WP		 2950 pbn_b1_bt_2_115200,
2951 pbn_b1_bt_4_115200,
2952
1da177e4
LT		 2953 pbn_b1_bt_2_921600,
2954
2955 pbn_b1_1_1382400,
2956 pbn_b1_2_1382400,
2957 pbn_b1_4_1382400,
2958 pbn_b1_8_1382400,
2959
2960 pbn_b2_1_115200,
737c1756 2961 pbn_b2_2_115200,
a9cccd34 2962 pbn_b2_4_115200,
1da177e4
LT		 2963 pbn_b2_8_115200,
2964
2965 pbn_b2_1_460800,
2966 pbn_b2_4_460800,
2967 pbn_b2_8_460800,
2968 pbn_b2_16_460800,
2969
2970 pbn_b2_1_921600,
2971 pbn_b2_4_921600,
2972 pbn_b2_8_921600,
2973
e847003f
LB		 2974 pbn_b2_8_1152000,
2975
1da177e4
LT		 2976 pbn_b2_bt_1_115200,
2977 pbn_b2_bt_2_115200,
2978 pbn_b2_bt_4_115200,
2979
2980 pbn_b2_bt_2_921600,
2981 pbn_b2_bt_4_921600,
2982
d9004eb4 2983 pbn_b3_2_115200,
1da177e4
LT		 2984 pbn_b3_4_115200,
2985 pbn_b3_8_115200,
2986
66169ad1
YY		 2987 pbn_b4_bt_2_921600,
2988 pbn_b4_bt_4_921600,
2989 pbn_b4_bt_8_921600,
2990
1da177e4
LT		 2991 /*
2992 * Board-specific versions.
2993 */
2994 pbn_panacom,
2995 pbn_panacom2,
2996 pbn_panacom4,
2997 pbn_plx_romulus,
1bc8cde4 2998 pbn_endrun_2_4000000,
1da177e4 2999 pbn_oxsemi,
7106b4e3
LH		 3000 pbn_oxsemi_1_4000000,
3001 pbn_oxsemi_2_4000000,
3002 pbn_oxsemi_4_4000000,
3003 pbn_oxsemi_8_4000000,
1da177e4
LT		 3004 pbn_intel_i960,
3005 pbn_sgi_ioc3,
1da177e4
LT		 3006 pbn_computone_4,
3007 pbn_computone_6,
3008 pbn_computone_8,
3009 pbn_sbsxrsio,
3010 pbn_exar_XR17C152,
3011 pbn_exar_XR17C154,
3012 pbn_exar_XR17C158,
dc96efb7
MS		 3013 pbn_exar_XR17V352,
3014 pbn_exar_XR17V354,
3015 pbn_exar_XR17V358,
c68d2b15 3016 pbn_exar_ibm_saturn,
aa798505 3017 pbn_pasemi_1682M,
46a0fac9
SB		 3018 pbn_ni8430_2,
3019 pbn_ni8430_4,
3020 pbn_ni8430_8,
3021 pbn_ni8430_16,
1b62cbf2
KJ		 3022 pbn_ADDIDATA_PCIe_1_3906250,
3023 pbn_ADDIDATA_PCIe_2_3906250,
3024 pbn_ADDIDATA_PCIe_4_3906250,
3025 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 3026 pbn_ce4100_1_115200,
b15e5691 3027 pbn_byt,
f549e94e 3028 pbn_pnw,
90b9aacf 3029 pbn_tng,
1ede7dcc 3030 pbn_qrk,
d9a0fbfd 3031 pbn_omegapci,
7808edcd 3032 pbn_NETMOS9900_2s_115200,
ebebd49a 3033 pbn_brcm_trumanage,
2c62a3c8
GKH		 3034 pbn_fintek_4,
3035 pbn_fintek_8,
3036 pbn_fintek_12,
72a3c0e4 3037 pbn_wch384_4,
1da177e4
LT		 3038};
3039
3040/*
3041 * uart_offset - the space between channels
3042 * reg_shift - describes how the UART registers are mapped
3043 * to PCI memory by the card.
3044 * For example IER register on SBS, Inc. PMC-OctPro is located at
3045 * offset 0x10 from the UART base, while UART_IER is defined as 1
3046 * in include/linux/serial_reg.h,
3047 * see first lines of serial_in() and serial_out() in 8250.c
3048*/
3049
de88b340 3050static struct pciserial_board pci_boards[] = {
1da177e4
LT		 3051 [pbn_default] = {
3052 .flags = FL_BASE0,
3053 .num_ports = 1,
3054 .base_baud = 115200,
3055 .uart_offset = 8,
3056 },
3057 [pbn_b0_1_115200] = {
3058 .flags = FL_BASE0,
3059 .num_ports = 1,
3060 .base_baud = 115200,
3061 .uart_offset = 8,
3062 },
3063 [pbn_b0_2_115200] = {
3064 .flags = FL_BASE0,
3065 .num_ports = 2,
3066 .base_baud = 115200,
3067 .uart_offset = 8,
3068 },
3069 [pbn_b0_4_115200] = {
3070 .flags = FL_BASE0,
3071 .num_ports = 4,
3072 .base_baud = 115200,
3073 .uart_offset = 8,
3074 },
3075 [pbn_b0_5_115200] = {
3076 .flags = FL_BASE0,
3077 .num_ports = 5,
3078 .base_baud = 115200,
3079 .uart_offset = 8,
3080 },
bf0df636
AC		 3081 [pbn_b0_8_115200] = {
3082 .flags = FL_BASE0,
3083 .num_ports = 8,
3084 .base_baud = 115200,
3085 .uart_offset = 8,
3086 },
1da177e4
LT		 3087 [pbn_b0_1_921600] = {
3088 .flags = FL_BASE0,
3089 .num_ports = 1,
3090 .base_baud = 921600,
3091 .uart_offset = 8,
3092 },
3093 [pbn_b0_2_921600] = {
3094 .flags = FL_BASE0,
3095 .num_ports = 2,
3096 .base_baud = 921600,
3097 .uart_offset = 8,
3098 },
3099 [pbn_b0_4_921600] = {
3100 .flags = FL_BASE0,
3101 .num_ports = 4,
3102 .base_baud = 921600,
3103 .uart_offset = 8,
3104 },
db1de159
DR		 3105
3106 [pbn_b0_2_1130000] = {
3107 .flags = FL_BASE0,
3108 .num_ports = 2,
3109 .base_baud = 1130000,
3110 .uart_offset = 8,
3111 },
3112
fbc0dc0d
AP		 3113 [pbn_b0_4_1152000] = {
3114 .flags = FL_BASE0,
3115 .num_ports = 4,
3116 .base_baud = 1152000,
3117 .uart_offset = 8,
3118 },
1da177e4 3119
14faa8cc
MS		 3120 [pbn_b0_2_1152000_200] = {
3121 .flags = FL_BASE0,
3122 .num_ports = 2,
3123 .base_baud = 1152000,
3124 .uart_offset = 0x200,
3125 },
3126
3127 [pbn_b0_4_1152000_200] = {
3128 .flags = FL_BASE0,
3129 .num_ports = 4,
3130 .base_baud = 1152000,
3131 .uart_offset = 0x200,
3132 },
3133
3134 [pbn_b0_8_1152000_200] = {
3135 .flags = FL_BASE0,
4f7d67d0 3136 .num_ports = 8,
14faa8cc
MS		 3137 .base_baud = 1152000,
3138 .uart_offset = 0x200,
3139 },
3140
26e92861
GH		 3141 [pbn_b0_2_1843200] = {
3142 .flags = FL_BASE0,
3143 .num_ports = 2,
3144 .base_baud = 1843200,
3145 .uart_offset = 8,
3146 },
3147 [pbn_b0_4_1843200] = {
3148 .flags = FL_BASE0,
3149 .num_ports = 4,
3150 .base_baud = 1843200,
3151 .uart_offset = 8,
3152 },
3153
3154 [pbn_b0_2_1843200_200] = {
3155 .flags = FL_BASE0,
3156 .num_ports = 2,
3157 .base_baud = 1843200,
3158 .uart_offset = 0x200,
3159 },
3160 [pbn_b0_4_1843200_200] = {
3161 .flags = FL_BASE0,
3162 .num_ports = 4,
3163 .base_baud = 1843200,
3164 .uart_offset = 0x200,
3165 },
3166 [pbn_b0_8_1843200_200] = {
3167 .flags = FL_BASE0,
3168 .num_ports = 8,
3169 .base_baud = 1843200,
3170 .uart_offset = 0x200,
3171 },
7106b4e3
LH		 3172 [pbn_b0_1_4000000] = {
3173 .flags = FL_BASE0,
3174 .num_ports = 1,
3175 .base_baud = 4000000,
3176 .uart_offset = 8,
3177 },
26e92861 3178
1da177e4
LT		 3179 [pbn_b0_bt_1_115200] = {
3180 .flags = FL_BASE0|FL_BASE_BARS,
3181 .num_ports = 1,
3182 .base_baud = 115200,
3183 .uart_offset = 8,
3184 },
3185 [pbn_b0_bt_2_115200] = {
3186 .flags = FL_BASE0|FL_BASE_BARS,
3187 .num_ports = 2,
3188 .base_baud = 115200,
3189 .uart_offset = 8,
3190 },
ac6ec5b1
IS		 3191 [pbn_b0_bt_4_115200] = {
3192 .flags = FL_BASE0|FL_BASE_BARS,
3193 .num_ports = 4,
3194 .base_baud = 115200,
3195 .uart_offset = 8,
3196 },
1da177e4
LT		 3197 [pbn_b0_bt_8_115200] = {
3198 .flags = FL_BASE0|FL_BASE_BARS,
3199 .num_ports = 8,
3200 .base_baud = 115200,
3201 .uart_offset = 8,
3202 },
3203
3204 [pbn_b0_bt_1_460800] = {
3205 .flags = FL_BASE0|FL_BASE_BARS,
3206 .num_ports = 1,
3207 .base_baud = 460800,
3208 .uart_offset = 8,
3209 },
3210 [pbn_b0_bt_2_460800] = {
3211 .flags = FL_BASE0|FL_BASE_BARS,
3212 .num_ports = 2,
3213 .base_baud = 460800,
3214 .uart_offset = 8,
3215 },
3216 [pbn_b0_bt_4_460800] = {
3217 .flags = FL_BASE0|FL_BASE_BARS,
3218 .num_ports = 4,
3219 .base_baud = 460800,
3220 .uart_offset = 8,
3221 },
3222
3223 [pbn_b0_bt_1_921600] = {
3224 .flags = FL_BASE0|FL_BASE_BARS,
3225 .num_ports = 1,
3226 .base_baud = 921600,
3227 .uart_offset = 8,
3228 },
3229 [pbn_b0_bt_2_921600] = {
3230 .flags = FL_BASE0|FL_BASE_BARS,
3231 .num_ports = 2,
3232 .base_baud = 921600,
3233 .uart_offset = 8,
3234 },
3235 [pbn_b0_bt_4_921600] = {
3236 .flags = FL_BASE0|FL_BASE_BARS,
3237 .num_ports = 4,
3238 .base_baud = 921600,
3239 .uart_offset = 8,
3240 },
3241 [pbn_b0_bt_8_921600] = {
3242 .flags = FL_BASE0|FL_BASE_BARS,
3243 .num_ports = 8,
3244 .base_baud = 921600,
3245 .uart_offset = 8,
3246 },
3247
3248 [pbn_b1_1_115200] = {
3249 .flags = FL_BASE1,
3250 .num_ports = 1,
3251 .base_baud = 115200,
3252 .uart_offset = 8,
3253 },
3254 [pbn_b1_2_115200] = {
3255 .flags = FL_BASE1,
3256 .num_ports = 2,
3257 .base_baud = 115200,
3258 .uart_offset = 8,
3259 },
3260 [pbn_b1_4_115200] = {
3261 .flags = FL_BASE1,
3262 .num_ports = 4,
3263 .base_baud = 115200,
3264 .uart_offset = 8,
3265 },
3266 [pbn_b1_8_115200] = {
3267 .flags = FL_BASE1,
3268 .num_ports = 8,
3269 .base_baud = 115200,
3270 .uart_offset = 8,
3271 },
04bf7e74
WP		 3272 [pbn_b1_16_115200] = {
3273 .flags = FL_BASE1,
3274 .num_ports = 16,
3275 .base_baud = 115200,
3276 .uart_offset = 8,
3277 },
1da177e4
LT		 3278
3279 [pbn_b1_1_921600] = {
3280 .flags = FL_BASE1,
3281 .num_ports = 1,
3282 .base_baud = 921600,
3283 .uart_offset = 8,
3284 },
3285 [pbn_b1_2_921600] = {
3286 .flags = FL_BASE1,
3287 .num_ports = 2,
3288 .base_baud = 921600,
3289 .uart_offset = 8,
3290 },
3291 [pbn_b1_4_921600] = {
3292 .flags = FL_BASE1,
3293 .num_ports = 4,
3294 .base_baud = 921600,
3295 .uart_offset = 8,
3296 },
3297 [pbn_b1_8_921600] = {
3298 .flags = FL_BASE1,
3299 .num_ports = 8,
3300 .base_baud = 921600,
3301 .uart_offset = 8,
3302 },
26e92861
GH		 3303 [pbn_b1_2_1250000] = {
3304 .flags = FL_BASE1,
3305 .num_ports = 2,
3306 .base_baud = 1250000,
3307 .uart_offset = 8,
3308 },
1da177e4 3309
84f8c6fc
NV		 3310 [pbn_b1_bt_1_115200] = {
3311 .flags = FL_BASE1|FL_BASE_BARS,
3312 .num_ports = 1,
3313 .base_baud = 115200,
3314 .uart_offset = 8,
3315 },
04bf7e74
WP		 3316 [pbn_b1_bt_2_115200] = {
3317 .flags = FL_BASE1|FL_BASE_BARS,
3318 .num_ports = 2,
3319 .base_baud = 115200,
3320 .uart_offset = 8,
3321 },
3322 [pbn_b1_bt_4_115200] = {
3323 .flags = FL_BASE1|FL_BASE_BARS,
3324 .num_ports = 4,
3325 .base_baud = 115200,
3326 .uart_offset = 8,
3327 },
84f8c6fc 3328
1da177e4
LT		 3329 [pbn_b1_bt_2_921600] = {
3330 .flags = FL_BASE1|FL_BASE_BARS,
3331 .num_ports = 2,
3332 .base_baud = 921600,
3333 .uart_offset = 8,
3334 },
3335
3336 [pbn_b1_1_1382400] = {
3337 .flags = FL_BASE1,
3338 .num_ports = 1,
3339 .base_baud = 1382400,
3340 .uart_offset = 8,
3341 },
3342 [pbn_b1_2_1382400] = {
3343 .flags = FL_BASE1,
3344 .num_ports = 2,
3345 .base_baud = 1382400,
3346 .uart_offset = 8,
3347 },
3348 [pbn_b1_4_1382400] = {
3349 .flags = FL_BASE1,
3350 .num_ports = 4,
3351 .base_baud = 1382400,
3352 .uart_offset = 8,
3353 },
3354 [pbn_b1_8_1382400] = {
3355 .flags = FL_BASE1,
3356 .num_ports = 8,
3357 .base_baud = 1382400,
3358 .uart_offset = 8,
3359 },
3360
3361 [pbn_b2_1_115200] = {
3362 .flags = FL_BASE2,
3363 .num_ports = 1,
3364 .base_baud = 115200,
3365 .uart_offset = 8,
3366 },
737c1756
PH		 3367 [pbn_b2_2_115200] = {
3368 .flags = FL_BASE2,
3369 .num_ports = 2,
3370 .base_baud = 115200,
3371 .uart_offset = 8,
3372 },
a9cccd34
MF		 3373 [pbn_b2_4_115200] = {
3374 .flags = FL_BASE2,
3375 .num_ports = 4,
3376 .base_baud = 115200,
3377 .uart_offset = 8,
3378 },
1da177e4
LT		 3379 [pbn_b2_8_115200] = {
3380 .flags = FL_BASE2,
3381 .num_ports = 8,
3382 .base_baud = 115200,
3383 .uart_offset = 8,
3384 },
3385
3386 [pbn_b2_1_460800] = {
3387 .flags = FL_BASE2,
3388 .num_ports = 1,
3389 .base_baud = 460800,
3390 .uart_offset = 8,
3391 },
3392 [pbn_b2_4_460800] = {
3393 .flags = FL_BASE2,
3394 .num_ports = 4,
3395 .base_baud = 460800,
3396 .uart_offset = 8,
3397 },
3398 [pbn_b2_8_460800] = {
3399 .flags = FL_BASE2,
3400 .num_ports = 8,
3401 .base_baud = 460800,
3402 .uart_offset = 8,
3403 },
3404 [pbn_b2_16_460800] = {
3405 .flags = FL_BASE2,
3406 .num_ports = 16,
3407 .base_baud = 460800,
3408 .uart_offset = 8,
3409 },
3410
3411 [pbn_b2_1_921600] = {
3412 .flags = FL_BASE2,
3413 .num_ports = 1,
3414 .base_baud = 921600,
3415 .uart_offset = 8,
3416 },
3417 [pbn_b2_4_921600] = {
3418 .flags = FL_BASE2,
3419 .num_ports = 4,
3420 .base_baud = 921600,
3421 .uart_offset = 8,
3422 },
3423 [pbn_b2_8_921600] = {
3424 .flags = FL_BASE2,
3425 .num_ports = 8,
3426 .base_baud = 921600,
3427 .uart_offset = 8,
3428 },
3429
e847003f
LB		 3430 [pbn_b2_8_1152000] = {
3431 .flags = FL_BASE2,
3432 .num_ports = 8,
3433 .base_baud = 1152000,
3434 .uart_offset = 8,
3435 },
3436
1da177e4
LT		 3437 [pbn_b2_bt_1_115200] = {
3438 .flags = FL_BASE2|FL_BASE_BARS,
3439 .num_ports = 1,
3440 .base_baud = 115200,
3441 .uart_offset = 8,
3442 },
3443 [pbn_b2_bt_2_115200] = {
3444 .flags = FL_BASE2|FL_BASE_BARS,
3445 .num_ports = 2,
3446 .base_baud = 115200,
3447 .uart_offset = 8,
3448 },
3449 [pbn_b2_bt_4_115200] = {
3450 .flags = FL_BASE2|FL_BASE_BARS,
3451 .num_ports = 4,
3452 .base_baud = 115200,
3453 .uart_offset = 8,
3454 },
3455
3456 [pbn_b2_bt_2_921600] = {
3457 .flags = FL_BASE2|FL_BASE_BARS,
3458 .num_ports = 2,
3459 .base_baud = 921600,
3460 .uart_offset = 8,
3461 },
3462 [pbn_b2_bt_4_921600] = {
3463 .flags = FL_BASE2|FL_BASE_BARS,
3464 .num_ports = 4,
3465 .base_baud = 921600,
3466 .uart_offset = 8,
3467 },
3468
d9004eb4
ABL		 3469 [pbn_b3_2_115200] = {
3470 .flags = FL_BASE3,
3471 .num_ports = 2,
3472 .base_baud = 115200,
3473 .uart_offset = 8,
3474 },
1da177e4
LT		 3475 [pbn_b3_4_115200] = {
3476 .flags = FL_BASE3,
3477 .num_ports = 4,
3478 .base_baud = 115200,
3479 .uart_offset = 8,
3480 },
3481 [pbn_b3_8_115200] = {
3482 .flags = FL_BASE3,
3483 .num_ports = 8,
3484 .base_baud = 115200,
3485 .uart_offset = 8,
3486 },
3487
66169ad1
YY		 3488 [pbn_b4_bt_2_921600] = {
3489 .flags = FL_BASE4,
3490 .num_ports = 2,
3491 .base_baud = 921600,
3492 .uart_offset = 8,
3493 },
3494 [pbn_b4_bt_4_921600] = {
3495 .flags = FL_BASE4,
3496 .num_ports = 4,
3497 .base_baud = 921600,
3498 .uart_offset = 8,
3499 },
3500 [pbn_b4_bt_8_921600] = {
3501 .flags = FL_BASE4,
3502 .num_ports = 8,
3503 .base_baud = 921600,
3504 .uart_offset = 8,
3505 },
3506
1da177e4
LT		 3507 /*
3508 * Entries following this are board-specific.
3509 */
3510
3511 /*
3512 * Panacom - IOMEM
3513 */
3514 [pbn_panacom] = {
3515 .flags = FL_BASE2,
3516 .num_ports = 2,
3517 .base_baud = 921600,
3518 .uart_offset = 0x400,
3519 .reg_shift = 7,
3520 },
3521 [pbn_panacom2] = {
3522 .flags = FL_BASE2|FL_BASE_BARS,
3523 .num_ports = 2,
3524 .base_baud = 921600,
3525 .uart_offset = 0x400,
3526 .reg_shift = 7,
3527 },
3528 [pbn_panacom4] = {
3529 .flags = FL_BASE2|FL_BASE_BARS,
3530 .num_ports = 4,
3531 .base_baud = 921600,
3532 .uart_offset = 0x400,
3533 .reg_shift = 7,
3534 },
3535
3536 /* I think this entry is broken - the first_offset looks wrong --rmk */
3537 [pbn_plx_romulus] = {
3538 .flags = FL_BASE2,
3539 .num_ports = 4,
3540 .base_baud = 921600,
3541 .uart_offset = 8 << 2,
3542 .reg_shift = 2,
3543 .first_offset = 0x03,
3544 },
3545
1bc8cde4
MS		 3546 /*
3547 * EndRun Technologies
3548 * Uses the size of PCI Base region 0 to
3549 * signal now many ports are available
3550 * 2 port 952 Uart support
3551 */
3552 [pbn_endrun_2_4000000] = {
3553 .flags = FL_BASE0,
3554 .num_ports = 2,
3555 .base_baud = 4000000,
3556 .uart_offset = 0x200,
3557 .first_offset = 0x1000,
3558 },
3559
1da177e4
LT		 3560 /*
3561 * This board uses the size of PCI Base region 0 to
3562 * signal now many ports are available
3563 */
3564 [pbn_oxsemi] = {
3565 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3566 .num_ports = 32,
3567 .base_baud = 115200,
3568 .uart_offset = 8,
3569 },
7106b4e3
LH		 3570 [pbn_oxsemi_1_4000000] = {
3571 .flags = FL_BASE0,
3572 .num_ports = 1,
3573 .base_baud = 4000000,
3574 .uart_offset = 0x200,
3575 .first_offset = 0x1000,
3576 },
3577 [pbn_oxsemi_2_4000000] = {
3578 .flags = FL_BASE0,
3579 .num_ports = 2,
3580 .base_baud = 4000000,
3581 .uart_offset = 0x200,
3582 .first_offset = 0x1000,
3583 },
3584 [pbn_oxsemi_4_4000000] = {
3585 .flags = FL_BASE0,
3586 .num_ports = 4,
3587 .base_baud = 4000000,
3588 .uart_offset = 0x200,
3589 .first_offset = 0x1000,
3590 },
3591 [pbn_oxsemi_8_4000000] = {
3592 .flags = FL_BASE0,
3593 .num_ports = 8,
3594 .base_baud = 4000000,
3595 .uart_offset = 0x200,
3596 .first_offset = 0x1000,
3597 },
3598
1da177e4
LT		 3599
3600 /*
3601 * EKF addition for i960 Boards form EKF with serial port.
3602 * Max 256 ports.
3603 */
3604 [pbn_intel_i960] = {
3605 .flags = FL_BASE0,
3606 .num_ports = 32,
3607 .base_baud = 921600,
3608 .uart_offset = 8 << 2,
3609 .reg_shift = 2,
3610 .first_offset = 0x10000,
3611 },
3612 [pbn_sgi_ioc3] = {
3613 .flags = FL_BASE0|FL_NOIRQ,
3614 .num_ports = 1,
3615 .base_baud = 458333,
3616 .uart_offset = 8,
3617 .reg_shift = 0,
3618 .first_offset = 0x20178,
3619 },
3620
1da177e4
LT		 3621 /*
3622 * Computone - uses IOMEM.
3623 */
3624 [pbn_computone_4] = {
3625 .flags = FL_BASE0,
3626 .num_ports = 4,
3627 .base_baud = 921600,
3628 .uart_offset = 0x40,
3629 .reg_shift = 2,
3630 .first_offset = 0x200,
3631 },
3632 [pbn_computone_6] = {
3633 .flags = FL_BASE0,
3634 .num_ports = 6,
3635 .base_baud = 921600,
3636 .uart_offset = 0x40,
3637 .reg_shift = 2,
3638 .first_offset = 0x200,
3639 },
3640 [pbn_computone_8] = {
3641 .flags = FL_BASE0,
3642 .num_ports = 8,
3643 .base_baud = 921600,
3644 .uart_offset = 0x40,
3645 .reg_shift = 2,
3646 .first_offset = 0x200,
3647 },
3648 [pbn_sbsxrsio] = {
3649 .flags = FL_BASE0,
3650 .num_ports = 8,
3651 .base_baud = 460800,
3652 .uart_offset = 256,
3653 .reg_shift = 4,
3654 },
3655 /*
3656 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3657 * Only basic 16550A support.
3658 * XR17C15[24] are not tested, but they should work.
3659 */
3660 [pbn_exar_XR17C152] = {
3661 .flags = FL_BASE0,
3662 .num_ports = 2,
3663 .base_baud = 921600,
3664 .uart_offset = 0x200,
3665 },
3666 [pbn_exar_XR17C154] = {
3667 .flags = FL_BASE0,
3668 .num_ports = 4,
3669 .base_baud = 921600,
3670 .uart_offset = 0x200,
3671 },
3672 [pbn_exar_XR17C158] = {
3673 .flags = FL_BASE0,
3674 .num_ports = 8,
3675 .base_baud = 921600,
3676 .uart_offset = 0x200,
3677 },
dc96efb7
MS		 3678 [pbn_exar_XR17V352] = {
3679 .flags = FL_BASE0,
3680 .num_ports = 2,
3681 .base_baud = 7812500,
3682 .uart_offset = 0x400,
3683 .reg_shift = 0,
3684 .first_offset = 0,
3685 },
3686 [pbn_exar_XR17V354] = {
3687 .flags = FL_BASE0,
3688 .num_ports = 4,
3689 .base_baud = 7812500,
3690 .uart_offset = 0x400,
3691 .reg_shift = 0,
3692 .first_offset = 0,
3693 },
3694 [pbn_exar_XR17V358] = {
3695 .flags = FL_BASE0,
3696 .num_ports = 8,
3697 .base_baud = 7812500,
3698 .uart_offset = 0x400,
3699 .reg_shift = 0,
3700 .first_offset = 0,
3701 },
c68d2b15
BH		 3702 [pbn_exar_ibm_saturn] = {
3703 .flags = FL_BASE0,
3704 .num_ports = 1,
3705 .base_baud = 921600,
3706 .uart_offset = 0x200,
3707 },
3708
aa798505
OJ		 3709 /*
3710 * PA Semi PWRficient PA6T-1682M on-chip UART
3711 */
3712 [pbn_pasemi_1682M] = {
3713 .flags = FL_BASE0,
3714 .num_ports = 1,
3715 .base_baud = 8333333,
3716 },
46a0fac9
SB		 3717 /*
3718 * National Instruments 843x
3719 */
3720 [pbn_ni8430_16] = {
3721 .flags = FL_BASE0,
3722 .num_ports = 16,
3723 .base_baud = 3686400,
3724 .uart_offset = 0x10,
3725 .first_offset = 0x800,
3726 },
3727 [pbn_ni8430_8] = {
3728 .flags = FL_BASE0,
3729 .num_ports = 8,
3730 .base_baud = 3686400,
3731 .uart_offset = 0x10,
3732 .first_offset = 0x800,
3733 },
3734 [pbn_ni8430_4] = {
3735 .flags = FL_BASE0,
3736 .num_ports = 4,
3737 .base_baud = 3686400,
3738 .uart_offset = 0x10,
3739 .first_offset = 0x800,
3740 },
3741 [pbn_ni8430_2] = {
3742 .flags = FL_BASE0,
3743 .num_ports = 2,
3744 .base_baud = 3686400,
3745 .uart_offset = 0x10,
3746 .first_offset = 0x800,
3747 },
1b62cbf2
KJ		 3748 /*
3749 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3750 */
3751 [pbn_ADDIDATA_PCIe_1_3906250] = {
3752 .flags = FL_BASE0,
3753 .num_ports = 1,
3754 .base_baud = 3906250,
3755 .uart_offset = 0x200,
3756 .first_offset = 0x1000,
3757 },
3758 [pbn_ADDIDATA_PCIe_2_3906250] = {
3759 .flags = FL_BASE0,
3760 .num_ports = 2,
3761 .base_baud = 3906250,
3762 .uart_offset = 0x200,
3763 .first_offset = 0x1000,
3764 },
3765 [pbn_ADDIDATA_PCIe_4_3906250] = {
3766 .flags = FL_BASE0,
3767 .num_ports = 4,
3768 .base_baud = 3906250,
3769 .uart_offset = 0x200,
3770 .first_offset = 0x1000,
3771 },
3772 [pbn_ADDIDATA_PCIe_8_3906250] = {
3773 .flags = FL_BASE0,
3774 .num_ports = 8,
3775 .base_baud = 3906250,
3776 .uart_offset = 0x200,
3777 .first_offset = 0x1000,
3778 },
095e24b0 3779 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3780 .flags = FL_BASE_BARS,
3781 .num_ports = 2,
095e24b0
DB		 3782 .base_baud = 921600,
3783 .reg_shift = 2,
3784 },
41d3f099
AS		 3785 /*
3786 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3787 * but is overridden by byt_set_termios.
3788 */
b15e5691
HK		 3789 [pbn_byt] = {
3790 .flags = FL_BASE0,
3791 .num_ports = 1,
3792 .base_baud = 2764800,
3793 .uart_offset = 0x80,
3794 .reg_shift = 2,
3795 },
f549e94e
AS		 3796 [pbn_pnw] = {
3797 .flags = FL_BASE0,
3798 .num_ports = 1,
3799 .base_baud = 115200,
3800 },
90b9aacf
AS		 3801 [pbn_tng] = {
3802 .flags = FL_BASE0,
3803 .num_ports = 1,
3804 .base_baud = 1843200,
3805 },
1ede7dcc
BD		 3806 [pbn_qrk] = {
3807 .flags = FL_BASE0,
3808 .num_ports = 1,
3809 .base_baud = 2764800,
3810 .reg_shift = 2,
3811 },
d9a0fbfd
AP		 3812 [pbn_omegapci] = {
3813 .flags = FL_BASE0,
3814 .num_ports = 8,
3815 .base_baud = 115200,
3816 .uart_offset = 0x200,
3817 },
7808edcd
NG		 3818 [pbn_NETMOS9900_2s_115200] = {
3819 .flags = FL_BASE0,
3820 .num_ports = 2,
3821 .base_baud = 115200,
3822 },
ebebd49a
SH		 3823 [pbn_brcm_trumanage] = {
3824 .flags = FL_BASE0,
3825 .num_ports = 1,
3826 .reg_shift = 2,
3827 .base_baud = 115200,
3828 },
2c62a3c8
GKH		 3829 [pbn_fintek_4] = {
3830 .num_ports = 4,
3831 .uart_offset = 8,
3832 .base_baud = 115200,
3833 .first_offset = 0x40,
3834 },
3835 [pbn_fintek_8] = {
3836 .num_ports = 8,
3837 .uart_offset = 8,
3838 .base_baud = 115200,
3839 .first_offset = 0x40,
3840 },
3841 [pbn_fintek_12] = {
3842 .num_ports = 12,
3843 .uart_offset = 8,
3844 .base_baud = 115200,
3845 .first_offset = 0x40,
3846 },
72a3c0e4
SP		 3847
3848 [pbn_wch384_4] = {
3849 .flags = FL_BASE0,
3850 .num_ports = 4,
3851 .base_baud = 115200,
3852 .uart_offset = 8,
3853 .first_offset = 0xC0,
3854 },
1da177e4
LT		 3855};
3856
6971c635
GA		 3857static const struct pci_device_id blacklist[] = {
3858 /* softmodems */
5756ee99 3859 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3860 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3861 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3862
3863 /* multi-io cards handled by parport_serial */
3864 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
feb58142 3865 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
2fdd8c8c 3866 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
72a3c0e4 3867 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
436bbd43
CS		 3868};
3869
1da177e4
LT		 3870/*
3871 * Given a complete unknown PCI device, try to use some heuristics to
3872 * guess what the configuration might be, based on the pitiful PCI
3873 * serial specs. Returns 0 on success, 1 on failure.
3874 */
9671f099 3875static int
1c7c1fe5 3876serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3877{
6971c635 3878 const struct pci_device_id *bldev;
1da177e4 3879 int num_iomem, num_port, first_port = -1, i;
5756ee99 3880
1da177e4
LT		 3881 /*
3882 * If it is not a communications device or the programming
3883 * interface is greater than 6, give up.
3884 *
3885 * (Should we try to make guesses for multiport serial devices
5756ee99 3886 * later?)
1da177e4
LT		 3887 */
3888 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3889 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3890 (dev->class & 0xff) > 6)
3891 return -ENODEV;
3892
436bbd43
CS		 3893 /*
3894 * Do not access blacklisted devices that are known not to
6971c635 3895 * feature serial ports or are handled by other modules.
436bbd43 3896 */
6971c635
GA		 3897 for (bldev = blacklist;
3898 bldev < blacklist + ARRAY_SIZE(blacklist);
3899 bldev++) {
3900 if (dev->vendor == bldev->vendor &&
3901 dev->device == bldev->device)
436bbd43
CS		 3902 return -ENODEV;
3903 }
3904
1da177e4
LT		 3905 num_iomem = num_port = 0;
3906 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3907 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3908 num_port++;
3909 if (first_port == -1)
3910 first_port = i;
3911 }
3912 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3913 num_iomem++;
3914 }
3915
3916 /*
3917 * If there is 1 or 0 iomem regions, and exactly one port,
3918 * use it. We guess the number of ports based on the IO
3919 * region size.
3920 */
3921 if (num_iomem <= 1 && num_port == 1) {
3922 board->flags = first_port;
3923 board->num_ports = pci_resource_len(dev, first_port) / 8;
3924 return 0;
3925 }
3926
3927 /*
3928 * Now guess if we've got a board which indexes by BARs.
3929 * Each IO BAR should be 8 bytes, and they should follow
3930 * consecutively.
3931 */
3932 first_port = -1;
3933 num_port = 0;
3934 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3935 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3936 pci_resource_len(dev, i) == 8 &&
3937 (first_port == -1 || (first_port + num_port) == i)) {
3938 num_port++;
3939 if (first_port == -1)
3940 first_port = i;
3941 }
3942 }
3943
3944 if (num_port > 1) {
3945 board->flags = first_port | FL_BASE_BARS;
3946 board->num_ports = num_port;
3947 return 0;
3948 }
3949
3950 return -ENODEV;
3951}
3952
3953static inline int
975a1a7d
RK		 3954serial_pci_matches(const struct pciserial_board *board,
3955 const struct pciserial_board *guessed)
1da177e4
LT		 3956{
3957 return
3958 board->num_ports == guessed->num_ports &&
3959 board->base_baud == guessed->base_baud &&
3960 board->uart_offset == guessed->uart_offset &&
3961 board->reg_shift == guessed->reg_shift &&
3962 board->first_offset == guessed->first_offset;
3963}
3964
241fc436 3965struct serial_private *
975a1a7d 3966pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3967{
2655a2c7 3968 struct uart_8250_port uart;
1da177e4 3969 struct serial_private *priv;
1da177e4
LT		 3970 struct pci_serial_quirk *quirk;
3971 int rc, nr_ports, i;
3972
1da177e4
LT		 3973 nr_ports = board->num_ports;
3974
3975 /*
3976 * Find an init and setup quirks.
3977 */
3978 quirk = find_quirk(dev);
3979
3980 /*
3981 * Run the new-style initialization function.
3982 * The initialization function returns:
3983 * <0 - error
3984 * 0 - use board->num_ports
3985 * >0 - number of ports
3986 */
3987 if (quirk->init) {
3988 rc = quirk->init(dev);
241fc436
RK		 3989 if (rc < 0) {
3990 priv = ERR_PTR(rc);
3991 goto err_out;
3992 }
1da177e4
LT		 3993 if (rc)
3994 nr_ports = rc;
3995 }
3996
8f31bb39 3997 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3998 sizeof(unsigned int) * nr_ports,
3999 GFP_KERNEL);
4000 if (!priv) {
241fc436
RK		 4001 priv = ERR_PTR(-ENOMEM);
4002 goto err_deinit;
1da177e4
LT		 4003 }
4004
70db3d91 4005 priv->dev = dev;
1da177e4 4006 priv->quirk = quirk;
1da177e4 4007
2655a2c7
AC		 4008 memset(&uart, 0, sizeof(uart));
4009 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4010 uart.port.uartclk = board->base_baud * 16;
4011 uart.port.irq = get_pci_irq(dev, board);
4012 uart.port.dev = &dev->dev;
72ce9a83 4013
1da177e4 4014 for (i = 0; i < nr_ports; i++) {
2655a2c7 4015 if (quirk->setup(priv, board, &uart, i))
1da177e4 4016 break;
72ce9a83 4017
af8c5b8d
GKH		 4018 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4019 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 4020
2655a2c7 4021 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 4022 if (priv->line[i] < 0) {
af8c5b8d
GKH		 4023 dev_err(&dev->dev,
4024 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4025 uart.port.iobase, uart.port.irq,
4026 uart.port.iotype, priv->line[i]);
1da177e4
LT		 4027 break;
4028 }
4029 }
1da177e4 4030 priv->nr = i;
241fc436 4031 return priv;
1da177e4 4032
5756ee99 4033err_deinit:
1da177e4
LT		 4034 if (quirk->exit)
4035 quirk->exit(dev);
5756ee99 4036err_out:
241fc436 4037 return priv;
1da177e4 4038}
241fc436 4039EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 4040
241fc436 4041void pciserial_remove_ports(struct serial_private *priv)
1da177e4 4042{
056a8763
RK		 4043 struct pci_serial_quirk *quirk;
4044 int i;
1da177e4 4045
056a8763
RK		 4046 for (i = 0; i < priv->nr; i++)
4047 serial8250_unregister_port(priv->line[i]);
1da177e4 4048
056a8763
RK		 4049 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4050 if (priv->remapped_bar[i])
4051 iounmap(priv->remapped_bar[i]);
4052 priv->remapped_bar[i] = NULL;
4053 }
1da177e4 4054
056a8763
RK		 4055 /*
4056 * Find the exit quirks.
4057 */
241fc436 4058 quirk = find_quirk(priv->dev);
056a8763 4059 if (quirk->exit)
241fc436
RK		 4060 quirk->exit(priv->dev);
4061
4062 kfree(priv);
4063}
4064EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4065
4066void pciserial_suspend_ports(struct serial_private *priv)
4067{
4068 int i;
4069
4070 for (i = 0; i < priv->nr; i++)
4071 if (priv->line[i] >= 0)
4072 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 4073
4074 /*
4075 * Ensure that every init quirk is properly torn down
4076 */
4077 if (priv->quirk->exit)
4078 priv->quirk->exit(priv->dev);
241fc436
RK		 4079}
4080EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4081
4082void pciserial_resume_ports(struct serial_private *priv)
4083{
4084 int i;
4085
4086 /*
4087 * Ensure that the board is correctly configured.
4088 */
4089 if (priv->quirk->init)
4090 priv->quirk->init(priv->dev);
4091
4092 for (i = 0; i < priv->nr; i++)
4093 if (priv->line[i] >= 0)
4094 serial8250_resume_port(priv->line[i]);
4095}
4096EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4097
4098/*
4099 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4100 * to the arrangement of serial ports on a PCI card.
4101 */
9671f099 4102static int
241fc436
RK		 4103pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4104{
5bf8f501 4105 struct pci_serial_quirk *quirk;
241fc436 4106 struct serial_private *priv;
975a1a7d
RK		 4107 const struct pciserial_board *board;
4108 struct pciserial_board tmp;
241fc436
RK		 4109 int rc;
4110
5bf8f501
FB		 4111 quirk = find_quirk(dev);
4112 if (quirk->probe) {
4113 rc = quirk->probe(dev);
4114 if (rc)
4115 return rc;
4116 }
4117
241fc436 4118 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 4119 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 4120 ent->driver_data);
4121 return -EINVAL;
4122 }
4123
4124 board = &pci_boards[ent->driver_data];
4125
4126 rc = pci_enable_device(dev);
2807190b 4127 pci_save_state(dev);
241fc436
RK		 4128 if (rc)
4129 return rc;
4130
4131 if (ent->driver_data == pbn_default) {
4132 /*
4133 * Use a copy of the pci_board entry for this;
4134 * avoid changing entries in the table.
4135 */
4136 memcpy(&tmp, board, sizeof(struct pciserial_board));
4137 board = &tmp;
4138
4139 /*
4140 * We matched one of our class entries. Try to
4141 * determine the parameters of this board.
4142 */
975a1a7d 4143 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 4144 if (rc)
4145 goto disable;
4146 } else {
4147 /*
4148 * We matched an explicit entry. If we are able to
4149 * detect this boards settings with our heuristic,
4150 * then we no longer need this entry.
4151 */
4152 memcpy(&tmp, &pci_boards[pbn_default],
4153 sizeof(struct pciserial_board));
4154 rc = serial_pci_guess_board(dev, &tmp);
4155 if (rc == 0 && serial_pci_matches(board, &tmp))
4156 moan_device("Redundant entry in serial pci_table.",
4157 dev);
4158 }
4159
4160 priv = pciserial_init_ports(dev, board);
4161 if (!IS_ERR(priv)) {
4162 pci_set_drvdata(dev, priv);
4163 return 0;
4164 }
4165
4166 rc = PTR_ERR(priv);
1da177e4 4167
241fc436 4168 disable:
056a8763 4169 pci_disable_device(dev);
241fc436
RK		 4170 return rc;
4171}
1da177e4 4172
ae8d8a14 4173static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 4174{
4175 struct serial_private *priv = pci_get_drvdata(dev);
4176
241fc436
RK		 4177 pciserial_remove_ports(priv);
4178
4179 pci_disable_device(dev);
1da177e4
LT		 4180}
4181
61702c3e
AS		 4182#ifdef CONFIG_PM_SLEEP
4183static int pciserial_suspend_one(struct device *dev)
1da177e4 4184{
61702c3e
AS		 4185 struct pci_dev *pdev = to_pci_dev(dev);
4186 struct serial_private *priv = pci_get_drvdata(pdev);
1da177e4 4187
241fc436
RK		 4188 if (priv)
4189 pciserial_suspend_ports(priv);
1da177e4 4190
1da177e4
LT		 4191 return 0;
4192}
4193
61702c3e 4194static int pciserial_resume_one(struct device *dev)
1da177e4 4195{
61702c3e
AS		 4196 struct pci_dev *pdev = to_pci_dev(dev);
4197 struct serial_private *priv = pci_get_drvdata(pdev);
ccb9d59e 4198 int err;
1da177e4
LT		 4199
4200 if (priv) {
1da177e4
LT		 4201 /*
4202 * The device may have been disabled. Re-enable it.
4203 */
61702c3e 4204 err = pci_enable_device(pdev);
40836c48 4205 /* FIXME: We cannot simply error out here */
ccb9d59e 4206 if (err)
61702c3e 4207 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 4208 pciserial_resume_ports(priv);
1da177e4
LT		 4209 }
4210 return 0;
4211}
1d5e7996 4212#endif
1da177e4 4213
61702c3e
AS		 4214static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4215 pciserial_resume_one);
4216
1da177e4 4217static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 4218 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4219 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4220 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4221 pbn_b2_8_921600 },
0c6d774c
TW		 4222 /* Advantech also use 0x3618 and 0xf618 */
4223 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4224 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4225 pbn_b0_4_921600 },
4226 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4227 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4228 pbn_b0_4_921600 },
1da177e4
LT		 4229 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4230 PCI_SUBVENDOR_ID_CONNECT_TECH,
4231 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4232 pbn_b1_8_1382400 },
4233 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4234 PCI_SUBVENDOR_ID_CONNECT_TECH,
4235 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4236 pbn_b1_4_1382400 },
4237 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4238 PCI_SUBVENDOR_ID_CONNECT_TECH,
4239 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4240 pbn_b1_2_1382400 },
4241 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4242 PCI_SUBVENDOR_ID_CONNECT_TECH,
4243 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4244 pbn_b1_8_1382400 },
4245 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4246 PCI_SUBVENDOR_ID_CONNECT_TECH,
4247 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4248 pbn_b1_4_1382400 },
4249 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4250 PCI_SUBVENDOR_ID_CONNECT_TECH,
4251 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4252 pbn_b1_2_1382400 },
4253 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4254 PCI_SUBVENDOR_ID_CONNECT_TECH,
4255 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4256 pbn_b1_8_921600 },
4257 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4258 PCI_SUBVENDOR_ID_CONNECT_TECH,
4259 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4260 pbn_b1_8_921600 },
4261 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4262 PCI_SUBVENDOR_ID_CONNECT_TECH,
4263 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4264 pbn_b1_4_921600 },
4265 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4266 PCI_SUBVENDOR_ID_CONNECT_TECH,
4267 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4268 pbn_b1_4_921600 },
4269 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4270 PCI_SUBVENDOR_ID_CONNECT_TECH,
4271 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4272 pbn_b1_2_921600 },
4273 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4274 PCI_SUBVENDOR_ID_CONNECT_TECH,
4275 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4276 pbn_b1_8_921600 },
4277 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4278 PCI_SUBVENDOR_ID_CONNECT_TECH,
4279 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4280 pbn_b1_8_921600 },
4281 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4282 PCI_SUBVENDOR_ID_CONNECT_TECH,
4283 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4284 pbn_b1_4_921600 },
26e92861
GH		 4285 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4286 PCI_SUBVENDOR_ID_CONNECT_TECH,
4287 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4288 pbn_b1_2_1250000 },
4289 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4290 PCI_SUBVENDOR_ID_CONNECT_TECH,
4291 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4292 pbn_b0_2_1843200 },
4293 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4294 PCI_SUBVENDOR_ID_CONNECT_TECH,
4295 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4296 pbn_b0_4_1843200 },
85d1494e
YY		 4297 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4298 PCI_VENDOR_ID_AFAVLAB,
4299 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4300 pbn_b0_4_1152000 },
26e92861
GH		 4301 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4302 PCI_SUBVENDOR_ID_CONNECT_TECH,
4303 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4304 pbn_b0_2_1843200_200 },
4305 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4306 PCI_SUBVENDOR_ID_CONNECT_TECH,
4307 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4308 pbn_b0_4_1843200_200 },
4309 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4310 PCI_SUBVENDOR_ID_CONNECT_TECH,
4311 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4312 pbn_b0_8_1843200_200 },
4313 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4314 PCI_SUBVENDOR_ID_CONNECT_TECH,
4315 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4316 pbn_b0_2_1843200_200 },
4317 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4318 PCI_SUBVENDOR_ID_CONNECT_TECH,
4319 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4320 pbn_b0_4_1843200_200 },
4321 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4322 PCI_SUBVENDOR_ID_CONNECT_TECH,
4323 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4324 pbn_b0_8_1843200_200 },
4325 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4326 PCI_SUBVENDOR_ID_CONNECT_TECH,
4327 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4328 pbn_b0_2_1843200_200 },
4329 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4330 PCI_SUBVENDOR_ID_CONNECT_TECH,
4331 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4332 pbn_b0_4_1843200_200 },
4333 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4334 PCI_SUBVENDOR_ID_CONNECT_TECH,
4335 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4336 pbn_b0_8_1843200_200 },
4337 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4338 PCI_SUBVENDOR_ID_CONNECT_TECH,
4339 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4340 pbn_b0_2_1843200_200 },
4341 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4342 PCI_SUBVENDOR_ID_CONNECT_TECH,
4343 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4344 pbn_b0_4_1843200_200 },
4345 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4346 PCI_SUBVENDOR_ID_CONNECT_TECH,
4347 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4348 pbn_b0_8_1843200_200 },
c68d2b15
BH		 4349 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4350 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4351 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 4352
4353 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4355 pbn_b2_bt_1_115200 },
4356 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4358 pbn_b2_bt_2_115200 },
4359 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4361 pbn_b2_bt_4_115200 },
4362 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4364 pbn_b2_bt_2_115200 },
4365 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4367 pbn_b2_bt_4_115200 },
4368 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4370 pbn_b2_8_115200 },
e65f0f82
FL		 4371 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373 pbn_b2_8_460800 },
1da177e4
LT		 4374 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 pbn_b2_8_115200 },
4377
4378 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380 pbn_b2_bt_2_115200 },
4381 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4383 pbn_b2_bt_2_921600 },
4384 /*
4385 * VScom SPCOM800, from sl@s.pl
4386 */
5756ee99
AC		 4387 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4389 pbn_b2_8_921600 },
4390 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4392 pbn_b2_4_921600 },
b76c5a07
CB		 4393 /* Unknown card - subdevice 0x1584 */
4394 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4395 PCI_VENDOR_ID_PLX,
4396 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4397 pbn_b2_4_115200 },
4398 /* Unknown card - subdevice 0x1588 */
4399 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4400 PCI_VENDOR_ID_PLX,
4401 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4402 pbn_b2_8_115200 },
1da177e4
LT		 4403 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4404 PCI_SUBVENDOR_ID_KEYSPAN,
4405 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4406 pbn_panacom },
4407 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_panacom4 },
4410 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_panacom2 },
a9cccd34
MF		 4413 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4414 PCI_VENDOR_ID_ESDGMBH,
4415 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4416 pbn_b2_4_115200 },
1da177e4
LT		 4417 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4418 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4419 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4420 pbn_b2_4_460800 },
4421 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4422 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4423 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4424 pbn_b2_8_460800 },
4425 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4426 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4427 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4428 pbn_b2_16_460800 },
4429 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4430 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4431 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4432 pbn_b2_16_460800 },
4433 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4434 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4435 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4436 pbn_b2_4_460800 },
4437 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4438 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4439 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4440 pbn_b2_8_460800 },
add7b58e
BH		 4441 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4442 PCI_SUBVENDOR_ID_EXSYS,
4443 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4444 pbn_b2_4_115200 },
1da177e4
LT		 4445 /*
4446 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4447 * (Exoray@isys.ca)
4448 */
4449 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4450 0x10b5, 0x106a, 0, 0,
4451 pbn_plx_romulus },
1bc8cde4
MS		 4452 /*
4453 * EndRun Technologies. PCI express device range.
4454 * EndRun PTP/1588 has 2 Native UARTs.
4455 */
4456 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458 pbn_endrun_2_4000000 },
55c7c0fd
AC		 4459 /*
4460 * Quatech cards. These actually have configurable clocks but for
4461 * now we just use the default.
4462 *
4463 * 100 series are RS232, 200 series RS422,
4464 */
1da177e4
LT		 4465 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467 pbn_b1_4_115200 },
4468 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470 pbn_b1_2_115200 },
55c7c0fd
AC		 4471 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473 pbn_b2_2_115200 },
4474 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476 pbn_b1_2_115200 },
4477 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 pbn_b2_2_115200 },
4480 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_b1_4_115200 },
1da177e4
LT		 4483 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 pbn_b1_8_115200 },
4486 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 pbn_b1_8_115200 },
55c7c0fd
AC		 4489 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_b1_4_115200 },
4492 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b1_2_115200 },
4495 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_b1_4_115200 },
4498 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_b1_2_115200 },
4501 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b2_4_115200 },
4504 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_b2_2_115200 },
4507 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 pbn_b2_1_115200 },
4510 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_b2_4_115200 },
4513 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515 pbn_b2_2_115200 },
4516 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 pbn_b2_1_115200 },
4519 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 pbn_b0_8_115200 },
4522
1da177e4 4523 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4524 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4525 0, 0,
1da177e4 4526 pbn_b0_4_921600 },
fbc0dc0d 4527 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4528 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4529 0, 0,
fbc0dc0d 4530 pbn_b0_4_1152000 },
c9bd9d01
MP		 4531 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_b0_bt_2_921600 },
db1de159
DR		 4534
4535 /*
4536 * The below card is a little controversial since it is the
4537 * subject of a PCI vendor/device ID clash. (See
4538 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4539 * For now just used the hex ID 0x950a.
4540 */
39aced68 4541 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4542 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4543 0, 0, pbn_b0_2_115200 },
4544 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4545 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4546 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4547 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 pbn_b0_2_1130000 },
70fd8fde
AP		 4550 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4551 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4552 pbn_b0_1_921600 },
1da177e4
LT		 4553 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555 pbn_b0_4_115200 },
4556 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558 pbn_b0_bt_2_921600 },
e847003f
LB		 4559 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4560 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4561 pbn_b2_8_1152000 },
1da177e4 4562
7106b4e3
LH		 4563 /*
4564 * Oxford Semiconductor Inc. Tornado PCI express device range.
4565 */
4566 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_b0_1_4000000 },
4569 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_b0_1_4000000 },
4572 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_oxsemi_1_4000000 },
4575 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_oxsemi_1_4000000 },
4578 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_b0_1_4000000 },
4581 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_b0_1_4000000 },
4584 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_oxsemi_1_4000000 },
4587 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_oxsemi_1_4000000 },
4590 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b0_1_4000000 },
4593 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b0_1_4000000 },
4596 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_b0_1_4000000 },
4599 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_b0_1_4000000 },
4602 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_oxsemi_2_4000000 },
4605 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_oxsemi_2_4000000 },
4608 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_oxsemi_4_4000000 },
4611 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_oxsemi_4_4000000 },
4614 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_oxsemi_8_4000000 },
4617 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_oxsemi_8_4000000 },
4620 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_oxsemi_1_4000000 },
4623 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_oxsemi_1_4000000 },
4626 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_oxsemi_1_4000000 },
4629 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_oxsemi_1_4000000 },
4632 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_oxsemi_1_4000000 },
4635 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_oxsemi_1_4000000 },
4638 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 pbn_oxsemi_1_4000000 },
4641 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_oxsemi_1_4000000 },
4644 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_oxsemi_1_4000000 },
4647 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_oxsemi_1_4000000 },
4650 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_oxsemi_1_4000000 },
4653 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_oxsemi_1_4000000 },
4656 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_oxsemi_1_4000000 },
4659 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_oxsemi_1_4000000 },
4662 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_oxsemi_1_4000000 },
4665 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667 pbn_oxsemi_1_4000000 },
4668 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 pbn_oxsemi_1_4000000 },
4671 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 pbn_oxsemi_1_4000000 },
4674 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 pbn_oxsemi_1_4000000 },
4677 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4679 pbn_oxsemi_1_4000000 },
4680 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 pbn_oxsemi_1_4000000 },
4683 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4685 pbn_oxsemi_1_4000000 },
4686 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688 pbn_oxsemi_1_4000000 },
4689 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 pbn_oxsemi_1_4000000 },
4692 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 pbn_oxsemi_1_4000000 },
4695 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_oxsemi_1_4000000 },
b80de369
LH		 4698 /*
4699 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4700 */
4701 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4702 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4703 pbn_oxsemi_1_4000000 },
4704 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4705 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4706 pbn_oxsemi_2_4000000 },
4707 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4708 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4709 pbn_oxsemi_4_4000000 },
4710 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4711 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4712 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4713
4714 /*
4715 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4716 */
4717 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4718 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4719 pbn_oxsemi_2_4000000 },
4720
1da177e4
LT		 4721 /*
4722 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4723 * from skokodyn@yahoo.com
4724 */
4725 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4726 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4727 pbn_sbsxrsio },
4728 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4729 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4730 pbn_sbsxrsio },
4731 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4732 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4733 pbn_sbsxrsio },
4734 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4735 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4736 pbn_sbsxrsio },
4737
4738 /*
4739 * Digitan DS560-558, from jimd@esoft.com
4740 */
4741 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4743 pbn_b1_1_115200 },
4744
4745 /*
4746 * Titan Electronic cards
4747 * The 400L and 800L have a custom setup quirk.
4748 */
4749 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4751 pbn_b0_1_921600 },
4752 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4754 pbn_b0_2_921600 },
4755 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4757 pbn_b0_4_921600 },
4758 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4760 pbn_b0_4_921600 },
4761 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_b1_1_921600 },
4764 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_b1_bt_2_921600 },
4767 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_b0_bt_4_921600 },
4770 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_b0_bt_8_921600 },
66169ad1
YY		 4773 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_b4_bt_2_921600 },
4776 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_b4_bt_4_921600 },
4779 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_b4_bt_8_921600 },
4782 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_b0_4_921600 },
4785 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_b0_4_921600 },
4788 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_b0_4_921600 },
4791 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_oxsemi_1_4000000 },
4794 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_oxsemi_2_4000000 },
4797 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_oxsemi_4_4000000 },
4800 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_oxsemi_8_4000000 },
4803 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_oxsemi_2_4000000 },
4806 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4809 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4812 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_b0_4_921600 },
4815 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_b0_4_921600 },
4818 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_b0_4_921600 },
4821 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 pbn_b0_4_921600 },
1da177e4
LT		 4824
4825 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4827 pbn_b2_1_460800 },
4828 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4830 pbn_b2_1_460800 },
4831 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4833 pbn_b2_1_460800 },
4834 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836 pbn_b2_bt_2_921600 },
4837 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4839 pbn_b2_bt_2_921600 },
4840 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4842 pbn_b2_bt_2_921600 },
4843 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4845 pbn_b2_bt_4_921600 },
4846 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848 pbn_b2_bt_4_921600 },
4849 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 pbn_b2_bt_4_921600 },
4852 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_b0_1_921600 },
4855 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b0_1_921600 },
4858 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b0_1_921600 },
4861 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4863 pbn_b0_bt_2_921600 },
4864 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4866 pbn_b0_bt_2_921600 },
4867 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869 pbn_b0_bt_2_921600 },
4870 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_b0_bt_4_921600 },
4873 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 pbn_b0_bt_4_921600 },
4876 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4879 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881 pbn_b0_bt_8_921600 },
4882 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884 pbn_b0_bt_8_921600 },
4885 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_b0_bt_8_921600 },
1da177e4
LT		 4888
4889 /*
4890 * Computone devices submitted by Doug McNash dmcnash@computone.com
4891 */
4892 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4893 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4894 0, 0, pbn_computone_4 },
4895 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4896 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4897 0, 0, pbn_computone_8 },
4898 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4899 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4900 0, 0, pbn_computone_6 },
4901
4902 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_oxsemi },
4905 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4906 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4907 pbn_b0_bt_1_921600 },
4908
abd7baca
SC		 4909 /*
4910 * SUNIX (TIMEDIA)
4911 */
4912 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4913 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4914 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4915 pbn_b0_bt_1_921600 },
4916
4917 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4918 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4919 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4920 pbn_b0_bt_1_921600 },
4921
1da177e4
LT		 4922 /*
4923 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4924 */
4925 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927 pbn_b0_bt_8_115200 },
4928 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930 pbn_b0_bt_8_115200 },
4931
4932 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 pbn_b0_bt_2_115200 },
4935 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937 pbn_b0_bt_2_115200 },
4938 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4941 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943 pbn_b0_bt_2_115200 },
4944 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946 pbn_b0_bt_2_115200 },
1da177e4
LT		 4947 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4949 pbn_b0_bt_4_460800 },
4950 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4952 pbn_b0_bt_4_460800 },
4953 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4955 pbn_b0_bt_2_460800 },
4956 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4958 pbn_b0_bt_2_460800 },
4959 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4961 pbn_b0_bt_2_460800 },
4962 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964 pbn_b0_bt_1_115200 },
4965 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967 pbn_b0_bt_1_460800 },
4968
1fb8cacc
RK		 4969 /*
4970 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4971 * Cards are identified by their subsystem vendor IDs, which
4972 * (in hex) match the model number.
4973 *
4974 * Note that JC140x are RS422/485 cards which require ox950
4975 * ACR = 0x10, and as such are not currently fully supported.
4976 */
4977 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4978 0x1204, 0x0004, 0, 0,
4979 pbn_b0_4_921600 },
4980 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4981 0x1208, 0x0004, 0, 0,
4982 pbn_b0_4_921600 },
4983/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4984 0x1402, 0x0002, 0, 0,
4985 pbn_b0_2_921600 }, */
4986/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4987 0x1404, 0x0004, 0, 0,
4988 pbn_b0_4_921600 }, */
4989 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4990 0x1208, 0x0004, 0, 0,
4991 pbn_b0_4_921600 },
4992
2a52fcb5
KY		 4993 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4994 0x1204, 0x0004, 0, 0,
4995 pbn_b0_4_921600 },
4996 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4997 0x1208, 0x0004, 0, 0,
4998 pbn_b0_4_921600 },
4999 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5000 0x1208, 0x0004, 0, 0,
5001 pbn_b0_4_921600 },
1da177e4
LT		 5002 /*
5003 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5004 */
5005 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 pbn_b1_1_1382400 },
5008
5009 /*
5010 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5011 */
5012 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 pbn_b1_1_1382400 },
5015
5016 /*
5017 * RAStel 2 port modem, gerg@moreton.com.au
5018 */
5019 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5021 pbn_b2_bt_2_115200 },
5022
5023 /*
5024 * EKF addition for i960 Boards form EKF with serial port
5025 */
5026 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5027 0xE4BF, PCI_ANY_ID, 0, 0,
5028 pbn_intel_i960 },
5029
5030 /*
5031 * Xircom Cardbus/Ethernet combos
5032 */
5033 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035 pbn_b0_1_115200 },
5036 /*
5037 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5038 */
5039 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 pbn_b0_1_115200 },
5042
5043 /*
5044 * Untested PCI modems, sent in from various folks...
5045 */
5046
5047 /*
5048 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5049 */
5050 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5051 0x1048, 0x1500, 0, 0,
5052 pbn_b1_1_115200 },
5053
5054 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5055 0xFF00, 0, 0, 0,
5056 pbn_sgi_ioc3 },
5057
5058 /*
5059 * HP Diva card
5060 */
5061 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5062 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5063 pbn_b1_1_115200 },
5064 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5066 pbn_b0_5_115200 },
5067 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5069 pbn_b2_1_115200 },
5070
d9004eb4
ABL		 5071 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5073 pbn_b3_2_115200 },
1da177e4
LT		 5074 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5076 pbn_b3_4_115200 },
5077 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5079 pbn_b3_8_115200 },
5080
5081 /*
5082 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5083 */
5084 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5085 PCI_ANY_ID, PCI_ANY_ID,
5086 0,
5087 0, pbn_exar_XR17C152 },
5088 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5089 PCI_ANY_ID, PCI_ANY_ID,
5090 0,
5091 0, pbn_exar_XR17C154 },
5092 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5093 PCI_ANY_ID, PCI_ANY_ID,
5094 0,
5095 0, pbn_exar_XR17C158 },
dc96efb7
MS		 5096 /*
5097 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
5098 */
5099 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5100 PCI_ANY_ID, PCI_ANY_ID,
5101 0,
5102 0, pbn_exar_XR17V352 },
5103 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5104 PCI_ANY_ID, PCI_ANY_ID,
5105 0,
5106 0, pbn_exar_XR17V354 },
5107 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5108 PCI_ANY_ID, PCI_ANY_ID,
5109 0,
5110 0, pbn_exar_XR17V358 },
1da177e4
LT		 5111
5112 /*
5113 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5114 */
5115 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5117 pbn_b0_1_115200 },
84f8c6fc
NV		 5118 /*
5119 * ITE
5120 */
5121 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5122 PCI_ANY_ID, PCI_ANY_ID,
5123 0, 0,
5124 pbn_b1_bt_1_115200 },
1da177e4 5125
737c1756
PH		 5126 /*
5127 * IntaShield IS-200
5128 */
5129 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5131 pbn_b2_2_115200 },
4b6f6ce9
IGP		 5132 /*
5133 * IntaShield IS-400
5134 */
5135 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5137 pbn_b2_4_115200 },
48212008
TH		 5138 /*
5139 * Perle PCI-RAS cards
5140 */
5141 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5142 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5143 0, 0, pbn_b2_4_921600 },
5144 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5145 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5146 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 5147
5148 /*
5149 * Mainpine series cards: Fairly standard layout but fools
5150 * parts of the autodetect in some cases and uses otherwise
5151 * unmatched communications subclasses in the PCI Express case
5152 */
5153
5154 { /* RockForceDUO */
5155 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5156 PCI_VENDOR_ID_MAINPINE, 0x0200,
5157 0, 0, pbn_b0_2_115200 },
5158 { /* RockForceQUATRO */
5159 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5160 PCI_VENDOR_ID_MAINPINE, 0x0300,
5161 0, 0, pbn_b0_4_115200 },
5162 { /* RockForceDUO+ */
5163 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5164 PCI_VENDOR_ID_MAINPINE, 0x0400,
5165 0, 0, pbn_b0_2_115200 },
5166 { /* RockForceQUATRO+ */
5167 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5168 PCI_VENDOR_ID_MAINPINE, 0x0500,
5169 0, 0, pbn_b0_4_115200 },
5170 { /* RockForce+ */
5171 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5172 PCI_VENDOR_ID_MAINPINE, 0x0600,
5173 0, 0, pbn_b0_2_115200 },
5174 { /* RockForce+ */
5175 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5176 PCI_VENDOR_ID_MAINPINE, 0x0700,
5177 0, 0, pbn_b0_4_115200 },
5178 { /* RockForceOCTO+ */
5179 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5180 PCI_VENDOR_ID_MAINPINE, 0x0800,
5181 0, 0, pbn_b0_8_115200 },
5182 { /* RockForceDUO+ */
5183 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5184 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5185 0, 0, pbn_b0_2_115200 },
5186 { /* RockForceQUARTRO+ */
5187 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5188 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5189 0, 0, pbn_b0_4_115200 },
5190 { /* RockForceOCTO+ */
5191 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5192 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5193 0, 0, pbn_b0_8_115200 },
5194 { /* RockForceD1 */
5195 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5196 PCI_VENDOR_ID_MAINPINE, 0x2000,
5197 0, 0, pbn_b0_1_115200 },
5198 { /* RockForceF1 */
5199 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5200 PCI_VENDOR_ID_MAINPINE, 0x2100,
5201 0, 0, pbn_b0_1_115200 },
5202 { /* RockForceD2 */
5203 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5204 PCI_VENDOR_ID_MAINPINE, 0x2200,
5205 0, 0, pbn_b0_2_115200 },
5206 { /* RockForceF2 */
5207 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5208 PCI_VENDOR_ID_MAINPINE, 0x2300,
5209 0, 0, pbn_b0_2_115200 },
5210 { /* RockForceD4 */
5211 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5212 PCI_VENDOR_ID_MAINPINE, 0x2400,
5213 0, 0, pbn_b0_4_115200 },
5214 { /* RockForceF4 */
5215 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5216 PCI_VENDOR_ID_MAINPINE, 0x2500,
5217 0, 0, pbn_b0_4_115200 },
5218 { /* RockForceD8 */
5219 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5220 PCI_VENDOR_ID_MAINPINE, 0x2600,
5221 0, 0, pbn_b0_8_115200 },
5222 { /* RockForceF8 */
5223 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5224 PCI_VENDOR_ID_MAINPINE, 0x2700,
5225 0, 0, pbn_b0_8_115200 },
5226 { /* IQ Express D1 */
5227 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5228 PCI_VENDOR_ID_MAINPINE, 0x3000,
5229 0, 0, pbn_b0_1_115200 },
5230 { /* IQ Express F1 */
5231 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5232 PCI_VENDOR_ID_MAINPINE, 0x3100,
5233 0, 0, pbn_b0_1_115200 },
5234 { /* IQ Express D2 */
5235 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5236 PCI_VENDOR_ID_MAINPINE, 0x3200,
5237 0, 0, pbn_b0_2_115200 },
5238 { /* IQ Express F2 */
5239 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5240 PCI_VENDOR_ID_MAINPINE, 0x3300,
5241 0, 0, pbn_b0_2_115200 },
5242 { /* IQ Express D4 */
5243 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5244 PCI_VENDOR_ID_MAINPINE, 0x3400,
5245 0, 0, pbn_b0_4_115200 },
5246 { /* IQ Express F4 */
5247 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5248 PCI_VENDOR_ID_MAINPINE, 0x3500,
5249 0, 0, pbn_b0_4_115200 },
5250 { /* IQ Express D8 */
5251 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5252 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5253 0, 0, pbn_b0_8_115200 },
5254 { /* IQ Express F8 */
5255 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5256 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5257 0, 0, pbn_b0_8_115200 },
5258
5259
aa798505
OJ		 5260 /*
5261 * PA Semi PA6T-1682M on-chip UART
5262 */
5263 { PCI_VENDOR_ID_PASEMI, 0xa004,
5264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5265 pbn_pasemi_1682M },
5266
46a0fac9
SB		 5267 /*
5268 * National Instruments
5269 */
04bf7e74
WP		 5270 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5272 pbn_b1_16_115200 },
5273 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5275 pbn_b1_8_115200 },
5276 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5278 pbn_b1_bt_4_115200 },
5279 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5281 pbn_b1_bt_2_115200 },
5282 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5284 pbn_b1_bt_4_115200 },
5285 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5287 pbn_b1_bt_2_115200 },
5288 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5290 pbn_b1_16_115200 },
5291 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5293 pbn_b1_8_115200 },
5294 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5296 pbn_b1_bt_4_115200 },
5297 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5299 pbn_b1_bt_2_115200 },
5300 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5302 pbn_b1_bt_4_115200 },
5303 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5305 pbn_b1_bt_2_115200 },
46a0fac9
SB		 5306 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5308 pbn_ni8430_2 },
5309 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5311 pbn_ni8430_2 },
5312 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5314 pbn_ni8430_4 },
5315 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5317 pbn_ni8430_4 },
5318 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5320 pbn_ni8430_8 },
5321 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5323 pbn_ni8430_8 },
5324 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5326 pbn_ni8430_16 },
5327 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5329 pbn_ni8430_16 },
5330 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5332 pbn_ni8430_2 },
5333 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5335 pbn_ni8430_2 },
5336 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5338 pbn_ni8430_4 },
5339 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5341 pbn_ni8430_4 },
5342
02c9b5cf
KJ		 5343 /*
5344 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5345 */
5346 { PCI_VENDOR_ID_ADDIDATA,
5347 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5348 PCI_ANY_ID,
5349 PCI_ANY_ID,
5350 0,
5351 0,
5352 pbn_b0_4_115200 },
5353
5354 { PCI_VENDOR_ID_ADDIDATA,
5355 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5356 PCI_ANY_ID,
5357 PCI_ANY_ID,
5358 0,
5359 0,
5360 pbn_b0_2_115200 },
5361
5362 { PCI_VENDOR_ID_ADDIDATA,
5363 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5364 PCI_ANY_ID,
5365 PCI_ANY_ID,
5366 0,
5367 0,
5368 pbn_b0_1_115200 },
5369
086231f7 5370 { PCI_VENDOR_ID_AMCC,
57c1f0e9 5371 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 5372 PCI_ANY_ID,
5373 PCI_ANY_ID,
5374 0,
5375 0,
5376 pbn_b1_8_115200 },
5377
5378 { PCI_VENDOR_ID_ADDIDATA,
5379 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5380 PCI_ANY_ID,
5381 PCI_ANY_ID,
5382 0,
5383 0,
5384 pbn_b0_4_115200 },
5385
5386 { PCI_VENDOR_ID_ADDIDATA,
5387 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5388 PCI_ANY_ID,
5389 PCI_ANY_ID,
5390 0,
5391 0,
5392 pbn_b0_2_115200 },
5393
5394 { PCI_VENDOR_ID_ADDIDATA,
5395 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5396 PCI_ANY_ID,
5397 PCI_ANY_ID,
5398 0,
5399 0,
5400 pbn_b0_1_115200 },
5401
5402 { PCI_VENDOR_ID_ADDIDATA,
5403 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5404 PCI_ANY_ID,
5405 PCI_ANY_ID,
5406 0,
5407 0,
5408 pbn_b0_4_115200 },
5409
5410 { PCI_VENDOR_ID_ADDIDATA,
5411 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5412 PCI_ANY_ID,
5413 PCI_ANY_ID,
5414 0,
5415 0,
5416 pbn_b0_2_115200 },
5417
5418 { PCI_VENDOR_ID_ADDIDATA,
5419 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5420 PCI_ANY_ID,
5421 PCI_ANY_ID,
5422 0,
5423 0,
5424 pbn_b0_1_115200 },
5425
5426 { PCI_VENDOR_ID_ADDIDATA,
5427 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5428 PCI_ANY_ID,
5429 PCI_ANY_ID,
5430 0,
5431 0,
5432 pbn_b0_8_115200 },
5433
1b62cbf2
KJ		 5434 { PCI_VENDOR_ID_ADDIDATA,
5435 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5436 PCI_ANY_ID,
5437 PCI_ANY_ID,
5438 0,
5439 0,
5440 pbn_ADDIDATA_PCIe_4_3906250 },
5441
5442 { PCI_VENDOR_ID_ADDIDATA,
5443 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5444 PCI_ANY_ID,
5445 PCI_ANY_ID,
5446 0,
5447 0,
5448 pbn_ADDIDATA_PCIe_2_3906250 },
5449
5450 { PCI_VENDOR_ID_ADDIDATA,
5451 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5452 PCI_ANY_ID,
5453 PCI_ANY_ID,
5454 0,
5455 0,
5456 pbn_ADDIDATA_PCIe_1_3906250 },
5457
5458 { PCI_VENDOR_ID_ADDIDATA,
5459 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5460 PCI_ANY_ID,
5461 PCI_ANY_ID,
5462 0,
5463 0,
5464 pbn_ADDIDATA_PCIe_8_3906250 },
5465
25cf9bc1
JS		 5466 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5467 PCI_VENDOR_ID_IBM, 0x0299,
5468 0, 0, pbn_b0_bt_2_115200 },
5469
972ce085
SS		 5470 /*
5471 * other NetMos 9835 devices are most likely handled by the
5472 * parport_serial driver, check drivers/parport/parport_serial.c
5473 * before adding them here.
5474 */
5475
c4285b47
MB		 5476 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5477 0xA000, 0x1000,
5478 0, 0, pbn_b0_1_115200 },
5479
7808edcd
NG		 5480 /* the 9901 is a rebranded 9912 */
5481 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5482 0xA000, 0x1000,
5483 0, 0, pbn_b0_1_115200 },
5484
5485 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5486 0xA000, 0x1000,
5487 0, 0, pbn_b0_1_115200 },
5488
5489 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5490 0xA000, 0x1000,
5491 0, 0, pbn_b0_1_115200 },
5492
5493 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5494 0xA000, 0x1000,
5495 0, 0, pbn_b0_1_115200 },
5496
5497 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5498 0xA000, 0x3002,
5499 0, 0, pbn_NETMOS9900_2s_115200 },
5500
ac6ec5b1 5501 /*
44178176 5502 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5503 */
5504
5505 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5506 0xA000, 0x1000,
5507 0, 0, pbn_b0_1_115200 },
5508
44178176
ES		 5509 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5510 0xA000, 0x3002,
5511 0, 0, pbn_b0_bt_2_115200 },
5512
ac6ec5b1
IS		 5513 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5514 0xA000, 0x3004,
5515 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5516 /* Intel CE4100 */
5517 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5519 pbn_ce4100_1_115200 },
b15e5691
HK		 5520 /* Intel BayTrail */
5521 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5522 PCI_ANY_ID, PCI_ANY_ID,
5523 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5524 pbn_byt },
5525 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5526 PCI_ANY_ID, PCI_ANY_ID,
5527 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5528 pbn_byt },
29897087
AC		 5529 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5530 PCI_ANY_ID, PCI_ANY_ID,
5531 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5532 pbn_byt },
5533 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
b15e5691
HK		 5534 PCI_ANY_ID, PCI_ANY_ID,
5535 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5536 pbn_byt },
095e24b0 5537
f549e94e
AS		 5538 /*
5539 * Intel Penwell
5540 */
5541 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
5542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5543 pbn_pnw},
5544 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
5545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5546 pbn_pnw},
5547 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
5548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5549 pbn_pnw},
5550
90b9aacf
AS		 5551 /*
5552 * Intel Tangier
5553 */
5554 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
5555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5556 pbn_tng},
5557
1ede7dcc
BD		 5558 /*
5559 * Intel Quark x1000
5560 */
5561 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5563 pbn_qrk },
d9a0fbfd
AP		 5564 /*
5565 * Cronyx Omega PCI
5566 */
5567 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5569 pbn_omegapci },
ac6ec5b1 5570
ebebd49a
SH		 5571 /*
5572 * Broadcom TruManage
5573 */
5574 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5576 pbn_brcm_trumanage },
5577
6683549e
AC		 5578 /*
5579 * AgeStar as-prs2-009
5580 */
5581 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5582 PCI_ANY_ID, PCI_ANY_ID,
5583 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5584
5585 /*
5586 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5587 * so not listed here.
5588 */
5589 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5590 PCI_ANY_ID, PCI_ANY_ID,
5591 0, 0, pbn_b0_bt_4_115200 },
5592
5593 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5594 PCI_ANY_ID, PCI_ANY_ID,
5595 0, 0, pbn_b0_bt_2_115200 },
5596
72a3c0e4
SP		 5597 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5598 PCI_ANY_ID, PCI_ANY_ID,
5599 0, 0, pbn_wch384_4 },
5600
14faa8cc
MS		 5601 /*
5602 * Commtech, Inc. Fastcom adapters
5603 */
5604 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5605 PCI_ANY_ID, PCI_ANY_ID,
5606 0,
5607 0, pbn_b0_2_1152000_200 },
5608 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5609 PCI_ANY_ID, PCI_ANY_ID,
5610 0,
5611 0, pbn_b0_4_1152000_200 },
5612 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5613 PCI_ANY_ID, PCI_ANY_ID,
5614 0,
5615 0, pbn_b0_4_1152000_200 },
5616 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5617 PCI_ANY_ID, PCI_ANY_ID,
5618 0,
5619 0, pbn_b0_8_1152000_200 },
5620 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5621 PCI_ANY_ID, PCI_ANY_ID,
5622 0,
5623 0, pbn_exar_XR17V352 },
5624 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5625 PCI_ANY_ID, PCI_ANY_ID,
5626 0,
5627 0, pbn_exar_XR17V354 },
5628 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5629 PCI_ANY_ID, PCI_ANY_ID,
5630 0,
5631 0, pbn_exar_XR17V358 },
5632
2c62a3c8
GKH		 5633 /* Fintek PCI serial cards */
5634 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5635 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5636 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5637
1da177e4
LT		 5638 /*
5639 * These entries match devices with class COMMUNICATION_SERIAL,
5640 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5641 */
5642 { PCI_ANY_ID, PCI_ANY_ID,
5643 PCI_ANY_ID, PCI_ANY_ID,
5644 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5645 0xffff00, pbn_default },
5646 { PCI_ANY_ID, PCI_ANY_ID,
5647 PCI_ANY_ID, PCI_ANY_ID,
5648 PCI_CLASS_COMMUNICATION_MODEM << 8,
5649 0xffff00, pbn_default },
5650 { PCI_ANY_ID, PCI_ANY_ID,
5651 PCI_ANY_ID, PCI_ANY_ID,
5652 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5653 0xffff00, pbn_default },
5654 { 0, }
5655};
5656
2807190b
MR		 5657static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5658 pci_channel_state_t state)
5659{
5660 struct serial_private *priv = pci_get_drvdata(dev);
5661
5662 if (state == pci_channel_io_perm_failure)
5663 return PCI_ERS_RESULT_DISCONNECT;
5664
5665 if (priv)
5666 pciserial_suspend_ports(priv);
5667
5668 pci_disable_device(dev);
5669
5670 return PCI_ERS_RESULT_NEED_RESET;
5671}
5672
5673static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5674{
5675 int rc;
5676
5677 rc = pci_enable_device(dev);
5678
5679 if (rc)
5680 return PCI_ERS_RESULT_DISCONNECT;
5681
5682 pci_restore_state(dev);
5683 pci_save_state(dev);
5684
5685 return PCI_ERS_RESULT_RECOVERED;
5686}
5687
5688static void serial8250_io_resume(struct pci_dev *dev)
5689{
5690 struct serial_private *priv = pci_get_drvdata(dev);
5691
5692 if (priv)
5693 pciserial_resume_ports(priv);
5694}
5695
1d352035 5696static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5697 .error_detected = serial8250_io_error_detected,
5698 .slot_reset = serial8250_io_slot_reset,
5699 .resume = serial8250_io_resume,
5700};
5701
1da177e4
LT		 5702static struct pci_driver serial_pci_driver = {
5703 .name = "serial",
5704 .probe = pciserial_init_one,
2d47b716 5705 .remove = pciserial_remove_one,
61702c3e
AS		 5706 .driver = {
5707 .pm = &pciserial_pm_ops,
5708 },
1da177e4 5709 .id_table = serial_pci_tbl,
2807190b 5710 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5711};
5712
15a12e83 5713module_pci_driver(serial_pci_driver);
1da177e4
LT		 5714
5715MODULE_LICENSE("GPL");
5716MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5717MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux 6.x block layer and io_uring tree(s)