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tty: serial: fsl_lpuart: add 32-bit register interface support
[linux-2.6-block.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
28#include "8250.h"
29
1da177e4
LT		 30/*
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
34 * < 0 - error
35 */
36struct pci_serial_quirk {
37 u32 vendor;
38 u32 device;
39 u32 subvendor;
40 u32 subdevice;
5bf8f501 41 int (*probe)(struct pci_dev *dev);
1da177e4 42 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
2655a2c7 45 struct uart_8250_port *, int);
1da177e4
LT		 46 void (*exit)(struct pci_dev *dev);
47};
48
49#define PCI_NUM_BAR_RESOURCES 6
50
51struct serial_private {
70db3d91 52 struct pci_dev *dev;
1da177e4
LT		 53 unsigned int nr;
54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
55 struct pci_serial_quirk *quirk;
56 int line[0];
57};
58
7808edcd 59static int pci_default_setup(struct serial_private*,
2655a2c7 60 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 61
1da177e4
LT		 62static void moan_device(const char *str, struct pci_dev *dev)
63{
af8c5b8d 64 dev_err(&dev->dev,
ad361c98
JP		 65 "%s: %s\n"
66 "Please send the output of lspci -vv, this\n"
67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 "manufacturer and name of serial board or\n"
69 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72}
73
74static int
2655a2c7 75setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 76 int bar, int offset, int regshift)
77{
70db3d91 78 struct pci_dev *dev = priv->dev;
1da177e4
LT		 79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
72ce9a83
RK		 84 base = pci_resource_start(dev, bar);
85
1da177e4 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
6f441fe9 90 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
2655a2c7
AC		 94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
96 port->port.mapbase = base + offset;
97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
1da177e4 99 } else {
2655a2c7
AC		 100 port->port.iotype = UPIO_PORT;
101 port->port.iobase = base + offset;
102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
02c9b5cf
KJ		 109/*
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 113 const struct pciserial_board *board,
2655a2c7 114 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 115{
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133}
134
1da177e4
LT		 135/*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139static int
975a1a7d 140afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 141 struct uart_8250_port *port, int idx)
1da177e4
LT		 142{
143 unsigned int bar, offset = board->first_offset;
5756ee99 144
1da177e4
LT		 145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
70db3d91 153 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 154}
155
156/*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
61a116ef 163static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 164{
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 182 rc = 1;
183 break;
184 }
185
186 return rc;
187}
188
189/*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193static int
975a1a7d
RK		 194pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
2655a2c7 196 struct uart_8250_port *port, int idx)
1da177e4
LT		 197{
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
70db3d91 201 switch (priv->dev->subsystem_device) {
1da177e4
LT		 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
70db3d91 218 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 219}
220
221/*
222 * Added for EKF Intel i960 serial boards
223 */
61a116ef 224static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 225{
226 unsigned long oldval;
227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
5756ee99
AC		 232 pci_read_config_dword(dev, 0x44, (void *)&oldval);
233 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 235 return -ENODEV;
236 }
237 return 0;
238}
239
240/*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
61a116ef 246static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 247{
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
add7b58e 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 259 irq_config = 0x43;
5756ee99 260
1da177e4 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
1da177e4
LT		 272 /*
273 * enable/disable interrupts
274 */
6f441fe9 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287}
288
ae8d8a14 289static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 290{
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
6f441fe9 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309}
310
04bf7e74
WP		 311#define NI8420_INT_ENABLE_REG 0x38
312#define NI8420_INT_ENABLE_BIT 0x2000
313
ae8d8a14 314static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 315{
316 void __iomem *p;
317 unsigned long base, len;
318 unsigned int bar = 0;
319
320 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
321 moan_device("no memory in bar", dev);
322 return;
323 }
324
325 base = pci_resource_start(dev, bar);
326 len = pci_resource_len(dev, bar);
327 p = ioremap_nocache(base, len);
328 if (p == NULL)
329 return;
330
331 /* Disable the CPU Interrupt */
332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
333 p + NI8420_INT_ENABLE_REG);
334 iounmap(p);
335}
336
337
46a0fac9
SB		 338/* MITE registers */
339#define MITE_IOWBSR1 0xc4
340#define MITE_IOWCR1 0xf4
341#define MITE_LCIMR1 0x08
342#define MITE_LCIMR2 0x10
343
344#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
345
ae8d8a14 346static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 347{
348 void __iomem *p;
349 unsigned long base, len;
350 unsigned int bar = 0;
351
352 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
353 moan_device("no memory in bar", dev);
354 return;
355 }
356
357 base = pci_resource_start(dev, bar);
358 len = pci_resource_len(dev, bar);
359 p = ioremap_nocache(base, len);
360 if (p == NULL)
361 return;
362
363 /* Disable the CPU Interrupt */
364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
365 iounmap(p);
366}
367
1da177e4
LT		 368/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
369static int
975a1a7d 370sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 371 struct uart_8250_port *port, int idx)
1da177e4
LT		 372{
373 unsigned int bar, offset = board->first_offset;
374
375 bar = 0;
376
377 if (idx < 4) {
378 /* first four channels map to 0, 0x100, 0x200, 0x300 */
379 offset += idx * board->uart_offset;
380 } else if (idx < 8) {
381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
382 offset += idx * board->uart_offset + 0xC00;
383 } else /* we have only 8 ports on PMC-OCTALPRO */
384 return 1;
385
70db3d91 386 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 387}
388
389/*
390* This does initialization for PMC OCTALPRO cards:
391* maps the device memory, resets the UARTs (needed, bc
392* if the module is removed and inserted again, the card
393* is in the sleep mode) and enables global interrupt.
394*/
395
396/* global control register offset for SBS PMC-OctalPro */
397#define OCT_REG_CR_OFF 0x500
398
61a116ef 399static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 400{
401 u8 __iomem *p;
402
24ed3aba 403 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 404
405 if (p == NULL)
406 return -ENOMEM;
407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 408 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 409 udelay(50);
5756ee99 410 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 411
412 /* Set bit-2 (INTENABLE) of Control Register */
413 writeb(0x4, p + OCT_REG_CR_OFF);
414 iounmap(p);
415
416 return 0;
417}
418
419/*
420 * Disables the global interrupt of PMC-OctalPro
421 */
422
ae8d8a14 423static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 424{
425 u8 __iomem *p;
426
24ed3aba 427 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 if (p != NULL)
1da177e4 430 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 431 iounmap(p);
432}
433
434/*
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
25985edc 437 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
444 *
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 446 *
1da177e4
LT		 447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
451 *
67d74b87
RK		 452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
454 *
fbc0dc0d
AP		 455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 *
1da177e4
LT		 458 * Note: some SIIG cards are probed by the parport_serial object.
459 */
460
461#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463
464static int pci_siig10x_init(struct pci_dev *dev)
465{
466 u16 data;
467 void __iomem *p;
468
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
471 data = 0xffdf;
472 break;
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
474 data = 0xf7ff;
475 break;
476 default: /* 1S1P, 4S */
477 data = 0xfffb;
478 break;
479 }
480
6f441fe9 481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 482 if (p == NULL)
483 return -ENOMEM;
484
485 writew(readw(p + 0x28) & data, p + 0x28);
486 readw(p + 0x28);
487 iounmap(p);
488 return 0;
489}
490
491#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493
494static int pci_siig20x_init(struct pci_dev *dev)
495{
496 u8 data;
497
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
501
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
507 }
508 return 0;
509}
510
67d74b87
RK		 511static int pci_siig_init(struct pci_dev *dev)
512{
513 unsigned int type = dev->device & 0xff00;
514
515 if (type == 0x1000)
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
519
520 moan_device("Unknown SIIG card", dev);
521 return -ENODEV;
522}
523
3ec9c594 524static int pci_siig_setup(struct serial_private *priv,
975a1a7d 525 const struct pciserial_board *board,
2655a2c7 526 struct uart_8250_port *port, int idx)
3ec9c594
AP		 527{
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
529
530 if (idx > 3) {
531 bar = 4;
532 offset = (idx - 4) * 8;
533 }
534
535 return setup_port(priv, port, bar, offset, 0);
536}
537
1da177e4
LT		 538/*
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
542 */
e9422e09 543static const unsigned short timedia_single_port[] = {
1da177e4
LT		 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
545};
546
e9422e09 547static const unsigned short timedia_dual_port[] = {
1da177e4 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
552 0xD079, 0
553};
554
e9422e09 555static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
559 0xB157, 0
560};
561
e9422e09 562static const unsigned short timedia_eight_port[] = {
5756ee99 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
565};
566
cb3592be 567static const struct timedia_struct {
1da177e4 568 int num;
e9422e09 569 const unsigned short *ids;
1da177e4
LT		 570} timedia_data[] = {
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
e9422e09 574 { 8, timedia_eight_port }
1da177e4
LT		 575};
576
b9b24558
FB		 577/*
578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
579 * listing them individually, this driver merely grabs them all with
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
581 * and should be left free to be claimed by parport_serial instead.
582 */
583static int pci_timedia_probe(struct pci_dev *dev)
584{
585 /*
586 * Check the third digit of the subdevice ID
587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
588 */
589 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
590 dev_info(&dev->dev,
591 "ignoring Timedia subdevice %04x for parport_serial\n",
592 dev->subsystem_device);
593 return -ENODEV;
594 }
595
596 return 0;
597}
598
61a116ef 599static int pci_timedia_init(struct pci_dev *dev)
1da177e4 600{
e9422e09 601 const unsigned short *ids;
1da177e4
LT		 602 int i, j;
603
e9422e09 604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 605 ids = timedia_data[i].ids;
606 for (j = 0; ids[j]; j++)
607 if (dev->subsystem_device == ids[j])
608 return timedia_data[i].num;
609 }
610 return 0;
611}
612
613/*
614 * Timedia/SUNIX uses a mixture of BARs and offsets
615 * Ugh, this is ugly as all hell --- TYT
616 */
617static int
975a1a7d
RK		 618pci_timedia_setup(struct serial_private *priv,
619 const struct pciserial_board *board,
2655a2c7 620 struct uart_8250_port *port, int idx)
1da177e4
LT		 621{
622 unsigned int bar = 0, offset = board->first_offset;
623
624 switch (idx) {
625 case 0:
626 bar = 0;
627 break;
628 case 1:
629 offset = board->uart_offset;
630 bar = 0;
631 break;
632 case 2:
633 bar = 1;
634 break;
635 case 3:
636 offset = board->uart_offset;
c2cd6d3c 637 /* FALLTHROUGH */
1da177e4
LT		 638 case 4: /* BAR 2 */
639 case 5: /* BAR 3 */
640 case 6: /* BAR 4 */
641 case 7: /* BAR 5 */
642 bar = idx - 2;
643 }
644
70db3d91 645 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 646}
647
648/*
649 * Some Titan cards are also a little weird
650 */
651static int
70db3d91 652titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 653 const struct pciserial_board *board,
2655a2c7 654 struct uart_8250_port *port, int idx)
1da177e4
LT		 655{
656 unsigned int bar, offset = board->first_offset;
657
658 switch (idx) {
659 case 0:
660 bar = 1;
661 break;
662 case 1:
663 bar = 2;
664 break;
665 default:
666 bar = 4;
667 offset = (idx - 2) * board->uart_offset;
668 }
669
70db3d91 670 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 671}
672
61a116ef 673static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 674{
675 msleep(100);
676 return 0;
677}
678
04bf7e74
WP		 679static int pci_ni8420_init(struct pci_dev *dev)
680{
681 void __iomem *p;
682 unsigned long base, len;
683 unsigned int bar = 0;
684
685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
686 moan_device("no memory in bar", dev);
687 return 0;
688 }
689
690 base = pci_resource_start(dev, bar);
691 len = pci_resource_len(dev, bar);
692 p = ioremap_nocache(base, len);
693 if (p == NULL)
694 return -ENOMEM;
695
696 /* Enable CPU Interrupt */
697 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
698 p + NI8420_INT_ENABLE_REG);
699
700 iounmap(p);
701 return 0;
702}
703
46a0fac9
SB		 704#define MITE_IOWBSR1_WSIZE 0xa
705#define MITE_IOWBSR1_WIN_OFFSET 0x800
706#define MITE_IOWBSR1_WENAB (1 << 7)
707#define MITE_LCIMR1_IO_IE_0 (1 << 24)
708#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
709#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
710
711static int pci_ni8430_init(struct pci_dev *dev)
712{
713 void __iomem *p;
714 unsigned long base, len;
715 u32 device_window;
716 unsigned int bar = 0;
717
718 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
719 moan_device("no memory in bar", dev);
720 return 0;
721 }
722
723 base = pci_resource_start(dev, bar);
724 len = pci_resource_len(dev, bar);
725 p = ioremap_nocache(base, len);
726 if (p == NULL)
727 return -ENOMEM;
728
729 /* Set device window address and size in BAR0 */
730 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
732 writel(device_window, p + MITE_IOWBSR1);
733
734 /* Set window access to go to RAMSEL IO address space */
735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
736 p + MITE_IOWCR1);
737
738 /* Enable IO Bus Interrupt 0 */
739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
740
741 /* Enable CPU Interrupt */
742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
743
744 iounmap(p);
745 return 0;
746}
747
748/* UART Port Control Register */
749#define NI8430_PORTCON 0x0f
750#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
751
752static int
bf538fe4
AC		 753pci_ni8430_setup(struct serial_private *priv,
754 const struct pciserial_board *board,
2655a2c7 755 struct uart_8250_port *port, int idx)
46a0fac9
SB		 756{
757 void __iomem *p;
758 unsigned long base, len;
759 unsigned int bar, offset = board->first_offset;
760
761 if (idx >= board->num_ports)
762 return 1;
763
764 bar = FL_GET_BASE(board->flags);
765 offset += idx * board->uart_offset;
766
767 base = pci_resource_start(priv->dev, bar);
768 len = pci_resource_len(priv->dev, bar);
769 p = ioremap_nocache(base, len);
770
7c9d440e 771 /* enable the transceiver */
46a0fac9
SB		 772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
773 p + offset + NI8430_PORTCON);
774
775 iounmap(p);
776
777 return setup_port(priv, port, bar, offset, board->reg_shift);
778}
779
7808edcd
NG		 780static int pci_netmos_9900_setup(struct serial_private *priv,
781 const struct pciserial_board *board,
2655a2c7 782 struct uart_8250_port *port, int idx)
7808edcd
NG		 783{
784 unsigned int bar;
785
333c085e
DES		 786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
787 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
7808edcd
NG		 788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
af8c5b8d 829 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
46a0fac9 837
61a116ef 838static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
ac6ec5b1
IS		 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 845 return 0;
7808edcd 846
25cf9bc1
JS		 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
7808edcd
NG		 851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
1da177e4
LT		 865 if (num_serial == 0)
866 return -ENODEV;
7808edcd 867
1da177e4
LT		 868 return num_serial;
869}
870
84f8c6fc 871/*
84f8c6fc
NV		 872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
f79abb82 899static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
5756ee99
AC		 919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
84f8c6fc
NV		 921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
af8c5b8d 933 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
ae8d8a14 993static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
9f2a036a
RK		 1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
af8c5b8d 1026 dev_dbg(&dev->dev,
9f2a036a 1027 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1028 number_uarts);
9f2a036a
RK		 1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
eb26dfe8
AC		 1034static int pci_asix_setup(struct serial_private *priv,
1035 const struct pciserial_board *board,
1036 struct uart_8250_port *port, int idx)
1037{
1038 port->bugs |= UART_BUG_PARITY;
1039 return pci_default_setup(priv, board, port, idx);
1040}
1041
55c7c0fd
AC		 1042/* Quatech devices have their own extra interface features */
1043
1044struct quatech_feature {
1045 u16 devid;
1046 bool amcc;
1047};
1048
1049#define QPCR_TEST_FOR1 0x3F
1050#define QPCR_TEST_GET1 0x00
1051#define QPCR_TEST_FOR2 0x40
1052#define QPCR_TEST_GET2 0x40
1053#define QPCR_TEST_FOR3 0x80
1054#define QPCR_TEST_GET3 0x40
1055#define QPCR_TEST_FOR4 0xC0
1056#define QPCR_TEST_GET4 0x80
1057
1058#define QOPR_CLOCK_X1 0x0000
1059#define QOPR_CLOCK_X2 0x0001
1060#define QOPR_CLOCK_X4 0x0002
1061#define QOPR_CLOCK_X8 0x0003
1062#define QOPR_CLOCK_RATE_MASK 0x0003
1063
1064
1065static struct quatech_feature quatech_cards[] = {
1066 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1067 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1069 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1071 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1073 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1074 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1076 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1078 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1085 { 0, }
1086};
1087
1088static int pci_quatech_amcc(u16 devid)
1089{
1090 struct quatech_feature *qf = &quatech_cards[0];
1091 while (qf->devid) {
1092 if (qf->devid == devid)
1093 return qf->amcc;
1094 qf++;
1095 }
1096 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1097 return 0;
1098};
1099
1100static int pci_quatech_rqopr(struct uart_8250_port *port)
1101{
1102 unsigned long base = port->port.iobase;
1103 u8 LCR, val;
1104
1105 LCR = inb(base + UART_LCR);
1106 outb(0xBF, base + UART_LCR);
1107 val = inb(base + UART_SCR);
1108 outb(LCR, base + UART_LCR);
1109 return val;
1110}
1111
1112static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1113{
1114 unsigned long base = port->port.iobase;
1115 u8 LCR, val;
1116
1117 LCR = inb(base + UART_LCR);
1118 outb(0xBF, base + UART_LCR);
1119 val = inb(base + UART_SCR);
1120 outb(qopr, base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1122}
1123
1124static int pci_quatech_rqmcr(struct uart_8250_port *port)
1125{
1126 unsigned long base = port->port.iobase;
1127 u8 LCR, val, qmcr;
1128
1129 LCR = inb(base + UART_LCR);
1130 outb(0xBF, base + UART_LCR);
1131 val = inb(base + UART_SCR);
1132 outb(val | 0x10, base + UART_SCR);
1133 qmcr = inb(base + UART_MCR);
1134 outb(val, base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1136
1137 return qmcr;
1138}
1139
1140static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1141{
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(val | 0x10, base + UART_SCR);
1149 outb(qmcr, base + UART_MCR);
1150 outb(val, base + UART_SCR);
1151 outb(LCR, base + UART_LCR);
1152}
1153
1154static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1155{
1156 unsigned long base = port->port.iobase;
1157 u8 LCR, val;
1158
1159 LCR = inb(base + UART_LCR);
1160 outb(0xBF, base + UART_LCR);
1161 val = inb(base + UART_SCR);
1162 if (val & 0x20) {
1163 outb(0x80, UART_LCR);
1164 if (!(inb(UART_SCR) & 0x20)) {
1165 outb(LCR, base + UART_LCR);
1166 return 1;
1167 }
1168 }
1169 return 0;
1170}
1171
1172static int pci_quatech_test(struct uart_8250_port *port)
1173{
1174 u8 reg;
1175 u8 qopr = pci_quatech_rqopr(port);
1176 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1177 reg = pci_quatech_rqopr(port) & 0xC0;
1178 if (reg != QPCR_TEST_GET1)
1179 return -EINVAL;
1180 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1181 reg = pci_quatech_rqopr(port) & 0xC0;
1182 if (reg != QPCR_TEST_GET2)
1183 return -EINVAL;
1184 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1185 reg = pci_quatech_rqopr(port) & 0xC0;
1186 if (reg != QPCR_TEST_GET3)
1187 return -EINVAL;
1188 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1189 reg = pci_quatech_rqopr(port) & 0xC0;
1190 if (reg != QPCR_TEST_GET4)
1191 return -EINVAL;
1192
1193 pci_quatech_wqopr(port, qopr);
1194 return 0;
1195}
1196
1197static int pci_quatech_clock(struct uart_8250_port *port)
1198{
1199 u8 qopr, reg, set;
1200 unsigned long clock;
1201
1202 if (pci_quatech_test(port) < 0)
1203 return 1843200;
1204
1205 qopr = pci_quatech_rqopr(port);
1206
1207 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1208 reg = pci_quatech_rqopr(port);
1209 if (reg & QOPR_CLOCK_X8) {
1210 clock = 1843200;
1211 goto out;
1212 }
1213 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1214 reg = pci_quatech_rqopr(port);
1215 if (!(reg & QOPR_CLOCK_X8)) {
1216 clock = 1843200;
1217 goto out;
1218 }
1219 reg &= QOPR_CLOCK_X8;
1220 if (reg == QOPR_CLOCK_X2) {
1221 clock = 3685400;
1222 set = QOPR_CLOCK_X2;
1223 } else if (reg == QOPR_CLOCK_X4) {
1224 clock = 7372800;
1225 set = QOPR_CLOCK_X4;
1226 } else if (reg == QOPR_CLOCK_X8) {
1227 clock = 14745600;
1228 set = QOPR_CLOCK_X8;
1229 } else {
1230 clock = 1843200;
1231 set = QOPR_CLOCK_X1;
1232 }
1233 qopr &= ~QOPR_CLOCK_RATE_MASK;
1234 qopr |= set;
1235
1236out:
1237 pci_quatech_wqopr(port, qopr);
1238 return clock;
1239}
1240
1241static int pci_quatech_rs422(struct uart_8250_port *port)
1242{
1243 u8 qmcr;
1244 int rs422 = 0;
1245
1246 if (!pci_quatech_has_qmcr(port))
1247 return 0;
1248 qmcr = pci_quatech_rqmcr(port);
1249 pci_quatech_wqmcr(port, 0xFF);
1250 if (pci_quatech_rqmcr(port))
1251 rs422 = 1;
1252 pci_quatech_wqmcr(port, qmcr);
1253 return rs422;
1254}
1255
1256static int pci_quatech_init(struct pci_dev *dev)
1257{
1258 if (pci_quatech_amcc(dev->device)) {
1259 unsigned long base = pci_resource_start(dev, 0);
1260 if (base) {
1261 u32 tmp;
9c5320f8 1262 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1263 tmp = inl(base + 0x3c);
1264 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1265 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1266 }
1267 }
1268 return 0;
1269}
1270
1271static int pci_quatech_setup(struct serial_private *priv,
1272 const struct pciserial_board *board,
1273 struct uart_8250_port *port, int idx)
1274{
1275 /* Needed by pci_quatech calls below */
1276 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1277 /* Set up the clocking */
1278 port->port.uartclk = pci_quatech_clock(port);
1279 /* For now just warn about RS422 */
1280 if (pci_quatech_rs422(port))
1281 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1282 return pci_default_setup(priv, board, port, idx);
1283}
1284
d73dfc6a 1285static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1286{
1287}
1288
eb26dfe8 1289static int pci_default_setup(struct serial_private *priv,
975a1a7d 1290 const struct pciserial_board *board,
2655a2c7 1291 struct uart_8250_port *port, int idx)
1da177e4
LT		 1292{
1293 unsigned int bar, offset = board->first_offset, maxnr;
1294
1295 bar = FL_GET_BASE(board->flags);
1296 if (board->flags & FL_BASE_BARS)
1297 bar += idx;
1298 else
1299 offset += idx * board->uart_offset;
1300
2427ddd8
GKH		 1301 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1302 (board->reg_shift + 3);
1da177e4
LT		 1303
1304 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1305 return 1;
5756ee99 1306
70db3d91 1307 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1308}
1309
94341475
AB		 1310static int pci_pericom_setup(struct serial_private *priv,
1311 const struct pciserial_board *board,
1312 struct uart_8250_port *port, int idx)
1313{
1314 unsigned int bar, offset = board->first_offset, maxnr;
1315
1316 bar = FL_GET_BASE(board->flags);
1317 if (board->flags & FL_BASE_BARS)
1318 bar += idx;
1319 else
1320 offset += idx * board->uart_offset;
1321
1322 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1323 (board->reg_shift + 3);
1324
1325 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1326 return 1;
1327
1328 port->port.uartclk = 14745600;
1329
1330 return setup_port(priv, port, bar, offset, board->reg_shift);
1331}
1332
095e24b0
DB		 1333static int
1334ce4100_serial_setup(struct serial_private *priv,
1335 const struct pciserial_board *board,
2655a2c7 1336 struct uart_8250_port *port, int idx)
095e24b0
DB		 1337{
1338 int ret;
1339
08ec212c 1340 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1341 port->port.iotype = UPIO_MEM32;
1342 port->port.type = PORT_XSCALE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 port->port.regshift = 2;
095e24b0
DB		 1345
1346 return ret;
1347}
1348
b15e5691
HK		 1349#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1350#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1351
1352#define BYT_PRV_CLK 0x800
1353#define BYT_PRV_CLK_EN (1 << 0)
1354#define BYT_PRV_CLK_M_VAL_SHIFT 1
1355#define BYT_PRV_CLK_N_VAL_SHIFT 16
1356#define BYT_PRV_CLK_UPDATE (1 << 31)
1357
1358#define BYT_GENERAL_REG 0x808
1359#define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3)
1360
1361#define BYT_TX_OVF_INT 0x820
1362#define BYT_TX_OVF_INT_MASK (1 << 1)
1363
1364static void
1365byt_set_termios(struct uart_port *p, struct ktermios *termios,
1366 struct ktermios *old)
1367{
1368 unsigned int baud = tty_termios_baud_rate(termios);
50825c57 1369 unsigned int m, n;
b15e5691
HK		 1370 u32 reg;
1371
50825c57
AS		 1372 /*
1373 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1374 * dividers must be adjusted.
1375 *
1376 * uartclk = (m / n) * 100 MHz, where m <= n
1377 */
1378 switch (baud) {
1379 case 500000:
1380 case 1000000:
1381 case 2000000:
1382 case 4000000:
b15e5691
HK		 1383 m = 64;
1384 n = 100;
b15e5691 1385 p->uartclk = 64000000;
50825c57
AS		 1386 break;
1387 case 3500000:
1388 m = 56;
1389 n = 100;
1390 p->uartclk = 56000000;
1391 break;
1392 case 1500000:
1393 case 3000000:
b15e5691
HK		 1394 m = 48;
1395 n = 100;
b15e5691 1396 p->uartclk = 48000000;
50825c57
AS		 1397 break;
1398 case 2500000:
1399 m = 40;
1400 n = 100;
1401 p->uartclk = 40000000;
1402 break;
1403 default:
41d3f099
AS		 1404 m = 2304;
1405 n = 3125;
1406 p->uartclk = 73728000;
b15e5691
HK		 1407 }
1408
1409 /* Reset the clock */
1410 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1411 writel(reg, p->membase + BYT_PRV_CLK);
1412 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1413 writel(reg, p->membase + BYT_PRV_CLK);
1414
1415 /*
1416 * If auto-handshake mechanism is not enabled,
1417 * disable rts_n override
1418 */
1419 reg = readl(p->membase + BYT_GENERAL_REG);
1420 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1421 if (termios->c_cflag & CRTSCTS)
1422 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1423 writel(reg, p->membase + BYT_GENERAL_REG);
1424
1425 serial8250_do_set_termios(p, termios, old);
1426}
1427
1428static bool byt_dma_filter(struct dma_chan *chan, void *param)
1429{
1430 return chan->chan_id == *(int *)param;
1431}
1432
1433static int
1434byt_serial_setup(struct serial_private *priv,
1435 const struct pciserial_board *board,
1436 struct uart_8250_port *port, int idx)
1437{
1438 struct uart_8250_dma *dma;
1439 int ret;
1440
1441 dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
1442 if (!dma)
1443 return -ENOMEM;
1444
1445 switch (priv->dev->device) {
1446 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1447 dma->rx_chan_id = 3;
1448 dma->tx_chan_id = 2;
1449 break;
1450 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1451 dma->rx_chan_id = 5;
1452 dma->tx_chan_id = 4;
1453 break;
1454 default:
1455 return -EINVAL;
1456 }
1457
1458 dma->rxconf.slave_id = dma->rx_chan_id;
1459 dma->rxconf.src_maxburst = 16;
1460
1461 dma->txconf.slave_id = dma->tx_chan_id;
1462 dma->txconf.dst_maxburst = 16;
1463
1464 dma->fn = byt_dma_filter;
1465 dma->rx_param = &dma->rx_chan_id;
1466 dma->tx_param = &dma->tx_chan_id;
1467
1468 ret = pci_default_setup(priv, board, port, idx);
1469 port->port.iotype = UPIO_MEM;
1470 port->port.type = PORT_16550A;
1471 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1472 port->port.set_termios = byt_set_termios;
1473 port->port.fifosize = 64;
1474 port->tx_loadsz = 64;
1475 port->dma = dma;
1476 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1477
1478 /* Disable Tx counter interrupts */
1479 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1480
1481 return ret;
1482}
1483
d9a0fbfd
AP		 1484static int
1485pci_omegapci_setup(struct serial_private *priv,
1798ca13 1486 const struct pciserial_board *board,
2655a2c7 1487 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1488{
1489 return setup_port(priv, port, 2, idx * 8, 0);
1490}
1491
ebebd49a
SH		 1492static int
1493pci_brcm_trumanage_setup(struct serial_private *priv,
1494 const struct pciserial_board *board,
1495 struct uart_8250_port *port, int idx)
1496{
1497 int ret = pci_default_setup(priv, board, port, idx);
1498
1499 port->port.type = PORT_BRCM_TRUMANAGE;
1500 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1501 return ret;
1502}
1503
2c62a3c8
GKH		 1504static int pci_fintek_setup(struct serial_private *priv,
1505 const struct pciserial_board *board,
1506 struct uart_8250_port *port, int idx)
1507{
1508 struct pci_dev *pdev = priv->dev;
1509 unsigned long base;
1510 unsigned long iobase;
1511 unsigned long ciobase = 0;
1512 u8 config_base;
1513
1514 /*
1515 * We are supposed to be able to read these from the PCI config space,
1516 * but the values there don't seem to match what we need to use, so
1517 * just use these hard-coded values for now, as they are correct.
1518 */
1519 switch (idx) {
1520 case 0: iobase = 0xe000; config_base = 0x40; break;
1521 case 1: iobase = 0xe008; config_base = 0x48; break;
1522 case 2: iobase = 0xe010; config_base = 0x50; break;
1523 case 3: iobase = 0xe018; config_base = 0x58; break;
1524 case 4: iobase = 0xe020; config_base = 0x60; break;
1525 case 5: iobase = 0xe028; config_base = 0x68; break;
1526 case 6: iobase = 0xe030; config_base = 0x70; break;
1527 case 7: iobase = 0xe038; config_base = 0x78; break;
1528 case 8: iobase = 0xe040; config_base = 0x80; break;
1529 case 9: iobase = 0xe048; config_base = 0x88; break;
1530 case 10: iobase = 0xe050; config_base = 0x90; break;
1531 case 11: iobase = 0xe058; config_base = 0x98; break;
1532 default:
1533 /* Unknown number of ports, get out of here */
1534 return -EINVAL;
1535 }
1536
1537 if (idx < 4) {
1538 base = pci_resource_start(priv->dev, 3);
1539 ciobase = (int)(base + (0x8 * idx));
1540 }
1541
1542 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1543 __func__, idx, iobase, ciobase, config_base);
1544
1545 /* Enable UART I/O port */
1546 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1547
1548 /* Select 128-byte FIFO and 8x FIFO threshold */
1549 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1550
1551 /* LSB UART */
1552 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1553
1554 /* MSB UART */
1555 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1556
1557 /* irq number, this usually fails, but the spec says to do it anyway. */
1558 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1559
1560 port->port.iotype = UPIO_PORT;
1561 port->port.iobase = iobase;
1562 port->port.mapbase = 0;
1563 port->port.membase = NULL;
1564 port->port.regshift = 0;
1565
1566 return 0;
1567}
1568
b6adea33
MCC		 1569static int skip_tx_en_setup(struct serial_private *priv,
1570 const struct pciserial_board *board,
2655a2c7 1571 struct uart_8250_port *port, int idx)
b6adea33 1572{
2655a2c7 1573 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1574 dev_dbg(&priv->dev->dev,
1575 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1576 priv->dev->vendor, priv->dev->device,
1577 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1578
1579 return pci_default_setup(priv, board, port, idx);
1580}
1581
0ad372b9
SM		 1582static void kt_handle_break(struct uart_port *p)
1583{
1584 struct uart_8250_port *up =
1585 container_of(p, struct uart_8250_port, port);
1586 /*
1587 * On receipt of a BI, serial device in Intel ME (Intel
1588 * management engine) needs to have its fifos cleared for sane
1589 * SOL (Serial Over Lan) output.
1590 */
1591 serial8250_clear_and_reinit_fifos(up);
1592}
1593
1594static unsigned int kt_serial_in(struct uart_port *p, int offset)
1595{
1596 struct uart_8250_port *up =
1597 container_of(p, struct uart_8250_port, port);
1598 unsigned int val;
1599
1600 /*
1601 * When the Intel ME (management engine) gets reset its serial
1602 * port registers could return 0 momentarily. Functions like
1603 * serial8250_console_write, read and save the IER, perform
1604 * some operation and then restore it. In order to avoid
1605 * setting IER register inadvertently to 0, if the value read
1606 * is 0, double check with ier value in uart_8250_port and use
1607 * that instead. up->ier should be the same value as what is
1608 * currently configured.
1609 */
1610 val = inb(p->iobase + offset);
1611 if (offset == UART_IER) {
1612 if (val == 0)
1613 val = up->ier;
1614 }
1615 return val;
1616}
1617
bc02d15a
DW		 1618static int kt_serial_setup(struct serial_private *priv,
1619 const struct pciserial_board *board,
2655a2c7 1620 struct uart_8250_port *port, int idx)
bc02d15a 1621{
2655a2c7
AC		 1622 port->port.flags |= UPF_BUG_THRE;
1623 port->port.serial_in = kt_serial_in;
1624 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1625 return skip_tx_en_setup(priv, board, port, idx);
1626}
1627
eb7073db
TM		 1628static int pci_eg20t_init(struct pci_dev *dev)
1629{
1630#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1631 return -ENODEV;
1632#else
1633 return 0;
1634#endif
1635}
1636
06315348
SH		 1637static int
1638pci_xr17c154_setup(struct serial_private *priv,
1639 const struct pciserial_board *board,
2655a2c7 1640 struct uart_8250_port *port, int idx)
06315348 1641{
2655a2c7 1642 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1643 return pci_default_setup(priv, board, port, idx);
1644}
1645
dc96efb7
MS		 1646static int
1647pci_xr17v35x_setup(struct serial_private *priv,
1648 const struct pciserial_board *board,
1649 struct uart_8250_port *port, int idx)
1650{
1651 u8 __iomem *p;
1652
1653 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1654 if (p == NULL)
1655 return -ENOMEM;
dc96efb7
MS		 1656
1657 port->port.flags |= UPF_EXAR_EFR;
1658
1659 /*
1660 * Setup Multipurpose Input/Output pins.
1661 */
1662 if (idx == 0) {
1663 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1664 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1665 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1666 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1667 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1668 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1669 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1670 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1671 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1672 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1673 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1674 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1675 }
f965b9c4
MS		 1676 writeb(0x00, p + UART_EXAR_8XMODE);
1677 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1678 writeb(128, p + UART_EXAR_TXTRG);
1679 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1680 iounmap(p);
1681
1682 return pci_default_setup(priv, board, port, idx);
1683}
1684
14faa8cc
MS		 1685#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1686#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1687#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1688#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1689
1690static int
1691pci_fastcom335_setup(struct serial_private *priv,
1692 const struct pciserial_board *board,
1693 struct uart_8250_port *port, int idx)
1694{
1695 u8 __iomem *p;
1696
1697 p = pci_ioremap_bar(priv->dev, 0);
1698 if (p == NULL)
1699 return -ENOMEM;
1700
1701 port->port.flags |= UPF_EXAR_EFR;
1702
1703 /*
1704 * Setup Multipurpose Input/Output pins.
1705 */
1706 if (idx == 0) {
1707 switch (priv->dev->device) {
1708 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1709 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1710 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1711 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1712 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1713 break;
1714 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1715 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1716 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1717 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1718 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1719 break;
1720 }
1721 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1722 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1723 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1724 }
1725 writeb(0x00, p + UART_EXAR_8XMODE);
1726 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1727 writeb(32, p + UART_EXAR_TXTRG);
1728 writeb(32, p + UART_EXAR_RXTRG);
1729 iounmap(p);
1730
1731 return pci_default_setup(priv, board, port, idx);
1732}
1733
6971c635
GA		 1734static int
1735pci_wch_ch353_setup(struct serial_private *priv,
1736 const struct pciserial_board *board,
1737 struct uart_8250_port *port, int idx)
1738{
1739 port->port.flags |= UPF_FIXED_TYPE;
1740 port->port.type = PORT_16550A;
06315348
SH		 1741 return pci_default_setup(priv, board, port, idx);
1742}
1743
1da177e4
LT		 1744#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1745#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1746#define PCI_DEVICE_ID_OCTPRO 0x0001
1747#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1748#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1749#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1750#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1751#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1752#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1753#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1754#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1755#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
0c6d774c
TW		 1756#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1757#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
66169ad1
YY		 1758#define PCI_DEVICE_ID_TITAN_200I 0x8028
1759#define PCI_DEVICE_ID_TITAN_400I 0x8048
1760#define PCI_DEVICE_ID_TITAN_800I 0x8088
1761#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1762#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1763#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1764#define PCI_DEVICE_ID_TITAN_100E 0xA010
1765#define PCI_DEVICE_ID_TITAN_200E 0xA012
1766#define PCI_DEVICE_ID_TITAN_400E 0xA013
1767#define PCI_DEVICE_ID_TITAN_800E 0xA014
1768#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1769#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 1770#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 1771#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1772#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1773#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1774#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1775#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1776#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1777#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1778#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1779#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1780#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1781#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1782#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
feb58142 1783#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
27788c5f 1784#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1785#define PCI_VENDOR_ID_AGESTAR 0x5372
1786#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1787#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1788#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1789#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1790#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1791#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 1792#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
14faa8cc 1793
abd7baca
SC		 1794#define PCI_VENDOR_ID_SUNIX 0x1fd4
1795#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1796
1da177e4 1797
b76c5a07
CB		 1798/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1799#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1800#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1801
1da177e4
LT		 1802/*
1803 * Master list of serial port init/setup/exit quirks.
1804 * This does not describe the general nature of the port.
1805 * (ie, baud base, number and location of ports, etc)
1806 *
1807 * This list is ordered alphabetically by vendor then device.
1808 * Specific entries must come before more generic entries.
1809 */
7a63ce5a 1810static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1811 /*
1812 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1813 */
1814 {
086231f7 1815 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 1816 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 1817 .subvendor = PCI_ANY_ID,
1818 .subdevice = PCI_ANY_ID,
1819 .setup = addidata_apci7800_setup,
1820 },
1da177e4 1821 /*
61a116ef 1822 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1823 * It is not clear whether this applies to all products.
1824 */
1825 {
1826 .vendor = PCI_VENDOR_ID_AFAVLAB,
1827 .device = PCI_ANY_ID,
1828 .subvendor = PCI_ANY_ID,
1829 .subdevice = PCI_ANY_ID,
1830 .setup = afavlab_setup,
1831 },
1832 /*
1833 * HP Diva
1834 */
1835 {
1836 .vendor = PCI_VENDOR_ID_HP,
1837 .device = PCI_DEVICE_ID_HP_DIVA,
1838 .subvendor = PCI_ANY_ID,
1839 .subdevice = PCI_ANY_ID,
1840 .init = pci_hp_diva_init,
1841 .setup = pci_hp_diva_setup,
1842 },
1843 /*
1844 * Intel
1845 */
1846 {
1847 .vendor = PCI_VENDOR_ID_INTEL,
1848 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1849 .subvendor = 0xe4bf,
1850 .subdevice = PCI_ANY_ID,
1851 .init = pci_inteli960ni_init,
1852 .setup = pci_default_setup,
1853 },
b6adea33
MCC		 1854 {
1855 .vendor = PCI_VENDOR_ID_INTEL,
1856 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1857 .subvendor = PCI_ANY_ID,
1858 .subdevice = PCI_ANY_ID,
1859 .setup = skip_tx_en_setup,
1860 },
1861 {
1862 .vendor = PCI_VENDOR_ID_INTEL,
1863 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1864 .subvendor = PCI_ANY_ID,
1865 .subdevice = PCI_ANY_ID,
1866 .setup = skip_tx_en_setup,
1867 },
1868 {
1869 .vendor = PCI_VENDOR_ID_INTEL,
1870 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1871 .subvendor = PCI_ANY_ID,
1872 .subdevice = PCI_ANY_ID,
1873 .setup = skip_tx_en_setup,
1874 },
095e24b0
DB		 1875 {
1876 .vendor = PCI_VENDOR_ID_INTEL,
1877 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1878 .subvendor = PCI_ANY_ID,
1879 .subdevice = PCI_ANY_ID,
1880 .setup = ce4100_serial_setup,
1881 },
bc02d15a
DW		 1882 {
1883 .vendor = PCI_VENDOR_ID_INTEL,
1884 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1885 .subvendor = PCI_ANY_ID,
1886 .subdevice = PCI_ANY_ID,
1887 .setup = kt_serial_setup,
1888 },
b15e5691
HK		 1889 {
1890 .vendor = PCI_VENDOR_ID_INTEL,
1891 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1892 .subvendor = PCI_ANY_ID,
1893 .subdevice = PCI_ANY_ID,
1894 .setup = byt_serial_setup,
1895 },
1896 {
1897 .vendor = PCI_VENDOR_ID_INTEL,
1898 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1899 .subvendor = PCI_ANY_ID,
1900 .subdevice = PCI_ANY_ID,
1901 .setup = byt_serial_setup,
1902 },
84f8c6fc
NV		 1903 /*
1904 * ITE
1905 */
1906 {
1907 .vendor = PCI_VENDOR_ID_ITE,
1908 .device = PCI_DEVICE_ID_ITE_8872,
1909 .subvendor = PCI_ANY_ID,
1910 .subdevice = PCI_ANY_ID,
1911 .init = pci_ite887x_init,
1912 .setup = pci_default_setup,
2d47b716 1913 .exit = pci_ite887x_exit,
84f8c6fc 1914 },
46a0fac9
SB		 1915 /*
1916 * National Instruments
1917 */
04bf7e74
WP		 1918 {
1919 .vendor = PCI_VENDOR_ID_NI,
1920 .device = PCI_DEVICE_ID_NI_PCI23216,
1921 .subvendor = PCI_ANY_ID,
1922 .subdevice = PCI_ANY_ID,
1923 .init = pci_ni8420_init,
1924 .setup = pci_default_setup,
2d47b716 1925 .exit = pci_ni8420_exit,
04bf7e74
WP		 1926 },
1927 {
1928 .vendor = PCI_VENDOR_ID_NI,
1929 .device = PCI_DEVICE_ID_NI_PCI2328,
1930 .subvendor = PCI_ANY_ID,
1931 .subdevice = PCI_ANY_ID,
1932 .init = pci_ni8420_init,
1933 .setup = pci_default_setup,
2d47b716 1934 .exit = pci_ni8420_exit,
04bf7e74
WP		 1935 },
1936 {
1937 .vendor = PCI_VENDOR_ID_NI,
1938 .device = PCI_DEVICE_ID_NI_PCI2324,
1939 .subvendor = PCI_ANY_ID,
1940 .subdevice = PCI_ANY_ID,
1941 .init = pci_ni8420_init,
1942 .setup = pci_default_setup,
2d47b716 1943 .exit = pci_ni8420_exit,
04bf7e74
WP		 1944 },
1945 {
1946 .vendor = PCI_VENDOR_ID_NI,
1947 .device = PCI_DEVICE_ID_NI_PCI2322,
1948 .subvendor = PCI_ANY_ID,
1949 .subdevice = PCI_ANY_ID,
1950 .init = pci_ni8420_init,
1951 .setup = pci_default_setup,
2d47b716 1952 .exit = pci_ni8420_exit,
04bf7e74
WP		 1953 },
1954 {
1955 .vendor = PCI_VENDOR_ID_NI,
1956 .device = PCI_DEVICE_ID_NI_PCI2324I,
1957 .subvendor = PCI_ANY_ID,
1958 .subdevice = PCI_ANY_ID,
1959 .init = pci_ni8420_init,
1960 .setup = pci_default_setup,
2d47b716 1961 .exit = pci_ni8420_exit,
04bf7e74
WP		 1962 },
1963 {
1964 .vendor = PCI_VENDOR_ID_NI,
1965 .device = PCI_DEVICE_ID_NI_PCI2322I,
1966 .subvendor = PCI_ANY_ID,
1967 .subdevice = PCI_ANY_ID,
1968 .init = pci_ni8420_init,
1969 .setup = pci_default_setup,
2d47b716 1970 .exit = pci_ni8420_exit,
04bf7e74
WP		 1971 },
1972 {
1973 .vendor = PCI_VENDOR_ID_NI,
1974 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1975 .subvendor = PCI_ANY_ID,
1976 .subdevice = PCI_ANY_ID,
1977 .init = pci_ni8420_init,
1978 .setup = pci_default_setup,
2d47b716 1979 .exit = pci_ni8420_exit,
04bf7e74
WP		 1980 },
1981 {
1982 .vendor = PCI_VENDOR_ID_NI,
1983 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1984 .subvendor = PCI_ANY_ID,
1985 .subdevice = PCI_ANY_ID,
1986 .init = pci_ni8420_init,
1987 .setup = pci_default_setup,
2d47b716 1988 .exit = pci_ni8420_exit,
04bf7e74
WP		 1989 },
1990 {
1991 .vendor = PCI_VENDOR_ID_NI,
1992 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1993 .subvendor = PCI_ANY_ID,
1994 .subdevice = PCI_ANY_ID,
1995 .init = pci_ni8420_init,
1996 .setup = pci_default_setup,
2d47b716 1997 .exit = pci_ni8420_exit,
04bf7e74
WP		 1998 },
1999 {
2000 .vendor = PCI_VENDOR_ID_NI,
2001 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2002 .subvendor = PCI_ANY_ID,
2003 .subdevice = PCI_ANY_ID,
2004 .init = pci_ni8420_init,
2005 .setup = pci_default_setup,
2d47b716 2006 .exit = pci_ni8420_exit,
04bf7e74
WP		 2007 },
2008 {
2009 .vendor = PCI_VENDOR_ID_NI,
2010 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2011 .subvendor = PCI_ANY_ID,
2012 .subdevice = PCI_ANY_ID,
2013 .init = pci_ni8420_init,
2014 .setup = pci_default_setup,
2d47b716 2015 .exit = pci_ni8420_exit,
04bf7e74
WP		 2016 },
2017 {
2018 .vendor = PCI_VENDOR_ID_NI,
2019 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2020 .subvendor = PCI_ANY_ID,
2021 .subdevice = PCI_ANY_ID,
2022 .init = pci_ni8420_init,
2023 .setup = pci_default_setup,
2d47b716 2024 .exit = pci_ni8420_exit,
04bf7e74 2025 },
46a0fac9
SB		 2026 {
2027 .vendor = PCI_VENDOR_ID_NI,
2028 .device = PCI_ANY_ID,
2029 .subvendor = PCI_ANY_ID,
2030 .subdevice = PCI_ANY_ID,
2031 .init = pci_ni8430_init,
2032 .setup = pci_ni8430_setup,
2d47b716 2033 .exit = pci_ni8430_exit,
46a0fac9 2034 },
55c7c0fd
AC		 2035 /* Quatech */
2036 {
2037 .vendor = PCI_VENDOR_ID_QUATECH,
2038 .device = PCI_ANY_ID,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .init = pci_quatech_init,
2042 .setup = pci_quatech_setup,
d73dfc6a 2043 .exit = pci_quatech_exit,
55c7c0fd 2044 },
1da177e4
LT		 2045 /*
2046 * Panacom
2047 */
2048 {
2049 .vendor = PCI_VENDOR_ID_PANACOM,
2050 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2051 .subvendor = PCI_ANY_ID,
2052 .subdevice = PCI_ANY_ID,
2053 .init = pci_plx9050_init,
2054 .setup = pci_default_setup,
2d47b716 2055 .exit = pci_plx9050_exit,
5756ee99 2056 },
1da177e4
LT		 2057 {
2058 .vendor = PCI_VENDOR_ID_PANACOM,
2059 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2060 .subvendor = PCI_ANY_ID,
2061 .subdevice = PCI_ANY_ID,
2062 .init = pci_plx9050_init,
2063 .setup = pci_default_setup,
2d47b716 2064 .exit = pci_plx9050_exit,
1da177e4 2065 },
94341475
AB		 2066 /*
2067 * Pericom
2068 */
2069 {
2070 .vendor = 0x12d8,
2071 .device = 0x7952,
2072 .subvendor = PCI_ANY_ID,
2073 .subdevice = PCI_ANY_ID,
2074 .setup = pci_pericom_setup,
2075 },
2076 {
2077 .vendor = 0x12d8,
2078 .device = 0x7954,
2079 .subvendor = PCI_ANY_ID,
2080 .subdevice = PCI_ANY_ID,
2081 .setup = pci_pericom_setup,
2082 },
2083 {
2084 .vendor = 0x12d8,
2085 .device = 0x7958,
2086 .subvendor = PCI_ANY_ID,
2087 .subdevice = PCI_ANY_ID,
2088 .setup = pci_pericom_setup,
2089 },
2090
1da177e4
LT		 2091 /*
2092 * PLX
2093 */
48212008
TH		 2094 {
2095 .vendor = PCI_VENDOR_ID_PLX,
2096 .device = PCI_DEVICE_ID_PLX_9030,
2097 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2098 .subdevice = PCI_ANY_ID,
2099 .setup = pci_default_setup,
2100 },
add7b58e
BH		 2101 {
2102 .vendor = PCI_VENDOR_ID_PLX,
2103 .device = PCI_DEVICE_ID_PLX_9050,
2104 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2105 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2106 .init = pci_plx9050_init,
2107 .setup = pci_default_setup,
2d47b716 2108 .exit = pci_plx9050_exit,
add7b58e 2109 },
1da177e4
LT		 2110 {
2111 .vendor = PCI_VENDOR_ID_PLX,
2112 .device = PCI_DEVICE_ID_PLX_9050,
2113 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2114 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2115 .init = pci_plx9050_init,
2116 .setup = pci_default_setup,
2d47b716 2117 .exit = pci_plx9050_exit,
1da177e4
LT		 2118 },
2119 {
2120 .vendor = PCI_VENDOR_ID_PLX,
2121 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2122 .subvendor = PCI_VENDOR_ID_PLX,
2123 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2124 .init = pci_plx9050_init,
2125 .setup = pci_default_setup,
2d47b716 2126 .exit = pci_plx9050_exit,
1da177e4
LT		 2127 },
2128 /*
2129 * SBS Technologies, Inc., PMC-OCTALPRO 232
2130 */
2131 {
2132 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2133 .device = PCI_DEVICE_ID_OCTPRO,
2134 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2135 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2136 .init = sbs_init,
2137 .setup = sbs_setup,
2d47b716 2138 .exit = sbs_exit,
1da177e4
LT		 2139 },
2140 /*
2141 * SBS Technologies, Inc., PMC-OCTALPRO 422
2142 */
2143 {
2144 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2145 .device = PCI_DEVICE_ID_OCTPRO,
2146 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2147 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2148 .init = sbs_init,
2149 .setup = sbs_setup,
2d47b716 2150 .exit = sbs_exit,
1da177e4
LT		 2151 },
2152 /*
2153 * SBS Technologies, Inc., P-Octal 232
2154 */
2155 {
2156 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2157 .device = PCI_DEVICE_ID_OCTPRO,
2158 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2159 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2160 .init = sbs_init,
2161 .setup = sbs_setup,
2d47b716 2162 .exit = sbs_exit,
1da177e4
LT		 2163 },
2164 /*
2165 * SBS Technologies, Inc., P-Octal 422
2166 */
2167 {
2168 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2169 .device = PCI_DEVICE_ID_OCTPRO,
2170 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2171 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2172 .init = sbs_init,
2173 .setup = sbs_setup,
2d47b716 2174 .exit = sbs_exit,
1da177e4 2175 },
1da177e4 2176 /*
61a116ef 2177 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2178 */
2179 {
2180 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2181 .device = PCI_ANY_ID,
1da177e4
LT		 2182 .subvendor = PCI_ANY_ID,
2183 .subdevice = PCI_ANY_ID,
67d74b87 2184 .init = pci_siig_init,
3ec9c594 2185 .setup = pci_siig_setup,
1da177e4
LT		 2186 },
2187 /*
2188 * Titan cards
2189 */
2190 {
2191 .vendor = PCI_VENDOR_ID_TITAN,
2192 .device = PCI_DEVICE_ID_TITAN_400L,
2193 .subvendor = PCI_ANY_ID,
2194 .subdevice = PCI_ANY_ID,
2195 .setup = titan_400l_800l_setup,
2196 },
2197 {
2198 .vendor = PCI_VENDOR_ID_TITAN,
2199 .device = PCI_DEVICE_ID_TITAN_800L,
2200 .subvendor = PCI_ANY_ID,
2201 .subdevice = PCI_ANY_ID,
2202 .setup = titan_400l_800l_setup,
2203 },
2204 /*
2205 * Timedia cards
2206 */
2207 {
2208 .vendor = PCI_VENDOR_ID_TIMEDIA,
2209 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2210 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2211 .subdevice = PCI_ANY_ID,
b9b24558 2212 .probe = pci_timedia_probe,
1da177e4
LT		 2213 .init = pci_timedia_init,
2214 .setup = pci_timedia_setup,
2215 },
2216 {
2217 .vendor = PCI_VENDOR_ID_TIMEDIA,
2218 .device = PCI_ANY_ID,
2219 .subvendor = PCI_ANY_ID,
2220 .subdevice = PCI_ANY_ID,
2221 .setup = pci_timedia_setup,
2222 },
abd7baca
SC		 2223 /*
2224 * SUNIX (Timedia) cards
2225 * Do not "probe" for these cards as there is at least one combination
2226 * card that should be handled by parport_pc that doesn't match the
2227 * rule in pci_timedia_probe.
2228 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2229 * There are some boards with part number SER5037AL that report
2230 * subdevice ID 0x0002.
2231 */
2232 {
2233 .vendor = PCI_VENDOR_ID_SUNIX,
2234 .device = PCI_DEVICE_ID_SUNIX_1999,
2235 .subvendor = PCI_VENDOR_ID_SUNIX,
2236 .subdevice = PCI_ANY_ID,
2237 .init = pci_timedia_init,
2238 .setup = pci_timedia_setup,
2239 },
06315348
SH		 2240 /*
2241 * Exar cards
2242 */
2243 {
2244 .vendor = PCI_VENDOR_ID_EXAR,
2245 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .setup = pci_xr17c154_setup,
2249 },
2250 {
2251 .vendor = PCI_VENDOR_ID_EXAR,
2252 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .setup = pci_xr17c154_setup,
2256 },
2257 {
2258 .vendor = PCI_VENDOR_ID_EXAR,
2259 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2260 .subvendor = PCI_ANY_ID,
2261 .subdevice = PCI_ANY_ID,
2262 .setup = pci_xr17c154_setup,
2263 },
dc96efb7
MS		 2264 {
2265 .vendor = PCI_VENDOR_ID_EXAR,
2266 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2267 .subvendor = PCI_ANY_ID,
2268 .subdevice = PCI_ANY_ID,
2269 .setup = pci_xr17v35x_setup,
2270 },
2271 {
2272 .vendor = PCI_VENDOR_ID_EXAR,
2273 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2274 .subvendor = PCI_ANY_ID,
2275 .subdevice = PCI_ANY_ID,
2276 .setup = pci_xr17v35x_setup,
2277 },
2278 {
2279 .vendor = PCI_VENDOR_ID_EXAR,
2280 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2281 .subvendor = PCI_ANY_ID,
2282 .subdevice = PCI_ANY_ID,
2283 .setup = pci_xr17v35x_setup,
2284 },
1da177e4
LT		 2285 /*
2286 * Xircom cards
2287 */
2288 {
2289 .vendor = PCI_VENDOR_ID_XIRCOM,
2290 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .init = pci_xircom_init,
2294 .setup = pci_default_setup,
2295 },
2296 /*
61a116ef 2297 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2298 */
2299 {
2300 .vendor = PCI_VENDOR_ID_NETMOS,
2301 .device = PCI_ANY_ID,
2302 .subvendor = PCI_ANY_ID,
2303 .subdevice = PCI_ANY_ID,
2304 .init = pci_netmos_init,
7808edcd 2305 .setup = pci_netmos_9900_setup,
1da177e4 2306 },
9f2a036a 2307 /*
aa273ae5 2308 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2309 */
2310 {
2311 .vendor = PCI_VENDOR_ID_OXSEMI,
2312 .device = PCI_ANY_ID,
2313 .subvendor = PCI_ANY_ID,
2314 .subdevice = PCI_ANY_ID,
2315 .init = pci_oxsemi_tornado_init,
2316 .setup = pci_default_setup,
2317 },
2318 {
2319 .vendor = PCI_VENDOR_ID_MAINPINE,
2320 .device = PCI_ANY_ID,
2321 .subvendor = PCI_ANY_ID,
2322 .subdevice = PCI_ANY_ID,
2323 .init = pci_oxsemi_tornado_init,
2324 .setup = pci_default_setup,
2325 },
aa273ae5
SK		 2326 {
2327 .vendor = PCI_VENDOR_ID_DIGI,
2328 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2329 .subvendor = PCI_SUBVENDOR_ID_IBM,
2330 .subdevice = PCI_ANY_ID,
2331 .init = pci_oxsemi_tornado_init,
2332 .setup = pci_default_setup,
2333 },
eb7073db
TM		 2334 {
2335 .vendor = PCI_VENDOR_ID_INTEL,
2336 .device = 0x8811,
aaa10eb1
AP		 2337 .subvendor = PCI_ANY_ID,
2338 .subdevice = PCI_ANY_ID,
eb7073db 2339 .init = pci_eg20t_init,
64d91cfa 2340 .setup = pci_default_setup,
eb7073db
TM		 2341 },
2342 {
2343 .vendor = PCI_VENDOR_ID_INTEL,
2344 .device = 0x8812,
aaa10eb1
AP		 2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
eb7073db 2347 .init = pci_eg20t_init,
64d91cfa 2348 .setup = pci_default_setup,
eb7073db
TM		 2349 },
2350 {
2351 .vendor = PCI_VENDOR_ID_INTEL,
2352 .device = 0x8813,
aaa10eb1
AP		 2353 .subvendor = PCI_ANY_ID,
2354 .subdevice = PCI_ANY_ID,
eb7073db 2355 .init = pci_eg20t_init,
64d91cfa 2356 .setup = pci_default_setup,
eb7073db
TM		 2357 },
2358 {
2359 .vendor = PCI_VENDOR_ID_INTEL,
2360 .device = 0x8814,
aaa10eb1
AP		 2361 .subvendor = PCI_ANY_ID,
2362 .subdevice = PCI_ANY_ID,
eb7073db 2363 .init = pci_eg20t_init,
64d91cfa 2364 .setup = pci_default_setup,
eb7073db
TM		 2365 },
2366 {
2367 .vendor = 0x10DB,
2368 .device = 0x8027,
aaa10eb1
AP		 2369 .subvendor = PCI_ANY_ID,
2370 .subdevice = PCI_ANY_ID,
eb7073db 2371 .init = pci_eg20t_init,
64d91cfa 2372 .setup = pci_default_setup,
eb7073db
TM		 2373 },
2374 {
2375 .vendor = 0x10DB,
2376 .device = 0x8028,
aaa10eb1
AP		 2377 .subvendor = PCI_ANY_ID,
2378 .subdevice = PCI_ANY_ID,
eb7073db 2379 .init = pci_eg20t_init,
64d91cfa 2380 .setup = pci_default_setup,
eb7073db
TM		 2381 },
2382 {
2383 .vendor = 0x10DB,
2384 .device = 0x8029,
aaa10eb1
AP		 2385 .subvendor = PCI_ANY_ID,
2386 .subdevice = PCI_ANY_ID,
eb7073db 2387 .init = pci_eg20t_init,
64d91cfa 2388 .setup = pci_default_setup,
eb7073db
TM		 2389 },
2390 {
2391 .vendor = 0x10DB,
2392 .device = 0x800C,
aaa10eb1
AP		 2393 .subvendor = PCI_ANY_ID,
2394 .subdevice = PCI_ANY_ID,
eb7073db 2395 .init = pci_eg20t_init,
64d91cfa 2396 .setup = pci_default_setup,
eb7073db
TM		 2397 },
2398 {
2399 .vendor = 0x10DB,
2400 .device = 0x800D,
aaa10eb1
AP		 2401 .subvendor = PCI_ANY_ID,
2402 .subdevice = PCI_ANY_ID,
eb7073db 2403 .init = pci_eg20t_init,
64d91cfa 2404 .setup = pci_default_setup,
eb7073db 2405 },
d9a0fbfd
AP		 2406 /*
2407 * Cronyx Omega PCI (PLX-chip based)
2408 */
2409 {
2410 .vendor = PCI_VENDOR_ID_PLX,
2411 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2412 .subvendor = PCI_ANY_ID,
2413 .subdevice = PCI_ANY_ID,
2414 .setup = pci_omegapci_setup,
eb26dfe8 2415 },
feb58142
EG		 2416 /* WCH CH353 1S1P card (16550 clone) */
2417 {
2418 .vendor = PCI_VENDOR_ID_WCH,
2419 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
2422 .setup = pci_wch_ch353_setup,
2423 },
6971c635
GA		 2424 /* WCH CH353 2S1P card (16550 clone) */
2425 {
27788c5f
AC		 2426 .vendor = PCI_VENDOR_ID_WCH,
2427 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
2430 .setup = pci_wch_ch353_setup,
2431 },
2432 /* WCH CH353 4S card (16550 clone) */
2433 {
2434 .vendor = PCI_VENDOR_ID_WCH,
2435 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2436 .subvendor = PCI_ANY_ID,
2437 .subdevice = PCI_ANY_ID,
2438 .setup = pci_wch_ch353_setup,
2439 },
2440 /* WCH CH353 2S1PF card (16550 clone) */
2441 {
2442 .vendor = PCI_VENDOR_ID_WCH,
2443 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2444 .subvendor = PCI_ANY_ID,
2445 .subdevice = PCI_ANY_ID,
6971c635
GA		 2446 .setup = pci_wch_ch353_setup,
2447 },
8b5c913f
WY		 2448 /* WCH CH352 2S card (16550 clone) */
2449 {
2450 .vendor = PCI_VENDOR_ID_WCH,
2451 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2452 .subvendor = PCI_ANY_ID,
2453 .subdevice = PCI_ANY_ID,
2454 .setup = pci_wch_ch353_setup,
2455 },
eb26dfe8
AC		 2456 /*
2457 * ASIX devices with FIFO bug
2458 */
2459 {
2460 .vendor = PCI_VENDOR_ID_ASIX,
2461 .device = PCI_ANY_ID,
2462 .subvendor = PCI_ANY_ID,
2463 .subdevice = PCI_ANY_ID,
2464 .setup = pci_asix_setup,
2465 },
14faa8cc
MS		 2466 /*
2467 * Commtech, Inc. Fastcom adapters
2468 *
2469 */
2470 {
2471 .vendor = PCI_VENDOR_ID_COMMTECH,
2472 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2473 .subvendor = PCI_ANY_ID,
2474 .subdevice = PCI_ANY_ID,
2475 .setup = pci_fastcom335_setup,
2476 },
2477 {
2478 .vendor = PCI_VENDOR_ID_COMMTECH,
2479 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2480 .subvendor = PCI_ANY_ID,
2481 .subdevice = PCI_ANY_ID,
2482 .setup = pci_fastcom335_setup,
2483 },
2484 {
2485 .vendor = PCI_VENDOR_ID_COMMTECH,
2486 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2487 .subvendor = PCI_ANY_ID,
2488 .subdevice = PCI_ANY_ID,
2489 .setup = pci_fastcom335_setup,
2490 },
2491 {
2492 .vendor = PCI_VENDOR_ID_COMMTECH,
2493 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2494 .subvendor = PCI_ANY_ID,
2495 .subdevice = PCI_ANY_ID,
2496 .setup = pci_fastcom335_setup,
2497 },
2498 {
2499 .vendor = PCI_VENDOR_ID_COMMTECH,
2500 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2501 .subvendor = PCI_ANY_ID,
2502 .subdevice = PCI_ANY_ID,
2503 .setup = pci_xr17v35x_setup,
2504 },
2505 {
2506 .vendor = PCI_VENDOR_ID_COMMTECH,
2507 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2508 .subvendor = PCI_ANY_ID,
2509 .subdevice = PCI_ANY_ID,
2510 .setup = pci_xr17v35x_setup,
2511 },
2512 {
2513 .vendor = PCI_VENDOR_ID_COMMTECH,
2514 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2515 .subvendor = PCI_ANY_ID,
2516 .subdevice = PCI_ANY_ID,
2517 .setup = pci_xr17v35x_setup,
2518 },
ebebd49a
SH		 2519 /*
2520 * Broadcom TruManage (NetXtreme)
2521 */
2522 {
2523 .vendor = PCI_VENDOR_ID_BROADCOM,
2524 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2525 .subvendor = PCI_ANY_ID,
2526 .subdevice = PCI_ANY_ID,
2527 .setup = pci_brcm_trumanage_setup,
2528 },
2c62a3c8
GKH		 2529 {
2530 .vendor = 0x1c29,
2531 .device = 0x1104,
2532 .subvendor = PCI_ANY_ID,
2533 .subdevice = PCI_ANY_ID,
2534 .setup = pci_fintek_setup,
2535 },
2536 {
2537 .vendor = 0x1c29,
2538 .device = 0x1108,
2539 .subvendor = PCI_ANY_ID,
2540 .subdevice = PCI_ANY_ID,
2541 .setup = pci_fintek_setup,
2542 },
2543 {
2544 .vendor = 0x1c29,
2545 .device = 0x1112,
2546 .subvendor = PCI_ANY_ID,
2547 .subdevice = PCI_ANY_ID,
2548 .setup = pci_fintek_setup,
2549 },
ebebd49a 2550
1da177e4
LT		 2551 /*
2552 * Default "match everything" terminator entry
2553 */
2554 {
2555 .vendor = PCI_ANY_ID,
2556 .device = PCI_ANY_ID,
2557 .subvendor = PCI_ANY_ID,
2558 .subdevice = PCI_ANY_ID,
2559 .setup = pci_default_setup,
2560 }
2561};
2562
2563static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2564{
2565 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2566}
2567
2568static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2569{
2570 struct pci_serial_quirk *quirk;
2571
2572 for (quirk = pci_serial_quirks; ; quirk++)
2573 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2574 quirk_id_matches(quirk->device, dev->device) &&
2575 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2576 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2577 break;
1da177e4
LT		 2578 return quirk;
2579}
2580
dd68e88c 2581static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2582 const struct pciserial_board *board)
1da177e4
LT		 2583{
2584 if (board->flags & FL_NOIRQ)
2585 return 0;
2586 else
2587 return dev->irq;
2588}
2589
2590/*
2591 * This is the configuration table for all of the PCI serial boards
2592 * which we support. It is directly indexed by the pci_board_num_t enum
2593 * value, which is encoded in the pci_device_id PCI probe table's
2594 * driver_data member.
2595 *
2596 * The makeup of these names are:
26e92861 2597 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2598 *
26e92861
GH		 2599 * bn = PCI BAR number
2600 * bt = Index using PCI BARs
2601 * n = number of serial ports
2602 * baud = baud rate
2603 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2604 *
26e92861 2605 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2606 *
1da177e4
LT		 2607 * Please note: in theory if n = 1, _bt infix should make no difference.
2608 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2609 */
2610enum pci_board_num_t {
2611 pbn_default = 0,
2612
2613 pbn_b0_1_115200,
2614 pbn_b0_2_115200,
2615 pbn_b0_4_115200,
2616 pbn_b0_5_115200,
bf0df636 2617 pbn_b0_8_115200,
1da177e4
LT		 2618
2619 pbn_b0_1_921600,
2620 pbn_b0_2_921600,
2621 pbn_b0_4_921600,
2622
db1de159
DR		 2623 pbn_b0_2_1130000,
2624
fbc0dc0d
AP		 2625 pbn_b0_4_1152000,
2626
14faa8cc
MS		 2627 pbn_b0_2_1152000_200,
2628 pbn_b0_4_1152000_200,
2629 pbn_b0_8_1152000_200,
2630
26e92861
GH		 2631 pbn_b0_2_1843200,
2632 pbn_b0_4_1843200,
2633
2634 pbn_b0_2_1843200_200,
2635 pbn_b0_4_1843200_200,
2636 pbn_b0_8_1843200_200,
2637
7106b4e3
LH		 2638 pbn_b0_1_4000000,
2639
1da177e4
LT		 2640 pbn_b0_bt_1_115200,
2641 pbn_b0_bt_2_115200,
ac6ec5b1 2642 pbn_b0_bt_4_115200,
1da177e4
LT		 2643 pbn_b0_bt_8_115200,
2644
2645 pbn_b0_bt_1_460800,
2646 pbn_b0_bt_2_460800,
2647 pbn_b0_bt_4_460800,
2648
2649 pbn_b0_bt_1_921600,
2650 pbn_b0_bt_2_921600,
2651 pbn_b0_bt_4_921600,
2652 pbn_b0_bt_8_921600,
2653
2654 pbn_b1_1_115200,
2655 pbn_b1_2_115200,
2656 pbn_b1_4_115200,
2657 pbn_b1_8_115200,
04bf7e74 2658 pbn_b1_16_115200,
1da177e4
LT		 2659
2660 pbn_b1_1_921600,
2661 pbn_b1_2_921600,
2662 pbn_b1_4_921600,
2663 pbn_b1_8_921600,
2664
26e92861
GH		 2665 pbn_b1_2_1250000,
2666
84f8c6fc 2667 pbn_b1_bt_1_115200,
04bf7e74
WP		 2668 pbn_b1_bt_2_115200,
2669 pbn_b1_bt_4_115200,
2670
1da177e4
LT		 2671 pbn_b1_bt_2_921600,
2672
2673 pbn_b1_1_1382400,
2674 pbn_b1_2_1382400,
2675 pbn_b1_4_1382400,
2676 pbn_b1_8_1382400,
2677
2678 pbn_b2_1_115200,
737c1756 2679 pbn_b2_2_115200,
a9cccd34 2680 pbn_b2_4_115200,
1da177e4
LT		 2681 pbn_b2_8_115200,
2682
2683 pbn_b2_1_460800,
2684 pbn_b2_4_460800,
2685 pbn_b2_8_460800,
2686 pbn_b2_16_460800,
2687
2688 pbn_b2_1_921600,
2689 pbn_b2_4_921600,
2690 pbn_b2_8_921600,
2691
e847003f
LB		 2692 pbn_b2_8_1152000,
2693
1da177e4
LT		 2694 pbn_b2_bt_1_115200,
2695 pbn_b2_bt_2_115200,
2696 pbn_b2_bt_4_115200,
2697
2698 pbn_b2_bt_2_921600,
2699 pbn_b2_bt_4_921600,
2700
d9004eb4 2701 pbn_b3_2_115200,
1da177e4
LT		 2702 pbn_b3_4_115200,
2703 pbn_b3_8_115200,
2704
66169ad1
YY		 2705 pbn_b4_bt_2_921600,
2706 pbn_b4_bt_4_921600,
2707 pbn_b4_bt_8_921600,
2708
1da177e4
LT		 2709 /*
2710 * Board-specific versions.
2711 */
2712 pbn_panacom,
2713 pbn_panacom2,
2714 pbn_panacom4,
2715 pbn_plx_romulus,
2716 pbn_oxsemi,
7106b4e3
LH		 2717 pbn_oxsemi_1_4000000,
2718 pbn_oxsemi_2_4000000,
2719 pbn_oxsemi_4_4000000,
2720 pbn_oxsemi_8_4000000,
1da177e4
LT		 2721 pbn_intel_i960,
2722 pbn_sgi_ioc3,
1da177e4
LT		 2723 pbn_computone_4,
2724 pbn_computone_6,
2725 pbn_computone_8,
2726 pbn_sbsxrsio,
2727 pbn_exar_XR17C152,
2728 pbn_exar_XR17C154,
2729 pbn_exar_XR17C158,
dc96efb7
MS		 2730 pbn_exar_XR17V352,
2731 pbn_exar_XR17V354,
2732 pbn_exar_XR17V358,
c68d2b15 2733 pbn_exar_ibm_saturn,
aa798505 2734 pbn_pasemi_1682M,
46a0fac9
SB		 2735 pbn_ni8430_2,
2736 pbn_ni8430_4,
2737 pbn_ni8430_8,
2738 pbn_ni8430_16,
1b62cbf2
KJ		 2739 pbn_ADDIDATA_PCIe_1_3906250,
2740 pbn_ADDIDATA_PCIe_2_3906250,
2741 pbn_ADDIDATA_PCIe_4_3906250,
2742 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2743 pbn_ce4100_1_115200,
b15e5691 2744 pbn_byt,
d9a0fbfd 2745 pbn_omegapci,
7808edcd 2746 pbn_NETMOS9900_2s_115200,
ebebd49a 2747 pbn_brcm_trumanage,
2c62a3c8
GKH		 2748 pbn_fintek_4,
2749 pbn_fintek_8,
2750 pbn_fintek_12,
1da177e4
LT		 2751};
2752
2753/*
2754 * uart_offset - the space between channels
2755 * reg_shift - describes how the UART registers are mapped
2756 * to PCI memory by the card.
2757 * For example IER register on SBS, Inc. PMC-OctPro is located at
2758 * offset 0x10 from the UART base, while UART_IER is defined as 1
2759 * in include/linux/serial_reg.h,
2760 * see first lines of serial_in() and serial_out() in 8250.c
2761*/
2762
de88b340 2763static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2764 [pbn_default] = {
2765 .flags = FL_BASE0,
2766 .num_ports = 1,
2767 .base_baud = 115200,
2768 .uart_offset = 8,
2769 },
2770 [pbn_b0_1_115200] = {
2771 .flags = FL_BASE0,
2772 .num_ports = 1,
2773 .base_baud = 115200,
2774 .uart_offset = 8,
2775 },
2776 [pbn_b0_2_115200] = {
2777 .flags = FL_BASE0,
2778 .num_ports = 2,
2779 .base_baud = 115200,
2780 .uart_offset = 8,
2781 },
2782 [pbn_b0_4_115200] = {
2783 .flags = FL_BASE0,
2784 .num_ports = 4,
2785 .base_baud = 115200,
2786 .uart_offset = 8,
2787 },
2788 [pbn_b0_5_115200] = {
2789 .flags = FL_BASE0,
2790 .num_ports = 5,
2791 .base_baud = 115200,
2792 .uart_offset = 8,
2793 },
bf0df636
AC		 2794 [pbn_b0_8_115200] = {
2795 .flags = FL_BASE0,
2796 .num_ports = 8,
2797 .base_baud = 115200,
2798 .uart_offset = 8,
2799 },
1da177e4
LT		 2800 [pbn_b0_1_921600] = {
2801 .flags = FL_BASE0,
2802 .num_ports = 1,
2803 .base_baud = 921600,
2804 .uart_offset = 8,
2805 },
2806 [pbn_b0_2_921600] = {
2807 .flags = FL_BASE0,
2808 .num_ports = 2,
2809 .base_baud = 921600,
2810 .uart_offset = 8,
2811 },
2812 [pbn_b0_4_921600] = {
2813 .flags = FL_BASE0,
2814 .num_ports = 4,
2815 .base_baud = 921600,
2816 .uart_offset = 8,
2817 },
db1de159
DR		 2818
2819 [pbn_b0_2_1130000] = {
2820 .flags = FL_BASE0,
2821 .num_ports = 2,
2822 .base_baud = 1130000,
2823 .uart_offset = 8,
2824 },
2825
fbc0dc0d
AP		 2826 [pbn_b0_4_1152000] = {
2827 .flags = FL_BASE0,
2828 .num_ports = 4,
2829 .base_baud = 1152000,
2830 .uart_offset = 8,
2831 },
1da177e4 2832
14faa8cc
MS		 2833 [pbn_b0_2_1152000_200] = {
2834 .flags = FL_BASE0,
2835 .num_ports = 2,
2836 .base_baud = 1152000,
2837 .uart_offset = 0x200,
2838 },
2839
2840 [pbn_b0_4_1152000_200] = {
2841 .flags = FL_BASE0,
2842 .num_ports = 4,
2843 .base_baud = 1152000,
2844 .uart_offset = 0x200,
2845 },
2846
2847 [pbn_b0_8_1152000_200] = {
2848 .flags = FL_BASE0,
4f7d67d0 2849 .num_ports = 8,
14faa8cc
MS		 2850 .base_baud = 1152000,
2851 .uart_offset = 0x200,
2852 },
2853
26e92861
GH		 2854 [pbn_b0_2_1843200] = {
2855 .flags = FL_BASE0,
2856 .num_ports = 2,
2857 .base_baud = 1843200,
2858 .uart_offset = 8,
2859 },
2860 [pbn_b0_4_1843200] = {
2861 .flags = FL_BASE0,
2862 .num_ports = 4,
2863 .base_baud = 1843200,
2864 .uart_offset = 8,
2865 },
2866
2867 [pbn_b0_2_1843200_200] = {
2868 .flags = FL_BASE0,
2869 .num_ports = 2,
2870 .base_baud = 1843200,
2871 .uart_offset = 0x200,
2872 },
2873 [pbn_b0_4_1843200_200] = {
2874 .flags = FL_BASE0,
2875 .num_ports = 4,
2876 .base_baud = 1843200,
2877 .uart_offset = 0x200,
2878 },
2879 [pbn_b0_8_1843200_200] = {
2880 .flags = FL_BASE0,
2881 .num_ports = 8,
2882 .base_baud = 1843200,
2883 .uart_offset = 0x200,
2884 },
7106b4e3
LH		 2885 [pbn_b0_1_4000000] = {
2886 .flags = FL_BASE0,
2887 .num_ports = 1,
2888 .base_baud = 4000000,
2889 .uart_offset = 8,
2890 },
26e92861 2891
1da177e4
LT		 2892 [pbn_b0_bt_1_115200] = {
2893 .flags = FL_BASE0|FL_BASE_BARS,
2894 .num_ports = 1,
2895 .base_baud = 115200,
2896 .uart_offset = 8,
2897 },
2898 [pbn_b0_bt_2_115200] = {
2899 .flags = FL_BASE0|FL_BASE_BARS,
2900 .num_ports = 2,
2901 .base_baud = 115200,
2902 .uart_offset = 8,
2903 },
ac6ec5b1
IS		 2904 [pbn_b0_bt_4_115200] = {
2905 .flags = FL_BASE0|FL_BASE_BARS,
2906 .num_ports = 4,
2907 .base_baud = 115200,
2908 .uart_offset = 8,
2909 },
1da177e4
LT		 2910 [pbn_b0_bt_8_115200] = {
2911 .flags = FL_BASE0|FL_BASE_BARS,
2912 .num_ports = 8,
2913 .base_baud = 115200,
2914 .uart_offset = 8,
2915 },
2916
2917 [pbn_b0_bt_1_460800] = {
2918 .flags = FL_BASE0|FL_BASE_BARS,
2919 .num_ports = 1,
2920 .base_baud = 460800,
2921 .uart_offset = 8,
2922 },
2923 [pbn_b0_bt_2_460800] = {
2924 .flags = FL_BASE0|FL_BASE_BARS,
2925 .num_ports = 2,
2926 .base_baud = 460800,
2927 .uart_offset = 8,
2928 },
2929 [pbn_b0_bt_4_460800] = {
2930 .flags = FL_BASE0|FL_BASE_BARS,
2931 .num_ports = 4,
2932 .base_baud = 460800,
2933 .uart_offset = 8,
2934 },
2935
2936 [pbn_b0_bt_1_921600] = {
2937 .flags = FL_BASE0|FL_BASE_BARS,
2938 .num_ports = 1,
2939 .base_baud = 921600,
2940 .uart_offset = 8,
2941 },
2942 [pbn_b0_bt_2_921600] = {
2943 .flags = FL_BASE0|FL_BASE_BARS,
2944 .num_ports = 2,
2945 .base_baud = 921600,
2946 .uart_offset = 8,
2947 },
2948 [pbn_b0_bt_4_921600] = {
2949 .flags = FL_BASE0|FL_BASE_BARS,
2950 .num_ports = 4,
2951 .base_baud = 921600,
2952 .uart_offset = 8,
2953 },
2954 [pbn_b0_bt_8_921600] = {
2955 .flags = FL_BASE0|FL_BASE_BARS,
2956 .num_ports = 8,
2957 .base_baud = 921600,
2958 .uart_offset = 8,
2959 },
2960
2961 [pbn_b1_1_115200] = {
2962 .flags = FL_BASE1,
2963 .num_ports = 1,
2964 .base_baud = 115200,
2965 .uart_offset = 8,
2966 },
2967 [pbn_b1_2_115200] = {
2968 .flags = FL_BASE1,
2969 .num_ports = 2,
2970 .base_baud = 115200,
2971 .uart_offset = 8,
2972 },
2973 [pbn_b1_4_115200] = {
2974 .flags = FL_BASE1,
2975 .num_ports = 4,
2976 .base_baud = 115200,
2977 .uart_offset = 8,
2978 },
2979 [pbn_b1_8_115200] = {
2980 .flags = FL_BASE1,
2981 .num_ports = 8,
2982 .base_baud = 115200,
2983 .uart_offset = 8,
2984 },
04bf7e74
WP		 2985 [pbn_b1_16_115200] = {
2986 .flags = FL_BASE1,
2987 .num_ports = 16,
2988 .base_baud = 115200,
2989 .uart_offset = 8,
2990 },
1da177e4
LT		 2991
2992 [pbn_b1_1_921600] = {
2993 .flags = FL_BASE1,
2994 .num_ports = 1,
2995 .base_baud = 921600,
2996 .uart_offset = 8,
2997 },
2998 [pbn_b1_2_921600] = {
2999 .flags = FL_BASE1,
3000 .num_ports = 2,
3001 .base_baud = 921600,
3002 .uart_offset = 8,
3003 },
3004 [pbn_b1_4_921600] = {
3005 .flags = FL_BASE1,
3006 .num_ports = 4,
3007 .base_baud = 921600,
3008 .uart_offset = 8,
3009 },
3010 [pbn_b1_8_921600] = {
3011 .flags = FL_BASE1,
3012 .num_ports = 8,
3013 .base_baud = 921600,
3014 .uart_offset = 8,
3015 },
26e92861
GH		 3016 [pbn_b1_2_1250000] = {
3017 .flags = FL_BASE1,
3018 .num_ports = 2,
3019 .base_baud = 1250000,
3020 .uart_offset = 8,
3021 },
1da177e4 3022
84f8c6fc
NV		 3023 [pbn_b1_bt_1_115200] = {
3024 .flags = FL_BASE1|FL_BASE_BARS,
3025 .num_ports = 1,
3026 .base_baud = 115200,
3027 .uart_offset = 8,
3028 },
04bf7e74
WP		 3029 [pbn_b1_bt_2_115200] = {
3030 .flags = FL_BASE1|FL_BASE_BARS,
3031 .num_ports = 2,
3032 .base_baud = 115200,
3033 .uart_offset = 8,
3034 },
3035 [pbn_b1_bt_4_115200] = {
3036 .flags = FL_BASE1|FL_BASE_BARS,
3037 .num_ports = 4,
3038 .base_baud = 115200,
3039 .uart_offset = 8,
3040 },
84f8c6fc 3041
1da177e4
LT		 3042 [pbn_b1_bt_2_921600] = {
3043 .flags = FL_BASE1|FL_BASE_BARS,
3044 .num_ports = 2,
3045 .base_baud = 921600,
3046 .uart_offset = 8,
3047 },
3048
3049 [pbn_b1_1_1382400] = {
3050 .flags = FL_BASE1,
3051 .num_ports = 1,
3052 .base_baud = 1382400,
3053 .uart_offset = 8,
3054 },
3055 [pbn_b1_2_1382400] = {
3056 .flags = FL_BASE1,
3057 .num_ports = 2,
3058 .base_baud = 1382400,
3059 .uart_offset = 8,
3060 },
3061 [pbn_b1_4_1382400] = {
3062 .flags = FL_BASE1,
3063 .num_ports = 4,
3064 .base_baud = 1382400,
3065 .uart_offset = 8,
3066 },
3067 [pbn_b1_8_1382400] = {
3068 .flags = FL_BASE1,
3069 .num_ports = 8,
3070 .base_baud = 1382400,
3071 .uart_offset = 8,
3072 },
3073
3074 [pbn_b2_1_115200] = {
3075 .flags = FL_BASE2,
3076 .num_ports = 1,
3077 .base_baud = 115200,
3078 .uart_offset = 8,
3079 },
737c1756
PH		 3080 [pbn_b2_2_115200] = {
3081 .flags = FL_BASE2,
3082 .num_ports = 2,
3083 .base_baud = 115200,
3084 .uart_offset = 8,
3085 },
a9cccd34
MF		 3086 [pbn_b2_4_115200] = {
3087 .flags = FL_BASE2,
3088 .num_ports = 4,
3089 .base_baud = 115200,
3090 .uart_offset = 8,
3091 },
1da177e4
LT		 3092 [pbn_b2_8_115200] = {
3093 .flags = FL_BASE2,
3094 .num_ports = 8,
3095 .base_baud = 115200,
3096 .uart_offset = 8,
3097 },
3098
3099 [pbn_b2_1_460800] = {
3100 .flags = FL_BASE2,
3101 .num_ports = 1,
3102 .base_baud = 460800,
3103 .uart_offset = 8,
3104 },
3105 [pbn_b2_4_460800] = {
3106 .flags = FL_BASE2,
3107 .num_ports = 4,
3108 .base_baud = 460800,
3109 .uart_offset = 8,
3110 },
3111 [pbn_b2_8_460800] = {
3112 .flags = FL_BASE2,
3113 .num_ports = 8,
3114 .base_baud = 460800,
3115 .uart_offset = 8,
3116 },
3117 [pbn_b2_16_460800] = {
3118 .flags = FL_BASE2,
3119 .num_ports = 16,
3120 .base_baud = 460800,
3121 .uart_offset = 8,
3122 },
3123
3124 [pbn_b2_1_921600] = {
3125 .flags = FL_BASE2,
3126 .num_ports = 1,
3127 .base_baud = 921600,
3128 .uart_offset = 8,
3129 },
3130 [pbn_b2_4_921600] = {
3131 .flags = FL_BASE2,
3132 .num_ports = 4,
3133 .base_baud = 921600,
3134 .uart_offset = 8,
3135 },
3136 [pbn_b2_8_921600] = {
3137 .flags = FL_BASE2,
3138 .num_ports = 8,
3139 .base_baud = 921600,
3140 .uart_offset = 8,
3141 },
3142
e847003f
LB		 3143 [pbn_b2_8_1152000] = {
3144 .flags = FL_BASE2,
3145 .num_ports = 8,
3146 .base_baud = 1152000,
3147 .uart_offset = 8,
3148 },
3149
1da177e4
LT		 3150 [pbn_b2_bt_1_115200] = {
3151 .flags = FL_BASE2|FL_BASE_BARS,
3152 .num_ports = 1,
3153 .base_baud = 115200,
3154 .uart_offset = 8,
3155 },
3156 [pbn_b2_bt_2_115200] = {
3157 .flags = FL_BASE2|FL_BASE_BARS,
3158 .num_ports = 2,
3159 .base_baud = 115200,
3160 .uart_offset = 8,
3161 },
3162 [pbn_b2_bt_4_115200] = {
3163 .flags = FL_BASE2|FL_BASE_BARS,
3164 .num_ports = 4,
3165 .base_baud = 115200,
3166 .uart_offset = 8,
3167 },
3168
3169 [pbn_b2_bt_2_921600] = {
3170 .flags = FL_BASE2|FL_BASE_BARS,
3171 .num_ports = 2,
3172 .base_baud = 921600,
3173 .uart_offset = 8,
3174 },
3175 [pbn_b2_bt_4_921600] = {
3176 .flags = FL_BASE2|FL_BASE_BARS,
3177 .num_ports = 4,
3178 .base_baud = 921600,
3179 .uart_offset = 8,
3180 },
3181
d9004eb4
ABL		 3182 [pbn_b3_2_115200] = {
3183 .flags = FL_BASE3,
3184 .num_ports = 2,
3185 .base_baud = 115200,
3186 .uart_offset = 8,
3187 },
1da177e4
LT		 3188 [pbn_b3_4_115200] = {
3189 .flags = FL_BASE3,
3190 .num_ports = 4,
3191 .base_baud = 115200,
3192 .uart_offset = 8,
3193 },
3194 [pbn_b3_8_115200] = {
3195 .flags = FL_BASE3,
3196 .num_ports = 8,
3197 .base_baud = 115200,
3198 .uart_offset = 8,
3199 },
3200
66169ad1
YY		 3201 [pbn_b4_bt_2_921600] = {
3202 .flags = FL_BASE4,
3203 .num_ports = 2,
3204 .base_baud = 921600,
3205 .uart_offset = 8,
3206 },
3207 [pbn_b4_bt_4_921600] = {
3208 .flags = FL_BASE4,
3209 .num_ports = 4,
3210 .base_baud = 921600,
3211 .uart_offset = 8,
3212 },
3213 [pbn_b4_bt_8_921600] = {
3214 .flags = FL_BASE4,
3215 .num_ports = 8,
3216 .base_baud = 921600,
3217 .uart_offset = 8,
3218 },
3219
1da177e4
LT		 3220 /*
3221 * Entries following this are board-specific.
3222 */
3223
3224 /*
3225 * Panacom - IOMEM
3226 */
3227 [pbn_panacom] = {
3228 .flags = FL_BASE2,
3229 .num_ports = 2,
3230 .base_baud = 921600,
3231 .uart_offset = 0x400,
3232 .reg_shift = 7,
3233 },
3234 [pbn_panacom2] = {
3235 .flags = FL_BASE2|FL_BASE_BARS,
3236 .num_ports = 2,
3237 .base_baud = 921600,
3238 .uart_offset = 0x400,
3239 .reg_shift = 7,
3240 },
3241 [pbn_panacom4] = {
3242 .flags = FL_BASE2|FL_BASE_BARS,
3243 .num_ports = 4,
3244 .base_baud = 921600,
3245 .uart_offset = 0x400,
3246 .reg_shift = 7,
3247 },
3248
3249 /* I think this entry is broken - the first_offset looks wrong --rmk */
3250 [pbn_plx_romulus] = {
3251 .flags = FL_BASE2,
3252 .num_ports = 4,
3253 .base_baud = 921600,
3254 .uart_offset = 8 << 2,
3255 .reg_shift = 2,
3256 .first_offset = 0x03,
3257 },
3258
3259 /*
3260 * This board uses the size of PCI Base region 0 to
3261 * signal now many ports are available
3262 */
3263 [pbn_oxsemi] = {
3264 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3265 .num_ports = 32,
3266 .base_baud = 115200,
3267 .uart_offset = 8,
3268 },
7106b4e3
LH		 3269 [pbn_oxsemi_1_4000000] = {
3270 .flags = FL_BASE0,
3271 .num_ports = 1,
3272 .base_baud = 4000000,
3273 .uart_offset = 0x200,
3274 .first_offset = 0x1000,
3275 },
3276 [pbn_oxsemi_2_4000000] = {
3277 .flags = FL_BASE0,
3278 .num_ports = 2,
3279 .base_baud = 4000000,
3280 .uart_offset = 0x200,
3281 .first_offset = 0x1000,
3282 },
3283 [pbn_oxsemi_4_4000000] = {
3284 .flags = FL_BASE0,
3285 .num_ports = 4,
3286 .base_baud = 4000000,
3287 .uart_offset = 0x200,
3288 .first_offset = 0x1000,
3289 },
3290 [pbn_oxsemi_8_4000000] = {
3291 .flags = FL_BASE0,
3292 .num_ports = 8,
3293 .base_baud = 4000000,
3294 .uart_offset = 0x200,
3295 .first_offset = 0x1000,
3296 },
3297
1da177e4
LT		 3298
3299 /*
3300 * EKF addition for i960 Boards form EKF with serial port.
3301 * Max 256 ports.
3302 */
3303 [pbn_intel_i960] = {
3304 .flags = FL_BASE0,
3305 .num_ports = 32,
3306 .base_baud = 921600,
3307 .uart_offset = 8 << 2,
3308 .reg_shift = 2,
3309 .first_offset = 0x10000,
3310 },
3311 [pbn_sgi_ioc3] = {
3312 .flags = FL_BASE0|FL_NOIRQ,
3313 .num_ports = 1,
3314 .base_baud = 458333,
3315 .uart_offset = 8,
3316 .reg_shift = 0,
3317 .first_offset = 0x20178,
3318 },
3319
1da177e4
LT		 3320 /*
3321 * Computone - uses IOMEM.
3322 */
3323 [pbn_computone_4] = {
3324 .flags = FL_BASE0,
3325 .num_ports = 4,
3326 .base_baud = 921600,
3327 .uart_offset = 0x40,
3328 .reg_shift = 2,
3329 .first_offset = 0x200,
3330 },
3331 [pbn_computone_6] = {
3332 .flags = FL_BASE0,
3333 .num_ports = 6,
3334 .base_baud = 921600,
3335 .uart_offset = 0x40,
3336 .reg_shift = 2,
3337 .first_offset = 0x200,
3338 },
3339 [pbn_computone_8] = {
3340 .flags = FL_BASE0,
3341 .num_ports = 8,
3342 .base_baud = 921600,
3343 .uart_offset = 0x40,
3344 .reg_shift = 2,
3345 .first_offset = 0x200,
3346 },
3347 [pbn_sbsxrsio] = {
3348 .flags = FL_BASE0,
3349 .num_ports = 8,
3350 .base_baud = 460800,
3351 .uart_offset = 256,
3352 .reg_shift = 4,
3353 },
3354 /*
3355 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3356 * Only basic 16550A support.
3357 * XR17C15[24] are not tested, but they should work.
3358 */
3359 [pbn_exar_XR17C152] = {
3360 .flags = FL_BASE0,
3361 .num_ports = 2,
3362 .base_baud = 921600,
3363 .uart_offset = 0x200,
3364 },
3365 [pbn_exar_XR17C154] = {
3366 .flags = FL_BASE0,
3367 .num_ports = 4,
3368 .base_baud = 921600,
3369 .uart_offset = 0x200,
3370 },
3371 [pbn_exar_XR17C158] = {
3372 .flags = FL_BASE0,
3373 .num_ports = 8,
3374 .base_baud = 921600,
3375 .uart_offset = 0x200,
3376 },
dc96efb7
MS		 3377 [pbn_exar_XR17V352] = {
3378 .flags = FL_BASE0,
3379 .num_ports = 2,
3380 .base_baud = 7812500,
3381 .uart_offset = 0x400,
3382 .reg_shift = 0,
3383 .first_offset = 0,
3384 },
3385 [pbn_exar_XR17V354] = {
3386 .flags = FL_BASE0,
3387 .num_ports = 4,
3388 .base_baud = 7812500,
3389 .uart_offset = 0x400,
3390 .reg_shift = 0,
3391 .first_offset = 0,
3392 },
3393 [pbn_exar_XR17V358] = {
3394 .flags = FL_BASE0,
3395 .num_ports = 8,
3396 .base_baud = 7812500,
3397 .uart_offset = 0x400,
3398 .reg_shift = 0,
3399 .first_offset = 0,
3400 },
c68d2b15
BH		 3401 [pbn_exar_ibm_saturn] = {
3402 .flags = FL_BASE0,
3403 .num_ports = 1,
3404 .base_baud = 921600,
3405 .uart_offset = 0x200,
3406 },
3407
aa798505
OJ		 3408 /*
3409 * PA Semi PWRficient PA6T-1682M on-chip UART
3410 */
3411 [pbn_pasemi_1682M] = {
3412 .flags = FL_BASE0,
3413 .num_ports = 1,
3414 .base_baud = 8333333,
3415 },
46a0fac9
SB		 3416 /*
3417 * National Instruments 843x
3418 */
3419 [pbn_ni8430_16] = {
3420 .flags = FL_BASE0,
3421 .num_ports = 16,
3422 .base_baud = 3686400,
3423 .uart_offset = 0x10,
3424 .first_offset = 0x800,
3425 },
3426 [pbn_ni8430_8] = {
3427 .flags = FL_BASE0,
3428 .num_ports = 8,
3429 .base_baud = 3686400,
3430 .uart_offset = 0x10,
3431 .first_offset = 0x800,
3432 },
3433 [pbn_ni8430_4] = {
3434 .flags = FL_BASE0,
3435 .num_ports = 4,
3436 .base_baud = 3686400,
3437 .uart_offset = 0x10,
3438 .first_offset = 0x800,
3439 },
3440 [pbn_ni8430_2] = {
3441 .flags = FL_BASE0,
3442 .num_ports = 2,
3443 .base_baud = 3686400,
3444 .uart_offset = 0x10,
3445 .first_offset = 0x800,
3446 },
1b62cbf2
KJ		 3447 /*
3448 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3449 */
3450 [pbn_ADDIDATA_PCIe_1_3906250] = {
3451 .flags = FL_BASE0,
3452 .num_ports = 1,
3453 .base_baud = 3906250,
3454 .uart_offset = 0x200,
3455 .first_offset = 0x1000,
3456 },
3457 [pbn_ADDIDATA_PCIe_2_3906250] = {
3458 .flags = FL_BASE0,
3459 .num_ports = 2,
3460 .base_baud = 3906250,
3461 .uart_offset = 0x200,
3462 .first_offset = 0x1000,
3463 },
3464 [pbn_ADDIDATA_PCIe_4_3906250] = {
3465 .flags = FL_BASE0,
3466 .num_ports = 4,
3467 .base_baud = 3906250,
3468 .uart_offset = 0x200,
3469 .first_offset = 0x1000,
3470 },
3471 [pbn_ADDIDATA_PCIe_8_3906250] = {
3472 .flags = FL_BASE0,
3473 .num_ports = 8,
3474 .base_baud = 3906250,
3475 .uart_offset = 0x200,
3476 .first_offset = 0x1000,
3477 },
095e24b0 3478 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3479 .flags = FL_BASE_BARS,
3480 .num_ports = 2,
095e24b0
DB		 3481 .base_baud = 921600,
3482 .reg_shift = 2,
3483 },
41d3f099
AS		 3484 /*
3485 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3486 * but is overridden by byt_set_termios.
3487 */
b15e5691
HK		 3488 [pbn_byt] = {
3489 .flags = FL_BASE0,
3490 .num_ports = 1,
3491 .base_baud = 2764800,
3492 .uart_offset = 0x80,
3493 .reg_shift = 2,
3494 },
d9a0fbfd
AP		 3495 [pbn_omegapci] = {
3496 .flags = FL_BASE0,
3497 .num_ports = 8,
3498 .base_baud = 115200,
3499 .uart_offset = 0x200,
3500 },
7808edcd
NG		 3501 [pbn_NETMOS9900_2s_115200] = {
3502 .flags = FL_BASE0,
3503 .num_ports = 2,
3504 .base_baud = 115200,
3505 },
ebebd49a
SH		 3506 [pbn_brcm_trumanage] = {
3507 .flags = FL_BASE0,
3508 .num_ports = 1,
3509 .reg_shift = 2,
3510 .base_baud = 115200,
3511 },
2c62a3c8
GKH		 3512 [pbn_fintek_4] = {
3513 .num_ports = 4,
3514 .uart_offset = 8,
3515 .base_baud = 115200,
3516 .first_offset = 0x40,
3517 },
3518 [pbn_fintek_8] = {
3519 .num_ports = 8,
3520 .uart_offset = 8,
3521 .base_baud = 115200,
3522 .first_offset = 0x40,
3523 },
3524 [pbn_fintek_12] = {
3525 .num_ports = 12,
3526 .uart_offset = 8,
3527 .base_baud = 115200,
3528 .first_offset = 0x40,
3529 },
1da177e4
LT		 3530};
3531
6971c635
GA		 3532static const struct pci_device_id blacklist[] = {
3533 /* softmodems */
5756ee99 3534 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3535 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3536 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3537
3538 /* multi-io cards handled by parport_serial */
3539 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
feb58142 3540 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
436bbd43
CS		 3541};
3542
1da177e4
LT		 3543/*
3544 * Given a complete unknown PCI device, try to use some heuristics to
3545 * guess what the configuration might be, based on the pitiful PCI
3546 * serial specs. Returns 0 on success, 1 on failure.
3547 */
9671f099 3548static int
1c7c1fe5 3549serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3550{
6971c635 3551 const struct pci_device_id *bldev;
1da177e4 3552 int num_iomem, num_port, first_port = -1, i;
5756ee99 3553
1da177e4
LT		 3554 /*
3555 * If it is not a communications device or the programming
3556 * interface is greater than 6, give up.
3557 *
3558 * (Should we try to make guesses for multiport serial devices
5756ee99 3559 * later?)
1da177e4
LT		 3560 */
3561 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3562 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3563 (dev->class & 0xff) > 6)
3564 return -ENODEV;
3565
436bbd43
CS		 3566 /*
3567 * Do not access blacklisted devices that are known not to
6971c635 3568 * feature serial ports or are handled by other modules.
436bbd43 3569 */
6971c635
GA		 3570 for (bldev = blacklist;
3571 bldev < blacklist + ARRAY_SIZE(blacklist);
3572 bldev++) {
3573 if (dev->vendor == bldev->vendor &&
3574 dev->device == bldev->device)
436bbd43
CS		 3575 return -ENODEV;
3576 }
3577
1da177e4
LT		 3578 num_iomem = num_port = 0;
3579 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3580 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3581 num_port++;
3582 if (first_port == -1)
3583 first_port = i;
3584 }
3585 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3586 num_iomem++;
3587 }
3588
3589 /*
3590 * If there is 1 or 0 iomem regions, and exactly one port,
3591 * use it. We guess the number of ports based on the IO
3592 * region size.
3593 */
3594 if (num_iomem <= 1 && num_port == 1) {
3595 board->flags = first_port;
3596 board->num_ports = pci_resource_len(dev, first_port) / 8;
3597 return 0;
3598 }
3599
3600 /*
3601 * Now guess if we've got a board which indexes by BARs.
3602 * Each IO BAR should be 8 bytes, and they should follow
3603 * consecutively.
3604 */
3605 first_port = -1;
3606 num_port = 0;
3607 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3608 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3609 pci_resource_len(dev, i) == 8 &&
3610 (first_port == -1 || (first_port + num_port) == i)) {
3611 num_port++;
3612 if (first_port == -1)
3613 first_port = i;
3614 }
3615 }
3616
3617 if (num_port > 1) {
3618 board->flags = first_port | FL_BASE_BARS;
3619 board->num_ports = num_port;
3620 return 0;
3621 }
3622
3623 return -ENODEV;
3624}
3625
3626static inline int
975a1a7d
RK		 3627serial_pci_matches(const struct pciserial_board *board,
3628 const struct pciserial_board *guessed)
1da177e4
LT		 3629{
3630 return
3631 board->num_ports == guessed->num_ports &&
3632 board->base_baud == guessed->base_baud &&
3633 board->uart_offset == guessed->uart_offset &&
3634 board->reg_shift == guessed->reg_shift &&
3635 board->first_offset == guessed->first_offset;
3636}
3637
241fc436 3638struct serial_private *
975a1a7d 3639pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3640{
2655a2c7 3641 struct uart_8250_port uart;
1da177e4 3642 struct serial_private *priv;
1da177e4
LT		 3643 struct pci_serial_quirk *quirk;
3644 int rc, nr_ports, i;
3645
1da177e4
LT		 3646 nr_ports = board->num_ports;
3647
3648 /*
3649 * Find an init and setup quirks.
3650 */
3651 quirk = find_quirk(dev);
3652
3653 /*
3654 * Run the new-style initialization function.
3655 * The initialization function returns:
3656 * <0 - error
3657 * 0 - use board->num_ports
3658 * >0 - number of ports
3659 */
3660 if (quirk->init) {
3661 rc = quirk->init(dev);
241fc436
RK		 3662 if (rc < 0) {
3663 priv = ERR_PTR(rc);
3664 goto err_out;
3665 }
1da177e4
LT		 3666 if (rc)
3667 nr_ports = rc;
3668 }
3669
8f31bb39 3670 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3671 sizeof(unsigned int) * nr_ports,
3672 GFP_KERNEL);
3673 if (!priv) {
241fc436
RK		 3674 priv = ERR_PTR(-ENOMEM);
3675 goto err_deinit;
1da177e4
LT		 3676 }
3677
70db3d91 3678 priv->dev = dev;
1da177e4 3679 priv->quirk = quirk;
1da177e4 3680
2655a2c7
AC		 3681 memset(&uart, 0, sizeof(uart));
3682 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3683 uart.port.uartclk = board->base_baud * 16;
3684 uart.port.irq = get_pci_irq(dev, board);
3685 uart.port.dev = &dev->dev;
72ce9a83 3686
1da177e4 3687 for (i = 0; i < nr_ports; i++) {
2655a2c7 3688 if (quirk->setup(priv, board, &uart, i))
1da177e4 3689 break;
72ce9a83 3690
af8c5b8d
GKH		 3691 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3692 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 3693
2655a2c7 3694 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 3695 if (priv->line[i] < 0) {
af8c5b8d
GKH		 3696 dev_err(&dev->dev,
3697 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3698 uart.port.iobase, uart.port.irq,
3699 uart.port.iotype, priv->line[i]);
1da177e4
LT		 3700 break;
3701 }
3702 }
1da177e4 3703 priv->nr = i;
241fc436 3704 return priv;
1da177e4 3705
5756ee99 3706err_deinit:
1da177e4
LT		 3707 if (quirk->exit)
3708 quirk->exit(dev);
5756ee99 3709err_out:
241fc436 3710 return priv;
1da177e4 3711}
241fc436 3712EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3713
241fc436 3714void pciserial_remove_ports(struct serial_private *priv)
1da177e4 3715{
056a8763
RK		 3716 struct pci_serial_quirk *quirk;
3717 int i;
1da177e4 3718
056a8763
RK		 3719 for (i = 0; i < priv->nr; i++)
3720 serial8250_unregister_port(priv->line[i]);
1da177e4 3721
056a8763
RK		 3722 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3723 if (priv->remapped_bar[i])
3724 iounmap(priv->remapped_bar[i]);
3725 priv->remapped_bar[i] = NULL;
3726 }
1da177e4 3727
056a8763
RK		 3728 /*
3729 * Find the exit quirks.
3730 */
241fc436 3731 quirk = find_quirk(priv->dev);
056a8763 3732 if (quirk->exit)
241fc436
RK		 3733 quirk->exit(priv->dev);
3734
3735 kfree(priv);
3736}
3737EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3738
3739void pciserial_suspend_ports(struct serial_private *priv)
3740{
3741 int i;
3742
3743 for (i = 0; i < priv->nr; i++)
3744 if (priv->line[i] >= 0)
3745 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3746
3747 /*
3748 * Ensure that every init quirk is properly torn down
3749 */
3750 if (priv->quirk->exit)
3751 priv->quirk->exit(priv->dev);
241fc436
RK		 3752}
3753EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3754
3755void pciserial_resume_ports(struct serial_private *priv)
3756{
3757 int i;
3758
3759 /*
3760 * Ensure that the board is correctly configured.
3761 */
3762 if (priv->quirk->init)
3763 priv->quirk->init(priv->dev);
3764
3765 for (i = 0; i < priv->nr; i++)
3766 if (priv->line[i] >= 0)
3767 serial8250_resume_port(priv->line[i]);
3768}
3769EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3770
3771/*
3772 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3773 * to the arrangement of serial ports on a PCI card.
3774 */
9671f099 3775static int
241fc436
RK		 3776pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3777{
5bf8f501 3778 struct pci_serial_quirk *quirk;
241fc436 3779 struct serial_private *priv;
975a1a7d
RK		 3780 const struct pciserial_board *board;
3781 struct pciserial_board tmp;
241fc436
RK		 3782 int rc;
3783
5bf8f501
FB		 3784 quirk = find_quirk(dev);
3785 if (quirk->probe) {
3786 rc = quirk->probe(dev);
3787 if (rc)
3788 return rc;
3789 }
3790
241fc436 3791 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 3792 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 3793 ent->driver_data);
3794 return -EINVAL;
3795 }
3796
3797 board = &pci_boards[ent->driver_data];
3798
3799 rc = pci_enable_device(dev);
2807190b 3800 pci_save_state(dev);
241fc436
RK		 3801 if (rc)
3802 return rc;
3803
3804 if (ent->driver_data == pbn_default) {
3805 /*
3806 * Use a copy of the pci_board entry for this;
3807 * avoid changing entries in the table.
3808 */
3809 memcpy(&tmp, board, sizeof(struct pciserial_board));
3810 board = &tmp;
3811
3812 /*
3813 * We matched one of our class entries. Try to
3814 * determine the parameters of this board.
3815 */
975a1a7d 3816 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3817 if (rc)
3818 goto disable;
3819 } else {
3820 /*
3821 * We matched an explicit entry. If we are able to
3822 * detect this boards settings with our heuristic,
3823 * then we no longer need this entry.
3824 */
3825 memcpy(&tmp, &pci_boards[pbn_default],
3826 sizeof(struct pciserial_board));
3827 rc = serial_pci_guess_board(dev, &tmp);
3828 if (rc == 0 && serial_pci_matches(board, &tmp))
3829 moan_device("Redundant entry in serial pci_table.",
3830 dev);
3831 }
3832
3833 priv = pciserial_init_ports(dev, board);
3834 if (!IS_ERR(priv)) {
3835 pci_set_drvdata(dev, priv);
3836 return 0;
3837 }
3838
3839 rc = PTR_ERR(priv);
1da177e4 3840
241fc436 3841 disable:
056a8763 3842 pci_disable_device(dev);
241fc436
RK		 3843 return rc;
3844}
1da177e4 3845
ae8d8a14 3846static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3847{
3848 struct serial_private *priv = pci_get_drvdata(dev);
3849
241fc436
RK		 3850 pciserial_remove_ports(priv);
3851
3852 pci_disable_device(dev);
1da177e4
LT		 3853}
3854
1d5e7996 3855#ifdef CONFIG_PM
1da177e4
LT		 3856static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3857{
3858 struct serial_private *priv = pci_get_drvdata(dev);
3859
241fc436
RK		 3860 if (priv)
3861 pciserial_suspend_ports(priv);
1da177e4 3862
1da177e4
LT		 3863 pci_save_state(dev);
3864 pci_set_power_state(dev, pci_choose_state(dev, state));
3865 return 0;
3866}
3867
3868static int pciserial_resume_one(struct pci_dev *dev)
3869{
ccb9d59e 3870 int err;
1da177e4
LT		 3871 struct serial_private *priv = pci_get_drvdata(dev);
3872
3873 pci_set_power_state(dev, PCI_D0);
3874 pci_restore_state(dev);
3875
3876 if (priv) {
1da177e4
LT		 3877 /*
3878 * The device may have been disabled. Re-enable it.
3879 */
ccb9d59e 3880 err = pci_enable_device(dev);
40836c48 3881 /* FIXME: We cannot simply error out here */
ccb9d59e 3882 if (err)
af8c5b8d 3883 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 3884 pciserial_resume_ports(priv);
1da177e4
LT		 3885 }
3886 return 0;
3887}
1d5e7996 3888#endif
1da177e4
LT		 3889
3890static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3891 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3892 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3893 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3894 pbn_b2_8_921600 },
0c6d774c
TW		 3895 /* Advantech also use 0x3618 and 0xf618 */
3896 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3897 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3898 pbn_b0_4_921600 },
3899 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3900 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3901 pbn_b0_4_921600 },
1da177e4
LT		 3902 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3903 PCI_SUBVENDOR_ID_CONNECT_TECH,
3904 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3905 pbn_b1_8_1382400 },
3906 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3907 PCI_SUBVENDOR_ID_CONNECT_TECH,
3908 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3909 pbn_b1_4_1382400 },
3910 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3911 PCI_SUBVENDOR_ID_CONNECT_TECH,
3912 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3913 pbn_b1_2_1382400 },
3914 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3915 PCI_SUBVENDOR_ID_CONNECT_TECH,
3916 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3917 pbn_b1_8_1382400 },
3918 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3919 PCI_SUBVENDOR_ID_CONNECT_TECH,
3920 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3921 pbn_b1_4_1382400 },
3922 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3923 PCI_SUBVENDOR_ID_CONNECT_TECH,
3924 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3925 pbn_b1_2_1382400 },
3926 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3927 PCI_SUBVENDOR_ID_CONNECT_TECH,
3928 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3929 pbn_b1_8_921600 },
3930 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3931 PCI_SUBVENDOR_ID_CONNECT_TECH,
3932 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3933 pbn_b1_8_921600 },
3934 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3935 PCI_SUBVENDOR_ID_CONNECT_TECH,
3936 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3937 pbn_b1_4_921600 },
3938 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3939 PCI_SUBVENDOR_ID_CONNECT_TECH,
3940 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3941 pbn_b1_4_921600 },
3942 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3943 PCI_SUBVENDOR_ID_CONNECT_TECH,
3944 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3945 pbn_b1_2_921600 },
3946 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3947 PCI_SUBVENDOR_ID_CONNECT_TECH,
3948 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3949 pbn_b1_8_921600 },
3950 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3951 PCI_SUBVENDOR_ID_CONNECT_TECH,
3952 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3953 pbn_b1_8_921600 },
3954 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3955 PCI_SUBVENDOR_ID_CONNECT_TECH,
3956 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3957 pbn_b1_4_921600 },
26e92861
GH		 3958 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3959 PCI_SUBVENDOR_ID_CONNECT_TECH,
3960 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3961 pbn_b1_2_1250000 },
3962 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3963 PCI_SUBVENDOR_ID_CONNECT_TECH,
3964 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3965 pbn_b0_2_1843200 },
3966 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3967 PCI_SUBVENDOR_ID_CONNECT_TECH,
3968 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3969 pbn_b0_4_1843200 },
85d1494e
YY		 3970 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3971 PCI_VENDOR_ID_AFAVLAB,
3972 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3973 pbn_b0_4_1152000 },
26e92861
GH		 3974 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3975 PCI_SUBVENDOR_ID_CONNECT_TECH,
3976 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3977 pbn_b0_2_1843200_200 },
3978 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3979 PCI_SUBVENDOR_ID_CONNECT_TECH,
3980 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3981 pbn_b0_4_1843200_200 },
3982 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3983 PCI_SUBVENDOR_ID_CONNECT_TECH,
3984 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3985 pbn_b0_8_1843200_200 },
3986 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3987 PCI_SUBVENDOR_ID_CONNECT_TECH,
3988 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3989 pbn_b0_2_1843200_200 },
3990 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3991 PCI_SUBVENDOR_ID_CONNECT_TECH,
3992 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3993 pbn_b0_4_1843200_200 },
3994 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3995 PCI_SUBVENDOR_ID_CONNECT_TECH,
3996 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3997 pbn_b0_8_1843200_200 },
3998 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3999 PCI_SUBVENDOR_ID_CONNECT_TECH,
4000 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4001 pbn_b0_2_1843200_200 },
4002 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4003 PCI_SUBVENDOR_ID_CONNECT_TECH,
4004 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4005 pbn_b0_4_1843200_200 },
4006 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4007 PCI_SUBVENDOR_ID_CONNECT_TECH,
4008 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4009 pbn_b0_8_1843200_200 },
4010 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4011 PCI_SUBVENDOR_ID_CONNECT_TECH,
4012 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4013 pbn_b0_2_1843200_200 },
4014 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4015 PCI_SUBVENDOR_ID_CONNECT_TECH,
4016 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4017 pbn_b0_4_1843200_200 },
4018 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4019 PCI_SUBVENDOR_ID_CONNECT_TECH,
4020 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4021 pbn_b0_8_1843200_200 },
c68d2b15
BH		 4022 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4023 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4024 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 4025
4026 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 4027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4028 pbn_b2_bt_1_115200 },
4029 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 4030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4031 pbn_b2_bt_2_115200 },
4032 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 4033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4034 pbn_b2_bt_4_115200 },
4035 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 4036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4037 pbn_b2_bt_2_115200 },
4038 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4040 pbn_b2_bt_4_115200 },
4041 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4043 pbn_b2_8_115200 },
e65f0f82
FL		 4044 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4046 pbn_b2_8_460800 },
1da177e4
LT		 4047 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4049 pbn_b2_8_115200 },
4050
4051 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4053 pbn_b2_bt_2_115200 },
4054 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4056 pbn_b2_bt_2_921600 },
4057 /*
4058 * VScom SPCOM800, from sl@s.pl
4059 */
5756ee99
AC		 4060 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4062 pbn_b2_8_921600 },
4063 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4065 pbn_b2_4_921600 },
b76c5a07
CB		 4066 /* Unknown card - subdevice 0x1584 */
4067 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4068 PCI_VENDOR_ID_PLX,
4069 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4070 pbn_b2_4_115200 },
4071 /* Unknown card - subdevice 0x1588 */
4072 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4073 PCI_VENDOR_ID_PLX,
4074 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4075 pbn_b2_8_115200 },
1da177e4
LT		 4076 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4077 PCI_SUBVENDOR_ID_KEYSPAN,
4078 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4079 pbn_panacom },
4080 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4082 pbn_panacom4 },
4083 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085 pbn_panacom2 },
a9cccd34
MF		 4086 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4087 PCI_VENDOR_ID_ESDGMBH,
4088 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4089 pbn_b2_4_115200 },
1da177e4
LT		 4090 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4091 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4092 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4093 pbn_b2_4_460800 },
4094 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4095 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4096 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4097 pbn_b2_8_460800 },
4098 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4099 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4100 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4101 pbn_b2_16_460800 },
4102 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4103 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4104 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4105 pbn_b2_16_460800 },
4106 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4107 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4108 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4109 pbn_b2_4_460800 },
4110 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4111 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4112 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4113 pbn_b2_8_460800 },
add7b58e
BH		 4114 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4115 PCI_SUBVENDOR_ID_EXSYS,
4116 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4117 pbn_b2_4_115200 },
1da177e4
LT		 4118 /*
4119 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4120 * (Exoray@isys.ca)
4121 */
4122 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4123 0x10b5, 0x106a, 0, 0,
4124 pbn_plx_romulus },
55c7c0fd
AC		 4125 /*
4126 * Quatech cards. These actually have configurable clocks but for
4127 * now we just use the default.
4128 *
4129 * 100 series are RS232, 200 series RS422,
4130 */
1da177e4
LT		 4131 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4133 pbn_b1_4_115200 },
4134 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4136 pbn_b1_2_115200 },
55c7c0fd
AC		 4137 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4139 pbn_b2_2_115200 },
4140 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4142 pbn_b1_2_115200 },
4143 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4145 pbn_b2_2_115200 },
4146 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4148 pbn_b1_4_115200 },
1da177e4
LT		 4149 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4151 pbn_b1_8_115200 },
4152 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154 pbn_b1_8_115200 },
55c7c0fd
AC		 4155 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4157 pbn_b1_4_115200 },
4158 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4160 pbn_b1_2_115200 },
4161 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4163 pbn_b1_4_115200 },
4164 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4166 pbn_b1_2_115200 },
4167 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4169 pbn_b2_4_115200 },
4170 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172 pbn_b2_2_115200 },
4173 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4175 pbn_b2_1_115200 },
4176 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4178 pbn_b2_4_115200 },
4179 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4181 pbn_b2_2_115200 },
4182 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184 pbn_b2_1_115200 },
4185 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4187 pbn_b0_8_115200 },
4188
1da177e4 4189 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4190 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4191 0, 0,
1da177e4 4192 pbn_b0_4_921600 },
fbc0dc0d 4193 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4194 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4195 0, 0,
fbc0dc0d 4196 pbn_b0_4_1152000 },
c9bd9d01
MP		 4197 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199 pbn_b0_bt_2_921600 },
db1de159
DR		 4200
4201 /*
4202 * The below card is a little controversial since it is the
4203 * subject of a PCI vendor/device ID clash. (See
4204 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4205 * For now just used the hex ID 0x950a.
4206 */
39aced68 4207 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4208 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4209 0, 0, pbn_b0_2_115200 },
4210 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4211 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4212 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4213 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215 pbn_b0_2_1130000 },
70fd8fde
AP		 4216 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4217 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4218 pbn_b0_1_921600 },
1da177e4
LT		 4219 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4221 pbn_b0_4_115200 },
4222 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224 pbn_b0_bt_2_921600 },
e847003f
LB		 4225 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4226 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4227 pbn_b2_8_1152000 },
1da177e4 4228
7106b4e3
LH		 4229 /*
4230 * Oxford Semiconductor Inc. Tornado PCI express device range.
4231 */
4232 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 pbn_b0_1_4000000 },
4235 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 pbn_b0_1_4000000 },
4238 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_oxsemi_1_4000000 },
4241 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_oxsemi_1_4000000 },
4244 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 pbn_b0_1_4000000 },
4247 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249 pbn_b0_1_4000000 },
4250 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_oxsemi_1_4000000 },
4253 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_oxsemi_1_4000000 },
4256 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_b0_1_4000000 },
4259 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_b0_1_4000000 },
4262 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_b0_1_4000000 },
4265 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_b0_1_4000000 },
4268 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_oxsemi_2_4000000 },
4271 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_oxsemi_2_4000000 },
4274 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_oxsemi_4_4000000 },
4277 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_oxsemi_4_4000000 },
4280 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_oxsemi_8_4000000 },
4283 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_oxsemi_8_4000000 },
4286 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 pbn_oxsemi_1_4000000 },
4289 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 pbn_oxsemi_1_4000000 },
4292 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294 pbn_oxsemi_1_4000000 },
4295 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297 pbn_oxsemi_1_4000000 },
4298 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300 pbn_oxsemi_1_4000000 },
4301 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_oxsemi_1_4000000 },
4304 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_oxsemi_1_4000000 },
4307 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_oxsemi_1_4000000 },
4310 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_oxsemi_1_4000000 },
4313 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_oxsemi_1_4000000 },
4316 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 pbn_oxsemi_1_4000000 },
4319 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 pbn_oxsemi_1_4000000 },
4322 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 pbn_oxsemi_1_4000000 },
4325 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_oxsemi_1_4000000 },
4328 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_oxsemi_1_4000000 },
4331 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_oxsemi_1_4000000 },
4334 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_oxsemi_1_4000000 },
4337 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_oxsemi_1_4000000 },
4340 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_oxsemi_1_4000000 },
4343 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_oxsemi_1_4000000 },
4346 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_oxsemi_1_4000000 },
4349 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_oxsemi_1_4000000 },
4352 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_oxsemi_1_4000000 },
4355 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_oxsemi_1_4000000 },
4358 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_oxsemi_1_4000000 },
4361 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 pbn_oxsemi_1_4000000 },
b80de369
LH		 4364 /*
4365 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4366 */
4367 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4368 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4369 pbn_oxsemi_1_4000000 },
4370 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4371 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4372 pbn_oxsemi_2_4000000 },
4373 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4374 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4375 pbn_oxsemi_4_4000000 },
4376 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4377 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4378 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4379
4380 /*
4381 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4382 */
4383 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4384 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4385 pbn_oxsemi_2_4000000 },
4386
1da177e4
LT		 4387 /*
4388 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4389 * from skokodyn@yahoo.com
4390 */
4391 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4392 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4393 pbn_sbsxrsio },
4394 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4395 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4396 pbn_sbsxrsio },
4397 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4398 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4399 pbn_sbsxrsio },
4400 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4401 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4402 pbn_sbsxrsio },
4403
4404 /*
4405 * Digitan DS560-558, from jimd@esoft.com
4406 */
4407 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4409 pbn_b1_1_115200 },
4410
4411 /*
4412 * Titan Electronic cards
4413 * The 400L and 800L have a custom setup quirk.
4414 */
4415 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4417 pbn_b0_1_921600 },
4418 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4420 pbn_b0_2_921600 },
4421 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4423 pbn_b0_4_921600 },
4424 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4426 pbn_b0_4_921600 },
4427 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 pbn_b1_1_921600 },
4430 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 pbn_b1_bt_2_921600 },
4433 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_b0_bt_4_921600 },
4436 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 pbn_b0_bt_8_921600 },
66169ad1
YY		 4439 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 pbn_b4_bt_2_921600 },
4442 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b4_bt_4_921600 },
4445 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_b4_bt_8_921600 },
4448 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 pbn_b0_4_921600 },
4451 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 pbn_b0_4_921600 },
4454 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 pbn_b0_4_921600 },
4457 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_oxsemi_1_4000000 },
4460 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_oxsemi_2_4000000 },
4463 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_oxsemi_4_4000000 },
4466 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_oxsemi_8_4000000 },
4469 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_oxsemi_2_4000000 },
4472 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4475 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4478 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b0_4_921600 },
4481 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 pbn_b0_4_921600 },
4484 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_b0_4_921600 },
4487 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_b0_4_921600 },
1da177e4
LT		 4490
4491 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_b2_1_460800 },
4494 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_b2_1_460800 },
4497 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_b2_1_460800 },
4500 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502 pbn_b2_bt_2_921600 },
4503 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_b2_bt_2_921600 },
4506 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_b2_bt_2_921600 },
4509 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 pbn_b2_bt_4_921600 },
4512 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_b2_bt_4_921600 },
4515 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_b2_bt_4_921600 },
4518 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_b0_1_921600 },
4521 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_b0_1_921600 },
4524 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_b0_1_921600 },
4527 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 pbn_b0_bt_2_921600 },
4530 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_b0_bt_2_921600 },
4533 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_b0_bt_2_921600 },
4536 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_b0_bt_4_921600 },
4539 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_b0_bt_4_921600 },
4542 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4545 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_b0_bt_8_921600 },
4548 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_b0_bt_8_921600 },
4551 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_b0_bt_8_921600 },
1da177e4
LT		 4554
4555 /*
4556 * Computone devices submitted by Doug McNash dmcnash@computone.com
4557 */
4558 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4559 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4560 0, 0, pbn_computone_4 },
4561 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4562 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4563 0, 0, pbn_computone_8 },
4564 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4565 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4566 0, 0, pbn_computone_6 },
4567
4568 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570 pbn_oxsemi },
4571 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4572 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4573 pbn_b0_bt_1_921600 },
4574
abd7baca
SC		 4575 /*
4576 * SUNIX (TIMEDIA)
4577 */
4578 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4579 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4580 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4581 pbn_b0_bt_1_921600 },
4582
4583 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4584 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4585 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4586 pbn_b0_bt_1_921600 },
4587
1da177e4
LT		 4588 /*
4589 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4590 */
4591 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b0_bt_8_115200 },
4594 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b0_bt_8_115200 },
4597
4598 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_b0_bt_2_115200 },
4601 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_b0_bt_2_115200 },
4604 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4607 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 pbn_b0_bt_2_115200 },
4610 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_b0_bt_2_115200 },
1da177e4
LT		 4613 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_b0_bt_4_460800 },
4616 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_b0_bt_4_460800 },
4619 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_b0_bt_2_460800 },
4622 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_b0_bt_2_460800 },
4625 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_b0_bt_2_460800 },
4628 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_b0_bt_1_115200 },
4631 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b0_bt_1_460800 },
4634
1fb8cacc
RK		 4635 /*
4636 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4637 * Cards are identified by their subsystem vendor IDs, which
4638 * (in hex) match the model number.
4639 *
4640 * Note that JC140x are RS422/485 cards which require ox950
4641 * ACR = 0x10, and as such are not currently fully supported.
4642 */
4643 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4644 0x1204, 0x0004, 0, 0,
4645 pbn_b0_4_921600 },
4646 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4647 0x1208, 0x0004, 0, 0,
4648 pbn_b0_4_921600 },
4649/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4650 0x1402, 0x0002, 0, 0,
4651 pbn_b0_2_921600 }, */
4652/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4653 0x1404, 0x0004, 0, 0,
4654 pbn_b0_4_921600 }, */
4655 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4656 0x1208, 0x0004, 0, 0,
4657 pbn_b0_4_921600 },
4658
2a52fcb5
KY		 4659 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4660 0x1204, 0x0004, 0, 0,
4661 pbn_b0_4_921600 },
4662 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4663 0x1208, 0x0004, 0, 0,
4664 pbn_b0_4_921600 },
4665 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4666 0x1208, 0x0004, 0, 0,
4667 pbn_b0_4_921600 },
1da177e4
LT		 4668 /*
4669 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4670 */
4671 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 pbn_b1_1_1382400 },
4674
4675 /*
4676 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4677 */
4678 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 pbn_b1_1_1382400 },
4681
4682 /*
4683 * RAStel 2 port modem, gerg@moreton.com.au
4684 */
4685 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b2_bt_2_115200 },
4688
4689 /*
4690 * EKF addition for i960 Boards form EKF with serial port
4691 */
4692 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4693 0xE4BF, PCI_ANY_ID, 0, 0,
4694 pbn_intel_i960 },
4695
4696 /*
4697 * Xircom Cardbus/Ethernet combos
4698 */
4699 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_b0_1_115200 },
4702 /*
4703 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4704 */
4705 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_b0_1_115200 },
4708
4709 /*
4710 * Untested PCI modems, sent in from various folks...
4711 */
4712
4713 /*
4714 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4715 */
4716 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4717 0x1048, 0x1500, 0, 0,
4718 pbn_b1_1_115200 },
4719
4720 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4721 0xFF00, 0, 0, 0,
4722 pbn_sgi_ioc3 },
4723
4724 /*
4725 * HP Diva card
4726 */
4727 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4728 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4729 pbn_b1_1_115200 },
4730 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_b0_5_115200 },
4733 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_b2_1_115200 },
4736
d9004eb4
ABL		 4737 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 pbn_b3_2_115200 },
1da177e4
LT		 4740 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_b3_4_115200 },
4743 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_b3_8_115200 },
4746
4747 /*
4748 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4749 */
4750 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4751 PCI_ANY_ID, PCI_ANY_ID,
4752 0,
4753 0, pbn_exar_XR17C152 },
4754 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4755 PCI_ANY_ID, PCI_ANY_ID,
4756 0,
4757 0, pbn_exar_XR17C154 },
4758 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4759 PCI_ANY_ID, PCI_ANY_ID,
4760 0,
4761 0, pbn_exar_XR17C158 },
dc96efb7
MS		 4762 /*
4763 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4764 */
4765 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4766 PCI_ANY_ID, PCI_ANY_ID,
4767 0,
4768 0, pbn_exar_XR17V352 },
4769 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4770 PCI_ANY_ID, PCI_ANY_ID,
4771 0,
4772 0, pbn_exar_XR17V354 },
4773 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4774 PCI_ANY_ID, PCI_ANY_ID,
4775 0,
4776 0, pbn_exar_XR17V358 },
1da177e4
LT		 4777
4778 /*
4779 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4780 */
4781 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 pbn_b0_1_115200 },
84f8c6fc
NV		 4784 /*
4785 * ITE
4786 */
4787 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4788 PCI_ANY_ID, PCI_ANY_ID,
4789 0, 0,
4790 pbn_b1_bt_1_115200 },
1da177e4 4791
737c1756
PH		 4792 /*
4793 * IntaShield IS-200
4794 */
4795 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4797 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4798 /*
4799 * IntaShield IS-400
4800 */
4801 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4803 pbn_b2_4_115200 },
48212008
TH		 4804 /*
4805 * Perle PCI-RAS cards
4806 */
4807 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4808 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4809 0, 0, pbn_b2_4_921600 },
4810 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4811 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4812 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4813
4814 /*
4815 * Mainpine series cards: Fairly standard layout but fools
4816 * parts of the autodetect in some cases and uses otherwise
4817 * unmatched communications subclasses in the PCI Express case
4818 */
4819
4820 { /* RockForceDUO */
4821 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4822 PCI_VENDOR_ID_MAINPINE, 0x0200,
4823 0, 0, pbn_b0_2_115200 },
4824 { /* RockForceQUATRO */
4825 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4826 PCI_VENDOR_ID_MAINPINE, 0x0300,
4827 0, 0, pbn_b0_4_115200 },
4828 { /* RockForceDUO+ */
4829 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4830 PCI_VENDOR_ID_MAINPINE, 0x0400,
4831 0, 0, pbn_b0_2_115200 },
4832 { /* RockForceQUATRO+ */
4833 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4834 PCI_VENDOR_ID_MAINPINE, 0x0500,
4835 0, 0, pbn_b0_4_115200 },
4836 { /* RockForce+ */
4837 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4838 PCI_VENDOR_ID_MAINPINE, 0x0600,
4839 0, 0, pbn_b0_2_115200 },
4840 { /* RockForce+ */
4841 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4842 PCI_VENDOR_ID_MAINPINE, 0x0700,
4843 0, 0, pbn_b0_4_115200 },
4844 { /* RockForceOCTO+ */
4845 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4846 PCI_VENDOR_ID_MAINPINE, 0x0800,
4847 0, 0, pbn_b0_8_115200 },
4848 { /* RockForceDUO+ */
4849 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4850 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4851 0, 0, pbn_b0_2_115200 },
4852 { /* RockForceQUARTRO+ */
4853 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4854 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4855 0, 0, pbn_b0_4_115200 },
4856 { /* RockForceOCTO+ */
4857 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4858 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4859 0, 0, pbn_b0_8_115200 },
4860 { /* RockForceD1 */
4861 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4862 PCI_VENDOR_ID_MAINPINE, 0x2000,
4863 0, 0, pbn_b0_1_115200 },
4864 { /* RockForceF1 */
4865 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4866 PCI_VENDOR_ID_MAINPINE, 0x2100,
4867 0, 0, pbn_b0_1_115200 },
4868 { /* RockForceD2 */
4869 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4870 PCI_VENDOR_ID_MAINPINE, 0x2200,
4871 0, 0, pbn_b0_2_115200 },
4872 { /* RockForceF2 */
4873 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4874 PCI_VENDOR_ID_MAINPINE, 0x2300,
4875 0, 0, pbn_b0_2_115200 },
4876 { /* RockForceD4 */
4877 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4878 PCI_VENDOR_ID_MAINPINE, 0x2400,
4879 0, 0, pbn_b0_4_115200 },
4880 { /* RockForceF4 */
4881 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4882 PCI_VENDOR_ID_MAINPINE, 0x2500,
4883 0, 0, pbn_b0_4_115200 },
4884 { /* RockForceD8 */
4885 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4886 PCI_VENDOR_ID_MAINPINE, 0x2600,
4887 0, 0, pbn_b0_8_115200 },
4888 { /* RockForceF8 */
4889 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4890 PCI_VENDOR_ID_MAINPINE, 0x2700,
4891 0, 0, pbn_b0_8_115200 },
4892 { /* IQ Express D1 */
4893 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4894 PCI_VENDOR_ID_MAINPINE, 0x3000,
4895 0, 0, pbn_b0_1_115200 },
4896 { /* IQ Express F1 */
4897 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4898 PCI_VENDOR_ID_MAINPINE, 0x3100,
4899 0, 0, pbn_b0_1_115200 },
4900 { /* IQ Express D2 */
4901 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4902 PCI_VENDOR_ID_MAINPINE, 0x3200,
4903 0, 0, pbn_b0_2_115200 },
4904 { /* IQ Express F2 */
4905 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4906 PCI_VENDOR_ID_MAINPINE, 0x3300,
4907 0, 0, pbn_b0_2_115200 },
4908 { /* IQ Express D4 */
4909 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4910 PCI_VENDOR_ID_MAINPINE, 0x3400,
4911 0, 0, pbn_b0_4_115200 },
4912 { /* IQ Express F4 */
4913 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4914 PCI_VENDOR_ID_MAINPINE, 0x3500,
4915 0, 0, pbn_b0_4_115200 },
4916 { /* IQ Express D8 */
4917 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4918 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4919 0, 0, pbn_b0_8_115200 },
4920 { /* IQ Express F8 */
4921 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4922 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4923 0, 0, pbn_b0_8_115200 },
4924
4925
aa798505
OJ		 4926 /*
4927 * PA Semi PA6T-1682M on-chip UART
4928 */
4929 { PCI_VENDOR_ID_PASEMI, 0xa004,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931 pbn_pasemi_1682M },
4932
46a0fac9
SB		 4933 /*
4934 * National Instruments
4935 */
04bf7e74
WP		 4936 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_b1_16_115200 },
4939 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_b1_8_115200 },
4942 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b1_bt_4_115200 },
4945 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_b1_bt_2_115200 },
4948 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b1_bt_4_115200 },
4951 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_b1_bt_2_115200 },
4954 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_b1_16_115200 },
4957 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 pbn_b1_8_115200 },
4960 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_b1_bt_4_115200 },
4963 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b1_bt_2_115200 },
4966 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b1_bt_4_115200 },
4969 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b1_bt_2_115200 },
46a0fac9
SB		 4972 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 pbn_ni8430_2 },
4975 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 pbn_ni8430_2 },
4978 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 pbn_ni8430_4 },
4981 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 pbn_ni8430_4 },
4984 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 pbn_ni8430_8 },
4987 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_ni8430_8 },
4990 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 pbn_ni8430_16 },
4993 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995 pbn_ni8430_16 },
4996 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 pbn_ni8430_2 },
4999 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 pbn_ni8430_2 },
5002 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 pbn_ni8430_4 },
5005 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 pbn_ni8430_4 },
5008
02c9b5cf
KJ		 5009 /*
5010 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5011 */
5012 { PCI_VENDOR_ID_ADDIDATA,
5013 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5014 PCI_ANY_ID,
5015 PCI_ANY_ID,
5016 0,
5017 0,
5018 pbn_b0_4_115200 },
5019
5020 { PCI_VENDOR_ID_ADDIDATA,
5021 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5022 PCI_ANY_ID,
5023 PCI_ANY_ID,
5024 0,
5025 0,
5026 pbn_b0_2_115200 },
5027
5028 { PCI_VENDOR_ID_ADDIDATA,
5029 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5030 PCI_ANY_ID,
5031 PCI_ANY_ID,
5032 0,
5033 0,
5034 pbn_b0_1_115200 },
5035
086231f7 5036 { PCI_VENDOR_ID_AMCC,
57c1f0e9 5037 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 5038 PCI_ANY_ID,
5039 PCI_ANY_ID,
5040 0,
5041 0,
5042 pbn_b1_8_115200 },
5043
5044 { PCI_VENDOR_ID_ADDIDATA,
5045 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5046 PCI_ANY_ID,
5047 PCI_ANY_ID,
5048 0,
5049 0,
5050 pbn_b0_4_115200 },
5051
5052 { PCI_VENDOR_ID_ADDIDATA,
5053 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5054 PCI_ANY_ID,
5055 PCI_ANY_ID,
5056 0,
5057 0,
5058 pbn_b0_2_115200 },
5059
5060 { PCI_VENDOR_ID_ADDIDATA,
5061 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5062 PCI_ANY_ID,
5063 PCI_ANY_ID,
5064 0,
5065 0,
5066 pbn_b0_1_115200 },
5067
5068 { PCI_VENDOR_ID_ADDIDATA,
5069 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5070 PCI_ANY_ID,
5071 PCI_ANY_ID,
5072 0,
5073 0,
5074 pbn_b0_4_115200 },
5075
5076 { PCI_VENDOR_ID_ADDIDATA,
5077 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5078 PCI_ANY_ID,
5079 PCI_ANY_ID,
5080 0,
5081 0,
5082 pbn_b0_2_115200 },
5083
5084 { PCI_VENDOR_ID_ADDIDATA,
5085 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5086 PCI_ANY_ID,
5087 PCI_ANY_ID,
5088 0,
5089 0,
5090 pbn_b0_1_115200 },
5091
5092 { PCI_VENDOR_ID_ADDIDATA,
5093 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5094 PCI_ANY_ID,
5095 PCI_ANY_ID,
5096 0,
5097 0,
5098 pbn_b0_8_115200 },
5099
1b62cbf2
KJ		 5100 { PCI_VENDOR_ID_ADDIDATA,
5101 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5102 PCI_ANY_ID,
5103 PCI_ANY_ID,
5104 0,
5105 0,
5106 pbn_ADDIDATA_PCIe_4_3906250 },
5107
5108 { PCI_VENDOR_ID_ADDIDATA,
5109 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5110 PCI_ANY_ID,
5111 PCI_ANY_ID,
5112 0,
5113 0,
5114 pbn_ADDIDATA_PCIe_2_3906250 },
5115
5116 { PCI_VENDOR_ID_ADDIDATA,
5117 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5118 PCI_ANY_ID,
5119 PCI_ANY_ID,
5120 0,
5121 0,
5122 pbn_ADDIDATA_PCIe_1_3906250 },
5123
5124 { PCI_VENDOR_ID_ADDIDATA,
5125 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5126 PCI_ANY_ID,
5127 PCI_ANY_ID,
5128 0,
5129 0,
5130 pbn_ADDIDATA_PCIe_8_3906250 },
5131
25cf9bc1
JS		 5132 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5133 PCI_VENDOR_ID_IBM, 0x0299,
5134 0, 0, pbn_b0_bt_2_115200 },
5135
972ce085
SS		 5136 /*
5137 * other NetMos 9835 devices are most likely handled by the
5138 * parport_serial driver, check drivers/parport/parport_serial.c
5139 * before adding them here.
5140 */
5141
c4285b47
MB		 5142 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5143 0xA000, 0x1000,
5144 0, 0, pbn_b0_1_115200 },
5145
7808edcd
NG		 5146 /* the 9901 is a rebranded 9912 */
5147 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5148 0xA000, 0x1000,
5149 0, 0, pbn_b0_1_115200 },
5150
5151 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5152 0xA000, 0x1000,
5153 0, 0, pbn_b0_1_115200 },
5154
5155 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5156 0xA000, 0x1000,
5157 0, 0, pbn_b0_1_115200 },
5158
5159 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5160 0xA000, 0x1000,
5161 0, 0, pbn_b0_1_115200 },
5162
5163 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5164 0xA000, 0x3002,
5165 0, 0, pbn_NETMOS9900_2s_115200 },
5166
ac6ec5b1 5167 /*
44178176 5168 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5169 */
5170
5171 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5172 0xA000, 0x1000,
5173 0, 0, pbn_b0_1_115200 },
5174
44178176
ES		 5175 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5176 0xA000, 0x3002,
5177 0, 0, pbn_b0_bt_2_115200 },
5178
ac6ec5b1
IS		 5179 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5180 0xA000, 0x3004,
5181 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5182 /* Intel CE4100 */
5183 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5185 pbn_ce4100_1_115200 },
b15e5691
HK		 5186 /* Intel BayTrail */
5187 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5188 PCI_ANY_ID, PCI_ANY_ID,
5189 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5190 pbn_byt },
5191 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5192 PCI_ANY_ID, PCI_ANY_ID,
5193 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5194 pbn_byt },
095e24b0 5195
d9a0fbfd
AP		 5196 /*
5197 * Cronyx Omega PCI
5198 */
5199 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5201 pbn_omegapci },
ac6ec5b1 5202
ebebd49a
SH		 5203 /*
5204 * Broadcom TruManage
5205 */
5206 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5208 pbn_brcm_trumanage },
5209
6683549e
AC		 5210 /*
5211 * AgeStar as-prs2-009
5212 */
5213 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5214 PCI_ANY_ID, PCI_ANY_ID,
5215 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5216
5217 /*
5218 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5219 * so not listed here.
5220 */
5221 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5222 PCI_ANY_ID, PCI_ANY_ID,
5223 0, 0, pbn_b0_bt_4_115200 },
5224
5225 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5226 PCI_ANY_ID, PCI_ANY_ID,
5227 0, 0, pbn_b0_bt_2_115200 },
5228
8b5c913f
WY		 5229 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5230 PCI_ANY_ID, PCI_ANY_ID,
5231 0, 0, pbn_b0_bt_2_115200 },
5232
14faa8cc
MS		 5233 /*
5234 * Commtech, Inc. Fastcom adapters
5235 */
5236 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5237 PCI_ANY_ID, PCI_ANY_ID,
5238 0,
5239 0, pbn_b0_2_1152000_200 },
5240 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5241 PCI_ANY_ID, PCI_ANY_ID,
5242 0,
5243 0, pbn_b0_4_1152000_200 },
5244 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5245 PCI_ANY_ID, PCI_ANY_ID,
5246 0,
5247 0, pbn_b0_4_1152000_200 },
5248 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5249 PCI_ANY_ID, PCI_ANY_ID,
5250 0,
5251 0, pbn_b0_8_1152000_200 },
5252 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5253 PCI_ANY_ID, PCI_ANY_ID,
5254 0,
5255 0, pbn_exar_XR17V352 },
5256 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5257 PCI_ANY_ID, PCI_ANY_ID,
5258 0,
5259 0, pbn_exar_XR17V354 },
5260 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5261 PCI_ANY_ID, PCI_ANY_ID,
5262 0,
5263 0, pbn_exar_XR17V358 },
5264
2c62a3c8
GKH		 5265 /* Fintek PCI serial cards */
5266 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5267 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5268 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5269
1da177e4
LT		 5270 /*
5271 * These entries match devices with class COMMUNICATION_SERIAL,
5272 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5273 */
5274 { PCI_ANY_ID, PCI_ANY_ID,
5275 PCI_ANY_ID, PCI_ANY_ID,
5276 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5277 0xffff00, pbn_default },
5278 { PCI_ANY_ID, PCI_ANY_ID,
5279 PCI_ANY_ID, PCI_ANY_ID,
5280 PCI_CLASS_COMMUNICATION_MODEM << 8,
5281 0xffff00, pbn_default },
5282 { PCI_ANY_ID, PCI_ANY_ID,
5283 PCI_ANY_ID, PCI_ANY_ID,
5284 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5285 0xffff00, pbn_default },
5286 { 0, }
5287};
5288
2807190b
MR		 5289static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5290 pci_channel_state_t state)
5291{
5292 struct serial_private *priv = pci_get_drvdata(dev);
5293
5294 if (state == pci_channel_io_perm_failure)
5295 return PCI_ERS_RESULT_DISCONNECT;
5296
5297 if (priv)
5298 pciserial_suspend_ports(priv);
5299
5300 pci_disable_device(dev);
5301
5302 return PCI_ERS_RESULT_NEED_RESET;
5303}
5304
5305static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5306{
5307 int rc;
5308
5309 rc = pci_enable_device(dev);
5310
5311 if (rc)
5312 return PCI_ERS_RESULT_DISCONNECT;
5313
5314 pci_restore_state(dev);
5315 pci_save_state(dev);
5316
5317 return PCI_ERS_RESULT_RECOVERED;
5318}
5319
5320static void serial8250_io_resume(struct pci_dev *dev)
5321{
5322 struct serial_private *priv = pci_get_drvdata(dev);
5323
5324 if (priv)
5325 pciserial_resume_ports(priv);
5326}
5327
1d352035 5328static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5329 .error_detected = serial8250_io_error_detected,
5330 .slot_reset = serial8250_io_slot_reset,
5331 .resume = serial8250_io_resume,
5332};
5333
1da177e4
LT		 5334static struct pci_driver serial_pci_driver = {
5335 .name = "serial",
5336 .probe = pciserial_init_one,
2d47b716 5337 .remove = pciserial_remove_one,
1d5e7996 5338#ifdef CONFIG_PM
1da177e4
LT		 5339 .suspend = pciserial_suspend_one,
5340 .resume = pciserial_resume_one,
1d5e7996 5341#endif
1da177e4 5342 .id_table = serial_pci_tbl,
2807190b 5343 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5344};
5345
15a12e83 5346module_pci_driver(serial_pci_driver);
1da177e4
LT		 5347
5348MODULE_LICENSE("GPL");
5349MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5350MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux 6.x block layer and io_uring tree(s)