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serial: 8250_omap: check how many bytes were injected
[linux-2.6-block.git] / drivers / tty / serial / 8250 / 8250_omap.c
CommitLineData
61929cf0
SAS		 1/*
2 * 8250-core based driver for the OMAP internal UART
3 *
4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
5 *
6 * Copyright (C) 2014 Sebastian Andrzej Siewior
7 *
8 */
9
10#include <linux/device.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/serial_8250.h>
61929cf0 14#include <linux/serial_reg.h>
77285243 15#include <linux/tty_flip.h>
61929cf0
SAS		 16#include <linux/platform_device.h>
17#include <linux/slab.h>
18#include <linux/of.h>
4fcdff9b 19#include <linux/of_device.h>
61929cf0
SAS		 20#include <linux/of_gpio.h>
21#include <linux/of_irq.h>
22#include <linux/delay.h>
23#include <linux/pm_runtime.h>
24#include <linux/console.h>
25#include <linux/pm_qos.h>
a3e362f1 26#include <linux/pm_wakeirq.h>
31a17132 27#include <linux/dma-mapping.h>
61929cf0
SAS		 28
29#include "8250.h"
30
31#define DEFAULT_CLK_SPEED 48000000
32
33#define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
34#define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
31a17132 35#define OMAP_DMA_TX_KICK (1 << 2)
cdb929e4
SN		 36/*
37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
38 * The same errata is applicable to AM335x and DRA7x processors too.
39 */
40#define UART_ERRATA_CLOCK_DISABLE (1 << 3)
61929cf0
SAS		 41
42#define OMAP_UART_FCR_RX_TRIG 6
43#define OMAP_UART_FCR_TX_TRIG 4
44
45/* SCR register bitmasks */
46#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
47#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
48#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
49#define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
50#define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
51#define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
52
53/* MVR register bitmasks */
54#define OMAP_UART_MVR_SCHEME_SHIFT 30
55#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
56#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
57#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
58#define OMAP_UART_MVR_MAJ_MASK 0x700
59#define OMAP_UART_MVR_MAJ_SHIFT 8
60#define OMAP_UART_MVR_MIN_MASK 0x3f
61
cdb929e4
SN		 62/* SYSC register bitmasks */
63#define OMAP_UART_SYSC_SOFTRESET (1 << 1)
64
65/* SYSS register bitmasks */
66#define OMAP_UART_SYSS_RESETDONE (1 << 0)
67
61929cf0
SAS		 68#define UART_TI752_TLR_TX 0
69#define UART_TI752_TLR_RX 4
70
71#define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
72#define TRIGGER_FCR_MASK(x) (x & 3)
73
74/* Enable XON/XOFF flow control on output */
75#define OMAP_UART_SW_TX 0x08
76/* Enable XON/XOFF flow control on input */
77#define OMAP_UART_SW_RX 0x02
78
79#define OMAP_UART_WER_MOD_WKUP 0x7f
80#define OMAP_UART_TX_WAKEUP_EN (1 << 7)
81
82#define TX_TRIGGER 1
83#define RX_TRIGGER 48
84
85#define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
86#define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
87
88#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
89
90#define OMAP_UART_REV_46 0x0406
91#define OMAP_UART_REV_52 0x0502
92#define OMAP_UART_REV_63 0x0603
93
94struct omap8250_priv {
95 int line;
96 u8 habit;
97 u8 mdr1;
98 u8 efr;
99 u8 scr;
100 u8 wer;
101 u8 xon;
102 u8 xoff;
0a0661dd 103 u8 delayed_restore;
61929cf0
SAS		 104 u16 quot;
105
106 bool is_suspending;
107 int wakeirq;
108 int wakeups_enabled;
109 u32 latency;
110 u32 calc_latency;
111 struct pm_qos_request pm_qos_request;
112 struct work_struct qos_work;
113 struct uart_8250_dma omap8250_dma;
eda0cd35 114 spinlock_t rx_dma_lock;
830acf9e 115 bool rx_dma_broken;
61929cf0
SAS		 116};
117
118static u32 uart_read(struct uart_8250_port *up, u32 reg)
119{
120 return readl(up->port.membase + (reg << up->port.regshift));
121}
122
4bf4ea9d
PH		 123static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
124{
125 struct uart_8250_port *up = up_to_u8250p(port);
126 struct omap8250_priv *priv = up->port.private_data;
127 u8 lcr;
128
129 serial8250_do_set_mctrl(port, mctrl);
130
131 /*
132 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
133 * if RTS is raised
134 */
135 lcr = serial_in(up, UART_LCR);
136 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
9719acce
PH		 137 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
138 priv->efr |= UART_EFR_RTS;
4bf4ea9d 139 else
9719acce
PH		 140 priv->efr &= ~UART_EFR_RTS;
141 serial_out(up, UART_EFR, priv->efr);
4bf4ea9d
PH		 142 serial_out(up, UART_LCR, lcr);
143}
144
61929cf0
SAS		 145/*
146 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
147 * The access to uart register after MDR1 Access
148 * causes UART to corrupt data.
149 *
150 * Need a delay =
151 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
152 * give 10 times as much
153 */
154static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
155 struct omap8250_priv *priv)
156{
157 u8 timeout = 255;
158 u8 old_mdr1;
159
160 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
161 if (old_mdr1 == priv->mdr1)
162 return;
163
164 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
165 udelay(2);
166 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
167 UART_FCR_CLEAR_RCVR);
168 /*
169 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
170 * TX_FIFO_E bit is 1.
171 */
172 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
173 (UART_LSR_THRE | UART_LSR_DR))) {
174 timeout--;
175 if (!timeout) {
176 /* Should *never* happen. we warn and carry on */
177 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
178 serial_in(up, UART_LSR));
179 break;
180 }
181 udelay(1);
182 }
183}
184
185static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
186 struct omap8250_priv *priv)
187{
188 unsigned int uartclk = port->uartclk;
189 unsigned int div_13, div_16;
190 unsigned int abs_d13, abs_d16;
191
192 /*
193 * Old custom speed handling.
194 */
195 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
196 priv->quot = port->custom_divisor & 0xffff;
197 /*
198 * I assume that nobody is using this. But hey, if somebody
199 * would like to specify the divisor _and_ the mode then the
200 * driver is ready and waiting for it.
201 */
202 if (port->custom_divisor & (1 << 16))
203 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
204 else
205 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
206 return;
207 }
208 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
209 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
210
211 if (!div_13)
212 div_13 = 1;
213 if (!div_16)
214 div_16 = 1;
215
216 abs_d13 = abs(baud - uartclk / 13 / div_13);
217 abs_d16 = abs(baud - uartclk / 16 / div_16);
218
219 if (abs_d13 >= abs_d16) {
220 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
221 priv->quot = div_16;
222 } else {
223 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
224 priv->quot = div_13;
225 }
226}
227
228static void omap8250_update_scr(struct uart_8250_port *up,
229 struct omap8250_priv *priv)
230{
231 u8 old_scr;
232
233 old_scr = serial_in(up, UART_OMAP_SCR);
234 if (old_scr == priv->scr)
235 return;
236
237 /*
238 * The manual recommends not to enable the DMA mode selector in the SCR
239 * (instead of the FCR) register _and_ selecting the DMA mode as one
240 * register write because this may lead to malfunction.
241 */
242 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
243 serial_out(up, UART_OMAP_SCR,
244 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
245 serial_out(up, UART_OMAP_SCR, priv->scr);
246}
247
6f03541f
SN		 248static void omap8250_update_mdr1(struct uart_8250_port *up,
249 struct omap8250_priv *priv)
250{
251 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
252 omap_8250_mdr1_errataset(up, priv);
253 else
254 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
255}
256
61929cf0
SAS		 257static void omap8250_restore_regs(struct uart_8250_port *up)
258{
259 struct omap8250_priv *priv = up->port.private_data;
0a0661dd
SAS		 260 struct uart_8250_dma *dma = up->dma;
261
262 if (dma && dma->tx_running) {
263 /*
264 * TCSANOW requests the change to occur immediately however if
265 * we have a TX-DMA operation in progress then it has been
266 * observed that it might stall and never complete. Therefore we
267 * delay DMA completes to prevent this hang from happen.
268 */
269 priv->delayed_restore = 1;
270 return;
271 }
61929cf0
SAS		 272
273 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
274 serial_out(up, UART_EFR, UART_EFR_ECB);
275
276 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
277 serial_out(up, UART_MCR, UART_MCR_TCRTLR);
278 serial_out(up, UART_FCR, up->fcr);
279
280 omap8250_update_scr(up, priv);
281
282 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
283
284 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
285 OMAP_UART_TCR_HALT(52));
286 serial_out(up, UART_TI752_TLR,
287 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
288 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
289
290 serial_out(up, UART_LCR, 0);
291
292 /* drop TCR + TLR access, we setup XON/XOFF later */
293 serial_out(up, UART_MCR, up->mcr);
294 serial_out(up, UART_IER, up->ier);
295
296 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
297 serial_dl_write(up, priv->quot);
298
9719acce 299 serial_out(up, UART_EFR, priv->efr);
61929cf0
SAS		 300
301 /* Configure flow control */
302 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
303 serial_out(up, UART_XON1, priv->xon);
304 serial_out(up, UART_XOFF1, priv->xoff);
305
306 serial_out(up, UART_LCR, up->lcr);
6f03541f
SN		 307
308 omap8250_update_mdr1(up, priv);
309
61929cf0
SAS		 310 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
311}
312
313/*
314 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
315 * some differences in how we want to handle flow control.
316 */
317static void omap_8250_set_termios(struct uart_port *port,
318 struct ktermios *termios,
319 struct ktermios *old)
320{
321 struct uart_8250_port *up =
322 container_of(port, struct uart_8250_port, port);
323 struct omap8250_priv *priv = up->port.private_data;
324 unsigned char cval = 0;
325 unsigned int baud;
326
327 switch (termios->c_cflag & CSIZE) {
328 case CS5:
329 cval = UART_LCR_WLEN5;
330 break;
331 case CS6:
332 cval = UART_LCR_WLEN6;
333 break;
334 case CS7:
335 cval = UART_LCR_WLEN7;
336 break;
337 default:
338 case CS8:
339 cval = UART_LCR_WLEN8;
340 break;
341 }
342
343 if (termios->c_cflag & CSTOPB)
344 cval |= UART_LCR_STOP;
345 if (termios->c_cflag & PARENB)
346 cval |= UART_LCR_PARITY;
347 if (!(termios->c_cflag & PARODD))
348 cval |= UART_LCR_EPAR;
349 if (termios->c_cflag & CMSPAR)
350 cval |= UART_LCR_SPAR;
351
352 /*
353 * Ask the core to calculate the divisor for us.
354 */
355 baud = uart_get_baud_rate(port, termios, old,
356 port->uartclk / 16 / 0xffff,
357 port->uartclk / 13);
358 omap_8250_get_divisor(port, baud, priv);
359
360 /*
361 * Ok, we're now changing the port state. Do it with
362 * interrupts disabled.
363 */
364 pm_runtime_get_sync(port->dev);
365 spin_lock_irq(&port->lock);
366
367 /*
368 * Update the per-port timeout.
369 */
370 uart_update_timeout(port, termios->c_cflag, baud);
371
372 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
373 if (termios->c_iflag & INPCK)
374 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
375 if (termios->c_iflag & (IGNBRK | PARMRK))
376 up->port.read_status_mask |= UART_LSR_BI;
377
378 /*
379 * Characters to ignore
380 */
381 up->port.ignore_status_mask = 0;
382 if (termios->c_iflag & IGNPAR)
383 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
384 if (termios->c_iflag & IGNBRK) {
385 up->port.ignore_status_mask |= UART_LSR_BI;
386 /*
387 * If we're ignoring parity and break indicators,
388 * ignore overruns too (for real raw support).
389 */
390 if (termios->c_iflag & IGNPAR)
391 up->port.ignore_status_mask |= UART_LSR_OE;
392 }
393
394 /*
395 * ignore all characters if CREAD is not set
396 */
397 if ((termios->c_cflag & CREAD) == 0)
398 up->port.ignore_status_mask |= UART_LSR_DR;
399
400 /*
401 * Modem status interrupts
402 */
403 up->ier &= ~UART_IER_MSI;
404 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
405 up->ier |= UART_IER_MSI;
406
407 up->lcr = cval;
408 /* Up to here it was mostly serial8250_do_set_termios() */
409
410 /*
411 * We enable TRIG_GRANU for RX and TX and additionaly we set
412 * SCR_TX_EMPTY bit. The result is the following:
413 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
414 * - less than RX_TRIGGER number of bytes will also cause an interrupt
415 * once the UART decides that there no new bytes arriving.
416 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
417 * empty - the trigger level is ignored here.
418 *
419 * Once DMA is enabled:
420 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
421 * bytes in the TX FIFO. On each assert the DMA engine will move
422 * TX_TRIGGER bytes into the FIFO.
423 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
424 * the FIFO and move RX_TRIGGER bytes.
425 * This is because threshold and trigger values are the same.
426 */
427 up->fcr = UART_FCR_ENABLE_FIFO;
428 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
429 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
430
431 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
432 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
433
0a0661dd
SAS		 434 if (up->dma)
435 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
436 OMAP_UART_SCR_DMAMODE_CTL;
437
61929cf0
SAS		 438 priv->xon = termios->c_cc[VSTART];
439 priv->xoff = termios->c_cc[VSTOP];
440
441 priv->efr = 0;
442 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY);
391f93f2
PH		 443 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
444
61929cf0 445 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
9719acce 446 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
391f93f2 447 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
9719acce 448 priv->efr |= UART_EFR_CTS;
61929cf0
SAS		 449 } else if (up->port.flags & UPF_SOFT_FLOW) {
450 /*
5bac4b3d
PH		 451 * OMAP rx s/w flow control is borked; the transmitter remains
452 * stuck off even if rx flow control is subsequently disabled
61929cf0 453 */
61929cf0
SAS		 454
455 /*
456 * IXOFF Flag:
457 * Enable XON/XOFF flow control on output.
458 * Transmit XON1, XOFF1
459 */
391f93f2
PH		 460 if (termios->c_iflag & IXOFF) {
461 up->port.status |= UPSTAT_AUTOXOFF;
61929cf0 462 priv->efr |= OMAP_UART_SW_TX;
391f93f2 463 }
61929cf0
SAS		 464 }
465 omap8250_restore_regs(up);
466
467 spin_unlock_irq(&up->port.lock);
468 pm_runtime_mark_last_busy(port->dev);
469 pm_runtime_put_autosuspend(port->dev);
470
471 /* calculate wakeup latency constraint */
472 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
473 priv->latency = priv->calc_latency;
474
475 schedule_work(&priv->qos_work);
476
477 /* Don't rewrite B0 */
478 if (tty_termios_baud_rate(termios))
479 tty_termios_encode_baud_rate(termios, baud, baud);
480}
481
482/* same as 8250 except that we may have extra flow bits set in EFR */
483static void omap_8250_pm(struct uart_port *port, unsigned int state,
484 unsigned int oldstate)
485{
3e29af27
PH		 486 struct uart_8250_port *up = up_to_u8250p(port);
487 u8 efr;
61929cf0
SAS		 488
489 pm_runtime_get_sync(port->dev);
490 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
3e29af27
PH		 491 efr = serial_in(up, UART_EFR);
492 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
61929cf0
SAS		 493 serial_out(up, UART_LCR, 0);
494
495 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
496 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
3e29af27 497 serial_out(up, UART_EFR, efr);
61929cf0
SAS		 498 serial_out(up, UART_LCR, 0);
499
500 pm_runtime_mark_last_busy(port->dev);
501 pm_runtime_put_autosuspend(port->dev);
502}
503
504static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
505 struct omap8250_priv *priv)
506{
507 u32 mvr, scheme;
508 u16 revision, major, minor;
509
510 mvr = uart_read(up, UART_OMAP_MVER);
511
512 /* Check revision register scheme */
513 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
514
515 switch (scheme) {
516 case 0: /* Legacy Scheme: OMAP2/3 */
517 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
518 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
519 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
520 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
521 break;
522 case 1:
523 /* New Scheme: OMAP4+ */
524 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
525 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
526 OMAP_UART_MVR_MAJ_SHIFT;
527 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
528 break;
529 default:
530 dev_warn(up->port.dev,
531 "Unknown revision, defaulting to highest\n");
532 /* highest possible revision */
533 major = 0xff;
534 minor = 0xff;
535 }
536 /* normalize revision for the driver */
537 revision = UART_BUILD_REVISION(major, minor);
538
539 switch (revision) {
540 case OMAP_UART_REV_46:
4fcdff9b 541 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
61929cf0
SAS		 542 break;
543 case OMAP_UART_REV_52:
4fcdff9b 544 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
61929cf0
SAS		 545 OMAP_UART_WER_HAS_TX_WAKEUP;
546 break;
547 case OMAP_UART_REV_63:
4fcdff9b 548 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
61929cf0
SAS		 549 OMAP_UART_WER_HAS_TX_WAKEUP;
550 break;
551 default:
552 break;
553 }
554}
555
556static void omap8250_uart_qos_work(struct work_struct *work)
557{
558 struct omap8250_priv *priv;
559
560 priv = container_of(work, struct omap8250_priv, qos_work);
561 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
562}
563
9e91597f
SAS		 564#ifdef CONFIG_SERIAL_8250_DMA
565static int omap_8250_dma_handle_irq(struct uart_port *port);
566#endif
567
568static irqreturn_t omap8250_irq(int irq, void *dev_id)
569{
570 struct uart_port *port = dev_id;
571 struct uart_8250_port *up = up_to_u8250p(port);
572 unsigned int iir;
573 int ret;
574
575#ifdef CONFIG_SERIAL_8250_DMA
576 if (up->dma) {
577 ret = omap_8250_dma_handle_irq(port);
578 return IRQ_RETVAL(ret);
579 }
580#endif
581
582 serial8250_rpm_get(up);
583 iir = serial_port_in(port, UART_IIR);
584 ret = serial8250_handle_irq(port, iir);
585 serial8250_rpm_put(up);
586
587 return IRQ_RETVAL(ret);
588}
589
61929cf0
SAS		 590static int omap_8250_startup(struct uart_port *port)
591{
9e91597f 592 struct uart_8250_port *up = up_to_u8250p(port);
61929cf0 593 struct omap8250_priv *priv = port->private_data;
61929cf0
SAS		 594 int ret;
595
596 if (priv->wakeirq) {
a3e362f1 597 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
61929cf0
SAS		 598 if (ret)
599 return ret;
61929cf0
SAS		 600 }
601
602 pm_runtime_get_sync(port->dev);
603
9e91597f
SAS		 604 up->mcr = 0;
605 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
606
607 serial_out(up, UART_LCR, UART_LCR_WLEN8);
608
609 up->lsr_saved_flags = 0;
610 up->msr_saved_flags = 0;
611
612 if (up->dma) {
613 ret = serial8250_request_dma(up);
614 if (ret) {
615 dev_warn_ratelimited(port->dev,
616 "failed to request DMA\n");
617 up->dma = NULL;
618 }
619 }
620
621 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
622 dev_name(port->dev), port);
623 if (ret < 0)
61929cf0
SAS		 624 goto err;
625
9e91597f
SAS		 626 up->ier = UART_IER_RLSI | UART_IER_RDI;
627 serial_out(up, UART_IER, up->ier);
628
71504e51 629#ifdef CONFIG_PM
61929cf0
SAS		 630 up->capabilities |= UART_CAP_RPM;
631#endif
632
633 /* Enable module level wake up */
634 priv->wer = OMAP_UART_WER_MOD_WKUP;
635 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
636 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
637 serial_out(up, UART_OMAP_WER, priv->wer);
638
0a0661dd
SAS		 639 if (up->dma)
640 up->dma->rx_dma(up, 0);
641
61929cf0
SAS		 642 pm_runtime_mark_last_busy(port->dev);
643 pm_runtime_put_autosuspend(port->dev);
644 return 0;
645err:
646 pm_runtime_mark_last_busy(port->dev);
647 pm_runtime_put_autosuspend(port->dev);
a3e362f1 648 dev_pm_clear_wake_irq(port->dev);
61929cf0
SAS		 649 return ret;
650}
651
652static void omap_8250_shutdown(struct uart_port *port)
653{
9e91597f 654 struct uart_8250_port *up = up_to_u8250p(port);
61929cf0
SAS		 655 struct omap8250_priv *priv = port->private_data;
656
657 flush_work(&priv->qos_work);
0a0661dd
SAS		 658 if (up->dma)
659 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT);
61929cf0
SAS		 660
661 pm_runtime_get_sync(port->dev);
662
663 serial_out(up, UART_OMAP_WER, 0);
9e91597f
SAS		 664
665 up->ier = 0;
666 serial_out(up, UART_IER, 0);
667
668 if (up->dma)
669 serial8250_release_dma(up);
670
671 /*
672 * Disable break condition and FIFOs
673 */
674 if (up->lcr & UART_LCR_SBC)
675 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
676 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
61929cf0
SAS		 677
678 pm_runtime_mark_last_busy(port->dev);
679 pm_runtime_put_autosuspend(port->dev);
9e91597f 680 free_irq(port->irq, port);
a3e362f1 681 dev_pm_clear_wake_irq(port->dev);
61929cf0
SAS		 682}
683
684static void omap_8250_throttle(struct uart_port *port)
685{
686 unsigned long flags;
687 struct uart_8250_port *up =
688 container_of(port, struct uart_8250_port, port);
689
690 pm_runtime_get_sync(port->dev);
691
692 spin_lock_irqsave(&port->lock, flags);
693 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
694 serial_out(up, UART_IER, up->ier);
695 spin_unlock_irqrestore(&port->lock, flags);
696
697 pm_runtime_mark_last_busy(port->dev);
698 pm_runtime_put_autosuspend(port->dev);
699}
700
701static void omap_8250_unthrottle(struct uart_port *port)
702{
703 unsigned long flags;
704 struct uart_8250_port *up =
705 container_of(port, struct uart_8250_port, port);
706
707 pm_runtime_get_sync(port->dev);
708
709 spin_lock_irqsave(&port->lock, flags);
710 up->ier |= UART_IER_RLSI | UART_IER_RDI;
711 serial_out(up, UART_IER, up->ier);
712 spin_unlock_irqrestore(&port->lock, flags);
713
714 pm_runtime_mark_last_busy(port->dev);
715 pm_runtime_put_autosuspend(port->dev);
716}
717
31a17132 718#ifdef CONFIG_SERIAL_8250_DMA
0e31c8d1
SAS		 719static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir);
720
721static void __dma_rx_do_complete(struct uart_8250_port *p, bool error)
722{
eda0cd35 723 struct omap8250_priv *priv = p->port.private_data;
0e31c8d1
SAS		 724 struct uart_8250_dma *dma = p->dma;
725 struct tty_port *tty_port = &p->port.state->port;
726 struct dma_tx_state state;
727 int count;
eda0cd35 728 unsigned long flags;
658e2ebc 729 int ret;
0e31c8d1
SAS		 730
731 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
732 dma->rx_size, DMA_FROM_DEVICE);
733
eda0cd35
JO		 734 spin_lock_irqsave(&priv->rx_dma_lock, flags);
735
736 if (!dma->rx_running)
737 goto unlock;
738
0e31c8d1
SAS		 739 dma->rx_running = 0;
740 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
741 dmaengine_terminate_all(dma->rxchan);
742
743 count = dma->rx_size - state.residue;
744
658e2ebc
SAS		 745 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
746
747 p->port.icount.rx += ret;
748 p->port.icount.buf_overrun += count - ret;
eda0cd35
JO		 749unlock:
750 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
751
0e31c8d1
SAS		 752 if (!error)
753 omap_8250_rx_dma(p, 0);
754
755 tty_flip_buffer_push(tty_port);
756}
757
758static void __dma_rx_complete(void *param)
759{
760 __dma_rx_do_complete(param, false);
761}
762
eda0cd35
JO		 763static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
764{
765 struct omap8250_priv *priv = p->port.private_data;
766 struct uart_8250_dma *dma = p->dma;
767 unsigned long flags;
830acf9e 768 int ret;
eda0cd35
JO		 769
770 spin_lock_irqsave(&priv->rx_dma_lock, flags);
771
772 if (!dma->rx_running) {
773 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
774 return;
775 }
776
830acf9e
SAS		 777 ret = dmaengine_pause(dma->rxchan);
778 if (WARN_ON_ONCE(ret))
779 priv->rx_dma_broken = true;
eda0cd35
JO		 780
781 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
782
783 __dma_rx_do_complete(p, true);
784}
785
0e31c8d1
SAS		 786static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
787{
eda0cd35 788 struct omap8250_priv *priv = p->port.private_data;
0e31c8d1 789 struct uart_8250_dma *dma = p->dma;
eda0cd35 790 int err = 0;
0e31c8d1 791 struct dma_async_tx_descriptor *desc;
eda0cd35 792 unsigned long flags;
0e31c8d1
SAS		 793
794 switch (iir & 0x3f) {
795 case UART_IIR_RLSI:
796 /* 8250_core handles errors and break interrupts */
eda0cd35 797 omap_8250_rx_dma_flush(p);
0e31c8d1
SAS		 798 return -EIO;
799 case UART_IIR_RX_TIMEOUT:
800 /*
801 * If RCVR FIFO trigger level was not reached, complete the
802 * transfer and let 8250_core copy the remaining data.
803 */
eda0cd35 804 omap_8250_rx_dma_flush(p);
0e31c8d1
SAS		 805 return -ETIMEDOUT;
806 case UART_IIR_RDI:
807 /*
808 * The OMAP UART is a special BEAST. If we receive RDI we _have_
809 * a DMA transfer programmed but it didn't work. One reason is
810 * that we were too slow and there were too many bytes in the
811 * FIFO, the UART counted wrong and never kicked the DMA engine
812 * to do anything. That means once we receive RDI on OMAP then
813 * the DMA won't do anything soon so we have to cancel the DMA
814 * transfer and purge the FIFO manually.
815 */
eda0cd35 816 omap_8250_rx_dma_flush(p);
0e31c8d1
SAS		 817 return -ETIMEDOUT;
818
819 default:
820 break;
821 }
822
830acf9e
SAS		 823 if (priv->rx_dma_broken)
824 return -EINVAL;
825
eda0cd35
JO		 826 spin_lock_irqsave(&priv->rx_dma_lock, flags);
827
0e31c8d1 828 if (dma->rx_running)
eda0cd35 829 goto out;
0e31c8d1
SAS		 830
831 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
832 dma->rx_size, DMA_DEV_TO_MEM,
833 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
eda0cd35
JO		 834 if (!desc) {
835 err = -EBUSY;
836 goto out;
837 }
0e31c8d1
SAS		 838
839 dma->rx_running = 1;
840 desc->callback = __dma_rx_complete;
841 desc->callback_param = p;
842
843 dma->rx_cookie = dmaengine_submit(desc);
844
845 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
846 dma->rx_size, DMA_FROM_DEVICE);
847
848 dma_async_issue_pending(dma->rxchan);
eda0cd35
JO		 849out:
850 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
851 return err;
0e31c8d1
SAS		 852}
853
31a17132
SAS		 854static int omap_8250_tx_dma(struct uart_8250_port *p);
855
856static void omap_8250_dma_tx_complete(void *param)
857{
858 struct uart_8250_port *p = param;
859 struct uart_8250_dma *dma = p->dma;
860 struct circ_buf *xmit = &p->port.state->xmit;
861 unsigned long flags;
862 bool en_thri = false;
0a0661dd 863 struct omap8250_priv *priv = p->port.private_data;
31a17132
SAS		 864
865 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
866 UART_XMIT_SIZE, DMA_TO_DEVICE);
867
868 spin_lock_irqsave(&p->port.lock, flags);
869
870 dma->tx_running = 0;
871
872 xmit->tail += dma->tx_size;
873 xmit->tail &= UART_XMIT_SIZE - 1;
874 p->port.icount.tx += dma->tx_size;
875
0a0661dd
SAS		 876 if (priv->delayed_restore) {
877 priv->delayed_restore = 0;
878 omap8250_restore_regs(p);
879 }
880
31a17132
SAS		 881 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
882 uart_write_wakeup(&p->port);
883
884 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
885 int ret;
886
887 ret = omap_8250_tx_dma(p);
888 if (ret)
889 en_thri = true;
890
891 } else if (p->capabilities & UART_CAP_RPM) {
892 en_thri = true;
893 }
894
895 if (en_thri) {
896 dma->tx_err = 1;
897 p->ier |= UART_IER_THRI;
898 serial_port_out(&p->port, UART_IER, p->ier);
899 }
900
901 spin_unlock_irqrestore(&p->port.lock, flags);
902}
903
904static int omap_8250_tx_dma(struct uart_8250_port *p)
905{
906 struct uart_8250_dma *dma = p->dma;
907 struct omap8250_priv *priv = p->port.private_data;
908 struct circ_buf *xmit = &p->port.state->xmit;
909 struct dma_async_tx_descriptor *desc;
910 unsigned int skip_byte = 0;
911 int ret;
912
913 if (dma->tx_running)
914 return 0;
915 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
916
917 /*
918 * Even if no data, we need to return an error for the two cases
919 * below so serial8250_tx_chars() is invoked and properly clears
920 * THRI and/or runtime suspend.
921 */
922 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
923 ret = -EBUSY;
924 goto err;
925 }
926 if (p->ier & UART_IER_THRI) {
927 p->ier &= ~UART_IER_THRI;
928 serial_out(p, UART_IER, p->ier);
929 }
930 return 0;
931 }
932
933 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
934 if (priv->habit & OMAP_DMA_TX_KICK) {
935 u8 tx_lvl;
936
937 /*
938 * We need to put the first byte into the FIFO in order to start
939 * the DMA transfer. For transfers smaller than four bytes we
940 * don't bother doing DMA at all. It seem not matter if there
941 * are still bytes in the FIFO from the last transfer (in case
942 * we got here directly from omap_8250_dma_tx_complete()). Bytes
943 * leaving the FIFO seem not to trigger the DMA transfer. It is
944 * really the byte that we put into the FIFO.
945 * If the FIFO is already full then we most likely got here from
946 * omap_8250_dma_tx_complete(). And this means the DMA engine
947 * just completed its work. We don't have to wait the complete
948 * 86us at 115200,8n1 but around 60us (not to mention lower
949 * baudrates). So in that case we take the interrupt and try
950 * again with an empty FIFO.
951 */
952 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
953 if (tx_lvl == p->tx_loadsz) {
954 ret = -EBUSY;
955 goto err;
956 }
957 if (dma->tx_size < 4) {
958 ret = -EINVAL;
959 goto err;
960 }
961 skip_byte = 1;
962 }
963
964 desc = dmaengine_prep_slave_single(dma->txchan,
965 dma->tx_addr + xmit->tail + skip_byte,
966 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
967 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
968 if (!desc) {
969 ret = -EBUSY;
970 goto err;
971 }
972
973 dma->tx_running = 1;
974
975 desc->callback = omap_8250_dma_tx_complete;
976 desc->callback_param = p;
977
978 dma->tx_cookie = dmaengine_submit(desc);
979
980 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
981 UART_XMIT_SIZE, DMA_TO_DEVICE);
982
983 dma_async_issue_pending(dma->txchan);
984 if (dma->tx_err)
985 dma->tx_err = 0;
986
987 if (p->ier & UART_IER_THRI) {
988 p->ier &= ~UART_IER_THRI;
989 serial_out(p, UART_IER, p->ier);
990 }
991 if (skip_byte)
992 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
993 return 0;
994err:
995 dma->tx_err = 1;
996 return ret;
997}
998
77285243
SAS		 999/*
1000 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1001 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1002 * use the default routine in the non-DMA case and this one for with DMA.
1003 */
1004static int omap_8250_dma_handle_irq(struct uart_port *port)
1005{
1006 struct uart_8250_port *up = up_to_u8250p(port);
1007 unsigned char status;
1008 unsigned long flags;
1009 u8 iir;
1010 int dma_err = 0;
1011
1012 serial8250_rpm_get(up);
1013
1014 iir = serial_port_in(port, UART_IIR);
1015 if (iir & UART_IIR_NO_INT) {
1016 serial8250_rpm_put(up);
1017 return 0;
1018 }
1019
1020 spin_lock_irqsave(&port->lock, flags);
1021
1022 status = serial_port_in(port, UART_LSR);
1023
1024 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1025
1026 dma_err = omap_8250_rx_dma(up, iir);
1027 if (dma_err) {
1028 status = serial8250_rx_chars(up, status);
1029 omap_8250_rx_dma(up, 0);
1030 }
1031 }
1032 serial8250_modem_status(up);
1033 if (status & UART_LSR_THRE && up->dma->tx_err) {
1034 if (uart_tx_stopped(&up->port) ||
1035 uart_circ_empty(&up->port.state->xmit)) {
1036 up->dma->tx_err = 0;
1037 serial8250_tx_chars(up);
1038 } else {
1039 /*
1040 * try again due to an earlier failer which
1041 * might have been resolved by now.
1042 */
1043 dma_err = omap_8250_tx_dma(up);
1044 if (dma_err)
1045 serial8250_tx_chars(up);
1046 }
1047 }
1048
1049 spin_unlock_irqrestore(&port->lock, flags);
1050 serial8250_rpm_put(up);
1051 return 1;
1052}
0a0661dd
SAS		 1053
1054static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1055{
1056 return false;
1057}
1058
1059#else
1060
1061static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
1062{
1063 return -EINVAL;
1064}
31a17132
SAS		 1065#endif
1066
9e91597f
SAS		 1067static int omap8250_no_handle_irq(struct uart_port *port)
1068{
1069 /* IRQ has not been requested but handling irq? */
1070 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1071 return 0;
1072}
1073
cdb929e4
SN		 1074static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1075static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE;
4fcdff9b
SN		 1076
1077static const struct of_device_id omap8250_dt_ids[] = {
1078 { .compatible = "ti,omap2-uart" },
1079 { .compatible = "ti,omap3-uart" },
1080 { .compatible = "ti,omap4-uart" },
1081 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
cdb929e4 1082 { .compatible = "ti,am4372-uart", .data = &am4372_habit, },
27c93af7 1083 { .compatible = "ti,dra742-uart", .data = &am4372_habit, },
4fcdff9b
SN		 1084 {},
1085};
1086MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1087
61929cf0
SAS		 1088static int omap8250_probe(struct platform_device *pdev)
1089{
1090 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1091 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1092 struct omap8250_priv *priv;
1093 struct uart_8250_port up;
1094 int ret;
1095 void __iomem *membase;
1096
1097 if (!regs || !irq) {
1098 dev_err(&pdev->dev, "missing registers or irq\n");
1099 return -EINVAL;
1100 }
1101
1102 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1103 if (!priv)
1104 return -ENOMEM;
1105
1106 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1107 resource_size(regs));
1108 if (!membase)
1109 return -ENODEV;
1110
1111 memset(&up, 0, sizeof(up));
1112 up.port.dev = &pdev->dev;
1113 up.port.mapbase = regs->start;
1114 up.port.membase = membase;
1115 up.port.irq = irq->start;
1116 /*
1117 * It claims to be 16C750 compatible however it is a little different.
1118 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1119 * have) is enabled via EFR instead of MCR. The type is set here 8250
1120 * just to get things going. UNKNOWN does not work for a few reasons and
1121 * we don't need our own type since we don't use 8250's set_termios()
1122 * or pm callback.
1123 */
1124 up.port.type = PORT_8250;
1125 up.port.iotype = UPIO_MEM;
1126 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1127 UPF_HARD_FLOW;
1128 up.port.private_data = priv;
1129
1130 up.port.regshift = 2;
1131 up.port.fifosize = 64;
1132 up.tx_loadsz = 64;
1133 up.capabilities = UART_CAP_FIFO;
71504e51 1134#ifdef CONFIG_PM
61929cf0 1135 /*
71504e51 1136 * Runtime PM is mostly transparent. However to do it right we need to a
61929cf0 1137 * TX empty interrupt before we can put the device to auto idle. So if
71504e51
RW		 1138 * PM is not enabled we don't add that flag and can spare that one extra
1139 * interrupt in the TX path.
61929cf0
SAS		 1140 */
1141 up.capabilities |= UART_CAP_RPM;
1142#endif
1143 up.port.set_termios = omap_8250_set_termios;
4bf4ea9d 1144 up.port.set_mctrl = omap8250_set_mctrl;
61929cf0
SAS		 1145 up.port.pm = omap_8250_pm;
1146 up.port.startup = omap_8250_startup;
1147 up.port.shutdown = omap_8250_shutdown;
1148 up.port.throttle = omap_8250_throttle;
1149 up.port.unthrottle = omap_8250_unthrottle;
1150
1151 if (pdev->dev.of_node) {
4fcdff9b
SN		 1152 const struct of_device_id *id;
1153
54178fe6
SAS		 1154 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1155
61929cf0
SAS		 1156 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1157 &up.port.uartclk);
1158 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
4fcdff9b
SN		 1159
1160 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1161 if (id && id->data)
1162 priv->habit |= *(u8 *)id->data;
61929cf0 1163 } else {
54178fe6 1164 ret = pdev->id;
61929cf0 1165 }
54178fe6
SAS		 1166 if (ret < 0) {
1167 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1168 return ret;
61929cf0 1169 }
54178fe6
SAS		 1170 up.port.line = ret;
1171
61929cf0
SAS		 1172 if (!up.port.uartclk) {
1173 up.port.uartclk = DEFAULT_CLK_SPEED;
1174 dev_warn(&pdev->dev,
1175 "No clock speed specified: using default: %d\n",
1176 DEFAULT_CLK_SPEED);
1177 }
1178
1179 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1180 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1181 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1182 priv->latency);
1183 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1184
eda0cd35
JO		 1185 spin_lock_init(&priv->rx_dma_lock);
1186
61929cf0
SAS		 1187 device_init_wakeup(&pdev->dev, true);
1188 pm_runtime_use_autosuspend(&pdev->dev);
1189 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1190
1191 pm_runtime_irq_safe(&pdev->dev);
1192 pm_runtime_enable(&pdev->dev);
1193
1194 pm_runtime_get_sync(&pdev->dev);
1195
1196 omap_serial_fill_features_erratas(&up, priv);
9e91597f 1197 up.port.handle_irq = omap8250_no_handle_irq;
0a0661dd
SAS		 1198#ifdef CONFIG_SERIAL_8250_DMA
1199 if (pdev->dev.of_node) {
1200 /*
1201 * Oh DMA support. If there are no DMA properties in the DT then
1202 * we will fall back to a generic DMA channel which does not
1203 * really work here. To ensure that we do not get a generic DMA
1204 * channel assigned, we have the the_no_dma_filter_fn() here.
1205 * To avoid "failed to request DMA" messages we check for DMA
1206 * properties in DT.
1207 */
1208 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1209 if (ret == 2) {
1210 up.dma = &priv->omap8250_dma;
0a0661dd
SAS		 1211 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1212 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1213 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1214 priv->omap8250_dma.rx_size = RX_TRIGGER;
1215 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1216 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1217
1218 if (of_machine_is_compatible("ti,am33xx"))
1219 priv->habit |= OMAP_DMA_TX_KICK;
830acf9e
SAS		 1220 /*
1221 * pause is currently not supported atleast on omap-sdma
1222 * and edma on most earlier kernels.
1223 */
1224 priv->rx_dma_broken = true;
0a0661dd
SAS		 1225 }
1226 }
1227#endif
61929cf0
SAS		 1228 ret = serial8250_register_8250_port(&up);
1229 if (ret < 0) {
1230 dev_err(&pdev->dev, "unable to register 8250 port\n");
1231 goto err;
1232 }
1233 priv->line = ret;
1234 platform_set_drvdata(pdev, priv);
1235 pm_runtime_mark_last_busy(&pdev->dev);
1236 pm_runtime_put_autosuspend(&pdev->dev);
1237 return 0;
1238err:
1239 pm_runtime_put(&pdev->dev);
1240 pm_runtime_disable(&pdev->dev);
1241 return ret;
1242}
1243
1244static int omap8250_remove(struct platform_device *pdev)
1245{
1246 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1247
1248 pm_runtime_put_sync(&pdev->dev);
1249 pm_runtime_disable(&pdev->dev);
1250 serial8250_unregister_port(priv->line);
1251 pm_qos_remove_request(&priv->pm_qos_request);
1252 device_init_wakeup(&pdev->dev, false);
1253 return 0;
1254}
1255
61929cf0
SAS		 1256#ifdef CONFIG_PM_SLEEP
1257static int omap8250_prepare(struct device *dev)
1258{
1259 struct omap8250_priv *priv = dev_get_drvdata(dev);
1260
1261 if (!priv)
1262 return 0;
1263 priv->is_suspending = true;
1264 return 0;
1265}
1266
1267static void omap8250_complete(struct device *dev)
1268{
1269 struct omap8250_priv *priv = dev_get_drvdata(dev);
1270
1271 if (!priv)
1272 return;
1273 priv->is_suspending = false;
1274}
1275
1276static int omap8250_suspend(struct device *dev)
1277{
1278 struct omap8250_priv *priv = dev_get_drvdata(dev);
1279
1280 serial8250_suspend_port(priv->line);
1281 flush_work(&priv->qos_work);
61929cf0
SAS		 1282 return 0;
1283}
1284
1285static int omap8250_resume(struct device *dev)
1286{
1287 struct omap8250_priv *priv = dev_get_drvdata(dev);
1288
61929cf0
SAS		 1289 serial8250_resume_port(priv->line);
1290 return 0;
1291}
1292#else
1293#define omap8250_prepare NULL
1294#define omap8250_complete NULL
1295#endif
1296
71504e51 1297#ifdef CONFIG_PM
61929cf0
SAS		 1298static int omap8250_lost_context(struct uart_8250_port *up)
1299{
1300 u32 val;
1301
cdb929e4 1302 val = serial_in(up, UART_OMAP_SCR);
61929cf0 1303 /*
cdb929e4
SN		 1304 * If we lose context, then SCR is set to its reset value of zero.
1305 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1306 * among other bits, to never set the register back to zero again.
61929cf0 1307 */
cdb929e4 1308 if (!val)
61929cf0
SAS		 1309 return 1;
1310 return 0;
1311}
1312
cdb929e4
SN		 1313/* TODO: in future, this should happen via API in drivers/reset/ */
1314static int omap8250_soft_reset(struct device *dev)
1315{
1316 struct omap8250_priv *priv = dev_get_drvdata(dev);
1317 struct uart_8250_port *up = serial8250_get_port(priv->line);
1318 int timeout = 100;
1319 int sysc;
1320 int syss;
1321
1322 sysc = serial_in(up, UART_OMAP_SYSC);
1323
1324 /* softreset the UART */
1325 sysc |= OMAP_UART_SYSC_SOFTRESET;
1326 serial_out(up, UART_OMAP_SYSC, sysc);
1327
1328 /* By experiments, 1us enough for reset complete on AM335x */
1329 do {
1330 udelay(1);
1331 syss = serial_in(up, UART_OMAP_SYSS);
1332 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1333
1334 if (!timeout) {
1335 dev_err(dev, "timed out waiting for reset done\n");
1336 return -ETIMEDOUT;
1337 }
1338
1339 return 0;
1340}
1341
61929cf0
SAS		 1342static int omap8250_runtime_suspend(struct device *dev)
1343{
1344 struct omap8250_priv *priv = dev_get_drvdata(dev);
1345 struct uart_8250_port *up;
1346
1347 up = serial8250_get_port(priv->line);
1348 /*
1349 * When using 'no_console_suspend', the console UART must not be
1350 * suspended. Since driver suspend is managed by runtime suspend,
1351 * preventing runtime suspend (by returning error) will keep device
1352 * active during suspend.
1353 */
1354 if (priv->is_suspending && !console_suspend_enabled) {
1355 if (uart_console(&up->port))
1356 return -EBUSY;
1357 }
1358
cdb929e4
SN		 1359 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1360 int ret;
1361
1362 ret = omap8250_soft_reset(dev);
1363 if (ret)
1364 return ret;
1365
1366 /* Restore to UART mode after reset (for wakeup) */
1367 omap8250_update_mdr1(up, priv);
1368 }
1369
727fd8ab 1370 if (up->dma && up->dma->rxchan)
0a0661dd 1371 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT);
61929cf0
SAS		 1372
1373 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1374 schedule_work(&priv->qos_work);
1375
1376 return 0;
1377}
1378
1379static int omap8250_runtime_resume(struct device *dev)
1380{
1381 struct omap8250_priv *priv = dev_get_drvdata(dev);
1382 struct uart_8250_port *up;
1383 int loss_cntx;
1384
1385 /* In case runtime-pm tries this before we are setup */
1386 if (!priv)
1387 return 0;
1388
1389 up = serial8250_get_port(priv->line);
61929cf0
SAS		 1390 loss_cntx = omap8250_lost_context(up);
1391
1392 if (loss_cntx)
1393 omap8250_restore_regs(up);
1394
727fd8ab 1395 if (up->dma && up->dma->rxchan)
0a0661dd
SAS		 1396 omap_8250_rx_dma(up, 0);
1397
61929cf0
SAS		 1398 priv->latency = priv->calc_latency;
1399 schedule_work(&priv->qos_work);
1400 return 0;
1401}
1402#endif
1403
00648d02
SAS		 1404#ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1405static int __init omap8250_console_fixup(void)
1406{
1407 char *omap_str;
1408 char *options;
1409 u8 idx;
1410
1411 if (strstr(boot_command_line, "console=ttyS"))
1412 /* user set a ttyS based name for the console */
1413 return 0;
1414
1415 omap_str = strstr(boot_command_line, "console=ttyO");
1416 if (!omap_str)
1417 /* user did not set ttyO based console, so we don't care */
1418 return 0;
1419
1420 omap_str += 12;
1421 if ('0' <= *omap_str && *omap_str <= '9')
1422 idx = *omap_str - '0';
1423 else
1424 return 0;
1425
1426 omap_str++;
1427 if (omap_str[0] == ',') {
1428 omap_str++;
1429 options = omap_str;
1430 } else {
1431 options = NULL;
1432 }
1433
1434 add_preferred_console("ttyS", idx, options);
1435 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1436 idx, idx);
1437 pr_err("This ensures that you still see kernel messages. Please\n");
1438 pr_err("update your kernel commandline.\n");
1439 return 0;
1440}
1441console_initcall(omap8250_console_fixup);
1442#endif
1443
61929cf0
SAS		 1444static const struct dev_pm_ops omap8250_dev_pm_ops = {
1445 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1446 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1447 omap8250_runtime_resume, NULL)
1448 .prepare = omap8250_prepare,
1449 .complete = omap8250_complete,
1450};
1451
61929cf0
SAS		 1452static struct platform_driver omap8250_platform_driver = {
1453 .driver = {
1454 .name = "omap8250",
1455 .pm = &omap8250_dev_pm_ops,
1456 .of_match_table = omap8250_dt_ids,
61929cf0
SAS		 1457 },
1458 .probe = omap8250_probe,
1459 .remove = omap8250_remove,
1460};
1461module_platform_driver(omap8250_platform_driver);
1462
1463MODULE_AUTHOR("Sebastian Andrzej Siewior");
1464MODULE_DESCRIPTION("OMAP 8250 Driver");
1465MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)