[linux-2.6-block.git] / drivers / thermal / ti-soc-thermal / omap5xxx-bandgap.h

/*
 * OMAP5xxx bandgap registers, bitfields and temperature definitions
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 * Contact:
 *   Eduardo Valentin <eduardo.valentin@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */
#ifndef __OMAP5XXX_BANDGAP_H
#define __OMAP5XXX_BANDGAP_H

/**
 * *** OMAP5430 ***
 *
 * Below, in sequence, are the Register definitions,
 * the bitfields and the temperature definitions for OMAP5430.
 */

/**
 * OMAP5430 register definitions
 *
 * Registers are defined as offsets. The offsets are
 * relative to FUSE_OPP_BGAP_GPU on 5430.
 *
 * Register below are grouped by domain (not necessarily in offset order)
 */

/* OMAP5430.GPU register offsets */
#define OMAP5430_FUSE_OPP_BGAP_GPU			0x0
#define OMAP5430_TEMP_SENSOR_GPU_OFFSET			0x150
#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET		0x1A8
#define OMAP5430_BGAP_TSHUT_GPU_OFFSET			0x1B4
#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET		0x1F8
#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET		0x1FC

/* OMAP5430.MPU register offsets */
#define OMAP5430_FUSE_OPP_BGAP_MPU			0x4
#define OMAP5430_TEMP_SENSOR_MPU_OFFSET			0x14C
#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET		0x1A4
#define OMAP5430_BGAP_TSHUT_MPU_OFFSET			0x1B0
#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET		0x1E4
#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET		0x1E8

/* OMAP5430.MPU register offsets */
#define OMAP5430_FUSE_OPP_BGAP_CORE			0x8
#define OMAP5430_TEMP_SENSOR_CORE_OFFSET		0x154
#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET		0x1AC
#define OMAP5430_BGAP_TSHUT_CORE_OFFSET			0x1B8
#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET		0x20C
#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET		0x210

/* OMAP5430.common register offsets */
#define OMAP5430_BGAP_CTRL_OFFSET			0x1A0
#define OMAP5430_BGAP_STATUS_OFFSET			0x1C8

/**
 * Register bitfields for OMAP5430
 *
 * All the macros bellow define the required bits for
 * controlling temperature on OMAP5430. Bit defines are
 * grouped by register.
 */

/* OMAP5430.TEMP_SENSOR */
#define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK		BIT(12)
#define OMAP5430_BGAP_TEMPSOFF_MASK			BIT(11)
#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK		BIT(10)
#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK		(0x3ff << 0)

/* OMAP5430.BANDGAP_CTRL */
#define OMAP5430_MASK_COUNTER_DELAY_MASK		(0x7 << 27)
#define OMAP5430_MASK_FREEZE_CORE_MASK			BIT(23)
#define OMAP5430_MASK_FREEZE_GPU_MASK			BIT(22)
#define OMAP5430_MASK_FREEZE_MPU_MASK			BIT(21)
#define OMAP5430_MASK_HOT_CORE_MASK			BIT(5)
#define OMAP5430_MASK_COLD_CORE_MASK			BIT(4)
#define OMAP5430_MASK_HOT_GPU_MASK			BIT(3)
#define OMAP5430_MASK_COLD_GPU_MASK			BIT(2)
#define OMAP5430_MASK_HOT_MPU_MASK			BIT(1)
#define OMAP5430_MASK_COLD_MPU_MASK			BIT(0)

/* OMAP5430.BANDGAP_COUNTER */
#define OMAP5430_COUNTER_MASK				(0xffffff << 0)

/* OMAP5430.BANDGAP_THRESHOLD */
#define OMAP5430_T_HOT_MASK				(0x3ff << 16)
#define OMAP5430_T_COLD_MASK				(0x3ff << 0)

/* OMAP5430.TSHUT_THRESHOLD */
#define OMAP5430_TSHUT_HOT_MASK				(0x3ff << 16)
#define OMAP5430_TSHUT_COLD_MASK			(0x3ff << 0)

/* OMAP5430.BANDGAP_STATUS */
#define OMAP5430_HOT_CORE_FLAG_MASK			BIT(5)
#define OMAP5430_COLD_CORE_FLAG_MASK			BIT(4)
#define OMAP5430_HOT_GPU_FLAG_MASK			BIT(3)
#define OMAP5430_COLD_GPU_FLAG_MASK			BIT(2)
#define OMAP5430_HOT_MPU_FLAG_MASK			BIT(1)
#define OMAP5430_COLD_MPU_FLAG_MASK			BIT(0)

/**
 * Temperature limits and thresholds for OMAP5430
 *
 * All the macros bellow are definitions for handling the
 * ADC conversions and representation of temperature limits
 * and thresholds for OMAP5430. Definitions are grouped
 * by temperature domain.
 */

/* OMAP5430.common temperature definitions */
/* ADC conversion table limits */
#define OMAP5430_ADC_START_VALUE			540
#define OMAP5430_ADC_END_VALUE				945

/* OMAP5430.GPU temperature definitions */
/* bandgap clock limits */
#define OMAP5430_GPU_MAX_FREQ				1500000
#define OMAP5430_GPU_MIN_FREQ				1000000
/* interrupts thresholds */
#define OMAP5430_GPU_TSHUT_HOT				915
#define OMAP5430_GPU_TSHUT_COLD				900
#define OMAP5430_GPU_T_HOT				800
#define OMAP5430_GPU_T_COLD				795

/* OMAP5430.MPU temperature definitions */
/* bandgap clock limits */
#define OMAP5430_MPU_MAX_FREQ				1500000
#define OMAP5430_MPU_MIN_FREQ				1000000
/* interrupts thresholds */
#define OMAP5430_MPU_TSHUT_HOT				915
#define OMAP5430_MPU_TSHUT_COLD				900
#define OMAP5430_MPU_T_HOT				800
#define OMAP5430_MPU_T_COLD				795

/* OMAP5430.CORE temperature definitions */
/* bandgap clock limits */
#define OMAP5430_CORE_MAX_FREQ				1500000
#define OMAP5430_CORE_MIN_FREQ				1000000
/* interrupts thresholds */
#define OMAP5430_CORE_TSHUT_HOT				915
#define OMAP5430_CORE_TSHUT_COLD			900
#define OMAP5430_CORE_T_HOT				800
#define OMAP5430_CORE_T_COLD				795

#endif /* __OMAP5XXX_BANDGAP_H */
Commit	Line	Data
787f3c27 EV	1	/*
	2	* OMAP5xxx bandgap registers, bitfields and temperature definitions
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	5	* Contact:
	6	* Eduardo Valentin <eduardo.valentin@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23	#ifndef __OMAP5XXX_BANDGAP_H
	24	#define __OMAP5XXX_BANDGAP_H
	25
	26	/**
	27	* * OMAP5430 *
	28	*
	29	* Below, in sequence, are the Register definitions,
	30	* the bitfields and the temperature definitions for OMAP5430.
	31	*/
	32
	33	/**
	34	* OMAP5430 register definitions
	35	*
	36	* Registers are defined as offsets. The offsets are
	37	* relative to FUSE_OPP_BGAP_GPU on 5430.
	38	*
	39	* Register below are grouped by domain (not necessarily in offset order)
	40	*/
	41
	42	/* OMAP5430.GPU register offsets */
	43	#define OMAP5430_FUSE_OPP_BGAP_GPU 0x0
	44	#define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150
	45	#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8
	46	#define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4
787f3c27 EV	47	#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8
787f3c27 EV	48	#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC
787f3c27 EV	49
	50	/* OMAP5430.MPU register offsets */
	51	#define OMAP5430_FUSE_OPP_BGAP_MPU 0x4
	52	#define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C
	53	#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4
	54	#define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0
787f3c27 EV	55	#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4
787f3c27 EV	56	#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8
787f3c27 EV	57
	58	/* OMAP5430.MPU register offsets */
	59	#define OMAP5430_FUSE_OPP_BGAP_CORE 0x8
	60	#define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154
	61	#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC
	62	#define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8
787f3c27 EV	63	#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C
787f3c27 EV	64	#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210
787f3c27 EV	65
	66	/* OMAP5430.common register offsets */
	67	#define OMAP5430_BGAP_CTRL_OFFSET 0x1A0
	68	#define OMAP5430_BGAP_STATUS_OFFSET 0x1C8
	69
	70	/**
	71	* Register bitfields for OMAP5430
	72	*
	73	* All the macros bellow define the required bits for
	74	* controlling temperature on OMAP5430. Bit defines are
	75	* grouped by register.
	76	*/
	77
	78	/* OMAP5430.TEMP_SENSOR */
	79	#define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12)
	80	#define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11)
	81	#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
	82	#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
	83
	84	/* OMAP5430.BANDGAP_CTRL */
8b6ecd35	85	#define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27)
787f3c27 EV	86	#define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)
	87	#define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)
	88	#define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)
787f3c27 EV	89	#define OMAP5430_MASK_HOT_CORE_MASK BIT(5)
	90	#define OMAP5430_MASK_COLD_CORE_MASK BIT(4)
	91	#define OMAP5430_MASK_HOT_GPU_MASK BIT(3)
	92	#define OMAP5430_MASK_COLD_GPU_MASK BIT(2)
	93	#define OMAP5430_MASK_HOT_MPU_MASK BIT(1)
	94	#define OMAP5430_MASK_COLD_MPU_MASK BIT(0)
	95
	96	/* OMAP5430.BANDGAP_COUNTER */
	97	#define OMAP5430_COUNTER_MASK (0xffffff << 0)
	98
	99	/* OMAP5430.BANDGAP_THRESHOLD */
	100	#define OMAP5430_T_HOT_MASK (0x3ff << 16)
	101	#define OMAP5430_T_COLD_MASK (0x3ff << 0)
	102
	103	/* OMAP5430.TSHUT_THRESHOLD */
	104	#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
	105	#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
	106
787f3c27	107	/* OMAP5430.BANDGAP_STATUS */
787f3c27 EV	108	#define OMAP5430_HOT_CORE_FLAG_MASK BIT(5)
	109	#define OMAP5430_COLD_CORE_FLAG_MASK BIT(4)
	110	#define OMAP5430_HOT_GPU_FLAG_MASK BIT(3)
	111	#define OMAP5430_COLD_GPU_FLAG_MASK BIT(2)
	112	#define OMAP5430_HOT_MPU_FLAG_MASK BIT(1)
	113	#define OMAP5430_COLD_MPU_FLAG_MASK BIT(0)
	114
	115	/**
	116	* Temperature limits and thresholds for OMAP5430
	117	*
	118	* All the macros bellow are definitions for handling the
	119	* ADC conversions and representation of temperature limits
	120	* and thresholds for OMAP5430. Definitions are grouped
	121	* by temperature domain.
	122	*/
	123
	124	/* OMAP5430.common temperature definitions */
	125	/* ADC conversion table limits */
	126	#define OMAP5430_ADC_START_VALUE 540
	127	#define OMAP5430_ADC_END_VALUE 945
	128
	129	/* OMAP5430.GPU temperature definitions */
	130	/* bandgap clock limits */
	131	#define OMAP5430_GPU_MAX_FREQ 1500000
	132	#define OMAP5430_GPU_MIN_FREQ 1000000
787f3c27 EV	133	/* interrupts thresholds */
	134	#define OMAP5430_GPU_TSHUT_HOT 915
	135	#define OMAP5430_GPU_TSHUT_COLD 900
	136	#define OMAP5430_GPU_T_HOT 800
	137	#define OMAP5430_GPU_T_COLD 795
	138
	139	/* OMAP5430.MPU temperature definitions */
	140	/* bandgap clock limits */
	141	#define OMAP5430_MPU_MAX_FREQ 1500000
	142	#define OMAP5430_MPU_MIN_FREQ 1000000
787f3c27 EV	143	/* interrupts thresholds */
	144	#define OMAP5430_MPU_TSHUT_HOT 915
	145	#define OMAP5430_MPU_TSHUT_COLD 900
	146	#define OMAP5430_MPU_T_HOT 800
	147	#define OMAP5430_MPU_T_COLD 795
	148
	149	/* OMAP5430.CORE temperature definitions */
	150	/* bandgap clock limits */
	151	#define OMAP5430_CORE_MAX_FREQ 1500000
	152	#define OMAP5430_CORE_MIN_FREQ 1000000
787f3c27 EV	153	/* interrupts thresholds */
	154	#define OMAP5430_CORE_TSHUT_HOT 915
	155	#define OMAP5430_CORE_TSHUT_COLD 900
	156	#define OMAP5430_CORE_T_HOT 800
	157	#define OMAP5430_CORE_T_COLD 795
	158
	159	#endif /* __OMAP5XXX_BANDGAP_H */